A digital-to-analog conversion circuit and a digital-to-analog conversion device

Abstract

The present invention provides a digital-to-analog conversion circuit and a digital-to-analog conversion device, including: a first sampling capacitor, a second sampling capacitor, a third holding capacitor, and a fourth holding capacitor; a second switch is connected between the second ends of the first sampling capacitor and the second sampling capacitor; the second ends of the first sampling capacitor and the second sampling capacitor are respectively connected to one of a first reference voltage, a second reference voltage, or an intermediate reference voltage through a first switch module and a third switch module; a fourth switch is connected between the second end of the third holding capacitor and the second end of the first sampling capacitor; a fifth switch is connected between the second end of the fourth holding capacitor and the second end of the second sampling capacitor; the second ends of the third holding capacitor and the fourth holding capacitor are respectively connected to the intermediate reference voltage through a sixth switch and a seventh switch; the second ends of the third holding capacitor and the fourth holding capacitor are respectively used as the first and second voltage output ends of the digital-to-analog conversion circuit.

Description

Technical Field

[0001] The present invention mainly relates to the field of integrated circuits, and particularly relates to a digital-to-analog conversion circuit and a digital-to-analog conversion device. Background Art

[0002] A digital-to-analog converter (DAC) is a bridge between digital circuits and analog circuits and has wide applications in display technologies, signal transmission, etc. As the accuracy requirement of the digital-to-analog converter increases, the corresponding integrated circuit area of the digital-to-analog converter increases exponentially, which directly affects the area of the chip and thus the cost. Therefore, controlling the manufacturing area plays a crucial role in the application of the DAC.

[0003] A main error source of the digital-to-analog converter (DAC) is the mismatch between multiple devices in the circuit. Although enhancing the matching property in the integrated circuit layout can significantly reduce the error during output, the appearance of the error still cannot be avoided. Moreover, as the accuracy improves, the DAC still requires a large increase in manufacturing area. Also, for a serial DAC architecture, the error caused by parasitic capacitance accumulates each time the charge is redistributed, and with each additional bit, the error accumulates one more time. Therefore, for a serial DAC, to improve the conversion accuracy, only by increasing the area of the main capacitor and reducing the mismatch between capacitors can it be achieved. The accuracy impact caused by parasitic capacitance requires additional measures to further control. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a digital-to-analog conversion circuit and a digital-to-analog conversion device, which can eliminate the errors caused by parasitic capacitance and device mismatch in the circuit while improving the accuracy of the digital-to-analog converter, and can control the manufacturing area of the digital-to-analog converter.

[0005] To solve the above technical problems, the present invention provides a digital-to-analog conversion circuit, comprising: a first sampling capacitor, a second sampling capacitor, a third holding capacitor, a fourth holding capacitor, a first switch module, a third switch module, a second switch, a fourth switch, a fifth switch, a sixth switch, and a seventh switch; a first end of the first sampling capacitor and a first end of the second sampling capacitor are grounded; a second switch is connected between a second end of the first sampling capacitor and a second end of the second sampling capacitor; the second end of the first sampling capacitor and the second end of the second sampling capacitor are respectively connected to one of a first reference voltage, a second reference voltage, or an intermediate reference voltage through the first switch module and the third switch module; the intermediate reference voltage is obtained based on the first reference voltage and the second reference voltage; a first end of the third holding capacitor and a first end of the fourth holding capacitor are grounded; a fourth switch is connected between a second end of the third holding capacitor and a second end of the first sampling capacitor; a fifth switch is connected between a second end of the fourth holding capacitor and a second end of the second sampling capacitor; the second end of the third holding capacitor and the second end of the fourth holding capacitor are respectively connected to the intermediate reference voltage through the sixth switch and the seventh switch; wherein, the second end of the third holding capacitor and the second end of the fourth holding capacitor are respectively used as a first voltage output terminal and a second voltage output terminal of the digital-to-analog conversion circuit.

[0006] In an embodiment of the present invention, the obtaining of the intermediate reference voltage based on the first reference voltage and the second reference voltage includes: V CM = k1 * V REFP + k2 * V REFN ; wherein, V CM is the intermediate reference voltage, V REFP is the first reference voltage, V REFN is the second reference voltage; k1 and k2 are rational numbers, and k1, k2 ∈ (0, 1).

[0007] In an embodiment of the present invention, the first switch module and the third switch module include a plurality of transistors.

[0008] In an embodiment of the present invention, the second switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch are implemented through a transistor circuit.

[0009] The present invention further provides a digital-to-analog conversion device, comprising the digital-to-analog conversion circuit as described in any one of the preceding items; and a controller; the controller is configured to perform the following operations: obtain the voltage value corresponding to the first voltage output terminal according to the multi-bit coding value corresponding to the input digital signal; obtain the voltage value corresponding to the second voltage output terminal according to the multi-bit coding value corresponding to the input digital signal; and obtain the analog voltage output value of the digital-to-analog conversion circuit based on the voltage value corresponding to the first voltage output terminal and the voltage value corresponding to the second voltage output terminal.

[0010] In one embodiment of the present invention, obtaining the voltage value corresponding to the first voltage output terminal according to the multi-bit encoding value corresponding to the input digital signal includes: performing a first-round reset on the first sampling capacitor and the second sampling capacitor through a first-stage switch switching operation; sequentially reading the multi-bit encoding value from the low bit to the high bit, and for each encoding value, completing a first-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor through a second-stage switch switching operation; completing a second-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor, and the third holding capacitor through a third-stage switch switching operation, and obtaining the voltage value corresponding to the first voltage output terminal.

[0011] In one embodiment of the present invention, obtaining the voltage value corresponding to the second voltage output terminal according to the multi-bit encoding value corresponding to the input digital signal includes: performing a second-round reset on the first sampling capacitor and the second sampling capacitor through a fourth-stage switch switching operation; sequentially reading the multi-bit encoding value from the low bit to the high bit, and for each encoding value, completing a third-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor through a fifth-stage switch switching operation; completing a fourth-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor, and the fourth holding capacitor through a sixth-stage switch switching operation, and collecting the voltage value corresponding to the second voltage output terminal.

[0012] In one embodiment of the present invention, obtaining the analog voltage output value of the digital-to-analog conversion circuit based on the voltage value corresponding to the first voltage output terminal and the voltage value corresponding to the second voltage output terminal includes:

[0013] When the second switch is closed, V out = a1 * (V outp - V outn ), a1 = 2C sam / (2C sam + C hol ); when the second switch is open, V out = a2 * (V outp - V outn ), a2 = C sam / (C sam + C hol ); where, V out is the analog voltage output value of the digital-to-analog conversion circuit, V outp is the voltage value corresponding to the first voltage output terminal, V outn is the voltage value corresponding to the second voltage output terminal; C sam is the capacitance value of the first sampling capacitor or the second sampling capacitor, C holFor the capacitance values of the third holding capacitor or the fourth holding capacitor, the capacitance values of the first sampling capacitor and the second sampling capacitor are equal, and the capacitance values of the first holding capacitor and the second holding capacitor are equal.

[0014] In an embodiment of the present invention, the first round of resetting the first sampling capacitor and the second sampling capacitor through the first-stage switch switching operation includes: closing the sixth switch, and connecting the second ends of the first sampling capacitor and the second sampling capacitor to the intermediate reference voltage through the first switch module and the third switch module respectively; after a first time interval, disconnecting the sixth switch, and disconnecting the first switch module and the third switch module.

[0015] In an embodiment of the present invention, for each coded value, the first-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor is completed through the second-stage switch switching operation, including: when the coded value corresponds to a high level, connecting the second end of the first sampling capacitor to the first reference voltage through the first switch module; when the coded value corresponds to a low level, connecting the second end of the first sampling capacitor to the intermediate reference voltage through the first switch module; after a second time interval, disconnecting the first switch module, and closing the second switch; after a third time interval, disconnecting the second switch, and completing the first-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor.

[0016] In an embodiment of the present invention, the second-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor and the third holding capacitor is completed through the third-stage switch switching operation, and the voltage value corresponding to the first voltage output terminal is obtained, including: closing the second switch and the fourth switch; after a fourth time interval, disconnecting the second switch and the fourth switch, and completing the second-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor and the third holding capacitor.

[0017] In an embodiment of the present invention, the second round of resetting the first sampling capacitor and the second sampling capacitor through the fourth-stage switch switching operation includes: closing the seventh switch, and connecting the second ends of the first sampling capacitor and the second sampling capacitor to the intermediate reference voltage through the first switch module and the third switch module respectively; after a fifth time interval, disconnecting the seventh switch, and disconnecting the first switch module and the third switch module.

[0018] In an embodiment of the present invention, for each coding value, the third-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor completed through the fifth-stage switch switching operation includes: when the coding value corresponds to a high level, the second terminal of the second sampling capacitor is connected to the second reference voltage through the third switch module; when the coding value corresponds to a low level, the second terminal of the second sampling capacitor is connected to the intermediate reference voltage through the third switch module; after a sixth time interval, the third switch module is disconnected and the second switch is closed; after a seventh time interval, the second switch is disconnected to complete the third-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor.

[0019] In an embodiment of the present invention, the fourth-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor and the fourth holding capacitor is completed through the sixth-stage switch switching operation, and the voltage value corresponding to the second voltage output terminal is acquired, including: closing the second switch and the fifth switch; after an eighth time interval, disconnecting the second switch and the fifth switch to complete the fourth-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor and the fourth holding capacitor.

[0020] In an embodiment of the present invention, obtaining the analog voltage output value of the digital-to-analog conversion circuit based on the voltage value corresponding to the first voltage output terminal and the voltage value corresponding to the second voltage output terminal includes: when the second switch is closed, V out =(2P - 1)*a1*(V outp -V outn ), a1 = 2C sam / (2C sam +C hol ); when the second switch is disconnected, V out =(2P - 1)*a2*(V outp -V outn ), a2 = C sam / (C sam +C hol ); where V out is the analog voltage output value of the digital-to-analog conversion circuit, V outp is the voltage value corresponding to the first voltage output terminal, V outn is the voltage value corresponding to the second voltage output terminal; C sam is the capacitance value of the first sampling capacitor or the second sampling capacitor, C hol is the capacitance value of the first holding capacitor or the second holding capacitor, the capacitance values of the first sampling capacitor and the second sampling capacitor are equal, and the capacitance values of the first holding capacitor and the second holding capacitor are equal; P is the voltage polarity adjustment code, and the value of P is 0 or 1.

[0021] Compared with the prior art, the present invention has the following advantages: In the technical solution of the present application, the output voltage is output in a differential mode, and the errors caused by parasitic capacitances, device mismatches, etc. in the circuit are also equally included in the common-mode part of the two differential voltages, thereby eliminating the errors caused by parasitic capacitances, device mismatches, etc., and being able to control the fabrication area of the digital-to-analog converter, facilitating the expansion of the application scenarios of the digital-to-analog converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings are provided to further understand the present application. They are incorporated and constitute a part of the present application. The drawings illustrate the embodiments of the present application and, together with this specification, serve to explain the principles of the present application.

[0023] In the drawings:

[0024] Figure 1 is a schematic structural diagram of a digital-to-analog conversion circuit according to an embodiment of the present application.

[0025] Figure 2 is a schematic composition diagram of a digital-to-analog conversion device according to an embodiment of the present application.

[0026] Figure 3 is a schematic structural diagram of a digital-to-analog conversion circuit according to an embodiment of the present application.

[0027] Figure 4 is an operation flowchart of a controller of a digital-to-analog conversion device according to an embodiment of the present application.

[0028] Figure 5 is a step flowchart of obtaining the voltage value corresponding to the first voltage output terminal of a digital-to-analog conversion device according to an embodiment of the present application.

[0029] Figure 6 is a step flowchart of obtaining the voltage value corresponding to the second voltage output terminal of a digital-to-analog conversion device according to an embodiment of the present application.

[0030] Figure 7 is a first-stage switch switching operation flowchart of a digital-to-analog conversion device according to an embodiment of the present application.

[0031] Figure 8 is a second-stage switch switching operation flowchart of a digital-to-analog conversion device according to an embodiment of the present application.

[0032] Figure 9 is a third-stage switch switching operation flowchart of a digital-to-analog conversion device according to an embodiment of the present application.

[0033] Figure 10 is a fourth-stage switch switching operation flowchart of a digital-to-analog conversion device according to an embodiment of the present application.

[0034] Figure 11It is the flowchart of the fifth-stage switch switching operation of the digital-to-analog conversion device according to an embodiment of the present application.

[0035] Figure 12 It is the flowchart of the sixth-stage switch switching operation of the digital-to-analog conversion device according to an embodiment of the present application.

[0036] Figures 13 to 28 It is a schematic diagram of the operation process of the digital-to-analog conversion device according to an embodiment of the present application.

[0037] Figure 29 It is a schematic diagram of the voltage waveform at both ends of the sampling capacitor during the operation of the digital-to-analog conversion device according to an embodiment of the present application. Detailed implementation manners

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. Unless obvious from the language context or otherwise stated, the same reference numerals in the figures represent the same structure or operation.

[0039] As shown in the present application and the claims, unless the context clearly indicates an exception, words such as "a", "an", "one", and / or "the" are not specifically singular and may also include plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0040] Unless otherwise specifically stated, the relative arrangements, numerical expressions, and values of the components and steps described in these embodiments do not limit the scope of the present application. At the same time, it should be understood that for the sake of convenience of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship.

[0041] In addition, it should be noted that the use of words such as "first" and "second" to limit the components is only for the convenience of distinguishing the corresponding components. Without otherwise stating, the above words have no special meaning, so they cannot be understood as limiting the protection scope of the present application. In addition, although the terms used in the present application are selected from well-known and commonly used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant according to his or her judgment. Their detailed meanings are described in the relevant parts of this description. In addition, it is required to understand the present application not only through the actual terms used, but also through the meaning implied by each term.

[0042] In this application, flowcharts are used to illustrate the operations performed by the systems according to the embodiments of this application. It should be understood that the operations described above or below do not necessarily have to be performed precisely in order. Instead, various steps can be processed in reverse order or simultaneously. Also, one or more operations can be added to these processes, or one or more steps can be removed from these processes.

[0043] Embodiments of this application describe a digital-to-analog conversion circuit and a digital-to-analog conversion device.

[0044] Figure 1 It is a schematic structural diagram of a digital-to-analog conversion circuit according to an embodiment of this application.

[0045] Refer to Figure 1 , the digital-to-analog conversion circuit 100 includes: a first sampling capacitor C1, a second sampling capacitor C2, a third holding capacitor C3, a fourth holding capacitor C4, a first switch module S1, a third switch module S3, a second switch S2, a fourth switch S4, a fifth switch S5, a sixth switch S6, and a seventh switch S7.

[0046] The first end of the first sampling capacitor C1 and the first end of the second sampling capacitor C2 are grounded to GND. A second switch S2 is connected between the second end of the first sampling capacitor C1 and the second end of the second sampling capacitor C2.

[0047] The second end of the first sampling capacitor C1 and the second end of the second sampling capacitor C2 are also respectively connected to the first reference voltage V REFP , the second reference voltage V REFN or the intermediate reference voltage V CM through the first switch module S1 and the third switch module S3. The intermediate reference voltage V CM is based on the first reference voltage V REFP and the second reference voltage V REFN obtained. The first end of the third holding capacitor C3 and the first end of the fourth holding capacitor C4 are grounded to GND. A fourth switch S4 is connected between the second end of the third holding capacitor C3 and the second end of the first sampling capacitor C1. A fifth switch S5 is connected between the second end of the fourth holding capacitor C4 and the second end of the second sampling capacitor C2.

[0048] The second end of the third holding capacitor C3 and the second end of the fourth holding capacitor C4 are respectively connected to the intermediate reference voltage V CM through the sixth switch S6 and the seventh switch S7. The second end of the third holding capacitor C3 and the second end of the fourth holding capacitor C4 serve as the first voltage output terminal and the second voltage output terminal of the digital-to-analog conversion circuit 100 respectively.

[0049] The capacitance values of the first end of the first sampling capacitor C1 and the second sampling capacitor C2 can be set to be the same. The capacitance values of the third holding capacitor C3 and the fourth holding capacitor C4 can be set to be the same.

[0050] In some embodiments, the intermediate reference voltage V CM is based on the first reference voltage V REFP and the second reference voltage V REFN to obtain including:

[0051] V CM = k1 * V REFP + k2 * V REFN .

[0052] Wherein, k1 and k2 are rational numbers, and k1, k2 ∈ (0, 1).

[0053] The first switch module S1 and the third switch module S3 include multiple transistors. Figure 3 is a schematic structural diagram of a digital-to-analog conversion circuit according to an embodiment of the present application. Refer to Figure 3 , for example, the first switch module S1 includes a first transistor or transistor combination TR1, a second transistor or transistor combination TR2, and a third transistor or transistor combination TR3. The third switch module S3 includes, for example, a fourth transistor or transistor combination TR4, a fifth transistor or transistor combination TR5, and a sixth transistor or transistor combination TR6. The transistor combination includes, for example, a P-type transistor and an N-type transistor.

[0054] The second switch S2, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are implemented by a transistor circuit, for example. Each switch or switch module is parameter-matched, for example, to reduce the influence of parasitic capacitance.

[0055] Figure 2 is a schematic composition diagram of a digital-to-analog conversion device according to an embodiment of the present application.

[0056] Refer to Figure 2 , the digital-to-analog conversion device 200 includes a digital-to-analog conversion circuit 100 and a controller 201. Figure 4 is an operation flowchart of the controller of a digital-to-analog conversion device according to an embodiment of the present application. Refer to Figure 4 , the controller 201 is configured to perform the following operations: Step 401, obtain the voltage value corresponding to the first voltage output terminal according to the multi-bit coding value corresponding to the input digital signal; Step 402, obtain the voltage value corresponding to the second voltage output terminal according to the multi-bit coding value corresponding to the input digital signal. Step 403, obtain the analog voltage output value of the digital-to-analog conversion circuit 100 based on the voltage value corresponding to the first voltage output terminal and the voltage value corresponding to the second voltage output terminal.

[0057] In some embodiments, referring to Figure 5 , according to the multi-bit coded value corresponding to the input digital signal S d , obtaining the voltage value corresponding to the first voltage output terminal includes: Step 501, performing a first-round reset on the first sampling capacitor C1 and the second sampling capacitor C2 through a first-stage switch switching operation; Step 502, sequentially reading the multi-bit coded value from the low bit to the high bit, and for each coded value, completing a first-stage charge redistribution process of the first sampling capacitor C1 and the second sampling capacitor C2 through a second-stage switch switching operation; Step 503, completing a second-stage charge redistribution process of the first sampling capacitor C1, the second sampling capacitor C2, and the third holding capacitor C3 through a third-stage switch switching operation, and obtaining the voltage value corresponding to the first voltage output terminal.

[0058] In some embodiments, referring to Figure 6 , according to the multi-bit coded value corresponding to the input digital signal S d , obtaining the voltage value corresponding to the second voltage output terminal includes: Step 601, performing a second-round reset on the first sampling capacitor C1 and the second sampling capacitor C2 through a fourth-stage switch switching operation; Step 602, sequentially reading the multi-bit coded value from the low bit to the high bit, and for each coded value, completing a third-stage charge redistribution process of the first sampling capacitor C1 and the second sampling capacitor C2 through a fifth-stage switch switching operation; Step 603; completing a fourth-stage charge redistribution process of the first sampling capacitor C1, the second sampling capacitor C2, and the fourth holding capacitor C4 through a sixth-stage switch switching operation, and acquiring the voltage value corresponding to the second voltage output terminal.

[0059] In some embodiments, obtaining the analog voltage output value of the digital-to-analog conversion circuit 100 based on the voltage value corresponding to the first voltage output terminal and the voltage value corresponding to the second voltage output terminal includes: When the second switch S2 is closed, V iut = a1 * (V outp - V outn ), a1 = 2C sam / (2C sam + C hol ); When the second switch S2 is open, V out = a2 * (V outp - V outn ), a2 = C sam / (C sam + C hol ).

[0060] Wherein, V out is the analog voltage output value of the digital-to-analog conversion circuit 100, V outp is the voltage value corresponding to the first voltage output terminal, and V outn is the voltage value corresponding to the second voltage output terminal. Csam is the capacitance value of the first sampling capacitor C1 or the second sampling capacitor C2, C hol is the capacitance value of the third holding capacitor C3 or the fourth holding capacitor C4. The capacitance values of the first sampling capacitor and the second sampling capacitor are equal, and the capacitance values of the first holding capacitor and the second holding capacitor are equal.

[0061] In some other embodiments, obtaining the analog voltage output value of the digital-to-analog conversion circuit 100 based on the voltage value corresponding to the first voltage output terminal and the voltage value corresponding to the second voltage output terminal includes: when the second switch S2 is closed, V out =(2P - 1)*a1*(V outp - V outn ), a1 = 2C sam / (2C sam + C hol ); when the second switch S2 is open, V out =(2P - 1)*a2*(V outp - V outn ), a2 = C sam / (C sam + C hol ). Wherein, P is the voltage polarity adjustment code, and the value of P is 0 or 1.

[0062] In some embodiments, referring to Figure 7 , performing the first-round reset of the first sampling capacitor C1 and the second sampling capacitor C2 through the first-level switch switching operation includes: Step 701, closing the sixth switch S6, and connecting the second ends of the first sampling capacitor C1 and the second sampling capacitor C2 to the intermediate reference voltage V CM respectively through the first switch module S1 and the third switch module S3; Step 702, after the first time interval t1, disconnecting the sixth switch S6 and disconnecting the first switch module S1 and the third switch module S3. The first time interval t1 is, for example, in the order of microseconds (μs).

[0063] In some embodiments, referring to Figure 8 , for each coding value, completing the first-stage charge redistribution process of the first sampling capacitor C1 and the second sampling capacitor C2 through the second-level switch switching operation includes: Step 801, when the coding value corresponds to a high level, connecting the second end of the first sampling capacitor C1 to the first reference voltage V REFP through the first switch module S1; Step 802, when the coding value corresponds to a low level, connecting the second end of the first sampling capacitor C1 to the intermediate reference voltage V CM; Step 803, after the second time interval t2, disconnect the first switch module S1 and close the second switch S2; Step 804, after the third time interval t3, disconnect the second switch S2 to complete the first-stage charge redistribution process of the first sampling capacitor C1 and the second sampling capacitor C2.

[0064] In some embodiments, referring to Figure 9 , the second-stage charge redistribution process of the first sampling capacitor C1, the second sampling capacitor C2, and the third holding capacitor C3 is completed through a third-level switch switching operation, and obtaining the voltage value corresponding to the first voltage output terminal includes: Step 901, close the second switch S2 and the fourth switch S4; Step 902, after the fourth time interval t4, disconnect the second switch S2 and the fourth switch S4 to complete the second-stage charge redistribution process of the first sampling capacitor C1, the second sampling capacitor C2, and the third holding capacitor C3.

[0065] In some embodiments, referring to Figure 10 , the first sampling capacitor C1 and the second sampling capacitor C2 are reset for a second round through a fourth-level switch switching operation, including: Step 721, close the seventh switch S7, and connect the second ends of the first sampling capacitor C1 and the second sampling capacitor C2 to the intermediate reference voltage V through the first switch module S1 and the third switch module S3 respectively CM ; Step 722, after the fifth time interval t5, disconnect the seventh switch S7, and disconnect the first switch module S1 and the third switch module S3.

[0066] In some embodiments, referring to Figure 11 , for each coded value, the third-stage charge redistribution process of the first sampling capacitor C1 and the second sampling capacitor C2 is completed through a fifth-level switch switching operation, including: Step 821, when the coded value corresponds to a high level, connect the second end of the second sampling capacitor C2 to the second reference voltage V through the third switch module S3 REFN ; Step 822, when the coded value corresponds to a low level, connect the second end of the second sampling capacitor C2 to the intermediate reference voltage V CM ; Step 823, after the sixth time interval t6, disconnect the third switch module S3 and close the second switch S2; Step 824, after the seventh time interval t7, disconnect the second switch S2 to complete the third-stage charge redistribution process of the first sampling capacitor C1 and the second sampling capacitor C2.

[0067] In some embodiments, referring to Figure 12, the fourth-stage charge redistribution process of the first sampling capacitor C1, the second sampling capacitor C2, and the fourth holding capacitor C4 is completed through the sixth-stage switch switching operation, and the voltage value corresponding to the second voltage output terminal is acquired, including: Step 921, closing the second switch S2 and the fifth switch S5; Step 922, after the eighth time interval t8, disconnecting the second switch S2 and the fifth switch S5 to complete the fourth-stage charge redistribution process of the first sampling capacitor C1, the second sampling capacitor C2, and the fourth holding capacitor C4.

[0068] Figures 13 to 28 is a schematic diagram of the operation process of the digital-to-analog conversion device according to an embodiment of the present application. Refer to Figures 13 to 28 , for the digital signal S d when the corresponding multi-bit coding value is 101, Figures 13 to 20 shows the process of the first round of resetting, charge redistribution, etc. of the sampling capacitors (including the first sampling capacitor and the second sampling capacitor) to obtain the voltage value corresponding to the first voltage output terminal, that is, the process corresponding to the first-stage switch switching operation, the second-stage switch switching operation, and the third-stage switch switching operation. Among them, the charge redistribution process needs to be carried out once for each different coding value. Figures 21 to 28 then shows the process of the second round of resetting, charge redistribution, etc. of the sampling capacitors (including the first sampling capacitor and the second sampling capacitor) to obtain the voltage value corresponding to the second voltage output terminal, that is, the process corresponding to the fourth-stage switch switching operation, the fifth-stage switch switching operation, and the sixth-stage switch switching operation. Among them, the charge redistribution process needs to be carried out once for each different coding value. In Figures 13 to 28 the corresponding embodiment, the intermediate reference voltage V CM is taken as, for example, the average value of the first reference voltage VREFP and the second reference voltage V REFN . Figures 13 to 28 Adopting a simplified schematic diagram method, in which the controller 201 of the digital-to-analog conversion device 200 is not shown.

[0069] Figure 29 is a schematic diagram of the voltage waveforms at both ends of the sampling capacitor during the operation of the digital-to-analog conversion device according to an embodiment of the present application. Figure 29 For example, corresponding to the Figures 13 to 28 shown embodiment. Figure 29 In, the abscissa is time (t). Refer to Figure 29 , which shows a schematic diagram of the change process of the voltages VC1 and VC2 at both ends of the first sampling capacitor C1 and the second sampling capacitor C2 (corresponding to waveform 2901 and waveform 2902 respectively), and indicates the voltage value V outp (or V OUTP ) corresponding to the first voltage output terminal and the voltage value V outn (or V OUTN), and on this basis, the analog voltage output value V of the digital-to-analog conversion device is shown out (or V OUT ).

[0070] For the digital-to-analog conversion circuit and the digital-to-analog conversion device of the present application, the output voltage is output in a differential mode. At the same time, the errors caused by factors such as parasitic capacitance and device mismatch in the circuit are equally included in the common-mode part of the two differential voltages, thereby eliminating the errors caused by factors such as parasitic capacitance and device mismatch. The technical solution of the present application can control the manufacturing area of the digital-to-analog converter and facilitate the expansion of the application scenarios of the digital-to-analog converter.

[0071] The basic concepts have been described above. Obviously, for those skilled in the art, the above invention disclosure is only an example and does not constitute a limitation to the present application. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to the present application. Such modifications, improvements, and corrections are proposed in the present application, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of the present application.

[0072] At the same time, the present application uses specific terms to describe the embodiments of the present application. Such as "one embodiment", "an embodiment", and / or "some embodiments" mean a certain feature, structure, or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that the "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more at different positions in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the present application can be appropriately combined.

[0073] Some aspects of the present application can be executed entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. The above hardware or software can all be referred to as "data blocks", "modules", "engines", "units", "components", or "systems". The processor can be one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DAPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or combinations thereof. In addition, aspects of the present application may be embodied as a computer product located in one or more computer-readable media, which includes computer-readable program codes.

[0074] A computer-readable medium may include a propagated data signal that contains computer program code, for example, on a baseband or as part of a carrier wave. The propagated signal may take various forms, including electromagnetic, optical, and the like, or a suitable combination thereof. A computer-readable medium can be any computer-readable medium other than a computer-readable storage medium, which can be connected to an instruction execution system, apparatus, or device to effect communication, propagation, or transmission for use of a program. The program code located on the computer-readable medium can be propagated through any suitable medium, including radio, cable, fiber optic cable, radio frequency signal, or similar media, or any combination of the foregoing media.

[0075] Similarly, it should be noted that, for the sake of simplifying the presentation of the disclosure of the present application and thus facilitating the understanding of one or more embodiments of the invention, in the foregoing description of the embodiments of the present application, various features are sometimes grouped together in one embodiment, drawing, or description thereof. However, this method of disclosure does not imply that the features required by the subject matter of the present application are more than those recited in the claims. In fact, the features of the embodiments are fewer than all the features of the individual embodiments disclosed above.

[0076] Although the present application has been described with reference to the current specific embodiments, those of ordinary skill in the art in the technical field of the present application should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions can be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the scope of the spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A digital-to-analog conversion circuit, comprising: The first sampling capacitor, the second sampling capacitor, the third holding capacitor, the fourth holding capacitor, the first switch module, the third switch module, the second switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch; The first ends of the first sampling capacitor and the second sampling capacitor are grounded; a second switch is connected between the second ends of the first sampling capacitor and the second sampling capacitor; The second ends of the first sampling capacitor and the second sampling capacitor are also respectively connected to one of a first reference voltage, a second reference voltage, or an intermediate reference voltage through the first switch module and the third switch module; the intermediate reference voltage is obtained based on the first reference voltage and the second reference voltage; The first ends of the third holding capacitor and the fourth holding capacitor are grounded; a fourth switch is connected between the second end of the third holding capacitor and the second end of the first sampling capacitor; a fifth switch is connected between the second end of the fourth holding capacitor and the second end of the second sampling capacitor; The second ends of the third holding capacitor and the fourth holding capacitor are respectively connected to the intermediate reference voltage through the sixth switch and the seventh switch; Wherein, the second ends of the third holding capacitor and the fourth holding capacitor serve as the first voltage output terminal and the second voltage output terminal of the digital-to-analog conversion circuit respectively.

2. The digital-to-analog conversion circuit according to claim 1, wherein The obtaining of the intermediate reference voltage based on the first reference voltage and the second reference voltage includes: ； Among them, V CM is the intermediate reference voltage, V REFP is the first reference voltage, V REFN is the second reference voltage; k1 , k2 are rational numbers, and k1 , k2 ∈(0,1).

3. The digital-to-analog conversion circuit according to claim 1, wherein The first switch module and the third switch module include a plurality of transistors.

4. The digital-to-analog conversion circuit according to claim 1, wherein The second switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch are implemented through a transistor circuit.

5. A digital-to-analog conversion device, comprising the digital-to-analog conversion circuit according to any one of claims 1 to 4; and A controller; The controller is configured to perform the following operations: Obtain the voltage value corresponding to the first voltage output terminal according to the multi-bit coding value corresponding to the input digital signal; Obtain the voltage value corresponding to the second voltage output terminal according to the multi-bit coding value corresponding to the input digital signal; Obtain the analog voltage output value of the digital-to-analog conversion circuit based on the voltage value corresponding to the first voltage output terminal and the voltage value corresponding to the second voltage output terminal.

6. The digital-to-analog conversion device according to claim 5, wherein The obtaining of the voltage value corresponding to the first voltage output terminal according to the multi-bit coding value corresponding to the input digital signal includes: Perform the first round of resetting on the first sampling capacitor and the second sampling capacitor through the first-stage switch switching operation; Read the multi-bit coding value sequentially from the low bit to the high bit, and for each coding value, complete the first-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor through the second-stage switch switching operation; Complete the second-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor, and the third holding capacitor through the third-stage switch switching operation, and obtain the voltage value corresponding to the first voltage output terminal.

7. The digital-to-analog conversion device according to claim 5, wherein The obtaining of the voltage value corresponding to the second voltage output terminal according to the multi-bit coding value corresponding to the input digital signal includes: Perform the second round of resetting on the first sampling capacitor and the second sampling capacitor through the fourth-stage switch switching operation; Read the multi-bit coding value sequentially from the low bit to the high bit, and for each coding value, complete the third-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor through the fifth-stage switch switching operation; The fourth-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor, and the fourth holding capacitor is completed through the sixth-stage switch switching operation, and the voltage value corresponding to the second voltage output terminal is acquired.

8. The digital-to-analog conversion device according to claim 5, wherein Obtaining the analog voltage output value of the digital-to-analog conversion circuit based on the voltage value corresponding to the first voltage output terminal and the voltage value corresponding to the second voltage output terminal includes: When the second switch is closed, , ; When the second switch is turned off, , ; Among them, is the analog voltage output value of the digital-to-analog conversion circuit, is the voltage value corresponding to the first voltage output terminal, is the voltage value corresponding to the second voltage output terminal; is the capacitance value of the first sampling capacitor or the second sampling capacitor, is the capacitance value of the third holding capacitor or the fourth holding capacitor. The capacitance values of the first sampling capacitor and the second sampling capacitor are equal, and the capacitance values of the third holding capacitor and the fourth holding capacitor are equal.

9. The digital-to-analog conversion device according to claim 6, wherein Performing the first-round reset of the first sampling capacitor and the second sampling capacitor through the first-stage switch switching operation includes: Closing the sixth switch, and connecting the second ends of the first sampling capacitor and the second sampling capacitor to the intermediate reference voltage through the first switch module and the third switch module respectively; After a first time interval, disconnect the sixth switch, and disconnect the first switch module and the third switch module.

10. The digital-to-analog conversion device according to claim 6, characterized in that, For each coding value, completing the first-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor through the second-stage switch switching operation includes: When the coding value corresponds to a high level, connect the second end of the first sampling capacitor to the first reference voltage through the first switch module; When the coding value corresponds to a low level, connect the second end of the first sampling capacitor to the intermediate reference voltage through the first switch module; After a second time interval, disconnect the first switch module, and close the second switch; After a third time interval, disconnect the second switch to complete the first-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor.

11. The digital-to-analog conversion device according to claim 6, characterized in that, Completing the second-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor, and the third holding capacitor through the third-stage switch switching operation, and obtaining the voltage value corresponding to the first voltage output terminal includes: Closing the second switch and the fourth switch; After a fourth time interval, disconnect the second switch and the fourth switch to complete the second-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor, and the third holding capacitor.

12. The digital-to-analog conversion device according to claim 7, characterized in that, Performing the second-round reset of the first sampling capacitor and the second sampling capacitor through the fourth-stage switch switching operation includes: Closing the seventh switch, and connecting the second ends of the first sampling capacitor and the second sampling capacitor to the intermediate reference voltage through the first switch module and the third switch module respectively; After a fifth time interval, disconnect the seventh switch, and disconnect the first switch module and the third switch module.

13. The digital-to-analog conversion device according to claim 7, characterized in that, For each coding value, completing the third-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor through the fifth-stage switch switching operation includes: When the coding value corresponds to a high level, connect the second end of the second sampling capacitor to the second reference voltage through the third switch module; When the coding value corresponds to a low level, connect the second end of the second sampling capacitor to the intermediate reference voltage through the third switch module; After a sixth time interval, disconnect the third switch module, and close the second switch; After a seventh time interval, the second switch is turned off to complete the third-stage charge redistribution process of the first sampling capacitor and the second sampling capacitor.

14. The digital-to-analog conversion device according to claim 7, characterized in that, The fourth-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor, and the fourth holding capacitor is completed through the sixth-stage switch switching operation, and the voltage value corresponding to the second voltage output terminal is acquired, including: Close the second switch and the fifth switch; After an eighth time interval, the second switch and the fifth switch are turned off to complete the fourth-stage charge redistribution process of the first sampling capacitor, the second sampling capacitor, and the fourth holding capacitor.

15. The digital-to-analog conversion device according to claim 5, characterized in that, Obtaining the analog voltage output value of the digital-to-analog conversion circuit based on the voltage value corresponding to the first voltage output terminal and the voltage value corresponding to the second voltage output terminal includes: When the second switch is closed, , ; When the second switch is turned off, , ; Among them, is the analog voltage output value of the digital-to-analog conversion circuit, is the voltage value corresponding to the first voltage output terminal, is the voltage value corresponding to the second voltage output terminal; is the capacitance value of the first sampling capacitor or the second sampling capacitor, is the capacitance value of the third holding capacitor or the fourth holding capacitor. The capacitance values of the first sampling capacitor and the second sampling capacitor are equal, and the capacitance values of the third holding capacitor and the fourth holding capacitor are equal; P is the voltage polarity adjustment code, and the value of P is 0 or 1.

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