Regulation circuit, method and device for transmitting antenna envelope, transmitter

Abstract

The application relates to the technical field of transmitters, and discloses a kind of adjusting circuit for transmitting antenna envelope, including power tube configuration circuit and narrow pulse control circuit, wherein: power tube configuration circuit is configured to adjust the opening number of the power tube of transmitting antenna in the switching interval of the unmodulated transmission phase and the modulation phase of transmitter;Narrow pulse control circuit is configured to adjust the pulse width of transmitting antenna in the switching interval of the unmodulated transmission phase and the modulation phase of transmitter.In the switching interval of the unmodulated transmission phase and the modulation phase of transmitter, the opening number of the power tube of transmitting antenna is adjusted, which can greatly offset overshoot or undershoot, and the pulse width of transmitting antenna is adjusted, which can slightly fine-tune overshoot or undershoot, so that the modulation depth of the transmitting field envelope of transmitter remains consistent in each transmission phase, and the success rate of signal transmission of transmitter is improved.The application also discloses a kind of adjusting method and device for transmitting antenna envelope and transmitter.

Description

Technical Field

[0001] This application relates to the field of transmitter technology, such as to an adjustment circuit, method, and apparatus for transmitting antenna envelope, and a transmitter. Background Technology

[0002] A transmitter circuit is a device that transmits signals at a specific frequency. Its main task in signal transmission is to modulate a high-frequency carrier wave with a useful low-frequency signal, transforming it into an electromagnetic wave with a certain bandwidth at a specific center frequency, suitable for transmission through an antenna. In related technologies, differences in transmitter power, internal resistance, and antenna matching network matching can cause overshoot and undershoot issues in the antenna field envelope of the transmitted data.

[0003] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0004] Overshoot or undershoot issues in the transmitter's antenna field envelope can easily lead to a low success rate in transmitting signals.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides an adjustment circuit, method, apparatus, and transmitter for transmitting antenna envelope, to control overshoot or undershoot of the transmitter's antenna field envelope and improve the success rate of transmitter signal transmission.

[0008] In some embodiments, the adjustment circuit for the transmit antenna envelope includes a power transistor configuration circuit and a narrow pulse control circuit, wherein: the power transistor configuration circuit is configured to adjust the number of power transistors turned on in the transmit antenna during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, to perform a first envelope adjustment of the transmit antenna; the narrow pulse control circuit is configured to adjust the pulse width of the transmit antenna during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, to perform a second envelope adjustment of the transmit antenna; wherein the first envelope adjustment and the second envelope adjustment are performed sequentially.

[0009] In some embodiments, the method for adjusting the envelope of a transmitting antenna includes: adjusting the number of power transistors turned on in the transmitting antenna during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter to perform a first envelope adjustment of the transmitting antenna; and adjusting the pulse width of the transmitting antenna during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter to perform a second envelope adjustment of the transmitting antenna; wherein the first envelope adjustment and the second envelope adjustment are performed sequentially.

[0010] In some embodiments, the adjustment device for the transmit antenna envelope includes a processor and a memory storing program instructions, the processor being configured to execute the aforementioned adjustment method for the transmit antenna envelope when the program instructions are executed.

[0011] In some embodiments, the transmitter includes a transmitter body and the aforementioned adjustment circuit for the transmit antenna envelope, the adjustment circuit for the transmit antenna envelope being mounted on the transmitter body.

[0012] In some embodiments, the transmitter includes a transmitter body and the aforementioned adjustment device for the transmit antenna envelope, the adjustment device for the transmit antenna envelope being mounted on the transmitter body.

[0013] The adjustment circuit, method, apparatus, and transmitter for transmitting antenna envelope provided in this disclosure can achieve the following technical effects:

[0014] In this disclosed technical solution, the adjustment circuit for the transmit antenna envelope includes at least two parts: a power transistor configuration circuit and a narrow pulse control circuit. The power transistor configuration circuit adjusts the number of power transistors on the transmit antenna during the switching interval between the unmodulated and modulated transmission phases of the transmitter to perform the first envelope adjustment. The narrow pulse control circuit adjusts the pulse width of the transmit antenna during the switching interval between the unmodulated and modulated transmission phases of the transmitter to perform the second envelope adjustment. Thus, adjusting the number of power transistors on the transmit antenna during the switching interval between the unmodulated and modulated transmission phases can significantly offset overshoot or undershoot, while adjusting the pulse width of the transmit antenna can fine-tune overshoot or undershoot, ensuring that the transmit field envelope modulation depth remains consistent across all transmission phases, thereby improving the success rate of the transmitter signal transmission.

[0015] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0017] Figure 1A This is a schematic diagram of the envelope waveform of a TYPE A antenna provided in an embodiment of this disclosure;

[0018] Figure 1B This is a schematic diagram of the envelope waveform of a TYPE B antenna provided in an embodiment of this disclosure;

[0019] Figure 1C This is a schematic diagram of an overshoot and undershoot waveform generated on an antenna envelope according to an embodiment of this disclosure;

[0020] Figure 2A This is a schematic diagram of a scheme for eliminating antenna envelope overshoot and undershoot provided in an embodiment of this disclosure;

[0021] Figure 2B This is a schematic diagram of another antenna envelope overshoot elimination scheme provided in an embodiment of this disclosure;

[0022] Figure 2C This is a schematic diagram of another antenna envelope overshoot and undershoot elimination scheme provided in an embodiment of this disclosure;

[0023] Figure 3 This is a schematic diagram of a circuit for adjusting the envelope of a transmitting antenna provided in an embodiment of this disclosure;

[0024] Figure 4 This is a schematic diagram of another adjustment circuit for the transmitting antenna envelope provided in an embodiment of this disclosure;

[0025] Figure 5 This is a schematic diagram of a power transistor configuration circuit provided in an embodiment of this disclosure;

[0026] Figure 6 This is a schematic diagram of a power transistor configuration value provided in an embodiment of this disclosure;

[0027] Figure 7 This is a schematic diagram of a narrow pulse control circuit provided in an embodiment of this disclosure.

[0028] Figure 8A This is a schematic diagram of another narrow pulse control circuit provided in an embodiment of this disclosure;

[0029] Figure 8B This is a timing diagram illustrating the delay time of a narrow pulse control circuit provided in an embodiment of this disclosure;

[0030] Figure 9 This is a logic control schematic diagram of a narrow pulse control circuit provided in an embodiment of this disclosure;

[0031] Figure 10This is a schematic diagram of the structure of a driving clock control circuit provided in an embodiment of the present disclosure.

[0032] Figure 11 This is a schematic diagram of another driving clock control circuit provided in an embodiment of this disclosure;

[0033] Figure 12 This is a schematic diagram of the driving clock timing of a driving clock control circuit provided in an embodiment of this disclosure;

[0034] Figure 13 This is a schematic flowchart of a method for adjusting the envelope of a transmitting antenna provided in an embodiment of this disclosure;

[0035] Figure 14 This is a schematic flowchart of another method for adjusting the envelope of a transmitting antenna provided in an embodiment of this disclosure;

[0036] Figure 15 This is a schematic diagram of an adjustment scheme for the envelope of a transmitting antenna provided in an embodiment of this disclosure;

[0037] Figure 16 This is a schematic diagram of a scheme for driving clock duty cycle variation using a power transistor, provided in an embodiment of this disclosure;

[0038] Figure 17 This is a schematic diagram illustrating the effect of eliminating antenna envelope overshoot and undershoot provided in an embodiment of this disclosure;

[0039] Figure 18 This is a schematic diagram of a transmitter power adjustment device provided in an embodiment of the present disclosure;

[0040] Figure 19 This is a schematic diagram of the structure of a transmitter provided in an embodiment of this disclosure;

[0041] Figure 20 This is a schematic diagram of another transmitter provided in an embodiment of this disclosure. Detailed Implementation

[0042] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0043] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0044] Unless otherwise stated, the term "multiple" means two or more. In embodiments of this disclosure, the character " / " indicates that the preceding and following objects are in an "OR" relationship. For example, A / B means: A or B. The term "and / or" describes an association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B. The term "correspondence" can refer to an association or binding relationship; A corresponding to B means that there is an association or binding relationship between A and B.

[0045] In the field of Near Field Communication (NFC) technology, transmitters mainly operate in two modes: one is as a proximity coupling device (PCD) card transmitter emitting spatial field strength; the other is as a proximity card or object (PICC) transmitter emitting spatial field strength. This disclosure provides a method for adjusting the transmit antenna envelope. When the transmitter is in PCD or PICC mode actively emitting spatial field strength (e.g., during the communication process of an NFC device card transmitting the 14443 protocol), the overshoot or undershoot of the transmit antenna envelope is adjusted to ensure that the modulation depth of the transmit field envelope remains consistent across all transmission phases.

[0046] Combination Figure 1A and Figure 1B As shown, NFC devices, as card-to-device communication devices, follow the 14443 protocol and mainly transmit data in two types: TYPE A and TYPE B. Specifically, combining... Figure 1A As shown, the antenna envelope of a TYPE A type ideal transmission field is divided into two states: an unmodulated transmission field and a 100% modulated non-transmitting field; combined with Figure 1B As shown, the antenna envelope of a TYPE B type ideal transmission field is divided into an unmodulated transmission field and a field modulated according to a modulation depth of 9% to 14%.

[0047] In practice, NFC devices acting as PCD (Printed Circuit Disk Device) transmitters require a corresponding impedance-matched antenna network. However, in actual operation, combined with... Figure 1CAs shown, due to differences in transmitter power, internal resistance of the transmitter, and matching degree of the antenna matching network, overshoot (the peak or valley value of the envelope exceeds the set value) and undershoot (the peak or valley value of the envelope does not reach the set value) problems may occur in the antenna field envelope of the transmitted data.

[0048] According to the EMV protocol specification, there are strict constraints on the fall time and undershoot depth of the antenna envelope from the unmodulated stage to the modulated stage; similarly, there are strict constraints on the rise time and overshoot height of the antenna envelope from the modulated stage to the unmodulated stage. When the waveform of the transmitting antenna envelope does not meet the above constraints, it may result in failure to meet product specification levels and product compatibility requirements, or even direct communication failure.

[0049] In some specific applications, one solution to eliminate antenna envelope overshoot and undershoot is to combine... Figure 2A As shown, a square wave signal with a 50% duty cycle and two 13.56MHz carrier cycles is added after the switching edge between the unmodulated and modulated signals via digital control. Simultaneously, a square wave signal with a 50% duty cycle and two 13.56MHz carrier cycles is also added after the rising edge of the modulated and unmodulated signals. The power transistor value is configured as A during data DATA=1 and as B during data DATA=0. Because the configuration values ​​for the two carrier cycles for overshoot and undershoot elimination are fixed, and the positions for canceling overshoot and undershoot are fixed, the ability to eliminate overshoot and undershoot is limited.

[0050] In some specific applications, another approach to eliminating antenna envelope overshoot is to combine... Figure 2B As shown, overshoot can be eliminated by applying a pull-down control signal to the antenna matching network. The control logic signal is converted into a high-voltage control signal via an off-chip shifter (LOGIC CTRL+Levelshift). This high-voltage control signal controls the switching on and off of the high-voltage N-transistor, applying a pull-down current to the antenna and reducing the overshoot of the antenna field envelope. However, due to the on-chip and off-chip delays in the signal controlling the antenna pull-down, overshoot cannot be precisely controlled.

[0051] In some specific applications, another approach to eliminating antenna envelope overshoot is to combine... Figure 2C As shown, envelope detection is performed on the antenna's field envelope, and the real-time detected field envelope amplitude is compared with the transmitted field envelope amplitude during the reference unmodulated period. The comparison result is fed back to the power transistor control terminal. During the modulation phase, a feedback adjustment process is initiated. When overshoot occurs on the antenna envelope, it is suppressed through negative feedback adjustment; when undershoot occurs, the transmission capability is enhanced to compensate for the undershoot through the negative feedback adjustment process. However, the delay in the negative feedback loop prevents the elimination of overshoot and undershoot at precise moments.

[0052] The aforementioned schemes for eliminating antenna envelope overshoot exhibit a delayed cancellation effect during the process of canceling the antenna field envelope. That is, the cancellation process, which acts in the opposite direction, is initiated at the moment overshoot and undershoot occur, and the actual effect only becomes apparent several 13.56MHz carrier cycles later. This generally results in a slow response and an inability to cancel overshoot and undershoot at precise moments.

[0053] The adjustment circuit, method, apparatus, and transmitter for the transmit antenna envelope provided in this disclosure insert multiple (e.g., 16) carrier cycle transition intervals and multiple (e.g., two) pulse width controllable intervals between the unmodulated transmission phase and the modulation phase. Within both intervals, the number of power transistors turned on can be flexibly configured to cancel overshoot and undershoot. The 16 carrier cycles significantly cancel overshoot and undershoot, while the two narrow pulses can further fine-tune overshoot and undershoot, thereby more accurately canceling the overshoot and undershoot of the transmit antenna envelope.

[0054] This disclosure provides an adjustment circuit 100 for the envelope of a transmitting antenna, combined with... Figure 3 As shown, the adjustment circuit 100 for the transmit antenna envelope includes a power transistor configuration circuit 10 and a narrow pulse control circuit 20, wherein: the power transistor configuration circuit 10 is configured to adjust the number of power transistors turned on in the transmit antenna during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, so as to perform a first envelope adjustment of the transmit antenna; the narrow pulse control circuit 20 is configured to adjust the pulse width of the transmit antenna during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, so as to perform a second envelope adjustment of the transmit antenna; wherein the first envelope adjustment and the second envelope adjustment are performed sequentially.

[0055] The first envelope adjustment and the second envelope adjustment are performed sequentially. That is, the first envelope adjustment can be performed first, followed by the second envelope adjustment, or the second envelope adjustment can be performed first, followed by the first envelope adjustment.

[0056] Combination Figure 4As shown, in some embodiments, the power transistor configuration circuit 10 includes a P-type power transistor array 110, an N-type power transistor array 120, and a logic control sub-circuit 130, wherein: the P-type power transistor array 110 includes a plurality of P-type power transistors connected in series in sequence; the N-type power transistor array 120 is connected to the P-type power transistor array 110 and includes a plurality of N-type power transistors connected in series in sequence; the logic control sub-circuit 130 is connected to the P-type power transistor array 110 and the N-type power transistor array 120 respectively, and is configured to control a first predetermined number of P-type power transistors in the P-type power transistor array 110 to turn on, or control a second predetermined number of N-type power transistors in the N-type power transistor array 120 to turn on, or control the first predetermined number of P-type power transistors in the P-type power transistor array 110 to turn on and control the second predetermined number of N-type power transistors in the N-type power transistor array 120 to turn on.

[0057] In practical applications, the first set quantity and the second set quantity may be the same or different. The value range of the first set quantity is [1, 36], for example, 1, 10, 15, 18, 25, 36, and the value range of the second set quantity is [1, 36], for example, 1, 10, 15, 18, 25, 36. By adjusting the number of P-type power transistors and / or N-type power transistors turned on in the transmitting antenna, overshoot and undershoot can be significantly canceled more accurately.

[0058] In some possible implementations, the P-type power transistor array 110 includes: a plurality of P-type power transistor groups with different weight values ​​connected in series in sequence, each P-type power transistor group including one or more P-type power transistors.

[0059] Here, the weight values ​​of multiple P-type power transistor groups connected in series with different weight values ​​gradually decrease, for example, to 1 / 8, 1 / 4, and 1 / 2 respectively. This gradual decrease in the weight values ​​of the P-type power transistor groups, while achieving a large-scale adjustment of the transmit antenna envelope, further enables precise adjustment of the transmit antenna envelope.

[0060] Combination Figure 5 As shown, P1-P18 is the P-type power transistor array 110 for branch TX1, where P1, P2, and P3 are power transistors with weights of 1 / 8, 1 / 4, and 1 / 2 respectively, and P4-P18 are power transistors with a weight of 1. Power transistors P1, P2, and P3 each form a separate P-type power transistor group, and P4-P18 form another P-type power transistor group. Similarly, P19-P36 is the P-type power transistor array 110 for branch TX2, where P19, P20, and P21 are power transistors with weights of 1 / 8, 1 / 4, and 1 / 2 respectively, and P22-P36 are power transistors with a weight of 1. Power transistors P19, P20, and P21 each form a separate P-type power transistor group, and P22-P36 form another P-type power transistor group.

[0061] In some possible implementations, the N-type power transistor array 120 includes: a plurality of N-type power transistor groups with different weight values ​​connected in series in sequence, each N-type power transistor group including one or more N-type power transistors.

[0062] Here, the weight values ​​of multiple N-type power transistor groups connected in series with different weight values ​​gradually decrease, for example, to 1 / 8, 1 / 4, and 1 / 2 respectively. This gradual decrease in the weight values ​​of the N-type power transistor groups, while achieving a large-scale adjustment of the transmit antenna envelope, further enables precise adjustment of the transmit antenna envelope.

[0063] Combination Figure 5 As shown, N1-N18 is the N-type power transistor array 120 for branch TX1, where N1, N2, and N3 are power transistors with weights of 1 / 8, 1 / 4, and 1 / 2 respectively, and N4-N18 are power transistors with a weight of 1. Power transistors N1, N2, and N3 each form an N-type power transistor group, and N4-N18 form another N-type power transistor group. Similarly, N19-N36 is the N-type power transistor array 120 for branch TX2, where N19, N20, and N21 are power transistors with weights of 1 / 8, 1 / 4, and 1 / 2 respectively, and N22-N36 are power transistors with a weight of 1. Power transistors N19, N20, and N21 each form an N-type power transistor group, and N22-N36 form another N-type power transistor group.

[0064] By setting P-type and N-type power transistor arrays with different weight values, small-scale envelope adjustments are made using power transistor arrays with lower weights, while large-scale envelope adjustments are made using power transistor arrays with higher weights. For example, during the power transistor configuration process over 16 carrier cycles, power transistors with weights of 1 / 8, 1 / 4, and 1 / 2 are configured for fine-tuning of the transmit antenna envelope, while a power transistor with a weight of 1 is configured for large-scale adjustment of the transmit antenna envelope. The distribution of the power transistor array increases flexibility, allowing for adaptive cancellation based on the magnitude of overshoot and undershoot on the antenna envelope, thereby achieving precise cancellation of the transmit antenna envelope.

[0065] In practical applications, combined with Figure 6 As shown, the 16 power transistor values ​​of the logic control sub-circuit 130 (LOGIC_CTRL) are stored in registers. The logic control sub-circuit 130 identifies the falling or rising edge of the transmitted data DATA and outputs the value of each register (DPDN_SELOUT) sequentially according to the 13.56MHz carrier period. The values ​​of each register are pre-configured to compensate for overshoot and undershoot of the antenna envelope.

[0066] Combination Figure 4As shown, in some embodiments, the narrow pulse control circuit 20 includes a narrow pulse generating sub-circuit 210 and a narrow pulse control sub-circuit 220, wherein: the narrow pulse generating sub-circuit 210 is configured to generate an envelope overshoot compensated narrow pulse or an envelope undershoot compensated narrow pulse; the narrow pulse control sub-circuit 220 is connected to the narrow pulse generating sub-circuit 210 and is configured to control the narrow pulse generating sub-circuit 210 to output an envelope overshoot compensated narrow pulse according to a narrow pulse control signal, or to control the narrow pulse generating sub-circuit 210 to output an envelope undershoot compensated narrow pulse according to a narrow pulse control signal.

[0067] In some possible implementations, the narrow pulse control signal includes an overshoot narrow pulse control signal or an undershoot narrow pulse control signal. The narrow pulse control subcircuit 220 includes an overshoot narrow pulse control subcircuit and an undershoot narrow pulse control subcircuit, wherein: the overshoot narrow pulse control subcircuit, connected to the narrow pulse generation subcircuit 210, is configured to control the narrow pulse generation subcircuit 210 to output an envelope overshoot-compensated narrow pulse according to the overshoot narrow pulse control signal; the undershoot narrow pulse control subcircuit, connected to the narrow pulse generation subcircuit 210, is configured to control the narrow pulse generation subcircuit 210 to output an envelope undershoot-compensated narrow pulse according to the undershoot narrow pulse control signal.

[0068] The overshoot narrow pulse control subcircuit includes an overshoot delay subcircuit and an overshoot pulse width subcircuit. The overshoot delay subcircuit is connected to the narrow pulse generation subcircuit 210 and is configured to adjust the pulse width of the transmitting antenna according to the narrow pulse delay duration. The overshoot pulse width subcircuit is connected to the narrow pulse generation subcircuit 210 and is configured to adjust the pulse width of the transmitting antenna according to the narrow pulse width duration.

[0069] The underpinch narrow pulse control subcircuit includes an underpinch delay subcircuit and an underpinch pulse width subcircuit. The underpinch delay subcircuit is connected to the narrow pulse generation subcircuit 210 and is configured to adjust the pulse width of the transmitting antenna according to the narrow pulse delay duration. The underpinch pulse width subcircuit is connected to the narrow pulse generation subcircuit 210 and is configured to adjust the pulse width of the transmitting antenna according to the narrow pulse width duration.

[0070] Combination Figure 7 As shown, DI_OS and PW_OS are overshoot narrow pulse control subcircuits, generating overshoot narrow pulse control signals to control the narrow pulse generation subcircuit 210 to output envelope overshoot-compensated narrow pulses according to the overshoot narrow pulse control signals; DI_US and PW_US are undershoot narrow pulse control subcircuits, generating undershoot narrow pulse control signals to control the narrow pulse generation subcircuit 210 to output envelope undershoot-compensated narrow pulses according to the undershoot narrow pulse control signals. The overshoot narrow pulse control subcircuit and the undershoot narrow pulse control subcircuit control the narrow pulse generation subcircuit 210 to generate narrow pulse signals through combinational logic.

[0071] Specifically, in combination Figure 9 As shown, DI_OS and PW_OS are overshoot narrow pulse control sub-circuits, mainly operating on the rising edge of D. DI_OS is an overshoot delay sub-circuit, and PW_OS is an overshoot pulse width sub-circuit. DI_OS controls the durations of t_os_dl1 and t_os_dl2, while PW_OS controls the durations of t_us_pw1 and t_us_pw2, suppressing the energy transmitted on the antenna during t_us_pw1 and t_us_pw2, thus suppressing the overshoot waveform generated when DI switches from 0 to 1. t_os_dl1 and t_os_dl2 mainly control the delay time.

[0072] DI_US and PW_US are undershoot narrow pulse control sub-circuits, primarily operating on the falling edge of D. DI_US is an undershoot delay sub-circuit, and PW_US is an undershoot pulse width sub-circuit. DI_US controls the duration of t_us_dl1 and t_us_dl2, while PW_US primarily controls the duration of t_us_pw1 and t_us_pw2, compensating for the energy transmitted from the antenna during t_us_pw1 and t_us_pw2, and supplementing the undershoot waveform generated when DI switches from 1 to 0. The main control parameters for t_us_dl1 and t_us_dl2 are the delay times.

[0073] Therefore, the narrow pulse control circuit can accurately control the timing and magnitude of the energy beam, supplementing antenna energy where it is undershooting and suppressing antenna energy where it is overshooting.

[0074] In some possible implementations, the delay subcircuit 220 includes a charging circuit and a capacitor array, wherein: the charging circuit is configured to generate a charging current; the capacitor array is connected to the narrow pulse generating subcircuit 210 and the charging circuit, and is configured to charge according to the charging current to generate a narrow pulse control signal corresponding to the charging current.

[0075] The charging circuit includes a current mirror configured to generate a proportionally amplified charging current. The capacitor array includes multiple capacitors and a corresponding switch for each capacitor. The output capacitance value of the capacitor array is controlled by closing or opening the switches to generate a narrow pulse control signal corresponding to the capacitor connected to the capacitor array.

[0076] Combination Figure 8A As shown, taking the overshoot delay sub-circuit DI_OS as an example, the overshoot delay signal relies on the current to charge the capacitor array to generate a delay. The total capacitance value is configurable, and the corresponding delay time is also configurable.

[0077] In this configuration, transistors MP1 and MP2 form a current mirror, with a fixed current IBIAS charging the capacitor at the INV output node. Switches S1-S4 control the capacitor array. When all switches S1-S4 are closed, the capacitor connected to the INV1 output terminal has the largest capacitance, resulting in the longest delay between DO and DI. When all switches S1-S4 are open, the capacitor connected to the INV1 output terminal has the smallest capacitance, resulting in the shortest delay between DO and DI. By combining and controlling S1-S4, the delay time between DO and DI can be configured. Figure 8B This is a time-series diagram showing the relationship between DO and DI in generating DELAY times.

[0078] The function of transistor MP3 is to prevent the internal nodes of INV from exhibiting a high-impedance indeterminate state when IBIAS is in a state without current. By controlling the closing and closing of MP3 through OSPW_CTRL, MP3 can be forced to remain on when the overshoot delay sub-circuit is not working, thereby fixing the internal nodes of INV1 and preventing indeterminate states, thus preventing leakage of the overshoot delay sub-circuit.

[0079] Combination Figure 4 As shown, in some embodiments, the adjustment circuit 100 for the transmit antenna envelope further includes a drive clock control circuit 30, wherein the drive clock control circuit 30 is connected to the power transistor configuration circuit 10 and is configured to adjust the drive clock duty cycle of the power transistor of the transmit antenna during the switching interval between the unmodulated transmit phase and the modulated phase of the transmitter, so as to perform a third envelope adjustment of the transmit antenna.

[0080] In some possible implementations, the driving clock control circuit 30 includes a plurality of driving clock control sub-circuits (e.g., a first driving clock control sub-circuit 310, a second driving clock control sub-circuit 320, and a third driving clock control sub-circuit 330), wherein: the plurality of driving clock control sub-circuits form a plurality of driving clock control sub-circuit cross-delay chains; wherein each driving clock control sub-circuit in the driving clock control sub-circuit cross-delay chain is connected to one or more driving clock control sub-circuits.

[0081] Combination Figure 10As shown, multiple drive clock control sub-circuit cross-delay chains include cross-delay chains A1, A2, A3, and A4, and cross-delay chains B1, B2, B3, and B4. The drive clock control sub-circuit cross-delay chains utilize inverters to form a cross-chain structure. For example, the drive clock control sub-circuit in cross-delay chain A1 is connected to the drive clock control sub-circuit (inverter) within cross-delay chain A1 and the drive clock control sub-circuit (inverter) within cross-delay chain B4. The drive clock control sub-circuit in cross-delay chain A3 is connected to the drive clock control sub-circuit (inverter) within cross-delay chain A1 and the drive clock control sub-circuit (inverter) within cross-delay chain B3.

[0082] The driving clock control circuit 30 is configured as a cross-delay chain structure, which increases the flexibility of adjusting the driving clock duty cycle of the power transistor. It can adaptively cancel the overshoot and undershoot on the envelope of the transmitting antenna to achieve precise cancellation.

[0083] In some practical applications, combined Figure 11 The transmitter drive clock duty cycle control circuit shown uses CK1 to drive the P-type power transistor array 110 of TX1, CK1' to drive the N-type power transistor array 120 of TX1, CK2 to drive the P-type power transistor array 110 of TX2, and CK2' to drive the N-type power transistor array 120 of TX2. The timing diagrams of the drive clocks CK1, CK1', CK2, and CK2' are shown below. Figure 12 As shown, the drive clock duty cycle is 1 during the unmodulated transmission phase and 2 during the modulation phase. When the drive clock duty cycle is 1, the transmitter's transmit power is higher, which can compensate for undershoot in the transmit antenna envelope; when the drive clock duty cycle is 2, the transmitter's transmit power is lower, which can compensate for overshoot in the transmit antenna envelope. With a drive clock duty cycle of 2, the insertion dead time of P1 and N1 power transistors in TX1 increases. That is, in one 13.56MHz carrier cycle, the time during which both P and N transistors in TX1 are simultaneously off increases, while the time during which they alternately conduct decreases. The situation for branch TX2 is exactly the same as for branch TX1.

[0084] The adjustment circuit for the transmit antenna envelope provided in this embodiment includes at least two parts: a power transistor configuration circuit and a narrow pulse control circuit. The power transistor configuration circuit adjusts the number of power transistors on the transmit antenna during the switching interval between the unmodulated and modulated transmission phases of the transmitter to perform a first envelope adjustment. The narrow pulse control circuit adjusts the pulse width of the transmit antenna during the switching interval to perform a second envelope adjustment. Thus, adjusting the number of power transistors on the transmit antenna during the switching interval between the unmodulated and modulated transmission phases can significantly offset overshoot or undershoot, while adjusting the pulse width can fine-tune overshoot or undershoot, ensuring that the transmit field envelope modulation depth remains consistent across all transmission phases and improving the success rate of signal transmission.

[0085] In some embodiments, combined with Figure 13 As shown, a method for adjusting the envelope of a transmitting antenna is provided, comprising the following steps:

[0086] S1301, during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, adjust the number of power transistors turned on in the transmitting antenna to perform the first envelope adjustment of the transmitting antenna.

[0087] S1302, during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, adjust the pulse width of the transmitting antenna to perform a second envelope adjustment of the transmitting antenna.

[0088] The first envelope adjustment and the second inclusion adjustment are performed sequentially.

[0089] Here, the switching interval includes a first switching interval from the unregulated transmission stage to the modulation stage and a second switching interval from the modulation stage to the unregulated transmission stage.

[0090] In some possible implementations, the execution order of the first envelope adjustment and the second envelope adjustment is determined as follows: after the first envelope adjustment is performed in the first switching interval, the second envelope adjustment is performed; or, after the second envelope adjustment is performed in the first switching interval, the first envelope adjustment is performed.

[0091] In some possible implementations, the execution order of the first envelope adjustment and the second inclusion adjustment is determined as follows: in the second switching interval, after the first inclusion adjustment is executed, the second inclusion adjustment is executed.

[0092] Combination Figure 9As shown, the narrow pulse control circuit performs toggling processing on the data DATA. According to system requirements, the falling edge of DI corresponds to the completion of the 16-step carrier arbitrary configuration process, immediately followed by the narrow pulse processing; the two processes do not conflict. However, the rising edge of DI conflicts between the 16-step arbitrary configuration process and the narrow pulse processing, therefore, a... Figure 15 The DOPT_CTRL signal shielding narrow pulse processing process shown in the figure is completed. After the 16-step carrier arbitrary configuration process is completed, the DOPT_CTRL signal is released, and the unfinished narrow pulse processing process can continue.

[0093] Optionally, adjusting the pulse width of the transmitting antenna includes: obtaining the narrow pulse configuration duration of the transmitting antenna; wherein the narrow pulse configuration duration includes the narrow pulse delay duration and / or the narrow pulse width duration; and adjusting the pulse width of the transmitting antenna according to the narrow pulse configuration duration.

[0094] Here, the narrow pulse delay duration is the duration of the narrow pulse's delayed release, based on the switching edge between the unmodulated transmission phase and the modulation phase; the narrow pulse width duration is the duration of the narrow pulse during the release phase.

[0095] In practical applications, combined with Figure 9 As shown:

[0096] During the narrow pulse process, t_us_dl1 represents the delay duration of the first-stage narrow pulse at the falling edge, which can be configured, for example, from 0 to 2us; t_us_pw1 represents the width duration of the first-stage narrow pulse at the falling edge, which can be configured, for example, from 0 to 2us; t_us_dl2 represents the delay duration of the second-stage narrow pulse at the falling edge, which can be configured, for example, from 0 to 2us; t_us_pw2 represents the width duration of the second-stage narrow pulse at the falling edge, which can be configured, for example, from 0 to 2us.

[0097] During the narrow pulse process, t_os_dl1 represents the delay duration of the first-stage narrow pulse at the rising edge, which can be configured, for example, from 0 to 2µs; t_os_pw1 represents the width duration of the first-stage narrow pulse at the rising edge, which can be configured, for example, from 0 to 2µs; t_os_dl2 represents the delay duration of the second-stage narrow pulse at the rising edge, which can be configured, for example, from 0 to 2µs; t_os_pw2 represents the width duration of the second-stage narrow pulse at the rising edge, which can be configured, for example, from 0 to 2µs.

[0098] Adjusting the pulse width of the transmitting antenna according to the narrow pulse configuration duration allows for more precise narrow pulse configuration, thereby improving the accuracy of overshoot or undershoot resolution of the transmitting antenna envelope.

[0099] By using the method for adjusting the envelope of the transmitting antenna provided in this embodiment, the number of power transistors turned on in the transmitting antenna can be adjusted during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter. This can significantly offset overshoot or undershoot. Adjusting the pulse width of the transmitting antenna can finely adjust overshoot or undershoot, ensuring that the modulation depth of the transmitting field envelope of the transmitter remains consistent in each transmission phase, thereby improving the success rate of the transmitter signal transmission.

[0100] The method for adjusting the transmit antenna envelope provided in this disclosure can be executed by a controller. It is understood that the controller can implement the method for adjusting the transmit antenna envelope through a configured hardware adjustment circuit, or by executing corresponding computer program instructions.

[0101] In some embodiments, combined with Figure 14 As shown, a method for adjusting the envelope of a transmitting antenna is provided, comprising the following steps:

[0102] S1301, during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, adjust the number of power transistors turned on in the transmitting antenna to perform the first envelope adjustment of the transmitting antenna.

[0103] S1302, during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, adjust the pulse width of the transmitting antenna to perform a second envelope adjustment of the transmitting antenna.

[0104] S1403, during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, adjusts the duty cycle of the drive clock of the power transistor of the transmitting antenna to perform the third envelope adjustment of the transmitting antenna.

[0105] Optionally, adjusting the drive clock duty cycle of the power transistor of the transmitting antenna includes: obtaining a first drive clock duty cycle during the unmodulated transmission phase and a second drive clock duty cycle during the modulation phase; gradually adjusting the drive clock duty cycle of the power transistor from the first drive clock duty cycle to the second drive clock duty cycle during the switching interval, and / or gradually adjusting the drive clock duty cycle of the power transistor from the second drive clock duty cycle to the first drive clock duty cycle.

[0106] Here, the gradual adjustment can be a step-like gradual adjustment (for example, setting the drive clock duty cycle sequentially as: initial value DutycycleA, DutycycleA+0.2, DutycycleA+0.4, target value DutycycleB); or, the gradual adjustment can be a functional gradual adjustment conforming to a linear function, quadratic function, or other functional relationship. Gradually adjusting the drive clock duty cycle of the power transistor avoids excessive single-stage adjustment of the transmit antenna envelope, which could lead to excessive cancellation of the transmit antenna envelope.

[0107] Combination Figure 16 As shown, in some specific applications, the duty cycle of the driving clock of the power transistor of the transmitting antenna is configured in three nonlinear segments. The initial value DutycycleA gradually changes to the target value Dutycycle B and then stops changing. Correspondingly, the target value Dutycycle B gradually changes back to the initial value Dutycycle A and then stops changing.

[0108] Where delay_undershoot represents the PWM transition time of the falling edge of D, and delay_undershoot is divided into three intervals: delay1, delay2, and delay3, and delay_undershoot = delay1 + delay2 + delay3. N1, N2, and N3 represent the number of steps in the three transition intervals of the falling edge stage of D, and N1 + N2 + N3 = 32.

[0109] delay_overshoot represents the PWM transition time at the rising edge of D. delay_overshoot is divided into three intervals: delay4, delay5, and delay6. delay_overshoot = delay4 + delay5 + delay6. N5, N6, and N7 represent the number of steps in the three transition intervals during the rising edge phase of D. N4 + N5 + N6 = 32.

[0110] Tunit1 represents the duration of each step within the first interval delay1 of the falling edge phase of D, and satisfies delay1 = N1 * Tunit1; Tunit2 represents the duration of each step within the second interval delay2 of the falling edge phase of D, and satisfies delay2 = N2 * Tunit2; Tunit3 represents the duration of each step within the third interval delay3 of the falling edge phase of D, and satisfies delay3 = N3 * Tunit3.

[0111] Tunit4 represents the duration of each step within the first interval delay4 of the rising edge phase of D, and satisfies delay4 = N4 * Tunit4; Tunit5 represents the duration of each step within the second interval delay5 of the rising edge phase of D, and satisfies delay5 = N5 * Tunit5; Tunit6 represents the duration of each step within the third interval delay6 of the rising edge phase of D, and satisfies delay6 = N6 * Tunit6.

[0112] Step 1 represents the duty cycle of each step within the first interval delay 1 of the D falling edge phase; Step 2 represents the duty cycle of each step within the second interval delay 2 of the D falling edge phase; Step 3 represents the duty cycle of each step within the third interval delay 3 of the D falling edge phase.

[0113] Step 4 represents the duty cycle of each step within the first interval delay 4 of the rising edge phase of D; Step 5 represents the duty cycle of each step within the second interval delay 5 of the rising edge phase of D; Step 6 represents the duty cycle of each step within the third interval delay 6 of the rising edge phase of D.

[0114] Dutycycle A represents the stable value of the transmitter drive clock duty cycle during the unmodulated phase; Dutycycle B represents the stable value of the transmitter drive clock duty cycle during the modulation phase. The difference between Dutycycle A and Dutycycle B satisfies the following relationship:

[0115] Dutycycle A-Dutycycle B=N1*step1+N2*step2+N3*step3;

[0116] Dutycycle A-Dutycycle B=N4*step4+N5*step5+N6*step6.

[0117] In some practical applications, under certain combinations of conditions, N2+N3=0 and N5+N6=0. For example, N2=N3=0, or N2=8 and N3=-8; N5=N6=0, or N5=8 and N6=-8.

[0118] In some specific applications, a linear function can be y = a × N + DutycycleA, where y is the duty cycle of the Nth driving clock, a is the proportional coefficient, N is the number of gradual adjustments, DutycycleA is the initial value, and y = a × Nmax + DutycycleA = the target value DutycycleB.

[0119] In some specific applications, quadratic functions and other functional relationships satisfy the condition that the slope of the function gradually decreases. By gradually reducing the rate of change of the duty cycle of the power transistor's driving clock, the initial adjustment achieves a large adjustment of the transmit antenna envelope, while the later adjustment achieves a precise adjustment of the transmit antenna envelope.

[0120] The adjustment scheme for the transmitting antenna envelope provided in this embodiment of the disclosure, and the timing diagram of the transmission from the transmitter digital module to the analog transmitter are as follows: Figure 15 As shown.

[0121] The transmitter controls its state based on the DATA provided by the digital module. When DATA=1, the transmitter transmits a 13.56MHz field. When DATA=0, the transmitter is in the modulation stage. For TYPE A, the transmitter in the modulation stage does not transmit a field. For TYPE B, the transmitter in the modulation stage transmits a field with a modulation depth of 9% to 14%.

[0122] In this signal, D is the data sent by the digital module, and D' is the intermediate signal after processing D. The falling edge of the D' signal lags behind D by a delay of delay1, and the rising edge of the D' signal is synchronized with the rising edge of the D signal.

[0123] The analog transmitter controls itself according to D'. During the D'=1 phase, it transmits a 13.56MHz field. During the D'=0 phase, it is modulated. Simultaneously, automatic waveform control is activated at the falling edge of D. This means that during the 16 carrier cycles of delay 1 (13.56MHz), the number of P-power transistors and N-power transistors can be arbitrarily configured to achieve an appropriate transmit power value during delay 1 to compensate for overshoot and undershoot in the antenna waveform. Correspondingly, automatic waveform control is activated at the rising edge of D. This means that during the 16 carrier cycles of delay 2 (2), the number of P-power transistors and N-power transistors can be arbitrarily configured to achieve an appropriate transmit power value during delay 2 to compensate for overshoot and undershoot in the antenna waveform.

[0124] The number of PMOS represents the configuration change of the P-type power transistor throughout the data transmission process. At the initial moment when D=1, the configuration value of the P-type power transistor is fixed, representing the stable value in the unmodulated phase; during the delay1 transition, an appropriate value is configured to compensate for overshoot and undershoot of the antenna field envelope; during the period when D'=0, the configuration value of the P-type power transistor reaches a fixed value again, representing the stable value in the modulation phase; during the delay2 transition, an appropriate value is configured to compensate for overshoot and undershoot of the antenna field envelope; when returning to the moment when D=1 again, the configuration value of the P-type power transistor also returns to the fixed value during the unmodulated phase.

[0125] Similarly, the number of NMOS represents the configuration change of the N-type power transistor throughout the data transmission process. At the initial moment when D=1, the configuration value of the N-type power transistor is fixed, representing the stable value in the unmodulated phase; during the delay1 transition, an appropriate value is configured to compensate for overshoot and undershoot of the antenna field envelope; during the period when D'=0, the configuration value of the N-type power transistor reaches a fixed value again, representing the stable value in the modulation phase; during the delay2 transition, an appropriate value is configured to compensate for overshoot and undershoot of the antenna field envelope; when returning to the moment when D=1 again, the configuration value of the N-type power transistor also returns to the fixed value during the unmodulated period.

[0126] DOPT_INTER indicates that the narrow pulse generation module enables the narrow pulse function on the falling edge of D', generating a maximum of 2 consecutive square waves. The narrow pulse function is enabled again on the rising edge of D', and these two narrow pulses further cancel out overshoot and undershoot.

[0127] During the delay2 phase, which transitions from the modulation phase to the unmodulated transmission phase, the simultaneous operation of the power transistor arbitrary configuration function and the narrow pulse generation module would cause a conflict. Therefore, the DOPT_CTRL function selection signal is set to "1" during the delay2 phase. This ensures that during the switch from the unmodulated transmission phase to the modulation phase, the power transistor arbitrary configuration function and the narrow pulse generation function are performed sequentially. Conversely, during the switch from the modulation phase to the unmodulated phase, the power transistor arbitrary configuration function is prioritized, and the narrow pulse function can proceed immediately after 16 13.56MHz carrier cycles.

[0128] The method for adjusting the transmit antenna envelope provided in this embodiment of the invention, on the one hand, significantly eliminates overshoot and undershoot on the antenna envelope by using a power transistor in 16 carrier transition intervals and narrow pulse intervals; on the other hand, by combining the measure of segmented nonlinear variation of the duty cycle of the transmit power transistor driving clock, the overshoot and undershoot waveforms on the antenna field envelope are further optimized, which can more accurately cancel the overshoot or undershoot of the transmit antenna envelope and improve the success rate of data communication by the transmitter.

[0129] Using the adjustment circuit and method for transmitting antenna envelope provided in the embodiments of this disclosure, combined with Figure 17 As shown, Figure A represents the unprocessed transmit antenna envelope waveform, and Figure B represents the transmit antenna envelope waveform after overshoot and undershoot cancellation. Taking the transmitter sending TYPE B data as an example, there is a significant optimization effect on the undershoot waveform in the switching interval from the unmodulated stage to the modulation stage (first switching interval), and the overcharge waveform in the switching interval from the modulation stage to the unmodulated stage (second switching interval).

[0130] Combination Figure 18 As shown, this embodiment of the present disclosure provides an adjustment device 1800 for a transmitting antenna envelope, including a processor 180 and a memory 181, and may also include a communication interface 182 and a bus 183. The processor 180, communication interface 182, and memory 181 can communicate with each other via the bus 183. The communication interface 182 can be used for information transmission. The processor 180 can call logical instructions in the memory 181 to execute the adjustment method for the transmitting antenna envelope described in the above embodiment.

[0131] Furthermore, the logic instructions in the aforementioned memory 181 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0132] The memory 181, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 180 executes functional applications and data processing by running the program instructions / modules stored in the memory 181, that is, it implements the method for adjusting the transmitting antenna envelope in the above method embodiments.

[0133] The memory 181 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 181 may include high-speed random access memory and may also include non-volatile memory.

[0134] By using the adjustment device for the transmitting antenna envelope provided in this embodiment, the number of power transistors turned on in the transmitting antenna can be adjusted during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter. This can significantly offset overshoot or undershoot. Adjusting the pulse width of the transmitting antenna can finely adjust overshoot or undershoot, ensuring that the modulation depth of the transmitting field envelope of the transmitter remains consistent in each transmission phase, thereby improving the success rate of the transmitter signal transmission.

[0135] In some embodiments, combined with Figure 19 As shown, the transmitter includes a transmitter body 190 and the aforementioned adjustment circuit 100 for the transmit antenna envelope, the adjustment circuit for the transmit antenna envelope being mounted on the transmitter body 190.

[0136] In some embodiments, combined with Figure 20 As shown, the transmitter includes a transmitter body 190 and the aforementioned adjustment device 1800 for the transmit antenna envelope, the adjustment device for the transmit antenna envelope being mounted on the transmitter body 190.

[0137] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the above-described method for adjusting the envelope of a transmitting antenna.

[0138] This disclosure provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions that, when executed by a computer, cause the computer to perform the above-described method for adjusting the envelope of a transmitting antenna.

[0139] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0140] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0141] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. The scope of the embodiments of this disclosure includes the entire scope of the claims and all available equivalents of the claims. While the terms “first,” “second,” etc., may be used in this application to describe elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be called a second element without changing the meaning of the description, and similarly, a second element may be called a first element, provided that all occurrences of “first element” are consistently renamed and all occurrences of “second element” are consistently renamed. First and second elements are both elements, but may not be the same element. Moreover, the terminology used in this application is only for describing embodiments and is not intended to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. Similarly, the term “and / or” as used herein means including one or more of the associated listed elements and all possible combinations thereof. Additionally, when used herein, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase “comprising an…” does not exclude the presence of additional identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0142] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0143] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0144] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A circuit for adjusting the envelope of a transmitting antenna, characterized in that, include: The power transistor configuration circuit is configured to adjust the number of power transistors turned on in the transmitting antenna during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, so as to perform the first envelope adjustment of the transmitting antenna. A narrow pulse control circuit is configured to adjust the pulse width of the transmitting antenna during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, so as to perform a second envelope adjustment of the transmitting antenna. The first envelope adjustment and the second inclusion adjustment are performed sequentially.

2. The adjustment circuit according to claim 1, characterized in that, The power transistor configuration circuit includes: A P-type power transistor array, comprising multiple P-type power transistors connected in series in sequence; An N-type power transistor array, connected to a P-type power transistor array, includes multiple N-type power transistors connected in series in sequence; The logic control sub-circuit is connected to the P-type power transistor array and the N-type power transistor array respectively, and is configured to control a first set number of P-type power transistors in the P-type power transistor array to turn on, and / or control a second set number of N-type power transistors in the N-type power transistor array to turn on.

3. The adjustment circuit according to claim 2, characterized in that, P-type power transistor arrays include: Multiple P-type power transistor groups with different weight values ​​are connected in series in sequence, and each P-type power transistor group includes one or more P-type power transistors; And / or, N-type power transistor arrays include: Multiple N-type power transistor groups with different weight values ​​are connected in series in sequence. Each N-type power transistor group includes one or more N-type power transistors.

4. The adjustment circuit according to claim 1, characterized in that, The narrow pulse control circuit includes: The narrow pulse generator sub-circuit is configured to generate envelope overshoot compensated narrow pulses or envelope undershoot compensated narrow pulses; The narrow pulse control sub-circuit, connected to the narrow pulse generation sub-circuit, is configured to control the narrow pulse generation sub-circuit to output an envelope overshoot-compensated narrow pulse according to the narrow pulse control signal, or to control the narrow pulse generation sub-circuit to output an envelope undershoot-compensated narrow pulse according to the narrow pulse control signal.

5. The adjustment circuit according to claim 4, characterized in that, Narrow pulse control signals include overshoot narrow pulse control signals or undershoot narrow pulse control signals; the narrow pulse control sub-circuit includes: An overshoot narrow pulse control subcircuit, connected to a narrow pulse generation subcircuit, is configured to control the narrow pulse generation subcircuit to output an envelope overshoot-compensated narrow pulse according to the overshoot narrow pulse control signal; and / or, The undershoot narrow pulse control sub-circuit, connected to the narrow pulse generation sub-circuit, is configured to control the narrow pulse generation sub-circuit to output an envelope undershoot-compensated narrow pulse according to the undershoot narrow pulse control signal.

6. The adjustment circuit according to claim 4, characterized in that, The narrow pulse control sub-circuit includes: The charging circuit is configured to generate a charging current. The capacitor array, connected to the narrow pulse generator sub-circuit and the charging circuit, is configured to charge according to the charging current to generate a narrow pulse control signal corresponding to the charging current.

7. The adjustment circuit according to any one of claims 1 to 6, characterized in that, Also includes: The drive clock control circuit, connected to the power transistor configuration circuit, is configured to adjust the drive clock duty cycle of the power transistor of the transmit antenna during the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, so as to perform the third envelope adjustment of the transmit antenna.

8. The adjustment circuit according to claim 7, characterized in that, The drive clock control circuit includes multiple drive clock control sub-circuits, among which: Multiple drive clock control sub-circuits form multiple drive clock control sub-circuit cross-delay chains; In this context, each drive clock control sub-circuit in the cross-delay chain of the drive clock control sub-circuit is connected to one or more drive clock control sub-circuits.

9. A method for adjusting the envelope of a transmitting antenna, characterized in that, include: During the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, the number of power transistors turned on in the transmitting antenna is adjusted to perform the first envelope adjustment of the transmitting antenna. During the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, the pulse width of the transmitting antenna is adjusted to perform a second envelope adjustment of the transmitting antenna; The first envelope adjustment and the second inclusion adjustment are performed sequentially.

10. The adjustment method according to claim 9, characterized in that, The switching interval includes a first switching interval from the unregulated transmission stage to the modulation stage and a second switching interval from the modulation stage to the unregulated transmission stage. The execution order of the first envelope adjustment and the second inclusion adjustment is determined as follows: In the first switching interval, after performing the first envelope adjustment, the second envelope adjustment is performed; or, in the first switching interval, after performing the second envelope adjustment, the first envelope adjustment is performed; and / or, In the second switching interval, after performing the first adjustment, the second adjustment is performed.

11. The adjustment method according to claim 9, characterized in that, Adjusting the pulse width of the transmitting antenna includes: Obtain the narrow pulse configuration duration for the transmitting antenna; wherein the narrow pulse configuration duration includes the narrow pulse delay duration and / or the narrow pulse width duration; Adjust the pulse width of the transmitting antenna according to the narrow pulse configuration duration.

12. The adjustment method according to claim 9, 10 or 11, characterized in that, Also includes: During the switching interval between the unmodulated transmission phase and the modulation phase of the transmitter, the duty cycle of the drive clock of the power transistor of the transmitting antenna is adjusted to perform the third envelope adjustment of the transmitting antenna.

13. The adjustment method according to claim 12, characterized in that, Adjusting the duty cycle of the drive clock for the power transistor of the transmitting antenna includes: Obtain the first drive clock duty cycle for the unmodulated transmission phase and the second drive clock duty cycle for the modulation phase; During the switching interval, the duty cycle of the power transistor's drive clock is gradually adjusted from the first drive clock duty cycle to the second drive clock duty cycle, and / or the duty cycle of the power transistor's drive clock is gradually adjusted from the second drive clock duty cycle to the first drive clock duty cycle.

14. A device for adjusting the envelope of a transmitting antenna, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to perform, when executing the program instructions, the method for adjusting the transmit antenna envelope as described in any one of claims 9 to 13.

15. A transmitter, characterized in that, include: Transmitter body; The adjustment circuit for the transmitting antenna envelope as described in any one of claims 1 to 8 is mounted on the transmitter body; or, The adjustment device for the transmitting antenna envelope as described in claim 14 is mounted on the transmitter body.

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