Ferroelectric memory array and method of making same, memory, electronic device

Abstract

The application provides a ferroelectric memory array and a preparation method thereof, a memory and an electronic device, and relates to the technical field of semiconductors, aiming to improve the uniformity and reliability of the performance of the memory. The ferroelectric memory array can be a two-dimensional structure or a three-dimensional structure, and comprises a plurality of memory cells arranged in an array, each memory cell comprising a ferroelectric capacitor and a transistor. The ferroelectric capacitor comprises a first electrode and a second electrode arranged oppositely, and a ferroelectric film arranged between the first electrode and the second electrode. The crystal phase of the ferroelectric film comprises a tetragonal phase, the ferroelectric film comprises a first layer and a second layer in contact, at least one of the first layer and the second layer comprises a ferroelectric material, and the lattice constant of the first layer is different from the lattice constant of the second layer. The ferroelectric memory array can be applied to a ferroelectric memory, a ferroelectric field effect transistor memory or a ferroelectric tunnel junction memory to realize reading and writing of data.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a ferroelectric memory array and its fabrication method, a memory, and an electronic device. Background Technology

[0002] Currently, ferroelectric random access memory (FeRAM) has attracted widespread attention in the field due to its high integration and low power consumption.

[0003] Typically, ferroelectric memories (FRAMs) have multiple memory cells, each including a ferroelectric capacitor. The ferroelectric capacitor comprises two opposing electrodes and a ferroelectric thin film disposed between the two electrodes; that is, the ferroelectric capacitor has a metal-ferroelectric-metal (MFM) structure. The ferroelectric thin film exhibits the ferroelectric effect. An electric field generated by the two electrodes is applied to the ferroelectric thin film, causing ferroelectric domains in the film to form polarized charges under the influence of the electric field. When the electric field reverses, the ferroelectric domains undergo directional flipping. The polarized charges formed by the ferroelectric domains before and after the field reversal have different energies. This binary stable state (positive and negative polarization states) causes the ferroelectric capacitor to charge and discharge, which can then be detected by an external sensing amplifier to determine whether the ferroelectric memory is in a "0" or "1" storage state.

[0004] However, ferroelectric thin films prepared using atomic layer deposition (ALD) exhibit a polycrystalline structure, where the crystalline phases and crystal orientations cannot be uniform. For example, ferroelectric thin films include orthorhombic phase (O-phase, also known as ferroelectric phase), tetragonal phase (T-phase, also known as antiferroelectric phase), and monoclinic phase (M-phase, also known as nonferroelectric phase). Only the orthorhombic phase exhibits good ferroelectric effect, which will affect the uniformity and reliability of ferroelectric memory performance. Summary of the Invention

[0005] This application provides a ferroelectric memory array and its fabrication method, as well as a memory and electronic device, aiming to improve the uniformity and reliability of memory performance.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] Firstly, a ferroelectric memory array is provided, which can be a two-dimensional structure or a three-dimensional structure. Furthermore, this ferroelectric memory array can be applied to ferroelectric memories, ferroelectric field-effect transistor memories, or ferroelectric tunnel junction memories to achieve data reading and writing.

[0008] The aforementioned ferroelectric memory array includes multiple memory cells arranged in an array. Each memory cell includes a ferroelectric capacitor and a transistor. The ferroelectric capacitor includes a first electrode and a second electrode disposed opposite to each other, and a ferroelectric film disposed between the first electrode and the second electrode. The ferroelectric film has a tetragonal crystal phase and includes a first layer and a second layer in phase contact. At least one of the first layer and the second layer includes a ferroelectric material, and the lattice constants of the first layer and the second layer are different.

[0009] In the ferroelectric capacitor provided in the above embodiments of this application, the first layer and the second layer of the ferroelectric film are in contact. Since the lattice constants of the first layer and the second layer are different, lattice mismatch will occur between them, resulting in stress between the first layer and the second layer. This stress acts on the tetragonal crystal, causing lattice distortion in the tetragonal crystal and forming a "strained tetragonal phase".

[0010] Compared to the intrinsic tetragonal phase, which has no lattice distortion, the strained tetragonal phase has a larger remanent polarization intensity, which can improve the distinction between the positive and negative polarization states of the ferroelectric film, increase the storage window of the ferroelectric memory, and improve the accuracy of reading and writing data in the ferroelectric memory.

[0011] Furthermore, compared to the orthorhombic phase, the lowest potential barrier for oxygen vacancy migration is larger in the strained tetragonal phase, making it difficult for oxygen vacancy to migrate. This can improve the polarization fatigue phenomenon of the ferroelectric film, reduce the probability of breakdown of the ferroelectric capacitor, and thus improve the service life and durability of the ferroelectric memory.

[0012] In addition, the strained tetragonal phase has good thermal stability, which can improve the thermal stability of ferroelectric capacitors, thereby improving the thermal stability of ferroelectric memory.

[0013] In some embodiments, the tetragonal phase cell in the ferroelectric film includes oxygen ions, which are offset relative to the center of symmetry of the cell.

[0014] In the above embodiments, the tetragonal phase undergoes lattice distortion to form a strained tetragonal phase. The oxygen ions in the unit cell of the strained tetragonal phase are offset relative to the center of symmetry of the unit cell, giving it a larger remanent polarization intensity. This can improve the distinction between the positive and negative polarization states of the ferroelectric film, increase the storage window of the ferroelectric memory, and improve the accuracy of reading and writing data in the ferroelectric memory.

[0015] In some embodiments, both the first layer and the second layer comprise ferroelectric materials, and both the first layer and the second layer comprise tetragonal phases, with the proportion of tetragonal phase in the first layer and the second layer ranging from 30% to 100%.

[0016] In the above embodiments, when both the first layer and the second layer include ferroelectric materials and the lattice constants of the first layer and the second layer are different, a lattice mismatch can be formed on the surface where the first layer and the second layer are in contact, causing stress to be generated between the first layer and the second layer. This stress acts on the tetragonal phase crystals in the first layer and the second layer, causing lattice distortion in the tetragonal phase crystals, thereby forming strained tetragonal phases in both the first layer and the second layer.

[0017] In some embodiments, the first layer comprises hafnium oxide, the second layer comprises zirconium oxide, and the lattice constant of hafnium oxide is different from that of zirconium oxide.

[0018] In some embodiments, both the first layer and the second layer include hafnium zirconium oxide. The proportion of hafnium atoms in the first layer is different from that in the second layer, and the proportion of zirconium atoms in the first layer is also different from that in the second layer, so that the lattice constant of the first layer is different from that of the second layer.

[0019] In some embodiments, multiple first layers and multiple second layers are alternately arranged.

[0020] In the above embodiments, since the lattice constants of the first layer and the second layer are different, by setting multiple first layers and multiple second layers alternately, the surfaces of multiple first layers and multiple second layers in contact can form lattice mismatches, thereby increasing the stress between the first layer and the second layer. When this stress is applied to the tetragonal crystal, it will cause lattice distortion in the tetragonal crystal, which is conducive to the formation of strained tetragonal phase.

[0021] In some embodiments, the first layer comprises a ferroelectric material, and the second layer comprises a non-ferroelectric material. The ferroelectric film comprises a plurality of first layers and at least one second layer, with the first and second layers alternately disposed, and the second layer not contacting the first electrode or the second electrode. The first layer comprises a tetragonal phase, with the tetragonal phase comprising 30% to 100% of the first layer.

[0022] In the above embodiments, when the first layer includes a ferroelectric material and the second layer includes a non-ferroelectric material, and the lattice constants of the first layer and the second layer are different, by setting the first layer and the second layer alternately, a lattice mismatch can be formed on the surface where the first layer and the second layer are in contact, so that stress is generated between the first layer and the second layer. This stress acts on the tetragonal phase crystal in the first layer, causing the tetragonal phase crystal to produce lattice distortion, thereby forming a strained tetragonal phase in the first layer.

[0023] Furthermore, since the second layer includes non-ferroelectric materials, by setting the second layer to not contact the first electrode and the second electrode, the first electrode or the second electrode can be prevented from contacting the non-ferroelectric materials, thus avoiding any negative impact on the performance of the ferroelectric memory.

[0024] In some embodiments, the first layer comprises hafnium zirconium oxide, and the second layer comprises a metal oxide.

[0025] In some embodiments, the second layer includes at least one of titanium oxide, lanthanum oxide, and magnesium oxide.

[0026] In some embodiments, the proportion of hafnium atoms in the ferroelectric film is less than the proportion of zirconium atoms, which is beneficial for the formation of a tetragonal phase in the ferroelectric film during the preparation process.

[0027] In some embodiments, the ratio of the number of hafnium atoms in the ferroelectric film to the sum of the number of hafnium atoms and zirconium atoms ranges from 0.1 to 0.45; the ratio of the number of zirconium atoms to the sum of the number of hafnium atoms and zirconium atoms ranges from 0.55 to 0.9%.

[0028] In some embodiments, the ratio of the number of oxygen atoms in the ferroelectric film to the sum of the number of hafnium atoms and zirconium atoms ranges from 1.3 to 1.9. By reducing the proportion of oxygen atoms in the ferroelectric film, the number of oxygen vacancies in the ferroelectric film can be increased, which is beneficial for the formation of a tetragonal phase in the ferroelectric film.

[0029] In some embodiments, the thickness of the ferroelectric film ranges from 4 nm to 8 nm.

[0030] In the above embodiments, the thickness of the ferroelectric film is relatively small. By reducing the thickness of the ferroelectric film, it is beneficial to generate a tetragonal phase in the ferroelectric film during the preparation process.

[0031] In some embodiments, the coefficient of thermal expansion of the first electrode is different from that of the second electrode.

[0032] In the above embodiments, the process of preparing the ferroelectric capacitor needs to be carried out in a high-temperature environment. Since the thermal expansion coefficients of the first electrode and the second electrode are different, the volume expansion rates of the first electrode and the second electrode are different, which causes stress to be generated between the first electrode and the second electrode. This stress acts on the tetragonal phase crystal of the ferroelectric film, causing lattice distortion of the tetragonal phase crystal and forming a strained tetragonal phase.

[0033] In some embodiments, the crystalline phase of the ferroelectric film also includes an orthorhombic phase, which can also generate residual polarization intensity, further improving the uniformity and reliability of the ferroelectric memory and increasing the memory window of the ferroelectric memory.

[0034] In some embodiments, both the first electrode and the second electrode are planar electrodes, and the first electrode, the first layer, the second layer, and the second electrode are stacked. That is, the ferroelectric capacitor has a two-dimensional planar structure, which is simple and easy to fabricate.

[0035] In some embodiments, the first electrode is a planar electrode, the second electrode is a columnar electrode, the second electrode penetrates through the first electrode, and the first layer and the second layer are disposed around the second electrode.

[0036] In the above embodiments, the ferroelectric capacitor adopts a three-dimensional vertical structure design, which can reduce its area occupied in the plane, thereby increasing the number of ferroelectric capacitors per unit area in the plane, so as to increase the number of storage units per unit area, which is beneficial to improving the storage density of the memory.

[0037] In some embodiments, both the first electrode and the second electrode are planar electrodes, and one of the first electrode and the second electrode is electrically connected to a transistor to form a memory cell. Alternatively, the first electrode is a planar electrode, the second electrode is a cylindrical electrode, and the second electrode is electrically connected to a transistor to form a memory cell.

[0038] Secondly, a method for fabricating a ferroelectric memory array is provided. This method includes sequentially forming a first electrode, a ferroelectric film, and a second electrode. The ferroelectric film comprises a first layer and a second layer, at least one of which comprises a ferroelectric material, and the lattice constants of the first layer and the second layer are different. And / or, the coefficients of thermal expansion of the first electrode and the second electrode are different. After forming the second electrode, the method further includes rapidly heat-treating the ferroelectric film to form a tetragonal phase.

[0039] The preparation method provided in the above embodiments of this application sequentially forms a first electrode, a ferroelectric film, and a second electrode. After the second electrode is formed, the ferroelectric film is subjected to rapid heat treatment to form a tetragonal phase in the ferroelectric film.

[0040] Furthermore, since the lattice constants of the first layer and the second layer are different, lattice mismatch will occur between them, resulting in stress between the first and second layers. This stress acts on the tetragonal crystal, causing lattice distortion and forming a strained tetragonal phase.

[0041] In some embodiments, the temperature range for rapid heat treatment is 450°C to 650°C.

[0042] Compared to related technologies that form orthorhombic phases through rapid heat treatment at higher temperatures, the above embodiments facilitate the formation of tetragonal phases in ferroelectric films by reducing the temperature of rapid heat treatment.

[0043] Thirdly, a memory is provided, which includes the ferroelectric memory array described in any of the above embodiments, and a controller electrically connected to the ferroelectric memory array.

[0044] Fourthly, an electronic device is provided, such as a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, or a communication electronics product. The electronic device includes a circuit board and the memory described in the above embodiments, the memory being disposed on the circuit board and electrically connected to the circuit board.

[0045] It is understood that the beneficial effects of the memory and electronic device provided by the above embodiments of this application can be referred to the beneficial effects of the ferroelectric memory array mentioned above, and will not be repeated here. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0047] Figure 1 This is an architectural diagram of an electronic device according to some embodiments;

[0048] Figure 2 An exploded view of an electronic device according to some embodiments;

[0049] Figure 3 This is an architectural diagram of a ferroelectric memory according to some embodiments;

[0050] Figure 4 A circuit diagram of a memory cell according to some embodiments;

[0051] Figure 5 This is a structural diagram of a ferroelectric capacitor in related technologies;

[0052] Figure 6 The electron energy loss spectrum of oxygen vacancy content in the ferroelectric film;

[0053] Figure 7 This is a structural diagram of a ferroelectric capacitor according to some embodiments;

[0054] Figure 8 This is a crystal structure diagram of the strained tetragonal phase in a ferroelectric film.

[0055] Figure 9Atomic coordinate diagrams of strained tetragonal and orthorhombic phase unit cells in ferroelectric films;

[0056] Figure 10 Atomic coordinate diagrams of oxygen ions in strained tetragonal and orthorhombic phase unit cells in ferroelectric films;

[0057] Figure 11 This is a graph of the hysteresis loop of the ferroelectric film.

[0058] Figure 12 The electron energy loss spectrum of oxygen vacancy content in the ferroelectric film;

[0059] Figure 13 A bar chart showing the lowest potential barrier for oxygen vacancy migration in orthorhombic, monoclinic, and strained tetragonal phases;

[0060] Figure 14 This is a structural diagram of another ferroelectric capacitor according to some embodiments;

[0061] Figure 15 This is a structural diagram of another ferroelectric capacitor according to some embodiments;

[0062] Figure 16 This is a structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0063] Figure 17 This is a structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0064] Figures 18A to 18D The diagram shows the steps involved in preparing a ferroelectric capacitor according to some embodiments;

[0065] Figure 19 This is a three-dimensional vertical structure diagram of a ferroelectric capacitor according to some embodiments;

[0066] Figures 20A to 20D The diagram shows the steps involved in preparing a ferroelectric capacitor according to some embodiments;

[0067] Figure 21 This is another three-dimensional vertical structure diagram of a ferroelectric capacitor according to some embodiments. Detailed Implementation

[0068] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0069] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to has a specific orientation, or is constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this application.

[0070] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0071] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0072] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments claimed herein are not necessarily limited to the content of this document.

[0073] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B, and C.

[0074] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0075] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0076] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0077] As used herein, “approximately” includes the values ​​stated and the average value within an acceptable range of deviation from the given values, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0078] In the context of this application, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0079] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0080] The technical terms used in some embodiments of this application are as follows:

[0081] Grains: Grains are small, irregularly shaped crystals that make up a polycrystalline material.

[0082] Crystal: A structure composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules.

[0083] Crystal lattice: The atoms inside a crystal are arranged according to certain geometric rules, and the spatial framework of this atomic arrangement is called a crystal lattice.

[0084] Unit cell: The most basic geometric unit that makes up a crystal. Its shape and size are the same as the parallelepiped unit of the space lattice, and it retains all the characteristics of the entire crystal lattice.

[0085] Ferroelectric materials are materials that can maintain spontaneous polarization by applying an electric field to align their internal electric dipole moments, even when the externally applied electric field is removed. In other words, ferroelectrics are materials in which the polarization intensity (polarization) value (or electric field) is semi-permanently retained, even after a constant voltage is applied and the voltage is restored to zero volts.

[0086] Some embodiments of this application provide an electronic device, which may be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatch, smart bracelet), virtual reality (VR) terminal device, augmented reality (AR) terminal device, rechargeable small household appliances (e.g., soymilk maker, robot vacuum cleaner), drone, radar, aerospace equipment, and vehicle-mounted equipment, etc.; the electronic device may also be a network device such as a base station. The embodiments of this application do not impose special limitations on the specific form of the electronic device.

[0087] Figure 1 This is an architectural diagram of an electronic device according to some embodiments.

[0088] like Figure 1 As shown, electronic device 1 includes components such as a storage device 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art will understand that... Figure 1 The architecture of the electronic device 1 shown does not constitute a limitation on the electronic device 1, which may include, for example... Figure 1 The components shown may have more or fewer components, or may be combined as follows: Figure 1 Some of the components shown, or those that can be used with, for example Figure 1 The component arrangements shown are different.

[0089] The storage device 11 is used to store software programs and modules. The storage device 11 mainly includes a program storage area and a data storage area. The program storage area stores and backs up the operating system and at least one application program required for a function (such as sound playback, image playback, etc.). The data storage area stores data created based on the use of the electronic device 1 (such as audio data, image data, phonebook, etc.). Furthermore, the storage device 11 includes an external storage device 111 and an internal storage device 112. Data stored in the external storage device 111 and the internal storage device 112 can be transferred between each other. The external storage device 111 may include, for example, a hard disk, a USB flash drive, or a floppy disk. The internal storage device 112 may include, for example, random access memory (RAM), read-only memory (ROM), etc., wherein the random access memory may include, for example, ferroelectric memory, phase-change memory, or magnetic memory.

[0090] Processor 12 is the control center of the electronic device 1. It connects various parts of the electronic device 1 via various interfaces and lines, and performs various functions and processes data by running or executing software programs and / or modules stored in storage device 11, and by calling data stored in storage device 11, thereby providing overall monitoring of the electronic device 1. Optionally, processor 12 may include one or more processing units. For example, processor 12 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. Different processing units can be independent devices or integrated into one or more processors. For example, processor 12 may integrate an application processor and a modem processor, where the application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into processor 12. The application processor may, for example, be a central processing unit (CPU). Figure 1 Taking processor 12 as an example (CPU), the CPU may include an arithmetic logic unit (ALU) 121 and a control unit 122. The ALU 121 retrieves data stored in the internal memory 112, processes the data stored in the internal memory 112, and the processed result is usually sent back to the internal memory 112. The control unit 122 can control the ALU 121 to process the data, and the control unit 122 can also control the external memory 111 and the internal memory 112 to read or write data.

[0091] Input device 13 is used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic device. For example, input device 13 may include a touchscreen and other input devices. A touchscreen, also known as a touch panel, can collect touch operations performed by the user on or near the touchscreen (e.g., operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touchscreen) and drive corresponding connected devices according to a pre-set program. The controller 122 in the processor 12 can also control the input device 13 to receive or not receive input signals. Furthermore, the input numeric or character information received by input device 13 and the generated key signal inputs related to user settings and function control of the electronic device can be stored in internal memory 112.

[0092] Output device 14 is used to output signals corresponding to the input data of input device 13 and stored in internal memory 112. For example, output device 14 outputs audio signals or video signals. The controller 122 in the processor 12 can also control output device 14 to output signals or not output signals.

[0093] It should be noted that, Figure 1 The thick arrows in the diagram are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, a single arrow between input device 13 and internal memory 112 indicates that data received by input device 13 is transmitted to internal memory 112. As another example, a double arrow between arithmetic unit 121 and internal memory 112 indicates that data stored in internal memory 112 can be transmitted to arithmetic unit 121, and data processed by arithmetic unit 121 can be transmitted to internal memory 112. Figure 1 The thin arrows in the diagram indicate components that the controller 122 can control. For example, the controller 122 can control external memory 111, internal memory 112, arithmetic unit 121, input device 13, and output device 14, etc.

[0094] To facilitate further explanation of the structure of electronic device 1, the following description uses a mobile phone as an example.

[0095] Figure 2 An exploded view of an electronic device according to some embodiments.

[0096] See Figure 2 The electronic device 1 may also include a mid-frame 15, a rear housing 16, and a display screen 17. The rear housing 16 and the display screen 17 are located on opposite sides of the mid-frame 15, and the mid-frame 15 and the display screen 17 are disposed within the rear housing 16. The mid-frame 15 includes a support plate 150 for supporting the display screen 17, and a frame 151 surrounding the support plate 150.

[0097] See also Figure 2 The electronic device 1 may also include a circuit board 18, which is disposed on the side of the carrier plate 150 near the rear cover 16. The internal memory 112 in the electronic device 1 may be disposed on the circuit board 18 and is electrically connected to the circuit board 18.

[0098] Currently, ferroelectric memories, as a novel type of memory, are widely used in internal memory due to their characteristics such as non-volatility of stored data, fast access speed, low read / write voltage, low power consumption, small device size, good cycle performance, and radiation resistance. The internal memory 112 involved in this application is not limited to ferroelectric memories; it can also be a ferroelectric field-effect transistor (FeFET) memory or a ferroelectric tunnel junction (FTJ) memory.

[0099] The following embodiments use the internal memory 112 as an example of a ferroelectric memory. Figure 3 This is an architectural diagram of a ferroelectric memory according to some embodiments.

[0100] See Figure 3 The internal memory 112 includes a ferroelectric memory array 210, a decoder 220, a driver 230, a controller (timing controller) 240, a register 250, and an input / output interface 260. The ferroelectric memory array 210 includes multiple memory cells 200 arranged in an array.

[0101] Figure 4 This is a circuit diagram of a memory cell according to some embodiments.

[0102] See Figure 4 The memory cell 200 includes a circuit architecture based on a ferroelectric capacitor. The memory cell 200 has a 1T1C (1-Transistor-1-Capacitor) structure, that is, the memory cell 200 includes a transistor T and a ferroelectric capacitor C. The source of the transistor T is electrically connected to the bit line (BL), the drain is electrically connected to one electrode of the ferroelectric capacitor C, the gate is electrically connected to the word line (WL), and the other electrode of the ferroelectric capacitor C is electrically connected to the plate line (PL). The circuit architecture of the memory cell 200 in the embodiments of this application is not limited to this.

[0103] Based on this, the decoder 220 can decode the received address to determine the memory cell 200 in the ferroelectric memory array 210 that needs to be accessed. The driver 230 generates a control signal based on the decoding result output by the decoder 220. This control signal is transmitted via word line WL to the gate of transistor T in memory cell 200 to control transistor T to turn on or off, thereby enabling access to the specified memory cell 200. The buffer 250 receives the data signal output from memory cell 200 via board line PL and buffers the data signal, for example, using a first-in-first-out (FIFO) buffering method. The timing controller 240 controls the timing of the buffer 250 and controls the driver 230 to drive the ferroelectric memory array 210. The input / output interface 260 is used to transmit data signals, such as receiving or sending data signals.

[0104] The aforementioned ferroelectric memory array 210, decoder 220, driver 230, timing controller 240, buffer 250 and input / output interface 260 can be integrated into one chip or into multiple chips respectively.

[0105] The working principle of ferroelectric memory will be introduced below in conjunction with the structure of ferroelectric capacitors.

[0106] Figure 5 This is a structural diagram of a ferroelectric capacitor in related technologies.

[0107] See Figure 5 The ferroelectric capacitor C' includes a first electrode 01' and a second electrode 02' disposed opposite to each other, and a ferroelectric film 03' disposed between the first electrode 01' and the second electrode 02'. The ferroelectric capacitor C' has an MFM structure. The ferroelectric film 03' comprises a ferroelectric material, which has spontaneous polarization characteristics.

[0108] Specifically, in a ferroelectric material, a crystal with an orthorhombic phase is subjected to an electric field when the first electrode 01' and the second electrode 02' receive a voltage signal and generate an electric field. The electric field is applied to the ferroelectric film 03', and the central atoms of the unit cell of the orthorhombic phase in the ferroelectric material move along the electric field and stop in a low-energy state, which can be, for example, a "0" storage state.

[0109] It should be noted that a large number of central atoms move and couple within the unit cell to form ferroelectric domains, which will generate polarization charges under the influence of an electric field.

[0110] When the electric fields generated by the first electrode 01' and the second electrode 02' are reversed, the central atom moves in the unit cell along the direction of the electric field and stops in another low-energy state, which can be, for example, a "1" storage state, that is, the ferroelectric domains are oriented and flipped under the action of the reversed electric field.

[0111] It should be noted that the polarization charge energy formed by the ferroelectric domains before and after the electric field reversal is different. This positive and negative polarization state will cause the ferroelectric capacitor C' to charge and discharge, which can be identified by the external sensing amplifier to determine whether the storage cell 200 is in the storage state of "0" or "1", thereby realizing the reading or writing of data by the ferroelectric memory.

[0112] Typically, the aforementioned ferroelectric film 03' is prepared using atomic layer deposition (ALD). Ferroelectric film 03' exhibits a polycrystalline structure, with inconsistent crystalline phases and orientations. For example, ferroelectric film 03' includes an orthorhombic phase (also called ferroelectric phase), a tetragonal phase (also called antiferroelectric phase), and a monoclinic phase (also called nonferroelectric phase). The orthorhombic phase exhibits ferroelectric properties, the tetragonal phase exhibits antiferroelectric properties, and the monoclinic phase exhibits dielectric properties. The orthorhombic phase content is relatively low, and the presence of the tetragonal and monoclinic phases affects the uniformity and reliability of the ferroelectric memory's performance.

[0113] Figure 6 The image shows the electron energy loss spectrum of oxygen vacancy content in the ferroelectric film 03', where... Figure 5 and Figure 6 The horizontal axis represents the detection distance of the ferroelectric film 03' along the first direction X, and the vertical axis represents the oxygen vacancy content at the corresponding position.

[0114] In the ferroelectric film 03', the oxygen vacancy content varies significantly among the orthorhombic, tetragonal, and monoclinic phases. The orthorhombic and tetragonal phases have higher oxygen vacancy contents, while the monoclinic phase has lower contents. Furthermore, the inventors of this application have experimentally discovered that each orthorhombic and tetragonal phase grain contains exactly one oxygen vacancy enrichment peak. Therefore, the type of phase and the number of grains can be determined based on the oxygen vacancy enrichment peak.

[0115] like Figure 6 As shown, each oxygen vacancy enrichment peak represents an orthorhombic phase. Within a detection distance of 270 nm, the ferroelectric film 03' has 3 grains, including 1 orthorhombic phase and 2 monoclinic phases. The monoclinic phase has a relatively large length ratio, indicating that the content of the orthorhombic phase in the ferroelectric film 03' is low, resulting in poor uniformity and reliability of the ferroelectric memory performance.

[0116] Furthermore, with the miniaturization of ferroelectric memories, the polycrystalline structure of the ferroelectric film 03' makes the threshold voltages for editing and erasing in ferroelectric memories close, resulting in a decrease in the distinction between editing and erasing, which in turn leads to a reduction in the memory window (MW).

[0117] Furthermore, as the electric field generated by the first electrode 01' and the second electrode 02' changes cyclically, oxygen vacancies in the ferroelectric film 03' will migrate. The oxygen vacancies migrate to the surface of the ferroelectric film 03' near the first electrode 01' or the second electrode 02', which reduces the content of oxygen vacancies inside the ferroelectric film 03'. Under this condition, the orthorhombic crystal in the ferroelectric film 03' will undergo a phase transition and transform into a monoclinic crystal.

[0118] In the ferroelectric film 03', the migration of oxygen vacancies causes pinning of the domain walls, resulting in polarization fatigue. Polarization fatigue refers to the phenomenon where the polarization intensity of ferroelectric domains decreases after multiple orientation flips. Specifically, during data reading and writing, ferroelectric memories perform numerous edit / erase operations. The ferroelectric domains in ferroelectric film 03' continuously flip, and after multiple cycles, the residual polarization intensity of the ferroelectric domains in ferroelectric film 03' decreases, the coercive field increases, and the "0" or "1" states become increasingly similar. This leads to a decrease in the distinguishability of the positive and negative polarization states of ferroelectric film 03', eventually making them difficult to distinguish. Consequently, the storage window of the ferroelectric memory shrinks, increasing the error rate of data reading and writing.

[0119] Furthermore, in the ferroelectric film 03', the concentration of oxygen vacancy migration gradually decreases from near the electrodes (first electrode 01' and second electrode 02') towards the interior. The gradual accumulation of oxygen vacancy will also form conductive filaments, which will increase the leakage current in the ferroelectric capacitor C', making it easy for the ferroelectric capacitor C' to break down, thereby reducing the service life and durability of the ferroelectric memory.

[0120] Therefore, how to improve the storage window of ferroelectric memories and enhance their performance uniformity, reliability, and durability has become an urgent problem to be solved in the field.

[0121] Some embodiments of this application provide a ferroelectric capacitor. Figure 7 This is a structural diagram of a ferroelectric capacitor according to some embodiments.

[0122] See Figure 7 The ferroelectric capacitor C includes a first electrode 01 and a second electrode 02 disposed opposite to each other, and a ferroelectric film 03 located between the first electrode 01 and the second electrode 02. The crystalline phase of the ferroelectric film 03 includes a tetragonal phase.

[0123] For example, the phase structure of the ferroelectric film O3 can be directly analyzed using an electron microscope to determine that the crystalline phase of the ferroelectric film O3 includes a tetragonal phase. Alternatively, X-ray diffraction (XRD) can be used to perform X-ray diffraction on the ferroelectric film O3, and by analyzing its diffraction pattern, it can be determined that the crystalline phase of the ferroelectric film O3 includes a tetragonal phase. Figure 7 In the ferroelectric capacitor C shown, the part of the ferroelectric film 03 located in the "solid line frame" is the tetragonal phase.

[0124] See also Figure 7 The ferroelectric film 03 includes a first layer 031 and a second layer 032 in contact with each other. At least one of the first layer 031 and the second layer 032 includes a ferroelectric material, and the lattice constant of the first layer 031 is different from that of the second layer 032.

[0125] In the ferroelectric capacitor C provided in the above embodiments of this application, the first layer 031 and the second layer 032 of the ferroelectric film 03 are in contact. Since the lattice constants of the first layer 031 and the second layer 032 are different, lattice mismatch will occur between them, resulting in stress between the first layer 031 and the second layer 032. This stress acts on the tetragonal crystal, causing lattice distortion in the tetragonal crystal and forming a "strained tetragonal phase". Figure 8 This is a crystal structure diagram of the strained tetragonal phase in ferroelectric film 03.

[0126] Figure 9 This is an atomic coordinate diagram of strained tetragonal and orthorhombic phase unit cells in ferroelectric film 03, where the "horizontal axis" represents the number of unit cells and the "vertical axis" represents the interplanar spacing of the unit cells. Figure 8 and Figure 9 It is evident that, compared to the intrinsic tetragonal phase with no lattice distortion, the interplanar spacing of the strained tetragonal phase in ferroelectric film 03 is increased, and the interplanar spacing of the strained tetragonal phase is smaller than that of the orthorhombic phase. This indicates that stress acting on the tetragonal phase unit cell causes lattice distortion, forming the strained tetragonal phase. It is understandable that, according to... Figure 9 The range of interplanar spacing in the unit cell can also be used to determine whether the ferroelectric film 03 contains strained tetragonal and orthorhombic phase units.

[0127] like Figure 8 As shown, the oxygen ions in the "strained tetragonal phase" are offset relative to the center of symmetry of the unit cell, giving it a larger remanent polarization intensity. This can improve the distinction between the positive and negative polarization states of the ferroelectric film O3, increase the storage window of the ferroelectric memory, and improve the accuracy of reading and writing data in the ferroelectric memory.

[0128] Figure 10 The atomic coordinate diagrams of oxygen ions in the strained tetragonal and orthorhombic phase units of ferroelectric film 03 are shown. The "horizontal axis" represents the number of units, and the "vertical axis" represents the distance of oxygen ion shift in the unit cell. It can be seen that oxygen ions are shifted in both the strained tetragonal and orthorhombic phase units, with the shift of oxygen ions in the strained tetragonal phase being approximately 30 pm.

[0129] Figure 11The graph shows the hysteresis loop of ferroelectric film O3, where the "x-axis" represents the voltage applied to ferroelectric film O3 and the "y-axis" represents the remanent polarization intensity of ferroelectric film O3. At a voltage of -1.36V, the remanent polarization intensity is -18.58 μC / cm. 2 At a voltage of 1.7V, the remanent polarization intensity is 18.48 μC / cm. 2 At a voltage of 0, the remanent polarization of the ferroelectric film O3 is approximately 37 μC / cm. 2 This indicates that the strained tetragonal phase has a large residual polarization intensity.

[0130] Compared to related technologies, the orthorhombic phase in the ferroelectric film generates residual polarization intensity, and the content of the orthorhombic phase in the ferroelectric film is relatively low. However, this application generates residual polarization intensity through strained tetragonal phase, and the content of strained tetragonal phase in the ferroelectric film 03 is relatively high, which can improve the uniformity and reliability of the ferroelectric memory using the ferroelectric capacitor C.

[0131] Figure 12 The electron energy loss spectrum of oxygen vacancy content in ferroelectric film O3 is shown. Each oxygen vacancy enrichment peak represents either an orthorhombic phase or a strained tetragonal phase. Within a detection distance of 270 nm, ferroelectric film O3 contains 7 grains, a relatively large number with small spacing and close packing. These 7 grains include 3 orthorhombic phases and 4 strained tetragonal phases. The strained tetragonal phase has a larger length proportion, indicating a high content of this phase in ferroelectric film O3, which can improve the uniformity and reliability of the ferroelectric memory. Furthermore, the orthorhombic phase content in ferroelectric film O3 is also high. The orthorhombic phase can also generate remanent polarization, further improving the uniformity and reliability of the ferroelectric memory.

[0132] Figure 13 The bar chart shows the lowest potential barriers for oxygen vacancy migration in the orthorhombic, monoclinic, and strained tetragonal phases. The lowest potential barrier for oxygen vacancy migration in the orthorhombic phase is 1.883 eV, in the monoclinic phase it is 1.768 eV, and in the strained tetragonal phase it is 2.424 eV.

[0133] It is evident that the lowest potential barrier for oxygen vacancy migration is the largest in the strained tetragonal phase, indicating that oxygen vacancy migration is not easy in the strained tetragonal phase. This can improve the polarization fatigue phenomenon of ferroelectric film O3 and reduce the probability of breakdown of ferroelectric capacitor C, thereby improving the service life and durability of ferroelectric memory.

[0134] For example, the ferroelectric capacitor C provided in the above embodiments of this application has an operating voltage of 3 MV / cm applied to the first electrode 01 and the second electrode 02. In this case, the electric field of the ferroelectric capacitor C can cycle 1×10 12 This indicates that the ferroelectric memory has a long service life and good durability.

[0135] In addition, the strained tetragonal phase has better thermal stability, which can improve the thermal stability of the ferroelectric capacitor C, thereby improving the thermal stability of the ferroelectric memory.

[0136] In some embodiments, such as Figure 7 As shown, both the first layer 031 and the second layer 032 of the ferroelectric film 03 comprise ferroelectric materials. In this case, the crystal phases of both the first layer 031 and the second layer 032 comprise tetragonal phases, and the proportion of tetragonal phase in the first layer 031 and the second layer 032 ranges from 30% to 100%. For example, the proportion of tetragonal phase in the first layer 031 and the second layer 032 is 30%, 50%, 65%, 80%, or 100%.

[0137] It is understandable that when both the first layer 031 and the second layer 032 contain ferroelectric materials, and the lattice constants of the first layer 031 and the second layer 032 are different, a lattice mismatch can be formed on the surface where the first layer 031 and the second layer 032 are in contact. This causes stress between the first layer 031 and the second layer 032. This stress acts on the tetragonal phase crystals in the first layer 031 and the second layer 032, causing lattice distortion in the tetragonal phase crystals. As a result, strained tetragonal phases are formed in both the first layer 031 and the second layer 032.

[0138] For example, the first layer 031 includes hafnium oxide, the second layer 032 includes zirconium oxide, and the lattice constant of hafnium oxide is different from that of zirconium oxide.

[0139] For example, both the first layer 031 and the second layer 032 include hafnium zirconium oxide (chemical formula: Hf). x Zr 1-x O y The proportion of hafnium atoms in the first layer 031 (abbreviated as HZO) is different from that in the second layer 032, and the proportion of zirconium atoms in the first layer 031 is also different from that in the second layer 032, so that the lattice constant of the first layer 031 is different from that of the second layer 032.

[0140] Figure 14 This is a structural diagram of another ferroelectric capacitor according to some embodiments.

[0141] See Figure 14 The ferroelectric film 03 includes multiple first layers 031 and multiple second layers 032. Both the first layers 031 and the second layers 032 include ferroelectric materials, and the crystal phases of both the first layers 031 and the second layers 032 include tetragonal phases. The multiple first layers 031 and the multiple second layers 032 are alternately arranged.

[0142] It is understandable that, since the lattice constants of the first layer 031 and the second layer 032 are different, by setting multiple first layers 031 and multiple second layers 032 alternately, the surfaces in contact with multiple first layers 031 and multiple second layers 032 can form lattice mismatches, thereby increasing the stress between the first layer 031 and the second layer 032. When this stress acts on the tetragonal crystal, it will cause lattice distortion in the tetragonal crystal, which is conducive to the formation of strained tetragonal phase.

[0143] Figure 15 This is a structural diagram of another ferroelectric capacitor according to some embodiments; Figure 16 This is a structural diagram of another ferroelectric capacitor according to some embodiments.

[0144] See Figure 15 The ferroelectric film 03 includes multiple first layers 031 and at least one second layer 032. The first layer 031 comprises a ferroelectric material, and the second layer 032 comprises a non-ferroelectric material. The crystal phase of the first layer 031 comprises a tetragonal phase, and the proportion of the tetragonal phase in the first layer 031 ranges from 30% to 100%. For example, the proportion of the tetragonal phase in the first layer 031 is 30%, 50%, 65%, 80%, or 100%.

[0145] See also Figure 15 The first layer 031 and the second layer 032 are alternately arranged, and the second layer 032 does not contact the first electrode 01 and the second electrode 02.

[0146] It is understandable that when the first layer 031 includes ferroelectric materials and the second layer 032 includes nonferroelectric materials, and the lattice constants of the first layer 031 and the second layer 032 are different, by setting the first layer 031 and the second layer 032 alternately, the surfaces of the first layer 031 and the second layer 032 in contact can form a lattice mismatch, which generates stress between the first layer 031 and the second layer 032. This stress acts on the tetragonal phase crystal in the first layer 031, causing the tetragonal phase crystal to produce lattice distortion, thereby forming a strained tetragonal phase in the first layer 031.

[0147] Furthermore, since the second layer 032 includes non-ferroelectric materials, by setting the second layer 032 to not contact the first electrode 01 and the second electrode 02, the first electrode 01 or the second electrode 02 can be prevented from contacting the non-ferroelectric materials, thus avoiding any negative impact on the performance of the ferroelectric memory.

[0148] For example, such as Figure 15 As shown, the ferroelectric film 03 includes two first layers 031 and one second layer 032. In other words, the second layer 032 is inserted between the two first layers 031, which can prevent the second layer 032 from contacting the first electrode 01 and the second electrode 02.

[0149] For example, such as Figure 16 As shown, the ferroelectric film 03 includes multiple first layers 031 and multiple second layers 032. That is, multiple second layers 032 are inserted between multiple first layers 031. By setting multiple first layers 031 and multiple second layers 032 alternately, the surfaces of multiple first layers 031 and multiple second layers 032 in contact can form lattice mismatch, thereby increasing the stress between the first layers 031 and the second layers 032, which is beneficial to the formation of strained tetragonal phase.

[0150] For example, the first layer 031 comprises hafnium zirconium oxide, and the second layer 032 comprises a metal oxide. For instance, the second layer 032 may comprise at least one of titanium oxide, lanthanum oxide, and magnesium oxide, that is, the second layer 032 may comprise one or more of titanium oxide, lanthanum oxide, and magnesium oxide.

[0151] In some embodiments, when the first layer 031 of the ferroelectric film 03 includes hafnium oxide and the second layer 032 includes zirconium oxide, or when both the first layer 031 and the second layer 032 include hafnium-zirconium oxide, or when the first layer 031 includes hafnium-zirconium oxide and the second layer 032 includes a non-ferroelectric material, the proportion of hafnium atoms in the ferroelectric film 03 is less than the proportion of zirconium atoms. This is beneficial for the formation of a tetragonal phase in the ferroelectric film 03 during the preparation of the ferroelectric film 03.

[0152] It is understandable that both the first layer 031 and the second layer 032 contain hafnium zirconium oxide (chemical formula: Hf). x Zr 1-x O y In the case of ), x < 1 - x.

[0153] For example, the ratio of the number of hafnium atoms in the ferroelectric film 03 to the sum of the number of hafnium atoms and zirconium atoms ranges from 0.1 to 0.45, i.e., 0.1 ≤ x ≤ 0.45. For instance, the ratio of the number of hafnium atoms to the sum of the number of hafnium atoms and zirconium atoms is 0.1, 0.2, 0.275, 0.3, or 0.45.

[0154] For example, the ratio of the number of zirconium atoms in the ferroelectric film 03 to the sum of the number of hafnium atoms and zirconium atoms ranges from 0.55 to 0.9, i.e., 0.55 ≤ 1 - x ≤ 0.9. For example, the ratio of the number of zirconium atoms to the sum of the number of hafnium atoms and zirconium atoms is 0.55, 0.6, 0.725, 0.8, or 0.9.

[0155] In some embodiments, when the first layer 031 of the ferroelectric film 03 includes hafnium oxide and the second layer 032 includes zirconium oxide, or when both the first layer 031 and the second layer 032 include hafnium-zirconium oxide, or when the first layer 031 includes hafnium-zirconium oxide and the second layer 032 includes a non-ferroelectric material, the ratio of the number of oxygen atoms in the ferroelectric film 03 to the sum of the number of hafnium atoms and zirconium atoms ranges from 1.3 to 1.9.

[0156] It is understandable that both the first layer 031 and the second layer 032 contain hafnium zirconium oxide (chemical formula: Hf). x Zr 1-x O y In the case of ), 1.3 ≤ y ≤ 1.9. For example, the ratio of the number of oxygen atoms to the sum of the number of hafnium atoms and zirconium atoms is 1.3, 1.5, 1.6, 1.8 or 1.9.

[0157] Compared to hafnium zirconium oxide (chemical formula: Hf) x Zr 1-x In the above embodiments of this application, by reducing the proportion of oxygen atoms in the ferroelectric film O3, the number of oxygen vacancies in the ferroelectric film O3 can be increased, which is beneficial to the generation of tetragonal phase in the ferroelectric film O3.

[0158] In some embodiments, the thickness of the ferroelectric film O3 ranges from 4 nm to 8 nm. For example, the thickness of the ferroelectric film O3 is 4 nm, 5 nm, 6 nm, 7 nm, or 8 nm.

[0159] In related technologies, the thickness of ferroelectric films is usually greater than 10 nm, while the thickness of ferroelectric film 03 in the above embodiments of this application is relatively small. By reducing the thickness of ferroelectric film 03, it is beneficial to generate a tetragonal phase in ferroelectric film 03 during the preparation of ferroelectric film 03.

[0160] Figure 17 This is a structural diagram of another ferroelectric capacitor according to some embodiments.

[0161] See Figure 17 The thermal expansion coefficients of the first electrode 01 and the second electrode 02 of the ferroelectric capacitor C are different. During the preparation of the ferroelectric capacitor C, it is necessary to carry out the process in a high-temperature environment. Since the thermal expansion coefficients of the first electrode 01 and the second electrode 02 are different, the volume expansion rates of the first electrode 01 and the second electrode 02 are different, which causes stress to be generated between the first electrode 01 and the second electrode 02. This stress acts on the tetragonal phase crystal of the ferroelectric film 03, causing lattice distortion of the tetragonal phase crystal and forming a strained tetragonal phase.

[0162] For example, the materials of the first electrode 01 and the second electrode 02 may include TiN, TaN, Ir, and IrO.x The material must be any two of the following: Ti, TiCN, TiSiN, WSiN, TiAlN, TaAlN, TiAlCN, W, Pt, Au, and Al, and the two materials must have different coefficients of thermal expansion.

[0163] For example, such as Figure 17 As shown, the material of the first electrode 01 includes W, and the material of the second electrode 02 includes TiN.

[0164] In some embodiments, the ferroelectric capacitor C may further include a third electrode 04, which may be located on the side of the second electrode 02 away from the ferroelectric film 03.

[0165] For example, the material of the third electrode 04 may be the same as the material of the first electrode 01.

[0166] For example, the material of the third electrode 04 may include any one of TiN, TaN, Ir, IrOx, Ti, TiCN, TiSiN, WSiN, TiAlN, TaAlN, TiAlCN, W, Pt, Au, and Al. For instance, the material of the third electrode 04 may include W.

[0167] The ferroelectric capacitor C provided in the embodiments of this application can have a two-dimensional planar structure, for example, see Figure 7 , Figures 14-17 The first electrode 01 and the second electrode 02 are both planar electrodes. The first electrode 01, the first layer 031, the second layer 032 and the second electrode 02 of the ferroelectric film 03 are stacked. The structure of this ferroelectric capacitor C is simple and easy to manufacture.

[0168] For example, the memory cell 200 includes a ferroelectric capacitor C and a transistor T. The first electrode 01 and the second electrode 02 of the ferroelectric capacitor C are both planar electrodes. In this case, one of the first electrode 01 and the second electrode 02 is electrically connected to the transistor T to form the memory cell 200.

[0169] Some embodiments of this application provide Figure 17 The method for preparing the ferroelectric capacitor C shown is as follows: Figures 18A to 18D The diagram shows the steps involved in preparing a ferroelectric capacitor according to some embodiments.

[0170] like Figure 18A As shown, the first electrode 01 is formed.

[0171] For example, the first electrode 01 can be formed using a physical vapor deposition (PVD) process.

[0172] like Figure 18B As shown, a ferroelectric film O3 is formed.

[0173] For example, an atomic layer deposition (ALD) process can be used to sequentially form a second layer 032 and a first layer 031 on the first electrode 01 to obtain a ferroelectric film 03. At least one of the first layer 031 and the second layer 032 comprises a ferroelectric material, and the lattice constant of the first layer 031 is different from that of the second layer 032.

[0174] like Figure 18C As shown, a second electrode 02 is formed, which is located on the side of the ferroelectric film 03 away from the first electrode 01.

[0175] For example, an atomic layer deposition process can be used to form the second electrode O2.

[0176] For example, such as Figure 18D As shown, after the second electrode 02 is formed, a third electrode 04 can also be formed on the side of the second electrode 02 away from the ferroelectric film 03.

[0177] For example, the third electrode 04 can be formed using a physical vapor deposition process.

[0178] After the second electrode O2 is formed, the ferroelectric film O3 is subjected to rapid thermal processing (RTP) to form a tetragonal phase.

[0179] The preparation method provided in the above embodiments of this application sequentially forms a first electrode 01, a ferroelectric film 03, and a second electrode 02. After forming the second electrode 02, the ferroelectric film 03 is subjected to rapid heat treatment to form a tetragonal phase in the ferroelectric film 03.

[0180] Furthermore, since the lattice constants of the first layer 031 and the second layer 032 are different, lattice mismatch will occur between them, resulting in stress between the first layer 031 and the second layer 032. This stress acts on the tetragonal crystal, causing lattice distortion in the tetragonal crystal and forming a strained tetragonal phase.

[0181] In some embodiments, the ferroelectric film 03 is subjected to rapid heat treatment at a temperature range of 450°C to 650°C, for example, at temperatures of 450°C, 500°C, 550°C, 600°C, or 650°C.

[0182] Compared to related technologies that form orthorhombic phases through rapid heat treatment at higher temperatures (greater than 700°C), the above embodiments of this application facilitate the formation of tetragonal phases in ferroelectric film O3 by reducing the temperature of rapid heat treatment.

[0183] The ferroelectric capacitor C provided in the embodiments of this application can also have a three-dimensional vertical structure. Figure 19 This is a three-dimensional vertical structure diagram of a ferroelectric capacitor according to some embodiments.

[0184] See Figure 19 The first electrode 01 of the ferroelectric capacitor C is a planar electrode, and the second electrode 02 is a columnar electrode. The second electrode 02 penetrates the first electrode 01. The first layer 031 and the second layer 032 of the ferroelectric film 03 are arranged around the second electrode 02 to separate the first electrode 01 from the second electrode 02.

[0185] The ferroelectric capacitor C adopts the above-mentioned three-dimensional vertical structure design, which can reduce its occupied area in the XY plane, thereby increasing the number of ferroelectric capacitors C per unit area in the XY plane, so as to increase the number of storage units 200 per unit area, which is beneficial to improving the storage density of the ferroelectric memory.

[0186] For example, the memory cell 200 includes a ferroelectric capacitor C and a transistor T. The first electrode 01 of the ferroelectric capacitor C is a planar electrode and the second electrode 02 is a columnar electrode. In this case, the second electrode 02 is electrically connected to the transistor T, that is, the columnar electrode of the ferroelectric capacitor C is electrically connected to the transistor T to form the memory cell 200.

[0187] Some embodiments of this application provide Figure 19 The method for preparing the ferroelectric capacitor C shown is as follows: Figures 20A to 20D The diagram shows the steps involved in preparing a ferroelectric capacitor according to some embodiments.

[0188] like Figure 20A As shown, a stacked layer is formed, which includes alternating first electrodes 01 (planar electrodes) and a dielectric layer 06. The dielectric layer 06 can separate two adjacent first electrodes 01 along the Z direction to insulate between adjacent first electrodes 01.

[0189] like Figure 20B As shown, a via H is formed that penetrates the stacked layer, and the via H penetrates the first electrode 01 and the dielectric layer 06 in the stacked layer.

[0190] like Figure 20C As shown, a second layer 032 and a first layer 031 of ferroelectric film 03 are formed on the sidewall of via H.

[0191] like Figure 20D As shown, a second electrode 02 is formed inside the ferroelectric film 03.

[0192] The above-described preparation method of this application forms a three-dimensional vertical ferroelectric capacitor C.

[0193] Figure 21This is another three-dimensional vertical structure diagram of a ferroelectric capacitor according to some embodiments.

[0194] See Figure 21 In a ferroelectric capacitor C, a trench H is formed within the first electrode 01. A second layer 032 of a ferroelectric film 03 is disposed on the inner wall of the trench H, and a first layer 031 is disposed inside the second layer 032. A second electrode 02 is disposed inside the second layer 032, and the second electrode 02 fills the trench H. A ferroelectric capacitor C with this structure is also called a trench capacitor.

[0195] The ferroelectric capacitor C adopts the above-mentioned three-dimensional vertical structure design, which can also reduce its occupied area in the XY plane, thereby increasing the number of ferroelectric capacitors C per unit area in the XY plane, so as to increase the number of storage units 200 per unit area, which is beneficial to improving the storage density of the ferroelectric memory.

[0196] The memory and electronic device provided in some embodiments of this application, including the ferroelectric capacitor C provided in any of the above embodiments, can achieve the same beneficial effects as the ferroelectric capacitor C described above, and will not be repeated here.

[0197] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A ferroelectric memory array, characterized in that, It includes multiple memory cells arranged in an array, each memory cell comprising a ferroelectric capacitor and a transistor; The ferroelectric capacitor includes: The first and second electrodes are positioned relative to each other; A ferroelectric film is disposed between the first electrode and the second electrode; The ferroelectric film comprises a tetragonal phase. The ferroelectric film includes a first layer and a second layer in contact, at least one of the first layer and the second layer includes a ferroelectric material, and the lattice constant of the first layer is different from that of the second layer. The first layer comprises a ferroelectric material, and the second layer comprises a non-ferroelectric material; the ferroelectric film comprises a plurality of the first layers and at least one second layer, the first layers and the second layers are alternately arranged, and the second layer does not contact the first electrode and the second electrode.

2. The ferroelectric memory array according to claim 1, characterized in that, The tetragonal phase cell in the ferroelectric film includes oxygen ions, which are offset relative to the center of symmetry of the cell.

3. The ferroelectric memory array according to claim 1, characterized in that, The first layer comprises hafnium oxide, and the second layer comprises zirconium oxide.

4. The ferroelectric memory array according to any one of claims 1 to 3, characterized in that, Multiple first-level and multiple second-level layers are set alternately.

5. The ferroelectric memory array according to claim 1 or 2, characterized in that, The first layer contains tetragonal phases, and the proportion of tetragonal phases in the first layer ranges from 30% to 100%.

6. The ferroelectric memory array according to claim 5, characterized in that, The first layer comprises hafnium zirconium oxide, and the second layer comprises metal oxide.

7. The ferroelectric memory array according to claim 6, characterized in that, The second layer includes at least one of titanium oxide, lanthanum oxide, and magnesium oxide.

8. The ferroelectric memory array according to any one of claims 3, 6, and 7, characterized in that, The proportion of hafnium atoms in the ferroelectric film is less than the proportion of zirconium atoms.

9. The ferroelectric memory array according to claim 8, characterized in that, The ratio of the number of hafnium atoms in the ferroelectric film to the sum of the number of hafnium atoms and zirconium atoms ranges from 0.1 to 0.

45. The ratio of the number of zirconium atoms to the sum of the number of hafnium atoms and zirconium atoms ranges from 0.55 to 0.

9.

10. The ferroelectric memory array according to claim 8 or 9, characterized in that, The ratio of the number of oxygen atoms in the ferroelectric film to the sum of the number of hafnium atoms and zirconium atoms ranges from 1.3 to 1.

9.

11. The ferroelectric memory array according to any one of claims 1 to 10, characterized in that, The thickness of the ferroelectric film ranges from 4 nm to 8 nm.

12. The ferroelectric memory array according to any one of claims 1 to 11, characterized in that, The coefficient of thermal expansion of the first electrode is different from that of the second electrode.

13. The ferroelectric memory array according to any one of claims 1 to 12, characterized in that, The ferroelectric film also includes an orthorhombic phase in its crystal phase.

14. The ferroelectric memory array according to any one of claims 1 to 13, characterized in that, Both the first electrode and the second electrode are planar electrodes, and the first electrode, the first layer, the second layer, and the second electrode are stacked.

15. The ferroelectric memory array according to any one of claims 1 to 13, characterized in that, The first electrode is a planar electrode, and the second electrode is a cylindrical electrode; The second electrode penetrates the first electrode, and the first layer and the second layer are arranged around the second electrode.

16. The ferroelectric memory array according to any one of claims 1 to 15, characterized in that, Both the first electrode and the second electrode are planar electrodes, and one of the first electrode and the second electrode is electrically connected to the transistor; or, The first electrode is a planar electrode, the second electrode is a cylindrical electrode, and the second electrode is electrically connected to the transistor.

17. A method for fabricating a ferroelectric memory array, characterized in that, include: A first electrode, a ferroelectric film, and a second electrode are sequentially formed; the ferroelectric film includes a first layer and a second layer, at least one of the first layer and the second layer includes a ferroelectric material, and the lattice constant of the first layer is different from the lattice constant of the second layer; and / or, the coefficient of thermal expansion of the first electrode is different from the coefficient of thermal expansion of the second electrode. After forming the second electrode, the process further includes: The ferroelectric film is subjected to rapid heat treatment to form a tetragonal phase; The first layer comprises a ferroelectric material, and the second layer comprises a non-ferroelectric material; the ferroelectric film comprises a plurality of the first layers and at least one second layer, the first layers and the second layers are alternately arranged, and the second layer does not contact the first electrode and the second electrode.

18. The preparation method according to claim 17, characterized in that, The rapid heat treatment temperature range is 450℃~650℃.

19. A memory, characterized in that, include: Ferroelectric memory array as described in any one of claims 1 to 16; The controller is electrically connected to the ferroelectric storage array.

20. An electronic device, characterized in that, include: Circuit board; The memory as claimed in claim 19, wherein the memory is disposed on the circuit board and electrically connected to the circuit board.

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