Branch prediction method and system, instruction fetch control module, processor and storage medium

Abstract

The present application provides a branch prediction method and system, an instruction fetch control module, a processor and a storage medium. The branch prediction method is applied to the instruction fetch control module in the branch prediction system. The system includes a branch predictor, the instruction fetch control module and an instruction fetch address queue. The method includes: when the instruction fetch address queue does not meet the preset queue clearing condition and does not meet the preset prediction suspension condition, the virtual address from the branch predictor is written into the instruction fetch address queue. The instruction fetch address queue is used to access the page table cache module and / or the instruction cache module so that the downstream processing module receives the cache instruction, thereby realizing the decoupling between the branch predictor and the page table cache module and / or the instruction cache module. The branch predictor can continue to work when the cache is missing, which increases the frequency of the branch predictor and optimizes the prediction bandwidth.

Description

Technical Field

[0001] The present application relates to the technical field of branch prediction and instruction extraction, and in particular to a branch prediction method, an instruction fetch control module, a branch prediction system, a processor, and a computer-readable storage medium. Background Art

[0002] In related technologies, the branch predictor is often coupled with the page table cache module and the instruction cache module. Any page table miss or instruction miss will block the branch predictor, which may not be unblocked until the page table or instruction returns, causing insufficient prediction bandwidth.

[0003] Based on this, the present application provides a branch prediction method, an instruction fetch control module, a branch prediction system, a processor and a computer-readable storage medium to improve related technologies. Summary of the invention

[0004] The purpose of the present application is to provide a branch prediction method, an instruction fetch control module, a branch prediction system, a processor and a computer-readable storage medium to achieve decoupling between a branch predictor and a page table cache module and / or an instruction cache module, so that the branch predictor can continue to work when the cache is missing, thereby optimizing the prediction bandwidth.

[0005] The purpose of this application is achieved by the following technical solutions:

[0006] In a first aspect, the present application provides a branch prediction method, which is applied to an instruction fetch control module in a branch prediction system, wherein the system includes a branch predictor, the instruction fetch control module and an instruction fetch address queue, and the method includes:

[0007] When the instruction fetch address queue does not satisfy the preset queue clearing condition and does not satisfy the preset prediction suspension condition, the virtual address from the branch predictor is written into the instruction fetch address queue, and the instruction fetch address queue is used to access the page table cache module and / or the instruction cache module so that the downstream processing module receives the cached instructions, thereby realizing the decoupling between the branch predictor and the page table cache module and / or the instruction cache module.

[0008] In a second aspect, the present application provides an instruction fetch control module, which is configured to execute any one of the above-mentioned branch prediction methods.

[0009] In a third aspect, the present application provides a branch prediction system, the system comprising a branch predictor, an instruction fetch control module and an instruction fetch address queue;

[0010] The branch predictor is used to provide a virtual address;

[0011] The instruction fetch control module is used to write the virtual address from the branch predictor into the instruction fetch address queue when the instruction fetch address queue does not meet the preset queue clearing condition and does not meet the preset prediction suspension condition. The instruction fetch address queue is used to access the page table cache module and / or the instruction cache module so that the downstream processing module receives the cached instructions, thereby realizing decoupling between the branch predictor and the page table cache module and / or the instruction cache module.

[0012] In a fourth aspect, the present application provides a computing device, wherein the computing device comprises any one of the branch prediction systems described above.

[0013] In a fifth aspect, the present application provides a processor, comprising any one of the above-mentioned branch prediction systems.

[0014] In a sixth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions of any one of the above-mentioned branch prediction methods.

[0015] The branch prediction method, instruction fetch control module, branch prediction system, processor and computer-readable storage medium provided by the present application are designed by decoupling the branch predictor from the page table cache module and / or the instruction cache module, separating the prediction pipeline from the page table cache pipeline and / or the instruction cache pipeline, breaking the constraints caused by the missing page table or the missing instruction. The branch predictor is connected to the page table cache module and / or the instruction cache module through the instruction fetch control module and the instruction fetch address queue. The branch predictor stores the predicted virtual address sequence in the instruction fetch address queue via the instruction fetch control module. The instruction fetch address queue performs page table cache access and instruction cache access. If the cache is missing, it will only block the page table cache pipeline or the instruction cache pipeline, while the prediction pipeline can continue to work without interference. In summary, the prediction pipeline is separated from the page table cache pipeline and / or the instruction cache pipeline by the instruction fetch control module and the instruction fetch address queue. The prediction pipeline can continue to work when the cache is missing, which increases the frequency of the branch predictor, thereby improving the performance benefits brought by the prediction bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present application is further described below in conjunction with the accompanying drawings and specific implementation methods.

[0017] Figure 1 It is a flowchart of a branch prediction method provided in an embodiment of the present application.

[0018] Figure 2 It is a flowchart of another branch prediction method provided in an embodiment of the present application.

[0019] Figure 3It is a structural block diagram of a branch prediction system, a page table cache module, an instruction cache module and a downstream processing module provided in an embodiment of the present application.

[0020] Figure 4 It is a structural block diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in this application to clearly and completely describe the technical solutions in the implementation mode of this application. Obviously, the described implementation mode is only a part of the implementation mode of this application, not all the implementation modes. Based on the implementation mode in this application, all other implementation modes obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0022] In the description of the embodiments of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0023] The result of the branch predictor will guide the subsequent instruction fetch operation. Usually, the virtual address obtained by the branch predictor needs to be translated and checked by the ITLB. The address translation is to access the physical memory, and the permission check is to ensure the legality of the address. Therefore, the branch predictor and ITLB / ICache are often coupled together. Any page table missing or instruction missing will block the branch predictor until the page table or instruction returns, causing insufficient prediction bandwidth. Among them, ITLB refers to the page table cache, and ICache refers to the instruction cache.

[0024] Specifically, the branch predictor generates a virtual address in the pipeline, and the predicted virtual address will be used to access the ITLB and ICache to obtain cache instructions. When the ITLB or ICache is missing, it is necessary to wait for data or page table information from the memory, and wait for the cache to be refilled. This process takes a certain amount of time, and it is difficult to immediately obtain the required physical address or instruction. Since the cache access is blocked by the ITLB or ICache missing, the branch prediction will also be suspended until the ITLB or ICache returns the required information, which makes it difficult for the branch predictor to continue to work normally during the blocking period, which may cause the pipeline to stall, and then cause the prediction performance of the system to deteriorate. The branch predictor generates a virtual address in the pipeline and accesses the ITLB or ICache, and the branch predictor relies on obtaining the correct address information to predict the execution direction of the branch instruction. When the ITLB or ICache is missing, the branch predictor is difficult to continue to predict the execution path of the next instruction. In short, the coupling between the branch predictor and the ITLB and ICache is realized through data flow. When the ITLB or ICache is missing, the cache access is blocked, which makes it difficult for the branch predictor to continue to predict, thus affecting the progress of the entire pipeline. In this case, it is necessary to wait for the ITLB and ICache misses to be processed before continuing to predict and execute instructions.

[0025] The present application provides a branch prediction method, an instruction fetch control module, a branch prediction system, a processor and a computer-readable storage medium to improve the relevant technology. The present application decouples ITLB / ICache and branch predictor to break the constraints caused by page table missing or instruction missing. Specifically, the present application connects the branch predictor and ITLB / ICache through the instruction fetch control module and the instruction fetch address queue (Fetch Virtual Address Queue, referred to as FVAQ). The branch predictor stores the predicted virtual address sequence in FVAQ via the instruction fetch control module. FVAQ performs ITLB access and ICache access. If the cache is missing, only the ITLB and ICache pipelines need to be blocked, while the prediction pipeline can continue to work without interference. In summary, the prediction pipeline and ITLB / ICache pipeline are separated by the instruction fetch control module and FVAQ. ​​The prediction pipeline can continue to work when the cache is missing until the FVAQ is filled by the branch predictor and then blocked. As a result, the frequency of branch predictor operation is increased, thereby improving the performance benefits brought by the prediction bandwidth.

[0026] It should be noted that, although the present application takes the branch prediction scenario as an example, the present application can be applied to other bandwidth prediction scenarios, and the present application is not limited to this.

[0027] See also Figure 1, Figure 1 It is a flowchart of a branch prediction method provided in an embodiment of the present application.

[0028] The embodiment of the present application provides a branch prediction method, which is applied to an instruction fetch control module in a branch prediction system. The system includes a branch predictor, the instruction fetch control module and an instruction fetch address queue. Figure 1 As shown, the method includes step S101.

[0029] Step S101: When the instruction fetch address queue does not satisfy a preset queue clearing condition and does not satisfy a preset prediction suspension condition, the virtual address from the branch predictor is written into the instruction fetch address queue, and the instruction fetch address queue is used to access the page table cache module and / or the instruction cache module so that the downstream processing module receives the cache instruction, thereby realizing decoupling between the branch predictor and the page table cache module and / or the instruction cache module.

[0030] A cache miss refers to a page table miss or an instruction miss. When there is no cache miss, the instruction fetch address queue first accesses the ITLB to obtain the physical address (PA) corresponding to the virtual address (VA), and then accesses the ICache to obtain the cache instruction corresponding to PA, and the instruction fetch can be completed. However, once there is a cache miss, the pipeline accessing the cache needs to stop until the required information is returned from the lower-level cache before it can continue to work. "Blocking" means suspending or preventing access to the missing cache.

[0031] The cache instruction received by the downstream processing module may be, for example, a cache line, wherein a cache line is an instruction block or a cache line, which is a unit of cache operation.

[0032] In the embodiment of the present application, in step S101, when the instruction fetch address queue does not meet the queue clearing condition and does not meet the prediction suspension condition, FVAQ is written normally. By writing the virtual address from the branch predictor into the instruction fetch address queue, the decoupling between the branch predictor and the page table cache module and / or the instruction cache module is achieved, and the prediction pipeline and the page table cache pipeline and / or the instruction cache pipeline are separated. In the instruction fetch process, when the instruction fetch address queue does not meet the queue clearing condition and does not meet the prediction suspension condition, the virtual address continues to be written into the queue, and there is no need to wait for the processing of page table missing and / or instruction missing, which can effectively reduce the situation of blocking the branch predictor and the prediction pipeline due to page table missing and / or instruction missing, and improve the working efficiency of the branch predictor. Reducing the blocking time of the prediction pipeline and improving the working efficiency are helpful to improve the performance of the entire system, and the improvement of instruction acquisition efficiency will help accelerate the execution of the program, thereby improving the overall performance of the computing system.

[0033] Among them, the working process of the prediction pipeline may include, for example: the branch predictor notifies the instruction fetch control module to receive the virtual address, and the instruction fetch control module writes the received virtual address into the instruction fetch address queue. The working process of the page table cache pipeline may include, for example: the instruction fetch address queue initiates access to the page table cache module and the corresponding virtual address, and the page table cache module feeds back the physical address corresponding to the virtual address to the instruction cache module. The working process of the instruction cache pipeline may include, for example: the instruction fetch address queue initiates access to the instruction cache module and the corresponding virtual address, and the instruction cache module feeds back the cached instruction of the physical address corresponding to the virtual address to the downstream processing module.

[0034] The embodiments of the present application do not limit the downstream processing module. The downstream processing module may include, but is not limited to, an instruction decoding unit, an instruction dispatching unit, an instruction issuing unit, an instruction execution unit, an instruction submitting unit, etc.

[0035] In some embodiments, continuing as Figure 1 As shown, the method may further include step S102: when the instruction fetch address queue does not satisfy the queue clearing condition but satisfies the prediction suspension condition, suspending the prediction pipeline.

[0036] In some embodiments, continuing as Figure 1 As shown, the method may further include step S103: when the instruction fetch address queue meets the queue clearing condition, executing a clearing operation for the instruction fetch address queue.

[0037] In step S103, if the FVAQ meets the queue clearing condition, the FVAQ is cleared. A clearing operation, i.e., flushing, is performed on the instruction fetch address queue. Generally, it occurs when there is a misprediction or context switch. The purpose of flushing is to clear the erroneous instructions that have entered the pipeline.

[0038] See also Figure 2 , Figure 2 It is a flowchart of another branch prediction method provided in an embodiment of the present application.

[0039] The embodiments of the present application do not limit the queue clearing conditions. In some embodiments, for example, Figure 2As shown, the process of determining whether the instruction fetch address queue satisfies the queue clearing condition may include: when the downstream processing module feeds back misprediction and / or context switching, confirming that the instruction fetch address queue satisfies the queue clearing condition; when the downstream processing module does not feed back misprediction or context switching and the downstream processing module feeds back page table permission exception, confirming that the instruction fetch address queue satisfies the queue clearing condition; when the downstream processing module does not feed back misprediction or context switching and the downstream processing module does not feed back page table permission exception, confirming that the instruction fetch address queue does not meet the queue clearing condition.

[0040] In some embodiments, the process of determining whether the page table permissions are abnormal may include: parsing the output information of the page table cache module to confirm whether there is a page table permission abnormality. The page table permissions are the attribute permissions of the page table, including the execution permissions of the page table, etc. Check whether the execution permissions of the page table where the current virtual address is located are allowed. If not allowed, it means that the virtual address and subsequent virtual addresses cannot be fetched normally and need to be cleared from the FVAQ.

[0041] As an example, when an application (user level) is running on an operating system (privileged level), a page table miss occurs, and a page table that only allows execution at the privileged level but not at the user level is obtained from the lower-level cache. At this time, the virtual address of the application does not have execution permission, and a permission exception report can be generated to the system. For example, the downstream processing module can feedback the page table permission exception corresponding to the virtual address of the application to the instruction fetch control module.

[0042] In summary, the feedback of misprediction and / or context switching by the downstream processing module means that the program flow has shifted, and the address flow predicted by the current instruction fetch address queue is all wrong and needs to be cleared. The feedback of page table permission exception by the downstream processing module means that the current exception level (for example, the application in the above embodiment) does not have address access rights and needs to obtain execution rights, that is, the program flow has shifted, and the address flow predicted by the current instruction fetch address queue is all wrong and needs to be cleared.

[0043] The embodiment of the present application does not limit the prediction suspension condition, for example, it can be a condition indicating that the instruction fetch address queue is about to be full. In some embodiments, the prediction suspension condition can include at least one of the following: the instruction fetch address queue feedback full flag; the distance between the write pointer and the read pointer of the instruction fetch address queue is not less than a preset value.

[0044] The embodiments of the present application do not limit the preset value, which may be, for example, the capacity of the instruction fetch address queue, or slightly less than the capacity of the instruction fetch address queue. In some embodiments, the predicted pause condition includes: the distance between the write pointer and the read pointer of the instruction fetch address queue is equal to the preset value, and the preset value is the capacity of the instruction fetch address queue.

[0045] As an example, the instruction fetch address queue can be maintained empty or full by the read-write pointer. Once the branch predictor completes the prediction, it will write the predicted target address (for example, virtual address) into an item of the instruction fetch address queue, so the write pointer will increase accordingly. ITLB / ICache reads an item of the instruction fetch address queue through the read pointer to obtain the virtual address VA of the instruction fetch, so the read pointer will increase accordingly. The distance between the write pointer and the read pointer is monitored in real time. When the difference between the two is equal to the number of items in the queue, it can be regarded as FVAQ is about to be full. When the instruction fetch address queue is about to be full, it means that if the prediction continues, the obtained address will have nowhere to be cached, so the prediction needs to be suspended. If the prediction suspension condition is not met, the prediction can continue, and the instruction fetch address queue can be written normally.

[0046] Continue as Figure 2 As shown, the embodiment of the present application provides a FVAQ usage process based on a decoupled structure.

[0047] The first step is to check whether there is a misprediction or context switch (hereinafter referred to as condition 1). If condition 1 is true, it means that the program flow has been transferred, and the address flow predicted by the current FVAQ is wrong and needs to be cleared; if condition 1 is not true, go to the second step.

[0048] The second step is to check whether there is a page table permission exception in the current instruction fetch process (hereinafter referred to as condition 2). If condition 2 is true, it means that the current exception level does not have address access rights and needs to obtain execution rights, that is, the program flow is transferred and the address flow predicted by the current FVAQ is incorrect and needs to be cleared; if condition 2 is not true, go to the third step.

[0049] The third step is to check whether FVAQ is about to be full (hereinafter referred to as condition 3). If condition 3 is met, it means that if the prediction continues, the obtained address will have nowhere to be cached, so the prediction needs to be suspended; if condition 3 is not met, the prediction continues and FVAQ is accessed normally.

[0050] In the first step, by clearing the FVAQ when the downstream processing module feedbacks misprediction or context switching, and in the second step, by clearing the FVAQ when the downstream processing module feedbacks page table permission exception, it can respond to unexpected situations more flexibly, ensuring that invalid address streams are cleared in time when program flow is transferred or page table permission exceptions occur, thereby improving the robustness and stability of the entire system. By checking whether the instruction fetch address queue meets the queue clearing condition and the prediction suspension condition, it can decide whether to perform a clearing operation or suspend the prediction pipeline according to the current situation, effectively manage system resources, reduce unnecessary resource waste, and improve resource utilization efficiency. When the FVAQ meets the queue clearing condition, the clearing operation is performed, and when the FVAQ does not meet the queue clearing condition but meets the prediction suspension condition, the prediction pipeline is suspended. The clearing operation can clear the invalid address stream in time, and the suspension operation can avoid continuing to predict addresses that cannot be cached, thereby improving the overall performance of the system.

[0051] In some embodiments, the method may further include: performing a training operation on the branch predictor when the downstream processing module feeds back a misprediction.

[0052] In some embodiments, performing a training operation on the branch predictor may include: after the branch execution unit in the downstream processing module compares the actual result of the branch instruction with the predicted result, performing a correction and update operation on the branch predictor. For example, if the branch execution unit finds that the direction prediction of a specific branch instruction is wrong, it will perform a direction correction operation on the branch predictor.

[0053] As an example, the downstream processing module is a collection of multiple functional modules, in which the branch execution unit is responsible for initiating the training of the branch predictor. Specifically, the downstream processing module feeds back the misprediction to the prediction control module, and the prediction control module initiates access to the prediction cache module. This is because the access of the prediction control module to the prediction cache module involves multiple sources and requires arbitration priority. For example, in the prediction pipeline, the prediction control module must use address A to access the prediction cache module so that the prediction control module receives the prediction information; at the same time, when the downstream processing module wants to train the branch predictor, the prediction control module uses address B to access the prediction cache module in order to perform operations such as correction and update of the branch predictor.

[0054] By performing training operations when the downstream processing module feeds back mispredictions, such as correcting and updating the branch predictor, prediction errors can be corrected in a timely manner, thereby improving the accuracy of branch predictions, helping to reduce the probability of mispredictions, and reducing system instability caused by mispredictions. The system can quickly correct mispredictions when they occur, thereby improving the robustness and stability of the system. Reducing mispredictions can avoid unnecessary branch transfers and FVAQ clearing operations, can more effectively predict the execution path of branch instructions, reduce unnecessary computational and storage overhead, and avoid unnecessary waste of resources, thereby improving the utilization efficiency of system resources and helping to improve overall performance.

[0055] In some embodiments, after taking out a virtual address from the instruction fetch address queue, the page table cache module and the instruction cache module are accessed simultaneously: in the case of a page table hit, the page table cache module feeds back the physical address corresponding to the virtual address to the instruction cache module, and in the case of a page table miss, the page table cache module feeds back the page table missing flag corresponding to the virtual address to the instruction fetch control module; in the case of an instruction hit, the instruction cache module feeds back the cached instruction corresponding to the physical address to the downstream processing module, and in the case of an instruction miss, the instruction cache module feeds back the instruction missing flag corresponding to the virtual address to the instruction fetch control module.

[0056] In some embodiments, the method may further include: after receiving a page table miss flag corresponding to a first virtual address from the page table cache module, performing a page table backfill operation for the page table cache module and corresponding to the first virtual address, so that the instruction fetch address queue re-executes the page table cache access for the page table cache module and corresponding to the first virtual address, thereby causing the page table cache module to feedback the first physical address corresponding to the first virtual address to the instruction cache module; after receiving an instruction miss flag corresponding to a second virtual address from the instruction cache module, performing an instruction backfill operation for the instruction cache module and corresponding to the second virtual address, so that the instruction fetch address queue re-executes the page table cache access for the page table cache module and corresponding to the second virtual address, and re-executes the instruction cache access for the instruction cache module and corresponding to the second virtual address, thereby causing the instruction cache module to output the cached instruction of the second physical address corresponding to the second virtual address to the downstream processing module.

[0057] Among them, the process of performing the page table backfill operation may, for example, include: receiving a page table corresponding to the first virtual address from the lower-level cache and backfilling it to the page table cache module. The process of performing the instruction backfill operation may, for example, include: receiving an instruction corresponding to the second virtual address from the lower-level cache and backfilling it to the instruction cache module. The instruction fetch address queue re-executes the page table cache access corresponding to the first virtual address for the page table cache module, which can be regarded as the instruction fetch address queue restarting the page table cache access to the page table cache module, so that the page table cache module feeds back the first physical address corresponding to the first virtual address to the instruction cache module. The instruction fetch address queue re-executes the page table cache access corresponding to the second virtual address for the page table cache module, which can be regarded as the instruction fetch address queue restarting the page table cache access to the page table cache module, so that the page table cache module feeds back the second physical address corresponding to the second virtual address to the instruction cache module. The instruction fetch address queue re-executes the instruction cache access to the instruction cache module and corresponding to the second virtual address, which can be regarded as the instruction fetch address queue restarting the instruction cache access to the instruction cache module, so that the instruction cache module outputs the cache instruction (for example, cache line) of the second physical address corresponding to the second virtual address to the downstream processing module.

[0058] By accessing the page table cache module and the instruction cache module, the physical address and instruction corresponding to the virtual address can be obtained, thereby improving data access efficiency. On the one hand, when the page table hits, the physical address is directly fed back to the instruction cache module, and when the instruction cache hits, the cache instruction is output to the downstream processing module. On the other hand, in the case of a page table miss or an instruction miss, these missing situations can be identified and processed in a timely manner. By performing page table backfill and instruction backfill operations, the missing page table and instruction data can be obtained from the lower-level cache and filled into the corresponding cache module for subsequent restart access, which helps to reduce the performance degradation caused by data missing. Since the page table miss and instruction miss can be processed, the fault tolerance of the system is improved. When a miss occurs, the required data can be obtained from the lower-level cache to ensure the normal execution of the program. By re-executing the access to the page table cache module and the instruction cache module, the instruction fetch process can be optimized to ensure that the correct instruction data is passed to the downstream processing module.

[0059] In some embodiments, the method may further include: when the instruction fetch address queue is empty, directly writing the virtual address or bypassing the delivery to the page table cache module and / or the instruction cache module.

[0060] Bypass delivery is to enable the bypass mechanism when the instruction fetch address queue is empty to deliver the virtual address required by the page table cache module and / or the instruction cache module.

[0061] That is to say, if the instruction fetch address queue is empty, there is no need to wait for the access of the instruction fetch address queue, and the virtual address obtained by the branch predictor is directly written or bypassed to deliver the page table cache module and / or the instruction cache module. The advantage of doing this is that the performance and efficiency of the system can be further improved. When the instruction fetch address queue is empty, the system may be in a relatively idle state. At this time, the system resources can be fully utilized to directly write the virtual address into or bypass the delivery page table cache module and / or the instruction cache module without waiting for the access of the instruction fetch address queue. Specifically, on the one hand, directly writing the virtual address into the cache or turning on the bypass mechanism for delivery speeds up the access speed, reduces the delay of data access, and makes the system respond more quickly. On the other hand, by processing the write operation of the virtual address in parallel when the queue is empty, the throughput of the system can be improved and the processing requirements can be met more quickly. On the other hand, making full use of the idle period of the system can more effectively utilize the system resources and improve the overall efficiency of the system.

[0062] The embodiment of the present application further provides an instruction fetch control module, which is configured to execute any one of the above-mentioned branch prediction methods.

[0063] See also Figure 3 , Figure 3 It is a structural block diagram of a branch prediction system, a page table cache module, an instruction cache module and a downstream processing module provided in an embodiment of the present application.

[0064] An embodiment of the present application further provides a branch prediction system, which includes a branch predictor, an instruction fetch control module, and an instruction fetch address queue.

[0065] The branch predictor is used to provide virtual addresses.

[0066] The instruction fetch control module is used to write the virtual address from the branch predictor into the instruction fetch address queue when the instruction fetch address queue does not meet the preset queue clearing condition and does not meet the preset prediction suspension condition. The instruction fetch address queue is used to access the page table cache module and / or the instruction cache module so that the downstream processing module receives the cached instructions, thereby realizing decoupling between the branch predictor and the page table cache module and / or the instruction cache module.

[0067] In some embodiments, the branch predictor may include a prediction control module and a prediction cache module.

[0068] The prediction cache module is used to store prediction information.

[0069] The prediction control module is used to control the read and write access of the prediction cache module, read the prediction information from the prediction cache module, notify the instruction fetch control module to receive the virtual address, and receive feedback training data and context switching information from the downstream processing module.

[0070] The prediction information is the branch information obtained by the prediction control module through accessing the prediction cache module. The prediction control module can predict the direction, type and target address of the branch instruction execution through further analysis. The category of the target address is, for example, a virtual address. As an example, the direction correction operation is performed on the branch predictor, including updating the relevant parameters in the direction prediction process of the prediction control module.

[0071] In the branch prediction system, the virtual address from the branch predictor is written into the instruction fetch address queue through the instruction fetch control module, and the instruction fetch address queue initiates access to the page table cache module and the instruction cache module, thereby realizing the decoupling between the branch predictor and the page table cache module and / or the instruction cache module, which helps to reduce the blockage of the prediction pipeline caused by page table misses and instruction misses, and improves the overall performance and throughput of the system. The prediction control module obtains the prediction information through the prediction cache module, and further parses the execution direction, type, target address and other information of the branch instruction, thereby reducing the waiting time for subsequent data access and improving the availability of data. By performing a direction correction operation on the branch predictor, the prediction can be corrected and updated according to the actual results, which helps to improve the accuracy and performance of the branch predictor, reduce mispredictions, and thus improve the efficiency of program execution. The prediction control module can also receive context switching information to facilitate the response to the switch between different tasks or processes. The system can effectively manage and maintain prediction information between different contexts to ensure the accuracy of the prediction.

[0072] In some embodiments, the instruction fetch control module is further configured to directly write the virtual address into or bypass the page table cache module and / or the instruction cache module when the instruction fetch address queue is empty.

[0073] In some other embodiments, the system further includes an arbitration module, and the arbitration module is used to directly write the virtual address into or bypass the page table cache module and / or the instruction cache module when the instruction fetch address queue is empty.

[0074] That is to say, the implementation subject of the above arbitration function can be an instruction fetch control module or an independent arbitration module. The present application does not limit the implementation method of the arbitration function. As long as the instruction fetch address queue is empty, the above direct write or bypass delivery operation can be performed. Since the instruction fetch address queue must be empty when any queue clearing condition is met, or in other words, it is empty as long as the write pointer and the read pointer coincide, when the queue clearing condition is met or the write pointer and the read pointer coincide, direct write or bypass delivery operation can be performed to enable the page table cache module and / or the instruction cache module to receive the required virtual address.

[0075] In a specific application scenario, continue as Figure 3 As shown, the branch prediction system includes a branch predictor, an instruction fetch control module 200 and an instruction fetch address queue 201. The branch predictor includes a prediction control module 100 and a prediction cache module 101.

[0076] The prediction control module 100 controls the read and write access of the predictor cache, collects prediction information, notifies the instruction fetch control module to receive virtual addresses, and receives feedback training and context switch information from downstream processing modules.

[0077] The prediction cache module 101 is a storage body of the branch predictor and is a module with high power consumption. The prediction cache module 101 is used to store branch information executed by the branch execution unit, including the direction, type and target address (eg, virtual address) of the branch.

[0078] 102 is the interface for the prediction control module 100 to access the prediction cache module 101, 103 is the interface for the prediction cache module 101 to feed back prediction information to the prediction control module 100. 104 is the interface for the prediction control module 100 to notify the instruction fetch control module 200 to receive the predicted virtual address, and 105 is the interface for the instruction fetch control module 200 to feed back whether the prediction control module 100 has a page table exception and the full status of the instruction fetch address queue 201.

[0079] The instruction fetch control module 200 controls the writing of the instruction fetch address queue 201 (FVAQ), receives the virtual address from the prediction control module 100, receives the flush line feedback from the downstream processing module 300, receives feedback from the instruction fetch address queue 201, feedback from the page table cache module 202 and feedback from the instruction cache module 203.

[0080] The instruction fetch address queue 201 stores the predicted address (i.e. the predicted virtual address), initiates access to the page table cache module 202 and the instruction cache module 203, and feedbacks whether the instruction fetch address queue 201 is full. 205 is the current full flag of the instruction fetch address queue 201, and 209 is the access initiated by the instruction fetch address queue 201 to the page table cache module 202 and the instruction cache module 203.

[0081] The page table cache module 202 stores the virtual-to-real conversion mapping and the attribute permissions of the address, receives the access of the instruction fetch address queue 201, feeds back the page table missing flag 206 to the instruction fetch control module 200, and feeds back the physical address after the page table hit to the instruction cache module 203. 204 is the interface for page table hit. The page table cache module is used to save the page table information obtained from the lower-level cache, that is, the mapping relationship between the virtual address and the physical address and the attribute permissions, etc.

[0082] The instruction cache module 203 stores cache lines, receives access from the instruction fetch address queue 201, feeds back the instruction missing flag 207 to the instruction fetch control module 200, and feeds back the hit instruction (i.e., cache line) to the downstream processing module 300. 208 is the cache line delivered to the downstream processing module 300 after the instruction hit. The instruction cache module 203 is used to store the cache lines obtained from the lower-level cache.

[0083] The downstream processing module 300 includes multiple functions such as decoding, dispatching, transmitting, executing, and submitting, and is used to provide training after misprediction and context switch information. 301 is when the downstream processing module 300 finds misprediction, the feedback prediction control module 100 trains the branch predictor (including allocation, updating, correction, etc.), and notifies the instruction fetch control module 200 to flush the line (i.e., clear the instruction fetch address queue 201). 302 is when the downstream processing module 300 finds context switch, notifies the instruction fetch control module 200 to flush the line, and sends the context switch information to the prediction control module 100.

[0084] In an actual application, after the hardware is powered on and reset, the downstream processing module 300 will notify the prediction control module 100 to start and load the instruction of the first virtual address; the prediction control module 100 sends the first virtual address to the prediction cache module 101.

[0085] The prediction cache module 101 feeds back the prediction result after access to the prediction control module 100 through 103, and then the prediction control module 100 sends the virtual address in the prediction result to the instruction fetch control module 200 through 104 for subsequent instruction fetch address queue 201 write operation; at the same time, the prediction control module 100 uses the prediction result as the base address for the next round of prediction.

[0086] The instruction fetch control module 200 receives the predicted virtual address and initiates a write operation to the instruction fetch address queue 201 .

[0087] After the write operation is completed, the instruction fetch address queue 201 simultaneously initiates access to the page table cache module 202 and the instruction cache module 203 .

[0088] If the page table cache misses, the physical address is fed back to the instruction cache module 203 via 206 , and the instruction fetch address queue 201 restarts the page table cache access of the address after the page table is backfilled. If the page table hits, the physical address is fed back to the instruction cache module 203 .

[0089] If the instruction cache misses, it is fed back to the instruction fetch control module 200 via 207 , and the instruction fetch address queue 201 restarts the page table cache access and instruction cache access of the address after waiting for the instruction to be backfilled. If the instruction cache hits, the cache line is output to the downstream processing module 300 via 208 .

[0090] If a misprediction or context switch occurs in the downstream processing module 300 , the flushing and training branch predictors will be notified via 301 .

[0091] During the processing of page table misses and cache misses, the prediction control module 100 and the prediction cache module 101 have completed multiple predictions and sequentially filled the predicted virtual addresses into the instruction fetch address queue 201 .

[0092] When the instruction fetch address queue 201 is about to be full, the prediction operation is suspended, that is, the prediction pipeline is suspended.

[0093] When the instruction fetch address queue 201 initiates a request to the page table cache module 202, if a page table permission exception is found, the instruction fetch address queue 201 needs to be cleared to wait for exception processing. Specifically, when the page table permission exception is responded to by the downstream processing module 300, the prediction control module 100 will be notified through 302 to provide a new prediction address. And so on, it enters a repetitive operation, which will not be repeated here.

[0094] It can be seen from the above embodiments that with the instruction fetch control module 200 and the instruction fetch address queue 201, when the page table cache or instruction cache is missing, the prediction control module 100 can continue to perform forward prediction without waiting for the page table and instruction backfill before starting, which means that the system can make full use of the performance of the prediction control module without having to wait for the backfill operation of the page table and instruction to be completed, thereby improving the prediction speed and prediction bandwidth. During the page table missing and instruction missing period, the prediction pipeline can still continue to perform the prediction operation, and the virtual address can still be filled into the instruction fetch address queue 201, reducing the prediction pipeline blockage caused by cache missing, which helps to improve the overall performance. When a page table permission exception occurs, the instruction fetch address queue 201 can be cleared and wait for exception processing to ensure that the system can properly handle the exception without causing erroneous execution. The prediction cache module 101 is a module with relatively high power consumption. However, since the branch predictor can be trained and its parameters can be corrected and updated in a timely manner when a misprediction occurs, the prediction control module 100 can manage and use the prediction information more effectively. Therefore, the read and write access to the prediction cache module 101 can be reduced, thereby reducing the power consumption of the prediction cache module 101.

[0095] An embodiment of the present application further provides a processor, which includes any one of the above-mentioned branch prediction systems.

[0096] See also Figure 4 , Figure 4 It is a structural block diagram of a computing device provided in an embodiment of the present application.

[0097] An embodiment of the present application further provides a computing device, which includes any one of the above-mentioned branch prediction systems.

[0098] The embodiments of the present application do not limit the computing device, which may be, for example, a computer server, a cloud server, a distributed server, etc.

[0099] In an optional embodiment, the computing device may include the branch prediction system described above. Figure 4 As shown, the computing device may include: a memory 110, a processor 120, and a communication interface 130. The memory 110, the processor 120, and the communication interface 130 are connected via an internal connection path.

[0100] The memory 110 is used to store instructions and codes. In some implementations, the codes may be codes for implementing the methods of the embodiments of the present application.

[0101] The processor 120 is used to execute the instructions and codes stored in the memory 110 to control the communication interface 130 to receive input data and information and output data such as operation results. In some implementations, when the solution of the embodiment of the present application is implemented by software or firmware, the code used to implement the solution of the embodiment of the present application can be stored in the processor 120 and executed by the processor 120.

[0102] The memory 110 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory 110 described herein is intended to include, but is not limited to, any memory of these and other suitable types. As an example, the memory 110 includes a random access memory (RAM), a cache memory and a read-only memory (ROM). Among them, the memory 110 stores a computer program, and the computer program can be executed by the processor 120 so that the processor 120 implements the steps of any of the above methods.

[0103] The processor 120 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor 120 may be any conventional processor, etc.

[0104] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 120 or an instruction in the form of software. The method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in the processor 120 for execution. The software module can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 110, and the processor 120 reads the information in the memory 110 and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0105] In some implementations, in addition to the hardware units described above, the computing device may also include software modules, where the software modules may be, for example, an operating system, a basic input output system (BIOS), application software, etc.

[0106] The operating system is used to manage the hardware and / or software resources of a computing device and is the core and cornerstone of a computing device. The operating system needs to handle basic tasks such as managing and configuring memory, determining the priority of system resource supply and demand, controlling input and output devices, operating the network, and managing the file system. In order to facilitate user operation, most operating systems provide an operating interface for users to interact with the system.

[0107] BIOS is used to run hardware initialization during the power-on boot phase and provide runtime services for the operating system and application programs. In some implementations, BIOS can also monitor and display processor temperature and execute functions such as adjusting temperature protection strategies.

[0108] Application software, also known as application program, can be understood as software written for a specific application purpose of the user. It is one of the main categories of computer software. For example, application software can be a program for achieving purposes such as power control and temperature management.

[0109] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions of any of the above-mentioned branch prediction methods.

[0110] An embodiment of the present application also provides a computer program product, which includes instructions of any of the above-mentioned branch prediction methods.

[0111] The computer program product may be a portable compact disk read-only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the computer program product of the present application is not limited thereto, and the computer program product may be any combination of one or more computer readable media.

[0112] The user information or user account information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, etc.) involved in multiple implementation methods of this specification are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws and standards of relevant countries and regions, and provide corresponding instruction entrances for users to choose to authorize or refuse.

[0113] It should be understood that the specific examples in this specification are only intended to help those skilled in the art to better understand the implementation methods of the present application, rather than to limit the scope of protection of the present application.

[0114] It is understood that in the various implementations of this specification, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application.

[0115] It can be understood that the various implementation modes described in this specification can be implemented individually or in combination, and this application is not limited to this.

[0116] Unless otherwise specified, all technical and scientific terms used in this specification have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above", and "the" used in this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0117] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this specification.

[0118] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of each embodiment described above can refer to the corresponding process in other embodiments and will not be repeated here.

[0119] In the several embodiments provided in this specification, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0120] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the technical solution of the present application.

[0121] In addition, each functional unit in each embodiment of the present specification may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0122] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of this specification. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0123] The above are only specific implementations of this specification, but the protection scope of this application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be included in the protection scope of this specification. Therefore, the protection scope of this application should be based on the protection scope of the claims.

Claims

1. A branch prediction method, characterized in that: An instruction fetch control module applied to a branch prediction system, the system comprising a branch predictor, the instruction fetch control module and an instruction fetch address queue, the method comprising: When the instruction fetch address queue does not satisfy a preset queue clearing condition and does not satisfy a preset prediction suspension condition, the virtual address from the branch predictor is written into the instruction fetch address queue, and the instruction fetch address queue is used to access a page table cache module and / or an instruction cache module so that a downstream processing module receives a cache instruction, thereby realizing decoupling between the branch predictor and the page table cache module and / or the instruction cache module; After receiving a page table miss flag corresponding to the first virtual address from the page table cache module, a page table backfill operation is performed for the page table cache module and corresponding to the first virtual address, so that the instruction fetch address queue re-executes the page table cache access for the page table cache module and corresponding to the first virtual address, so that the page table cache module feeds back the first physical address corresponding to the first virtual address to the instruction cache module; and / or, after receiving an instruction miss flag corresponding to the second virtual address from the instruction cache module, an instruction backfill operation is performed for the instruction cache module and corresponding to the second virtual address, so that the instruction fetch address queue re-executes the page table cache access for the page table cache module and corresponding to the second virtual address, and re-executes the instruction cache access for the instruction cache module and corresponding to the second virtual address, so that the instruction cache module outputs the cache instruction of the second physical address corresponding to the second virtual address to the downstream processing module.

2. The branch prediction method according to claim 1, characterized in that: The method further comprises: When the instruction fetch address queue meets the queue clearing condition, performing a clearing operation on the instruction fetch address queue; and / or, When the instruction fetch address queue does not satisfy the queue clearing condition and satisfies the prediction suspension condition, the prediction pipeline is suspended.

3. The branch prediction method according to claim 1 or 2, characterized in that: The process of determining whether the instruction fetch address queue meets the queue clearing condition includes: In the case where the downstream processing module feeds back misprediction and / or context switching, confirming that the instruction fetch address queue satisfies the queue clearing condition; When the downstream processing module does not feedback misprediction or context switching and the downstream processing module feedbacks page table permission abnormality, confirming that the instruction fetch address queue meets the queue clearing condition; When the downstream processing module does not feedback misprediction or context switching and the downstream processing module does not feedback page table permission exception, it is confirmed that the instruction fetch address queue does not meet the queue clearing condition.

4. The branch prediction method according to claim 1, characterized in that: The method further comprises: When the instruction fetch address queue is empty, the virtual address is directly written into or delivered to the page table cache module and / or the instruction cache module in a bypass manner.

5. The branch prediction method according to claim 1 or 2, characterized in that: The predicted suspension condition includes at least one of the following: The instruction fetch address queue feeds back a full flag; The distance between the write pointer and the read pointer of the instruction fetch address queue is not less than a preset value.

6. The branch prediction method according to claim 5, characterized in that: The predicted suspension condition includes: the distance between the write pointer and the read pointer of the instruction fetch address queue is equal to the preset value, and the preset value is the capacity of the instruction fetch address queue.

7. An instruction fetch control module, characterized in that: The instruction fetch control module is configured to execute the branch prediction method according to any one of claims 1 to 6.

8. A branch prediction system, characterized in that: The system includes a branch predictor, an instruction fetch control module and an instruction fetch address queue; The branch predictor is used to provide a virtual address; The instruction fetch control module is used to write the virtual address from the branch predictor into the instruction fetch address queue when the instruction fetch address queue does not meet the preset queue clearing condition and does not meet the preset prediction suspension condition. The instruction fetch address queue is used to access the page table cache module and / or the instruction cache module so that the downstream processing module receives the cache instruction, thereby realizing the decoupling between the branch predictor and the page table cache module and / or the instruction cache module; The instruction fetch control module is also used for: after receiving a page table missing flag corresponding to a first virtual address from the page table cache module, performing a page table backfill operation for the page table cache module and corresponding to the first virtual address, so that the instruction fetch address queue re-executes the page table cache access for the page table cache module and corresponding to the first virtual address, so that the page table cache module feeds back the first physical address corresponding to the first virtual address to the instruction cache module; and / or, after receiving an instruction missing flag corresponding to a second virtual address from the instruction cache module, performing an instruction backfill operation for the instruction cache module and corresponding to the second virtual address, so that the instruction fetch address queue re-executes the page table cache access for the page table cache module and corresponding to the second virtual address, and re-executes the instruction cache access for the instruction cache module and corresponding to the second virtual address, so that the instruction cache module outputs the cache instruction of the second physical address corresponding to the second virtual address to the downstream processing module.

9. The branch prediction system according to claim 8, characterized in that: The branch predictor includes a prediction control module and a prediction cache module; The prediction cache module is used to store prediction information; The prediction control module is used to control the read and write access of the prediction cache module, read the prediction information from the prediction cache module, notify the instruction fetch control module to receive the virtual address, and receive feedback training data and context switching information from the downstream processing module.

10. A processor, characterized in that: The processor comprises the branch prediction system of claim 8 or 9.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions of the branch prediction method according to any one of claims 1 to 6.

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