AXI-PCIE outbound data path verification system and method

Abstract

The present invention discloses a verification system and method for an AXI-PCIE outbound data path, including: an IATU configuration component: used for configuring an IATU outbound register; a TLP2AXI conversion data component: used for converting a random TLP data packet intermediate generated by a verification component into an AXI data packet, and sending the AXI data packet to a driver module of the verification component; a driver module: used for driving an AXI data packet from a verification system to a DUT, and the DUT generates a TLP data packet to an upstream RC detection module according to the configured IATU outbound register; a detection module: used for comparing the TLP data packet received by the RC with the TLP data packet intermediate generated by the verification system, and if the comparison is passed, it proves that the EP TLP data packet is successfully sent. Applied to the verification of the outbound data path of a PCIE module, it can solve the problems of difficult verification of the outbound data path, complex comparison, incomplete verification and long verification cycle; it contains functions such as excitation, driving and verification, and supports most verification scenarios.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit verification, and in particular relates to a verification system and method for an AXI-PCIE outbound data path. Background Art

[0002] As a popular bus and interface standard, the Peripheral Component Interconnect Express (PCIE) has the characteristics of extremely high transmission rate and high bandwidth. The Advanced Extensible Interface (AXI) is a high-performance, high-bandwidth, low-latency on-chip bus that can be used as a bridge for data between PCIE devices. AXI is often used together with PCIE, so the outbound flow of AXI-PCIE and the inbound flow of PCIE-AXI are the focus of data path verification. Figure 1 As shown. With the rapid development of chip design and verification technology, verification personnel have higher and higher requirements for module function verification. In order to complete verification in a short time and ensure the correctness of the logical function during verification, the verification environment needs to be comprehensive and reusable. However, due to the complexity and diversity of the data layer message (Transaction Layer Packet, referred to as TLP) data packets, verification personnel need to perform a large number of random regression tests every time they redesign or modify the PCIE module, so it is imperative to improve the verification efficiency.

[0003] At present, in the process of verifying PCIE modules, the verification method of PCIE-AXI inbound data path is relatively simple. Using the stimulus provided by Verification IP (VIP), random TLP data packets can be generated at the PCIE root complex (RC, RC device is used to connect CPU / memory subsystem and I / O device) end and sent to the PCIE endpoint (EP, EP device usually represents a serial or I / O device). The verification method of AXI-PCIE outbound data path is usually to manually construct stimulus at the AXI interface to make PCIE EP form different types of TLP data packets and send them to the PCIE RC end. This method is very troublesome to generate TLP data packets and compare different types of PCIE TLP data packets, and temporary writing is prone to errors. At the same time, since AXI is used as the stimulus end, if the verification personnel use this method to perform random tests at will, it will often cause various abnormal situations that are not allowed in the PCIE module, making the verification impossible.

[0004] Some existing technologies related to PCIE data path verification mainly include:

[0005] 1. Use the UVM verification method to build a verification environment platform including a driver module and a monitoring module to perform functional verification on the PCIE module. The verification environment platform can be transplanted to verify PCIEs with different configurations; however, the verification environment platform does not verify the AXI-PCIE outbound data path. The outbound data path has problems such as difficult verification, incomplete verification, and a long verification cycle.

[0006] 2. Build a PCIE-based storage system through a DMA transfer controller to improve the data processing efficiency of the PCIE interface that uses the TLP protocol for transmission; however, the storage system only performs AXI-PCIE data transmission, does not verify the AXI-PCIE outbound data path, and does not provide a portable and randomizable verification component, resulting in low verification efficiency. Summary of the invention

[0007] The purpose of the present invention is to provide a verification system and method for an AXI-PCIE outbound data path to solve the technical problems existing in the background technology.

[0008] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0009] A verification system for an AXI-PCIE outbound data path, comprising:

[0010] IATU configuration component: used to configure the IATU outbound register;

[0011] TLP2AXI data conversion component: used to convert the random TLP data packet intermediate generated by the top-level function of the verification component into an AXI data packet, and send the AXI data packet to the driver module of the verification system;

[0012] Driver module: used to drive the AXI data packet from the verification system to the DUT. The DUT then generates the corresponding TLP data packet to the upstream RC detection module according to the configured IATUoutbound register;

[0013] Detection module: used to compare the TLP data packet received by the RC with the random TLP data packet intermediate generated by the verification system. If the comparison is successful, it proves that the EP TLP data packet is sent successfully.

[0014] Furthermore: the IATU outbound register converts the address of the AXI data packet and provides an interface for the top-level parameter transfer of the verification component, and randomizes the random TLP data packet intermediate type through random parameters input from the outside.

[0015] A method for verifying an AXI-PCIE outbound data path includes the following steps:

[0016] Step 1: Generate a random TLP data packet intermediate by verifying the top-level function of the component;

[0017] Step 2: Configure the IATU outbound register according to the random TLP data packet intermediate through the IATU configuration component;

[0018] Step 3: Convert the random TLP data packet intermediate into an AXI data packet through the TLP2AXI conversion data component, and send the AXI data packet to the driver module of the verification system;

[0019] Step 4: Drive the AXI data packet from the verification system to the DUT through the driver module. The DUT generates the corresponding TLP data packet and sends it to the upstream RC according to the configured IATUoutbound register.

[0020] Step 5: The detection module compares the TLP data packet received by the RC with the random TLP data packet intermediate generated by the verification system. If the comparison passes, it proves that the EP TLP data packet is sent successfully.

[0021] Further: the random TLP data packet intermediate includes a type field, an fmt field, an attr field, a tc field, a th field, a traffic_class field, a length field, a message_code field, a first_dw_be field and a last_dw_be field.

[0022] Further: the specific steps of configuring the IATU outbound register by the IATU configuration component in step 2 are:

[0023] Step 21: Determine whether the random TLP data packet intermediate is a specific type of TLP data packet that can be generated only by a level signal. If so, create an incentive to control the level signal to change so as to generate a TLP data packet, directly send the TLP data packet to the DUT and then enter step 5. Otherwise, enter step 22.

[0024] Step 22: Determine whether the random TLP data packet intermediate is a TLP type that requires address routing, if so, proceed to step 23, otherwise, proceed to step 24;

[0025] Step 23: configure the IATU outbound register offset base address and its restricted address range, assign the address of the random TLP data packet intermediate to the address register that needs to be converted in the IATU outbound register, and proceed to step 24;

[0026] Step 24: Determine whether the random TLP data packet intermediate is a type that carries data. If so, assign the random TLP data packet intermediate a constant value of the random data generated at this time. Otherwise, configure the data of the random TLP data packet intermediate to 0, and give the IATU outbound register a flag bit with no data.

[0027] Step 25: assign the type field, fmt field, attr field, tc field, th field, traffic_class field, length field and message_code field of the random TLP data packet intermediate to the fields of the IATU outbound register;

[0028] Step 26: Configure the assignment results of steps 21-25 into the IATU outbound register to complete the configuration of the IATU outbound register.

[0029] Further: in step 23, the address register to be converted by the IATU outbound register is bound to the channel selected by the IATU outbound register.

[0030] Further: In step 3, the specific steps of the TLP2AXI data conversion component converting the random TLP data packet intermediate into the AXI data packet are:

[0031] Step 31: The user selects the AXI bus width;

[0032] Step 32: determine whether the burst length value of the AXI data packet exceeds the maximum value. If so, the simulation reports an error, ends the process, and enters step 4. Otherwise, enters step 33.

[0033] Step 33: According to the AXI bus bit width selected in step 31, the numerical value of the random TLP data packet intermediate is assigned to the data interface of the AXI data packet;

[0034] Step 34: determine whether the random TLP data packet intermediate is a read or write operation, convert the read operation of the random TLP data packet intermediate into a read operation of the AXI data packet, and convert the write operation of the random TLP data packet intermediate into a write operation of the AXI data packet;

[0035] Step 35: Determine the first_dw_be field and the last_dw_be field of the random TLP data packet intermediate, and assign the first_dw_be field and the last_dw_be field to the strb interface of the AXI data packet;

[0036] Step 36: Determine whether the random TLP data packet intermediate contains a prefix. If so, assign the prefix field information to the USER interface of the AXI data packet and set other fields of the AXI data packet to default values. Otherwise, terminate this process and proceed to step 4.

[0037] Further: the value of the random TLP data packet intermediate in step 33 is assigned to the data interface of the AXI data packet in reverse order of bytes.

[0038] Further: in the step 35, the first_dw_be field and the last_dw_be field are assigned to the strb interface of the last burst of the AXI data packet, and the valid bit strb interface of the burst before the last burst is set to 0xf.

[0039] Further: Step 5 specifically includes: comparing the TLP data packet received by the RC with the random TLP data packet intermediate generated by the verification system through the detection module. If the fields of the TLP data packet are correctly compared and the address offset is correct, it proves that the EP TLP data packet is sent successfully.

[0040] Compared with the prior art, the AXI-PCIE outbound data path verification system and method provided by the embodiment of the present invention has the following advantages:

[0041] 1. Add IATU configuration component, TLP2AXI data conversion component, driver module and detection module to the verification system of AXI-PCIE outbound data path; the system is applied to the verification of the outbound data path of the PCIE module, which can solve the problems of difficult verification, complex comparison, incomplete verification and long verification cycle of the outbound data path; it contains functions such as excitation, driving and verification, and supports most verification scenarios.

[0042] 2. Provide a randomizable interface to convert the random verification format of the inbound data path into the random verification format of the outbound data path, which can achieve complete verification and save verification time.

[0043] 3. The IATU configuration component detects and processes each field of the randomized TLP data packet, and uses the detection and processing results to configure the IATU outbound register. The IATU configuration component can be used as a portable and reusable verification component to improve verification efficiency. The IATU configuration component focuses on internal address conversion, which can realize CPU reading, device memory writing, and device register configuration. Due to the flexibility of the IATU configuration component, it can optimize system performance and minimize the complexity of the software driver.

[0044] 4. The TLP2AXI conversion data component realizes the conversion from TLP format to AXI format. The TLP2AXI conversion data component can be used as a portable and reusable verification component to improve the verification efficiency.

[0045] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A schematic diagram of an inbound / outbound data path provided by an embodiment of the present invention;

[0048] Figure 2 The overall structure diagram of the verification system of the AXI-PCIE outbound data path provided by the embodiment of the present invention;

[0049] Figure 3 An overall flow chart of the verification system for the AXI-PCIE outbound data path provided by an embodiment of the present invention;

[0050] Figure 4 A specific flow chart of configuring the IATU outbound register by the IATU configuration component provided in the embodiment of the present invention;

[0051] Figure 5 A specific flow chart of the TLP2AXI data conversion component provided in an embodiment of the present invention converting a random TLP data packet intermediate into an AXI data packet. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0053] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0055] It should be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0056] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0057] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0058] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0059] like Figure 2 As shown, an embodiment of the present invention provides a verification system for an AXI-PCIE outbound data path, including:

[0060] Internal Address Translation Unit (IATU) configuration component: This component is used to configure the IATU outbound registers, firstly to convert the address of the AXI data packet, and secondly to provide an interface for the top-level parameter transfer of the verification component, and to randomize the type of the TLP data packet intermediate through random parameters input from the outside.

[0061] TLP2AXI data conversion component: used to convert the random TLP data packet intermediates generated by the top-level function of the verification component into AXI data packets, convert the random TLP data packet intermediate read and write operations into the required AXI data packet read and write formats, and send the AXI data packets to the driver module of the verification system.

[0062] Driver module: used to drive the AXI data packet from the verification system to the DUT. Subsequently, the DUT generates a TLP data packet to the upstream RC detection module according to the configured IATUoutbound register, and determines whether the AXI data packet has been sent.

[0063] Detection module: used to compare the TLP data packet received by the RC with the random TLP data packet intermediate generated by the verification system. If the comparison is successful, it proves that the EP TLP data packet is sent successfully, including the address of the TLP data packet and the data it carries.

[0064] like Figure 3 As shown, an embodiment of the present invention provides a method for verifying an AXI-PCIE outbound data path, comprising the following steps:

[0065] Step 1: Generate a random TLP packet intermediate by verifying the top-level function of the component.

[0066] A TLP message that the PCIE RC end wants to receive is randomly generated through the interface provided by the VIP inbound data path, and is sent to the verification system of the AXI-PCIE outbound data path through the packaged function. The entire structure of the random TLP data packet contained in the inbound data path is shown below, but not all are listed.

[0067] uvm_do_on_with(msg_seq,p_sequencer.root_virt_seqr.driver_transaction_seqr[0],{

[0068] msg_seq.ep == 0;

[0069] msg_seq.num_exceptions == 0;

[0070] msg_seq.length == 0;

[0071] msg_seq.message_code==svt_pcie_driver_app_transaction::PME_TURN_OFF;

[0072] msg_seq.routing_type==svt_pcie_driver_app_transaction::BROADCAST_FROM_RC;

[0073] msg_seq.traffic_class == 0;

[0074] msg_seq.block == 1;})

[0075] Verification of the flow direction of the outbound data path, that is, to verify whether the PCIE RC end receives a certain TLP data packet, the TLP data packet contained in the outbound data path is constructed into a format similar to the TLP data packet contained in the inbound data path. The writing method is simple and the field information such as the TLP format does not need to be repeatedly defined. The entire structure of the TLP data packet contained in the outbound data path is as follows:

[0076] msg=svt_pcie_tlp::type_id::create(“msg”);

[0077] msg.randomize with {

[0078] tlp_type == svt_pcie_tlp::BROADCAST_FROM_RC;

[0079] fmt == svt_pcie_tlp::NO_DATA_4_DWORD;

[0080] message_code == svt_pcie_tlp::PME_TURN_OFF;

[0081] length==0;

[0082] th==0;

[0083] attr_relaxed_ording==0;

[0084] };

[0085] do_tlp_msg(msg,axi_mstr_msg)

[0086] Step 2: Configure the IATU outbound register according to the random TLP data packet intermediate through the IATU configuration component; the specific steps are as follows Figure 4 As shown, specifically:

[0087] In the IATU configuration component, the IATU outbound register is configured according to the type field (the type field is used to describe whether the size of the TLP header consists of 3 double words or 4 double words), the fmt field (the fmt field indicates whether the current TLP contains a valid load), the th field (the th field is 1, indicating that the current TLP contains TLP Processing Hint information), the traffic_class field, the length field (the length field is used to describe the size of the TLP's valid load), the message_code field, the first_dw_be field, and the last_dw_be field configuration (depending on the random situation).

[0088] Step 21: Determine whether the random TLP data packet intermediate is a specific type of TLP data packet that can be generated only by a level signal (such as a TLP that can be triggered by a level signal such as an intx interrupt). If so, create an incentive to control the level signal change to generate a TLP data packet, directly send the TLP data packet to the DUT and enter the step 5. Otherwise, enter step 22.

[0089] Step 22: Determine whether the type of the random TLP data packet intermediate is a TLP type that requires address routing, if so, proceed to step 23, otherwise, proceed to step 24;

[0090] Step 23: First, configure the IATU outbound register offset base address and its restricted address range, assign the address of the random TLP data packet intermediate to the address register that needs to be converted by the IATU outbound register, and give the high 32-bit and low 32-bit addresses of the random TLP data packet intermediate to the corresponding registers respectively. The address register that needs to be converted by the IATU outbound register is bound to the channel selected by the IATU outbound register, and go to step 24;

[0091] Step 24: Determine whether the type of the random TLP data packet intermediate is a type that carries data. If so, assign the random TLP data packet intermediate a constant value of the random data generated at this time. Otherwise, configure the data of the random TLP data packet intermediate to 0, and give the IATU outbound register a flag bit with no data.

[0092] Step 25: assign the type field, fmt field, attr field, tc field, th field, traffic_class field, length field and message_code field of the random TLP data packet intermediate to the fields of the IATU outbound register;

[0093] Step 26: Configure the assignment results of steps 21-25 into the IATU outbound register to complete the configuration of the IATU outbound register.

[0094] Step 3: Convert the random TLP data packet intermediate into an AXI data packet through the TLP2AXI data conversion component, and send the AXI data packet to the driver module of the verification system; the specific steps are as follows Figure 5 As shown, specifically:

[0095] Step 31: The user selects the AXI bus width (32, 64, 128, 256 bits), and supports external parameter transmission or setting of default values;

[0096] Step 32: Determine whether the value of the burst length of the AXI data packet (the maximum value supported by different AXI data packet versions is different) exceeds the maximum value. If so, the simulation reports an error, ends the process, and enters step 4. Otherwise, enters step 33.

[0097] Step 33: According to the AXI bus bit width selected in step 31, the value of the random TLP data packet intermediate is assigned to the data interface of the AXI data packet. Since the data of the TLP packet is transmitted in little endian, the assignment here is in reverse order of bytes.

[0098] Step 34: determine whether the random TLP data packet intermediate is a read or write operation, convert the read operation of the random TLP data packet intermediate into a read operation of the AXI data packet, and convert the write operation of the random TLP data packet intermediate into a write operation of the AXI data packet;

[0099] Step 35: Determine the valid first_dw_be field (TLP field) and last_dw_be field (TLP data valid field) of the intermediate of the random TLP data packet, and assign the first_dw_be field and last_dw_be field to the strb interface of the AXI data packet. Here, only the last burst of the AXI data packet is judged, and the previous burst valid byte data written to the strb interface are all 0xf;

[0100] Step 36: Determine whether the random TLP data packet intermediate contains a prefix. If so, assign the prefix field information to the additional signal USER interface of the AXI data packet, and set the other fields of the AXI data packet to default values. Otherwise, terminate this process directly and enter step 4.

[0101] Step 4: Drive the AXI data packet from the verification system to the DUT through the driver module, and determine whether the AXI data packet is successfully sent according to the status of the AXI data packet event. Subsequently, the DUT sends the TLP data packet generated by the configured IATU outbound register to the detection module of the upstream RC;

[0102] Step 5: The detection module compares the TLP data packet received by the RC with the random TLP data packet intermediate generated by the verification system. If the fields of the TLP data packet are correctly compared and the address offset is correct, it proves that the EP TLP data packet is sent successfully.

[0103] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0104] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A verification system for an AXI-PCIE outbound data path, characterized in that: include: IATU configuration component: used to configure the IATU outbound register; TLP2AXI data conversion component: used to convert the random TLP data packet intermediate generated by the top-level function of the verification component into an AXI data packet, and send the AXI data packet to the driver module of the verification system; Driver module: used to drive the AXI data packet from the verification system to the DUT, and then the DUT transmits the TLP data packet generated by the IATU outbound register to the upstream RC detection module; Detection module: used to compare the TLP data packet received by the RC with the random TLP data packet intermediate generated by the verification system. If the comparison is successful, it proves that the EP TLP data packet is sent successfully; the random TLP data packet intermediate is the TLP data to be processed.

2. The AXI-PCIE outbound data path verification system according to claim 1, characterized in that: The IATU outbound register converts the address of the AXI data packet and provides an interface for the top-level parameter transfer of the verification component, and randomizes the random TLP data packet intermediate type through random parameters input from the outside.

3. A method for verifying an AXI-PCIE outbound data path, characterized in that: The following steps are involved: Step 1: Generate a random TLP data packet intermediate by verifying the top-level function of the component; Step 2: Configure the IATU outbound register according to the random TLP data packet intermediate through the IATU configuration component; Step 3: Convert the random TLP data packet intermediate into an AXI data packet through the TLP2AXI conversion data component, and send the AXI data packet to the driver module of the verification system; Step 4: Drive the AXI data packet from the verification system to the DUT through the driver module. The DUT generates the corresponding TLP data packet and sends it to the upstream RC according to the configured IATUoutbound register. Step 5: The detection module compares the TLP data packet received by the RC with the random TLP data packet intermediate generated by the verification system. If the comparison passes, it proves that the EP TLP data packet is sent successfully.

4. The AXI-PCIE outbound data path verification method according to claim 3, characterized in that: The random TLP data packet intermediate includes a type field, an fmt field, an attr field, a tc field, a th field, a traffic_class field, a length field, a message_code field, a first_dw_be field and a last_dw_be field.

5. The AXI-PCIE outbound data path verification method according to claim 3, characterized in that: The specific steps for the IATU configuration component to configure the IATU outbound register in step 2 are: Step 21: Determine whether the random TLP data packet intermediate is a specific type of TLP data packet that can be generated only by a level signal. If so, create an incentive to control the level signal to change so as to generate a TLP data packet, directly send the TLP data packet to the DUT and then enter step 5. Otherwise, enter step 22. Step 22: Determine whether the random TLP data packet intermediate is a TLP type that requires address routing, if so, proceed to step 23, otherwise, proceed to step 24; Step 23: configure the IATU outbound register offset base address and its restricted address range, assign the address of the random TLP data packet intermediate to the address register that needs to be converted in the IATU outbound register, and proceed to step 24; Step 24: Determine whether the random TLP data packet intermediate is a type that carries data. If so, assign the random TLP data packet intermediate a constant value of the random data generated at this time. Otherwise, configure the data of the random TLP data packet intermediate to 0, and give the IATU outbound register a flag bit with no data. Step 25: assign the type field, fmt field, attr field, tc field, th field, traffic_class field, length field and message_code field of the random TLP data packet intermediate to the fields of the IATU outbound register; Step 26: Configure the assignment results of steps 21-25 into the IATU outbound register to complete the IATU outbound Register configuration.

6. The AXI-PCIE outbound data path verification method according to claim 5, characterized in that: In step 23, the address register to be converted by the IATU outbound register is bound to the channel selected by the IATU outbound register.

7. The method for verifying an AXI-PCIE outbound data path according to claim 3, characterized in that: In step 3, the specific steps of the TLP2AXI data conversion component converting the random TLP data packet intermediate into an AXI data packet are: Step 31: The user selects the AXI bus width; Step 32: Determine whether the burst length value of the AXI data packet exceeds the maximum value. If so, the simulation reports an error, ends the process, and enters step 4. Otherwise, enters step 33; the burst length is the data length of one transmission; Step 33: According to the AXI bus bit width selected in step 31, the numerical value of the random TLP data packet intermediate is assigned to the data interface of the AXI data packet; Step 34: determine whether the random TLP data packet intermediate is a read or write operation, convert the read operation of the random TLP data packet intermediate into a read operation of the AXI data packet, and convert the write operation of the random TLP data packet intermediate into a write operation of the AXI data packet; Step 35: Determine the first_dw_be field and the last_dw_be field of the random TLP data packet intermediate, and assign the first_dw_be field and the last_dw_be field to the strb interface of the AXI data packet; Step 36: Determine whether the random TLP data packet intermediate contains a prefix. If so, assign the prefix field information to the USER interface of the AXI data packet and set other fields of the AXI data packet to default values. Otherwise, terminate this process and proceed to step 4.

8. The method for verifying an AXI-PCIE outbound data path according to claim 7, characterized in that: The value of the random TLP data packet intermediate in step 33 is assigned to the data interface of the AXI data packet in reverse byte order.

9. The method for verifying an AXI-PCIE outbound data path according to claim 7, wherein: In step 35, the first_dw_be field and the last_dw_be field are assigned to the strb interface of the last burst of the AXI data packet, and the valid bit strb interface of the burst before the last burst is set to 0xf.

10. The AXI-PCIE outbound data path verification method according to claim 3, characterized in that: The step 5 is specifically as follows: the TLP data packet received by the RC is compared with the random TLP data packet intermediate generated by the verification system through the detection module. If the fields of the TLP data packet are correctly compared and the address offset is correct, it proves that the EP TLP data packet is sent successfully.

Images