Memory devices, methods, and non-transitory machine-readable storage media

Abstract

The present disclosure relates to victim row counters in memory devices. In some examples, a memory device includes a plurality of memory cell rows, a plurality of victim counters associated with respective memory cell rows of the plurality of memory cell rows, and a plurality of aggressor counters associated with respective memory cell rows. A first victim counter of the plurality of victim counters is associated with a first row of the plurality of memory cell rows, the first victim counter to advance in response to an advancement in a count of an aggressor counter associated with a neighboring row of memory cells that are neighbors of the first row.

Description

Technical Field

[0001] This disclosure generally relates to memory devices. Background Technology

[0002] A memory device includes memory cells that store data. Each memory cell includes a data storage structure that stores the data. In some examples, the data storage structure of a memory cell may include a storage capacitor. In other examples, the data storage structure of a memory cell may include a floating gate that traps charge to represent data, a resistive element that represents data as resistance, and so on. Summary of the Invention

[0003] According to one aspect of this disclosure, a memory device includes: a plurality of memory cell rows; a plurality of victim counters associated with a respective memory cell row of the plurality of memory cell rows; and a plurality of intruder counters associated with the respective memory cell rows, wherein a first victim counter of the plurality of victim counters is associated with a first row of the plurality of memory cell rows, a count of the first victim counter is configured to proceed in response to a count of an intruder counter associated with an adjacent row of a memory cell that is a neighbor of the first row, and wherein the count of the first victim counter represents the amount of row hammer interference of the first row due to activation of the adjacent row of the memory cell.

[0004] According to another aspect of this disclosure, a memory device includes: a plurality of memory cell rows; a plurality of victim counters associated with a respective memory cell row of the plurality of memory cell rows; and a plurality of intruder counters associated with the respective memory cell rows, wherein a first victim counter of the plurality of victim counters is associated with a first row of the plurality of memory cell rows, the first victim counter being configured to advance in response to a count of an intruder counter associated with an adjacent row of memory cells that is a neighbor of the first row, wherein the adjacent row of memory cells includes a first adjacent row of memory cells and a second adjacent row of memory cells, and the intruder counter associated with the adjacent row of memory cells includes a first intruder counter associated with the first adjacent row of memory cells and a second intruder counter associated with the second adjacent row of memory cells, and wherein the first victim counter is configured to advance in response to a first scaling count of the first intruder counter and a second scaling count of the second intruder counter, the first scaling count being based on a first weight and the second scaling count being based on a second weight.

[0005] According to another aspect of this disclosure, a method for a memory device includes: advancing an intruder counter for a corresponding memory cell row based on activation of that row; advancing a first victim counter for the first victim row of memory cells in the memory device based on the advancement of intruder counters for adjacent rows of memory cells that are neighbors of the first victim row, wherein the advancement of the first victim counter includes: advancing the first victim counter in response to a first scaling count of a first intruder counter for a first adjacent row of the adjacent row of the memory cell, the first scaling count being based on a first weight; advancing the first victim counter in response to a second scaling count of a second intruder counter for a second adjacent row of the adjacent row of the memory cell, the second scaling count being based on a second weight different from the first weight; comparing the count of the first victim counter with a threshold; and based on the comparison, detecting row hammer interference in the first victim row and initiating a suppression action against the row hammer interference in the first victim row.

[0006] According to another aspect of this disclosure, a non-transitory machine-readable storage medium includes instructions that, when executed, cause a controller in a memory device to: receive a count of a first victim counter for a first victim row of memory cells in the memory device, the first victim counter being configured to advance in response to a scaling count of an intruder counter for an adjacent row of memory cells that is a neighbor of the first victim row, the scaling count including a first scaling count based on a first scaling factor of a first intruder counter associated with a first adjacent row of the adjacent row, and a second scaling count based on a second scaling factor of a second intruder counter associated with a second adjacent row of the adjacent row, wherein the first scaling factor is different from the second scaling factor; compare the count of the first victim counter with a threshold; and based on the comparison, detect row hammer interference of the first victim row and initiate a suppression action against the row hammer interference of the first victim row. Attached Figure Description

[0007] Some embodiments of this disclosure are described with reference to the following figures.

[0008] Figure 1 It is a block diagram based on some examples of memory devices.

[0009] Figure 2A It is a block diagram of a digital counter based on some examples.

[0010] Figure 2B This is a block diagram of an analog counter based on some examples.

[0011] Figure 3It is a block diagram of intruder and victim counters based on some examples.

[0012] Figure 4 It is a block diagram of an analog scaling circuit based on some examples.

[0013] Figure 5A and 5B This is a block diagram of a row hammer counter in a memory device based on some examples.

[0014] Figure 6 It is a flowchart based on some examples.

[0015] Figure 7 It is a block diagram of a storage medium with machine-readable instructions based on some examples of storage.

[0016] In all the accompanying drawings, the same reference numerals denote similar but not necessarily identical elements. The drawings are not necessarily drawn to scale, and the dimensions of some parts may be enlarged to show the examples more clearly. Furthermore, the drawings provide examples and / or embodiments consistent with the description; however, the description is not limited to the examples and / or embodiments provided in the drawings. Detailed Implementation

[0017] In this disclosure, the terms “a,” “an,” or “the” are also intended to include plural forms unless the context clearly indicates otherwise. Furthermore, the terms “include,” “including,” “comprise,” “comprising,” “have,” or “having” as used in this disclosure specify the presence of the stated element but do not preclude the presence or addition of other elements.

[0018] Example types of memory devices include dynamic random access memory (DRAM) devices. DRAM devices have memory cells, each of which includes a storage capacitor and an access transistor connected to the storage capacitor.

[0019] Although the following discussion relates to DRAM devices, it should be noted that the techniques or mechanisms of some embodiments of this disclosure can be applied to other types of memory devices, such as memory devices that use floating gates to store data (e.g., flash memory devices, electrically erasable programmable read-only memory devices, etc.), memory devices that use resistive memory elements to store data (e.g., resistive memory devices), etc.

[0020] With advancements in memory technology, the density of memory cells in memory devices continues to increase. While high memory cell density can reduce the cost per bit of a memory device, it can also lead to decreased reliability of data storage. For example, memory cells arranged in a high density may be more susceptible to interference caused by access from adjacent memory cells.

[0021] Memory cells in a memory device can be arranged in rows and columns. Each row of memory cells can be activated in response to the activation of a row signal line (also called a word line). When a given row signal line is activated, the memory cells in that row are connected to the corresponding column data line via a transfer transistor, enabling access to the memory cells in that row. In the row of activated memory cells, a column select signal can be used to select several column data lines (a single column data line or multiple column data lines) for access (reading or writing).

[0022] As used here, a “row” of memory cells can refer to any set of memory cells that are activated together in response to an activation signal.

[0023] Row hammer refers to a type of interference that occurs when a row of memory cells (such as memory cells in a DRAM device) is repeatedly activated within a time interval (e.g., the refresh interval of a DRAM device), which can cause data errors in adjacent rows of the memory cell. For example, interference can cause adjacent rows of memory cells to leak charge at a faster rate than expected. In a further example, electrical or magnetic interference to adjacent rows caused by a large number of accesses to memory cells in a given row can even flip the state of data bits in adjacent rows of memory cells.

[0024] Figure 1 This is a block diagram of a memory device 100 according to some examples of this disclosure. The memory device 100 includes various rows of memory cells. Figure 1 Two types of row hammer interference are illustrated in memory device 100. The first type of row hammer interference is caused by an "intruder" row 102 that interferes with multiple "victim" rows 104 and 106. An "intruder" row is a row of memory cells that, when activated, causes interference to another row of memory cells, which is referred to as the "victim" row. For example, intruder row 102 can interfere with two (or more) adjacent rows 104 and 106 on two corresponding sides 102-1 and 102-2 of intruder row 102. Note that intruder row 102 may interfere with multiple victim rows on a first side 102-1 of intruder row 102, and / or interfere with multiple victim rows on a second side 102-2 of intruder row 102.

[0025] although Figure 1Some memory cell rows are displayed as intruder rows, while other memory cell rows are displayed as victim rows. However, note that when an adjacent row of a memory cell is activated, the intruder row may be a victim row (that adjacent row is the intruder row).

[0026] The second type of row hammer interference is caused by multiple intruder rows 110, 112, 114, and 116 interfering with victim row 108. As an example, if accessed repeatedly within a time interval (e.g., a refresh interval), two (or more) intruder rows 110 and 112 on the first side 108-1 of victim row 108 may interfere with victim row 108, and if accessed repeatedly within that time interval, two (or more) intruder rows 114 and 116 on the second side 108-2 of victim row 108 may interfere with victim row 108.

[0027] In some examples, row hammer detection mechanisms capable of detecting the first type of row hammer interference cannot detect the second type. Inability to reliably detect the second type of row hammer interference in a memory device may result in data loss from memory cells stored in the memory device.

[0028] As described above, the "refresh interval" refers to the time interval between refreshes of a given subset of memory cells. Because DRAM devices store data in storage capacitors, the charge stored in these capacitors can slowly leak out, leading to data loss. To address this issue, a refresh operation can be performed in the DRAM device. The refresh operation refreshes a subset of the memory cells in the DRAM device. A "subset" of memory cells can refer to N (N≥1) rows of memory cells, or a refresh region of any other memory cell within the memory cell array of the memory device.

[0029] A refresh operation involves reading data bits from a subset of memory cells and writing the data bits back to the subset of memory cells without modification to preserve the data bits. The refresh interval is the maximum time interval between refreshes of any subset of memory cells (to avoid data loss in the subset of memory cells).

[0030] If repeated accesses to an intruder's row of memory cells occur within the refresh interval, causing data degradation in the memory cells of the victim row, the victim row's memory cells may lose their data before a refresh operation occurs to restore the data in the victim row's memory cells. If the victim row's memory cells are corrupted due to access to the intruder's row, subsequent refresh operations that refresh the victim row will cause the corrupted data to be read and written back to the memory cells, resulting in data corruption.

[0031] Some memory devices have burst operation modes, in which rows of memory cells can be accessed repeatedly within a short period of time. Such rows of memory cells accessed during burst mode can become intrusion rows.

[0032] In other examples, a malicious entity (e.g., a user, program, hardware device, etc.) might attempt to repeatedly access rows of memory cells within a short period of time, resulting in data loss.

[0033] According to some embodiments of this disclosure, the memory device 100 includes a row hammer interference suppression engine 130 to detect a second type of row hammer interference, and in response to detecting a condition in the memory device 100 indicating a second type of row hammer interference, initiates a suppression operation in the memory device. In some examples, the row hammer interference suppression engine 130 may also detect a first type of row hammer interference.

[0034] As used herein, "engine" can refer to one or more hardware processing circuits, which may include any one or a combination of a microprocessor, a core of a multi-core microprocessor, a microcontroller, a programmable integrated circuit, a programmable gate array, or another hardware processing circuit. Alternatively, "engine" can refer to a combination of one or more hardware processing circuits and machine-readable instructions (software and / or firmware) executable on one or more hardware processing circuits.

[0035] In some examples, the row hammer interference suppression engine 130 includes multiple counters associated with each row of memory cells in the memory device 100. For example, a first row of memory cells is associated with a first set of multiple counters, a second row of memory cells is associated with a second set of multiple counters, and so on.

[0036] According to Figure 1 In some examples, two counters, CTRA and CTRB, are associated with each row of memory cells to detect first and second types of row hammer interference. For example, memory cell row 102 is associated with counters CTRA-2 and CTRB-2, memory cell row 104 is associated with counters CTRA-4 and CTRB-4, memory cell row 106 is associated with counters CTRA-6 and CTRB-6, memory cell row 108 is associated with counters CTRA-8 and CTRB-8, memory cell row 110 is associated with counters CTRA-10 and CTRB-10, memory cell row 112 is associated with counters CTRA-12 and CTRA, memory cell row 114 is associated with counters CTRA-14 and CTRB-14, and memory cell row 116 is associated with counters CTRA-16 and CTRB-16.

[0037] In response to activation of an intruder row in a memory cell, the victim row's counter CTRB advances. The intruder row's counter CTRA advances in response to each activation of the intruder row. In some examples, the victim row's counter CTRB advances based on the advance of the adjacent intruder row's counter CTRA.

[0038] In some examples, a "marching" counter can refer to an incrementing counter that can be initialized to an initial low value (e.g., 0 or some other low value). In further examples, a "marching" counter can refer to a decrementing counter that can be initialized to an initial high value (e.g., the maximum value of the counter given the amount of bits used to implement the counter, or some other high value).

[0039] "Counter" can refer to a digital counter or an analog counter. For example... Figure 2A As shown, the example digital counter 200 has logic storing several bits 202-1 to 202-N (N≥2) that collectively represent the count of the counter. In response to a pass control signal 204 provided to the digital counter 200, the digital counter 200 advances its count, such as by 1 or some other increment value. For example, the pass control signal 204 could indicate the activation of an intrusion row in a memory cell, or the advance of another counter.

[0040] like Figure 2B As shown, the example analog counter 210 can be implemented using a circuit arrangement including an operational amplifier 212, a capacitor 214, and a resistor 216. In other examples, alternative circuit arrangements with additional resistors and / or capacitors can be used. The circuit arrangement of analog counter 210 implements an integrator that modulates the input voltage V over time. in Integrate. The output voltage V of the analog counter 210. out Having the property of integrating V over time in The resulting voltage level. The analog counter 210 can effectively maintain V. in The pulses are continuously counted by the analog counter 210. V out The higher the voltage level, the higher the "count" of the analog counter 210. For example, for each V... in A pulse can represent the activation of an intruder row in a memory cell, or the progress of another counter.

[0041] The movement of the counter CTRB can be a scaled movement based on the count of the counter CTRA. A scaled movement of the CTRB can also refer to a movement of the CTRB based on the count of the CTRA weighted by a scaling factor.

[0042] The counter CTRA advances when the associated row of a memory cell is activated. For example, counter CTRA-10 advances in response to the activation of memory cell row 110, counter CTRA-12 advances in response to the activation of memory cell row 112, counter CTRA-14 advances in response to the activation of memory cell row 114, counter CTRA-16 advances in response to the activation of memory cell row 116, and so on.

[0043] The following discusses an example of scaling the movement of the counter CTRB in response to the movement of the counter CTRA. For example, if the scaling factor is... ,in Then, CTRB responds to each of CTRA's... Each person proceeds in turn. For example, if Every 8 increments (or decrements) of CTRA, CTRB increments by one. For example, both CTRA and CTRB can be initialized to 0. The counter CTRA increments in response to successive activations of intruder rows in memory cells. CTRB only increments when CTRA reaches a value of 8, even if CTRA has already incremented from 0 to 7. When CTRA increments from 7 to 8, the counter CTRB increments from 0 to 1. Subsequently, in response to further successive activations of intruder rows in memory cells, CTRA can increment from 8 to 15, but CTRB remains at a value of 1. In response to CTRA incrementing from 15 to 16, the counter increments from 1 to 2.

[0044] The output of counter CTRB is used to detect the second type of horizontal hammer interference, while the output of counter CTRA can be used to detect the first type of horizontal hammer interference.

[0045] In response to the detection of row hammer interference (first type or second type) in a victim row of a memory cell, row hammer interference suppression engine 130 may initiate a suppression action to prevent data loss in the victim row. For example, row hammer interference suppression engine 130 may include memory refresh engine 132 to initiate a refresh operation that refreshes the victim row in which row hammer interference was detected. Memory refresh engine 132 may refresh only the specific victim row in which row hammer interference was detected, or alternatively, memory refresh engine 132 may refresh the refresh area of ​​memory device 100 that includes the victim row in which row hammer interference was detected.

[0046] although Figure 1The memory refresh engine 132 is shown as part of the row hammer interference suppression engine 130; however, in other examples, the memory refresh engine 132 may be separate from the row hammer interference suppression engine 130. In such examples, in response to detecting row hammer interference, the row hammer interference suppression engine 130 may provide a suppression control instruction to the separate memory refresh engine 132 to refresh at least the specific victim row where the row hammer interference was detected. The suppression control instruction may include a signal or message indicating which victim row(s) has experienced row hammer interference, and the memory refresh engine 132 may respond to the suppression control instruction by refreshing at least the indicated victim row(s).

[0047] Type II hammer interference detection

[0048] Figure 3 An example of a counter arrangement for detecting second-type row hammer interference is shown. Counter CTRB-8 is associated with victim row 108, while counters CTRA-10, CTRA-12, CTRA-14, and CTRA-16 are associated with the corresponding intruder rows 110, 112, 114, and 116, which are adjacent rows to victim row 108.

[0049] Intruder rows 110 and 114 are immediately adjacent to victim row 108; that is, there is no memory cell row between intruder rows 110 and 114 and victim row 108. Intruder rows 112 and 116 are distance-adjacent rows to victim row 108. A distance-adjacent row is a row with an intermediate memory cell row between the victim row and the adjacent row.

[0050] exist Figure 3 In the example, it is assumed that the counter CTRB-8 proceeds in response to the activation of four intruder rows on both sides 108-1 and 108-2 of the victim row 108. In a further example, the counter CTRB-8 may proceed in response to the activation of six (or more) intruder rows on both sides 108-1 and 108-2 of the victim row 108 (e.g., three or more intruder rows on each side 108-1 or 108-2 of the victim row 108).

[0051] In the following discussion, it is assumed that counter CTRB-8 and counters CTRA-10, CTRA-12, CTRA-14, and CTRA-16 increment. A similar technique can be applied to decrementing counters.

[0052] Counter CTRB-8 increments in response to the scaling counts of counters CTRA-10, CTRA-12, CTRA-14, and CTRA-16. First weight A first scaling factor is defined to increment CTRB-8 in response to the counts of counters CTRA-10 and CTRA-14 associated with the immediately adjacent intruder rows 110 and 114, and a second weight is defined. A second scaling factor is defined to increment CTRB-8 in response to the counts of counters CTRA-12 and CTRA-16 associated with adjacent intruder rows 112 and 116. Figure 3 In the text, W1 indicates that it is from... The scale counter of the exported scaling factor is the scaling count, W2 represents the scaling count from... The scale count of the exported scaling factor scaling counter.

[0053] The first scaling factor is In other words, CTRB-8 responds to each of CTRA-10 and CTRA-14. Each increases and increases. Figure 3 In this case, W1 equals the count of the counter (CTRA-10 or CTRA-14) multiplied by... More specifically, CTRB-8 responds to each of CTRA-10's... Each increment and independently, CTRB-8 responds to each CTRA-14. The number increases and increases.

[0054] The second scaling factor is In other words, CTRB-8 responds to each of CTRA-12 and CTRA-16. Each increases and increases. Figure 3 In this case, W2 equals the count of the counter (CTRA-12 or CTRA-16) multiplied by... More specifically, CTRB-8 responds to each of CTRA-12 Each increment and independently, CTRB-8 responds to each CTRA-16. Each increases and increases. Because Therefore, the CTRB-8 response to the increments of CTRA-12 and CTRA-16 is less frequent compared to the increments of CTRA-10 and CTRA-14, because the row hammer effect of the intruder rows 112 and 116 on the victim row 108 is less than that of the adjacent rows 110 and 114, since the distance from the intruder rows 112 and 116 is farther from the victim row 108 than the adjacent rows 110 and 114.

[0055] Counter CTRB-8 increments in response to the scaling count of any one of counters CTRA-10, CTRA-12, CTRA-14, and CTRA-16. The scaling counts of CTRA-10, CTRA-12, CTRA-14, and CTRA-16 are provided to the input of logic OR gate 304, which can be implemented using one or more hardware circuits or machine-readable instructions. The output of logic OR gate 304 provides an increment (I) input to counter CTRB-8 (in the example of CTRB-8 incrementing). In other examples of counter CTRB-8 decrementing, the output of logic OR gate 304 is the decrement input of the counter.

[0056] In a further example, the OR gate 304 can receive a further scaled count from an additional counter CTRA associated with an intruder row that is farther away than an intruder row. In such a further example, additional scaled counts W3, etc., can be input to the OR gate 304 to cause the counter CTRB-8 to advance.

[0057] The CTRB-8 count is compared by the line hammer interference suppression engine 130 with a threshold T2. The threshold T2 can be a configuration parameter stored in a storage medium (such as a configuration register or another type of storage medium) within the memory device 100. In the example of counter incrementing, if the line hammer interference suppression engine 130 determines that the CTRB-8 count exceeds the threshold T2, the line hammer interference suppression engine 130 activates a line hammer indicator to indicate that the associated victim line 108 has experienced line hammer interference. In response to the line hammer indicator, the memory refresh engine 132 can refresh the line including the victim line 108.

[0058] In other examples of counter decrement, if the line hammer interference suppression engine 130 determines that the count of CTRB-8 is less than the threshold T2, the line hammer interference suppression engine 130 activates the line hammer indicator to indicate that the associated victim line 108 has experienced line hammer interference.

[0059] In some examples, ,at the same time Typically, the scaling of the CTRB counter associated with the victim's row is based on a weight that increases proportionally to the distance from the intruder's row to the victim's row.

[0060] In a further example, different scaling techniques can be used to define a scaling factor for the counter CTRB based on the count of the associated counter CTRA.

[0061] In the example where the counter is an analog counter, the scaling factor can be based on the use of an isolation amplifier. Figure 4An example scaling circuit 400 for an analog counter is shown. The scaling circuit 400 includes an isolation amplifier 402 and a voltage divider formed by resistors R1 and R2. Based on the relative resistances of R1 and R2, the voltage divider reduces the input voltage V isolated to the amplifier 402. isol The input voltage V isol It is the input voltage V to the scaling circuit 400. sin A portion (less than 1).

[0062] Assuming isolation amplifier 402 has unity gain, isolation amplifier 402 generates voltage equal to V. isol Scaled output voltage V sout Scaled output voltage V sout It can be used as an input to an analog counter, such as... Figure 2B The V of the analog counter 210 in The isolation amplifier 402 provides V sin and V sout Electrical isolation between them to prevent the operation of analog counter 210 from changing V sin The voltage level. The scaling of the application is based on the relative resistances of resistors R1 and R2.

[0063] More specifically, V isol = V sin ,in In this example, the scaling factor is... .

[0064] In other examples, if the isolation amplifier 402 has a gain less than 1, the voltage divider including resistors R1 and R2 can be omitted. The gain of the isolation amplifier 402 is less than 1. ) provides scaling factor .

[0065] Each counter CTRB has a reset (R) input, which, when activated, triggers the CTRB to reset to its initial value (e.g., an initial low or initial high value). Figure 3In the example, counter CTRB-8 has a reset input connected to reset indicator 302. Reset indicator 302 (e.g., a reset signal or any other type of indicator) is activated in response to an operation accessing victim row 108. For example, reset indicator 302 may be activated in response to a refresh operation that refreshes the refresh area (of memory device 100) including victim row 108. As another example, reset indicator 302 may be activated in response to a read or write to victim row 108. A refresh or read / write access is used to restore the memory cells of victim row 108 to their respective states, allowing counter CTRB-8 to be reset and the row hammer detection process to restart for victim row 108.

[0066] In the example of refreshing a refresh region with multiple memory cell rows in a refresh operation, the counters CTRB associated with the multiple memory cell rows can be reset in response to the refresh operation.

[0067] Each of the other rows of memory device 100 is associated with a counter CTRB, which proceeds in a similar manner based on a scaled count from a counter CTRA associated with the set of the corresponding intruder rows.

[0068] Type 1 hammer interference detection

[0069] As described above, the counter CTRA associated with each row of memory cells can be used to detect the first type of row hammer interference.

[0070] The following example assumes an incrementing counter.

[0071] Assumption Figure 1 For example, intruder line 102 may cause line hammer interference to adjacent victim lines 104 and 106. In response to each activation of intruder line 102, the counter CTRA-2 associated with intruder line 102 increments.

[0072] The row hammer interference suppression engine 130 compares the count of counter CTRA-2 with a threshold T1. Threshold T1 can be a configuration parameter stored in a storage medium (such as a configuration register or another type of storage medium) within the memory device 100. In the example of counter incrementing, if the count of counter CTRA-2 exceeds threshold T1, the row hammer interference suppression engine 130 can cause a refresh of a refresh region (or multiple refresh regions), including victim rows 104 and 106, which are neighbors of the intruder row 102.

[0073] In the example of counter decrement, if the count of counter CTRA-2 is less than the threshold T1, the row hammer interference suppression engine 130 may cause the refresh of the refresh area (or multiple refresh areas) including victim rows 104 and 106.

[0074] Further examples

[0075] Figure 5A An example portion of a memory device is shown, which includes circuitry for five rows of memory cells (rows x-2, x-1, x, x+1, and x+2). Rows x-1 and x+1 are the immediate neighbors of row x, and rows x-2 and x+2 are the neighbors of row x at a distance of one adjacent row.

[0076] Row x is associated with counters CA and CB. Figure 5A In the table, "CA" represents the counter CTRA discussed above, and "CB" represents the counter CTRB discussed above. Row x-1 is associated with counters CA-1 and CB-1, and row x+1 is associated with counters CA+1 and CB+1. Row x-2 is associated with counters CA-2 and CB-2, and row x+2 is associated with counters CA+2 and CB+2.

[0077] Each counter CA-2, CA-1, CA, CA+1, and CA+2 outputs its own scaling count W1 (based on...). ) and their respective scaling counts W2 (based on ).

[0078] The following assumptions Figure 5A The counter is an incrementing counter. A decrementing counter can use a similar mechanism.

[0079] Counter CA-2 increments in response to the activation of row x-2 (“row activated x-2”), counter CA-1 increments in response to the activation of row x-1 (“row activated x-1”), counter CA increments in response to the activation of row x (“row activated x”), counter CA+1 increments in response to the activation of row x+1 (“row activated x+1”), and counter CA+2 increments in response to the activation of row x+2 (“row activated x+2”).

[0080] In response to a refresh (“refresh”) of the refresh area including counters CA-2, CA-1, CA, CA+1 and CA+2, counters CA-2, CA-1, CA, CA+1 and CA+2 are reset.

[0081] Each of the counters CB-1, CB, and CB+1 increments in response to a scaling count from a set of four adjacent rows; in other examples, each of the counters CB-1, CB, or CB+1 increments in response to a scaling count from a set of six or more adjacent rows. Counter CB-1 increments in response to the active output of OR gate 502-1, counter CB increments in response to the active output of OR gate 502, and counter CB+1 increments in response to the active output of OR gate 502+1.

[0082] Logic OR gate 502-1 receives the following scaling counts: W2 from counter CA-3 (which is associated with row x-3 three rows away from row x), W1 from counter CA-2, W1 from counter CA, and W2 from counter CA+1. Logic OR gate 502+1 receives the following scaling counts: W2 from counter CA-2, W1 from counter CA-1, W1 from counter CA+1, and W2 from counter CA+2.

[0083] exist Figure 5A In the table, "CB-2" refers to the counter CTRB associated with row x-2, "CB-3" refers to the counter CTRB associated with row x-3, and "CB-4" refers to the counter CTRB associated with row x-4 (which is four rows away from row x).

[0084] exist Figure 5A In the table, "CB+2" refers to the counter CTRB associated with row x+2, "CB+3" refers to the counter CTRB associated with row x+3, and "CB+4" refers to the counter CTRB associated with row x+4 (which is four rows away from row x).

[0085] In response to the activation of row x-1 (due to a read or write access to row x-1 or a refresh of row x-1), counter CB-1 is reset; in response to the activation of row x (due to a read or write access to row x or a refresh of row x), counter CB is reset; and in response to the activation of row x+1 (due to a read or write access to row x+1 or a refresh of row x+1), counter CB+1 is reset.

[0086] To detect the second type of horizontal hammer interference, comparator 504-1 of the horizontal hammer interference suppression engine 130 compares the count of counter CB-1 with a threshold T2, and activates the horizontal hammer interference indicator RH2 if the count of counter CB-1 is equal to (or greater than or equal to) T2. Comparator 504+1 of the horizontal hammer interference suppression engine 130 compares the count of counter CB+1 with the threshold T2, and activates the horizontal hammer interference indicator RH2 if the count of counter CB+1 is equal to (or greater than or equal to) T2.

[0087] RH2 activation indicates that a second type of row hammer interference has occurred and causes suppression actions (e.g., refresh operations) to be taken for victim rows affected by the second type of row hammer interference.

[0088] To detect the first type of horizontal hammer interference, comparator 506-2 of the horizontal hammer interference suppression engine 130 compares the count of counter CA-2 with the threshold T1, and activates the horizontal hammer interference indicator RH1 if the count of counter CA-2 is equal to (or greater than or equal to) T1. Comparator 506-1 of the horizontal hammer interference suppression engine 130 compares the count of counter CA-1 with the threshold T1, and activates the horizontal hammer interference indicator RH1 if the count of counter CA-1 is equal to (or greater than or equal to) T1. Comparator 506 of the horizontal hammer interference suppression engine 130 compares the count of counter CA with the threshold T1, and activates the horizontal hammer interference indicator RH1 if the count of counter CA is equal to (or greater than or equal to) T1. Comparator 506+1 of the horizontal hammer interference suppression engine 130 compares the count of counter CA+1 with the threshold T1, and activates the horizontal hammer interference indicator RH1 if the count of counter CA+1 is equal to (or greater than or equal to) T1. The comparator 506+2 of the walking hammer interference suppression engine 130 compares the count of counter CA+2 with the threshold T1, and if the count of counter CA+2 is equal to (or greater than or equal to) T1, the walking hammer interference indicator RH1 is activated.

[0089] exist Figure 1 , 3 In 5A, the counter CTRA can be called the "intruder counter" because it represents the amount of activation of a row that can cause row hammer interference in adjacent rows. The counter CTRB can be called the "victim counter" because it contains a count of victim rows.

[0090] exist Figure 5A In the memory cell that is the intruder of row x, the adjacent rows include rows x-1, x-2, x+1, and x+2.

[0091] Rows x-1 and x-2 are on the first side of row x, and rows x+1 and x+2 are on different second sides of row x. Each of rows x-1 and x+1 is a direct neighbor of row x, while each of rows x-2 and x+2 is a distance-adjacent neighbor of row x. Same weight. The counters CA-1 and CA+1 used for scaling the CB for row x are counted with the same weight. The counters CA-2 and CA+2 used to scale the CB for row x are used for counting, where Greater than .

[0092] The controller in the memory device is based on the count activation line x of the victim counter (CB). "Controller" can refer to one or more hardware processing circuits, or a combination of one or more hardware processing circuits and machine-readable instructions executable by one or more hardware processing circuits. As an example, the controller may include... Figure 1 The hammer interference suppression engine 130.

[0093] The controller activates row x by refreshing the refresh region of the memory device, where the refresh region includes row x.

[0094] The controller activates line x based on the count of the victim counter (CB), which has a specific relationship with respect to a threshold (e.g., if the victim counter is an incrementing counter, then the count of counter CB is equal to (or greater than or equal to) T2, or if the victim counter is a decrementing counter, then the count of counter CB is equal to (or less than or equal to) T2).

[0095] Figure 5B An example portion of a memory device is shown, which includes circuitry for five rows of memory cells (rows x-2, x-1, x, x+1, and x+2). Rows x-1 and x+1 are the immediate neighbors of row x, and rows x-2 and x+2 are the neighbors of row x at a distance of one adjacent row.

[0096] According to other examples in this disclosure, Figure 5B The circuit is used to detect hammer interference. Figure 5B The horizontal hammer interference detection circuit does not distinguish between the first and second types of horizontal hammer interference; it only indicates that horizontal hammer interference has occurred.

[0097] Figure 5B The row hammer interference detection circuit includes intruder counters CA-2, CA-1, CA, CA+1 and CA+2 associated with the corresponding rows x-2, x-1, x, x+1 and x+2.

[0098] exist Figure 5B In the example, assume the count W1 is This allows the corresponding row activation signal to be used as W1, as an input to the corresponding OR gates 522-1, 522, and 522 (and other OR gates).

[0099] Each counter CA-2, CA-1, CA, CA+1, or CA+2 can output corresponding scaling counts W2 to Wn (n≥2), where scaling count W2 will advance the victim counter (e.g., CB-1, CB, or CB+1) to reflect row hammer interference at a distance of one row, and scaling count Wn will advance the victim counter (e.g., CB-1, CB, or CB+1) to reflect row hammer interference at a distance of (n-1) rows. The distance of (n-1) rows is the intruder row, where there are (n-1) inserted memory cell rows between the victim row and the intruder row.

[0100] W2 indicates that it is from The scale count of the scale factor derived from the scale counter, Wn, represents the scale count derived from the scale factor derived from the scale factor derived from the scale counter. The exported scaling factor is a scaling counter for the scaling count. Although in Figure 5B Not shown, but the scaled count Wn from the intruder counters CA-2, CA-1, CA, CA+1 and CA+2 can be provided as further input to logic OR gates (e.g. 522-1, 522 and 522+1).

[0101] Although Figure 5A The counters CA-2, CA-1, CA, CA+1, and CA+2 are not shown, but each of them can also output its own scaled count Wn.

[0102] Counter CB-1 increments in response to the active output from logic OR gate 522-1, counter CB increments in response to the active output from logic OR gate 522, and counter CB+1 increments in response to the active output from logic OR gate 522+1.

[0103] To detect row hammer interference, comparator 524-1 of row hammer interference suppression engine 130 compares the count of counter CB-1 with a threshold T, and activates the row hammer interference indicator RH(row x-1) if the count of counter CB-1 is equal to (or greater than or equal to) T. Comparator 524 of row hammer interference suppression engine 130 compares the count of counter CB with the threshold T, and activates the row hammer interference indicator RH(row x) if the count of counter CB is equal to (or greater than or equal to) T. Comparator 524+1 of row hammer interference suppression engine 130 compares the count of counter CB+1 with the threshold T, and activates the row hammer interference indicator RH(row x+1) if the count of counter CB+1 is equal to (or greater than or equal to) T.

[0104] When activated, the hammer interference indicator RH(line x-1) indicates that the victim's line x-1 has experienced hammer interference. When activated, the hammer interference indicator RH(line x) indicates that the victim's line x has experienced hammer interference. When activated, the hammer interference indicator RH(line x+1) indicates that the victim's line x+1 has experienced hammer interference.

[0105] The row hammer interference indicators RH(x-1 row), RH(x row), and RH(x+1 row) provide indications of row hammer interference for each row.

[0106] The outputs of comparators 524-1, 524, and 524-2 can also be provided to the inputs of corresponding buffers 526-1, 526, and 526+1 (e.g., tri-state buffers). The outputs of buffers 526-1, 526, and 526+1 are connected to the RH signal. In effect, the set of buffers 526-1, 526, and 526+1 provides a logical OR operation such that when any of the row hammer interference indicators RH(row x-1), RH(row x), and RH(row x+1) are active, the RH signal is activated to provide an indication that a row hammer interference has occurred in at least one victim row of the memory device.

[0107] Despite Figure 5A Not shown in the image, but Figure 5A The horizontal hammer interference detection circuit can similarly generate individual horizontal hammer interference indicators, such as RH(row x-1), RH(row x), and RH(row x+1), where Figure 5A RH2 in the equation is the logical OR of these signals, where logical OR can be used with parameters such as... Figure 5B It is implemented using buffers of 526-1, 526, and 526+1.

[0108] Figure 6 It is a flowchart of process 600 based on some examples.

[0109] Process 600 includes, in response to activation of the corresponding row of a memory cell, proceeding (at 602) to an intruder counter for the corresponding row of the memory cell. For example, the intruder counter could be... Figure 1 , 3 The counters described in section 5, CTRA or CA, can be used. A moving intruder counter can include an incrementing or decrementing intruder counter.

[0110] Process 600 includes, in response to the advance of an intruder counter for an adjacent row of a memory cell that is a neighbor of the first victim row, advancing (at 604) the first victim counter of the memory cell in the memory device for the first victim row. For example, the victim counter could be... Figure 1 , 3The CTRB or CB counters described in section 5. The moving victim counter may include an incrementing or decrementing victim counter.

[0111] In some examples, the first victim counter advances in response to a first scaling count of the first intruder counter in the first adjacent row of the adjacent row, wherein the first scaling count is based on a first weight. In some examples, the first victim counter advances further in response to a second scaling count of the second intruder counter in the second adjacent row of the adjacent row, wherein the second scaling count is based on a second weight.

[0112] In some examples, the first weight corresponds to the first distance from the first adjacent row to the first victim row, and the second weight corresponds to the second distance from the second adjacent row to the first victim row.

[0113] Process 600 includes comparing the count of the first victim counter with a threshold (at 606) (e.g., comparing the count of counter CTRB or CB with T2).

[0114] Based on this comparison, process 600 includes detecting (at 608) row hammer interference in the first victim row and initiating (at 610) a suppression action against the row hammer interference in the first victim row. The suppression action may include refreshing the refresh area including the first victim row.

[0115] In some examples, Figure 1 The hammer interference suppression engine 130 can be implemented using machine-readable instructions. Figure 7 This is a block diagram of a non-transitory machine-readable or computer-readable storage medium 700 that stores machine-readable instructions, which, when executed, cause a controller in the memory device to perform various tasks. For example, the machine-readable instructions stored in storage medium 700 could be instructions for a line hammer interference suppression engine 130.

[0116] The machine-readable instructions include a victim counter count receiving instruction 702 to receive a count of a first victim counter for a first victim row of memory cells in a memory device, the first victim counter advancing in response to a scaling count of an intruder counter for an adjacent row of memory cells that is a neighbor of the first victim row. The scaling count includes a first scaling count based on a first scaling factor of the first intruder counter associated with a first adjacent row of the adjacent row, and a second scaling count based on a second scaling factor of a second intruder counter associated with a second adjacent row of the adjacent row, wherein the first scaling factor is different from the second scaling factor.

[0117] The machine-readable instructions include a count comparison instruction 704 to compare the count of the first victim counter with a threshold.

[0118] The machine-readable instructions include a row hammer interference suppression instruction 706, which detects row hammer interference in the first row based on the comparison and initiates a suppression action against row hammer interference in the first row.

[0119] Storage medium 700 may include any one or a combination of the following: semiconductor memory devices, such as dynamic or static random access memory (DRAM or SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory; magnetic disks, such as fixed disks, floppy disks, and removable disks; another magnetic medium, including magnetic tape; optical media, such as optical discs (CDs) or digital video discs (DVDs); or another type of storage device. Note that the instructions discussed above may be provided on a single computer-readable or machine-readable storage medium, or alternatively, on multiple computer-readable or machine-readable storage media distributed across a large system that may have multiple nodes. Such computer-readable or machine-readable storage media is considered part of an article (or manufactured article). An article or manufactured article may refer to any single or multiple manufactured components. One or more storage media may be located in a machine that executes machine-readable instructions, or at a remote site from which machine-readable instructions can be downloaded via a network for execution.

[0120] In the foregoing description, numerous details have been set forth to provide an understanding of the subject matter disclosed herein. However, implementations can be carried out without these details. Other implementations may include modifications and variations to the foregoing details. The appended claims are intended to cover such modifications and variations.

Claims

1. A memory device, comprising: Multiple rows of memory cells; Multiple victim counters are associated with corresponding memory cell rows of the multiple memory cell rows; as well as Multiple intruder counters are associated with the corresponding memory cell rows. Wherein, the first victim counter of the plurality of victim counters is associated with the first row of the plurality of memory cell rows, the count of the first victim counter is used to advance in response to the count of the intruder counter associated with the adjacent row of the memory cell that is a neighbor of the first row, and wherein the count of the first victim counter represents the amount of row hammer interference of the first row due to the activation of the adjacent row of the memory cell.

2. The memory device according to claim 1, wherein, The adjacent rows of the memory cells include a first adjacent row of memory cells and a second adjacent row of memory cells, and the intruder counter associated with the adjacent rows of the memory cells includes a first intruder counter associated with the first adjacent row of the memory cells and a second intruder counter associated with the second adjacent row of the memory cells, and The first victim counter is used to advance in response to a first scaling count of the first intruder counter.

3. A memory device, comprising: Multiple rows of memory cells; Multiple victim counters are associated with corresponding memory cell rows of the multiple memory cell rows; as well as Multiple intruder counters are associated with the corresponding memory cell rows. Wherein, a first victim counter of the plurality of victim counters is associated with a first row of the plurality of memory cell rows, the first victim counter being configured to advance in response to the counting of intruder counters associated with adjacent rows of memory cells that are neighbors of the first row, wherein the adjacent rows of memory cells include a first adjacent row of memory cells and a second adjacent row of memory cells, and the intruder counters associated with the adjacent rows of memory cells include a first intruder counter associated with the first adjacent row of memory cells and a second intruder counter associated with the second adjacent row of memory cells, and The first victim counter is used to advance in response to a first scaling count of the first intruder counter and a second scaling count of the second intruder counter, the first scaling count being based on a first weight and the second scaling count being based on a second weight.

4. The memory device according to claim 3, wherein, The first adjacent row of the memory cell is located on a first side of the first row, the second adjacent row of the memory cell is located on a different second side of the first row, and wherein the first weight is equal to the second weight.

5. The memory device according to claim 3, wherein, The first adjacent row of the memory cell is located between the first row and the second adjacent row of the memory cell, wherein the first weight is greater than the second weight.

6. The memory device according to claim 3, wherein, The first scaled count of the first intruder counter is based on the count of the first intruder counter scaled according to the first weight, and the second scaled count of the second intruder counter is based on the count of the second intruder counter scaled according to the second weight.

7. The memory device according to claim 3, wherein, The adjacent rows of the memory cells also include a third adjacent row of memory cells and a fourth adjacent row of memory cells, and the intruder counter associated with the adjacent rows of the memory cells includes a third intruder counter associated with the third adjacent row of the memory cells and a fourth intruder counter associated with the fourth adjacent row of the memory cells, and The first victim counter is used to advance in response to a third scaling count of the third intruder counter and a fourth scaling count of the fourth intruder counter.

8. The memory device according to claim 7, wherein, The third scaling count is based on the first weight, and the fourth scaling count is based on the second weight, wherein the second weight is different from the first weight.

9. The memory device according to claim 1, further comprising: A controller is used to activate the first row based on the count of the first victim counter.

10. The memory device according to claim 9, wherein, The controller is configured to activate the first row by refreshing a refresh region of the memory device, the refresh region including the first row.

11. The memory device according to claim 9, wherein, The controller is used to activate the first row based on the count of the first victim counter, which has a specified relationship with respect to a threshold.

12. The memory device of claim 1, further comprising: A controller, configured to reset the first victim counter in response to access to the first row.

13. The memory device according to claim 1, wherein, The first victim counter is used to advance by incrementing or decrementing the count of the first victim counter.

14. The memory device according to claim 1, wherein, The first victim counter may be a digital counter or an analog counter.

15. The memory device according to claim 1, wherein, The travel input of the first victim counter is connected to the output of a logic OR gate, which has an input connected to the output of the intruder counter.

16. The memory device according to claim 1, wherein, The first victim counter is used to detect a given type of row hammer interference, wherein multiple intruder rows of the memory cell interfere with the target victim row of the memory cell, and Among them, the first intruder counter of the plurality of intruder counters is used to detect different types of row hammer interference, wherein the first intruder row interference memory unit associated with the first intruder counter is a plurality of victim rows.

17. A method for using a memory device, comprising: Based on the activation of the corresponding memory cell row, the intruder counter of the corresponding memory cell row is advanced; The first victim counter of the memory cell in the memory device travels based on the travel of the intruder counter of the adjacent row of the memory cell that is a neighbor of the first victim row, wherein the travel of the first victim counter includes: In response to a first scaling count of a first intruder counter for a first adjacent row of the memory cell, the first victim counter is advanced, the first scaling count being based on a first weight; In response to a second scaled count of a second intruder counter for a second adjacent row of the memory cell, the first victim counter is advanced, the second scaled count being based on a second weight different from the first weight; and Compare the count of the first victim counter with a threshold; and Based on the comparison, a row hammer interference is detected in the first victim row, and a suppression action is initiated for the row hammer interference in the first victim row.

18. The method according to claim 17, wherein, The first weight corresponds to the first distance from the first adjacent row to the first victim row, and the second weight corresponds to the second distance from the second adjacent row to the first victim row.

19. A non-transitory machine-readable storage medium, comprising instructions that, when executed, cause a controller in a memory device to: The device receives a count from a first victim counter of a first victim row of memory cells in the memory device. The first victim counter is configured to advance in response to a scaling count from an intruder counter of an adjacent row of memory cells that is a neighbor of the first victim row. The scaling count includes a first scaling count based on a first scaling factor of a first intruder counter associated with a first adjacent row of the adjacent row, and a second scaling count based on a second scaling factor of a second intruder counter associated with a second adjacent row of the adjacent row, wherein the first scaling factor is different from the second scaling factor. Compare the count of the first victim counter with the threshold; as well as Based on the comparison, a row hammer interference is detected in the first victim row, and a suppression action is initiated for the row hammer interference in the first victim row.

20. The non-transitory machine-readable storage medium according to claim 19, wherein, The count of the first victim counter represents the amount of row hammer interference of the first victim row due to the activation of adjacent rows of the memory cell.

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