A New Digital Signal Distribution Module

Abstract

The present invention provides a novel digital signal distribution module, which relates to the technical field of signal transmission equipment, and includes a data input unit, a filtering unit, a signal processing unit, an encryption unit, a data sending unit, a data receiving unit, a decoding unit, a verification unit, a feedback unit, and a signal output unit. The present invention can protect the transmitted data, avoid data leakage, and improve the security of data transmission. Through the verification unit, the transmitted data can be detected to determine whether the data is missing or tampered with during transmission, and the quality of data transmission can be detected to ensure the integrity and correctness of the data. At the same time, according to the verification result of the data, it is determined whether the data can be output. If the data is abnormal during the transmission process, it can avoid outputting the abnormal data, and automatically apply for retransmission of the data, which further improves the security and correctness of data transmission.

Description

Technical Field

[0001] The invention relates to the technical field of metering signal transmission equipment, in particular to a novel digital signal distribution module. Background Art

[0002] Digital signal distribution modules are usually used to manage and distribute digital signals, allowing connections to be established between different inputs and outputs, and are usually used in base station communications, industrial automation, data transmission and other fields. However, in the prior art, the functions of digital signal distribution modules are relatively simple, and they can only distribute and manage digital signals, but cannot guarantee the security of data transmission, nor can they detect whether data is missing or tampered with during transmission. It is difficult to ensure the quality of transmission, and the applicability is not strong.

[0003] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The purpose of the present invention is to provide a novel digital signal distribution module to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A novel digital signal distribution module, comprising:

[0007] A data input unit, the data input unit is electrically connected to the filter unit, and is used to receive initial data and send the initial data to the filter unit;

[0008] A filtering unit, the filtering unit being electrically connected to the signal processing unit and configured to perform denoising on the initial data and send the denoised initial data to the signal processing unit;

[0009] A signal processing unit, the signal processing unit is electrically connected to the feedback unit and the encryption unit, and is used to process the initial data once to generate processed data, and then send the processed data to the encryption unit for encryption after port allocation, and is used to receive feedback instructions and repeatedly send the data according to the feedback instructions;

[0010] An encryption unit, the encryption unit being electrically connected to the data sending unit, and configured to encrypt the processed data to generate encrypted data, and send the encrypted data to the data sending unit;

[0011] A data sending unit, the data sending unit is communicatively connected with the data receiving unit and is used to send the encrypted data to the data receiving unit;

[0012] A data receiving unit, the data receiving unit is electrically connected to the decoding unit, and is used to receive the encrypted data and send the encrypted data to the decoding unit;

[0013] A decoding unit, the decoding unit being electrically connected to the verification unit, and configured to decode the encrypted data to obtain decoded data, and send the decoded data to the verification unit;

[0014] A verification unit, the verification unit is electrically connected to the feedback unit and the data output unit, and is used to verify the decoded data and then send it to the data output unit, and send the verification result to the feedback unit;

[0015] A feedback unit, the feedback unit being electrically connected to the signal processing unit and configured to generate a feedback instruction according to the verification result and send the feedback instruction to the signal processing unit;

[0016] A signal output unit, wherein the signal output unit is used to output the verified decoded data.

[0017] Preferably, the generation logic of the processing data is:

[0018] Generate a sequence number frame Axh and a time frame Asj of the initial data Acs according to the receiving time and receiving order of the initial data Acs;

[0019] Generate a check frame Ajy according to the total number of bits of the initial data Acs;

[0020] The sequence frame Axh, the time frame Asj, the check frame Ajy, and the initial data Acs are concatenated to obtain the processed data.

[0021] Preferably, the generation logic of the check frame Ajy is:

[0022] Mark each character on the initial data Acs as The subscript x represents the number of digits of the initial data Acs, and the superscript X represents the total number of digits of the initial data Acs. The total number of digits Y of the check frame Ajy is calculated based on the total number of digits X of the initial data Acs. The calculation formula is:

[0023]

[0024] Mark each character on the check frame Ajy as The calculation formula is:

[0025]

[0026] The subscript y represents the bit number of the check frame Ajy, y=1,2,3…Y.

[0027] Preferably, the logic for encrypting the processed data is:

[0028] For each character on the initial data Acs Invert it and then replace the X character Divide it into N initial character segments from right to left, and mark the initial character segment as Wcs n , the number of characters in each initial character segment is 4, the subscript n represents the number of the initial character segment, and n is a positive integer;

[0029] According to the initial character segment Wcs n Generate conversion character segment Wzh i , the calculation formula is:

[0030]

[0031] Convert the character segment Wzh i Sort from right to left in the order of the subscript i from small to large to generate conversion data Azh, and concatenate the sequence frame Axh, the time frame Asj, the check frame Ajy, and the conversion data Azh to obtain encrypted data.

[0032] Preferably, the logic for decoding the encrypted data is:

[0033] The encrypted data is split into a sequence frame Axh, a time frame Asj, a check frame Ajy, and a conversion data Azh. The conversion data Azh is divided from right to left into N conversion character segments Wzh. i , and then according to the conversion character segment Wzh i Get the decoded character segment Wjm j , the calculation formula is:

[0034]

[0035] The decoded character segment Wjm j Sort from right to left in the order of the subscript j from small to large, and then invert each character to generate the decoded data Ajm.

[0036] Preferably, the logic for verifying the decoded data is:

[0037] Mark each character on the decoded data Ajm as The subscript z represents the number of bits of the decoded data Ajm, and the superscript Z represents the total number of bits of the decoded data Ajm;

[0038] Each character on the check frame Ajy will be The character corresponding to the decoded data Ajm For comparison, the corresponding relationship is:

[0039] z=2 y

[0040] If each character on the check frame Ajy All correspond to the characters on the decoded data Ajm If they are equal, the verification result θ=0;

[0041] If there are characters on the check frame Ajy The character corresponding to the decoded data Ajm If they are not equal, the verification result θ=1.

[0042] Preferably, when the check result θ=0, the signal output unit outputs the decoded data, and the feedback unit does not generate a feedback instruction; when the check result θ=1, the signal output unit does not output the decoded data, and the feedback unit generates a feedback instruction.

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows: by setting an encryption unit and a decoding unit, the present invention can protect the transmitted data, avoid data leakage, and improve the security of data transmission; by setting a verification unit, the transmitted data can be detected to determine whether the data is missing or tampered with during transmission; the quality of data transmission can be detected to ensure the integrity and correctness of the data; at the same time, by setting a feedback unit, it can be determined whether the data can be output based on the verification result of the data; if the data is abnormal during the transmission process, the output of the abnormal data can be avoided, and an application for retransmission of the data can be automatically applied, which further improves the security and correctness of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic diagram of the overall module structure of the present invention. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0046] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0047] Embodiment 1:

[0048] See also Figure 1 , the present invention provides a technical solution:

[0049] A novel digital signal distribution module comprises: a data input unit, a filtering unit, a signal processing unit, an encryption unit, a data sending unit, a data receiving unit, a decoding unit, a verification unit, a feedback unit and a signal output unit.

[0050] The data input unit is an input interface, electrically connected to the filter unit, for receiving various data input sources, such as digital signals sent by communication equipment, audio and video equipment, etc. as initial data, and sending the initial data to the filter unit.

[0051] The filter unit is a communication filter chip of the AD9361 series, which is electrically connected to the signal processing unit and is used for denoising the initial data and sending the denoised initial data to the signal processing unit.

[0052] The signal processing unit adopts the DSP processor chip of the TMS320C6748 series, which is electrically connected to the feedback unit and the encryption unit. It is used to process the initial data once to generate processed data, which is then sent to the encryption unit for encryption after port allocation. It is also used to receive feedback instructions and repeatedly send data according to the feedback instructions.

[0053] The encryption unit adopts an encryption chip of the NXP A71CH series, which is electrically connected to the data sending unit, and is used to encrypt the processed data to generate encrypted data, and send the encrypted data to the data sending unit.

[0054] The data sending unit is communicatively connected to the data receiving unit, and can be connected by a network interface or RF communication, and is used to send encrypted data to the data receiving unit. The data receiving unit is electrically connected to the decoding unit, and is used to receive encrypted data and send the encrypted data to the decoding unit.

[0055] The decoding unit is electrically connected to the verification unit, and uses an encryption chip of the same model as the encryption unit to decode the encrypted data to obtain decoded data, and send the decoded data to the verification unit. The verification unit is electrically connected to the feedback unit and the data output unit, and is used to verify the decoded data and then send it to the data output unit, and send the verification result to the feedback unit.

[0056] The feedback unit is electrically connected to the signal processing unit, and is used to generate a feedback instruction according to the verification result, and send the feedback instruction to the signal processing unit. The signal output unit is an output interface, and is used to output the verified decoded data.

[0057] The generation logic of the processing data is:

[0058] According to the reception time and reception order of the initial data Acs, the sequence number frame Axh and time frame Asj of the initial data Acs are generated.

[0059] The check frame Ajy is generated according to the total number of bits of the initial data Acs.

[0060] The sequence frame Axh, the time frame Asj, the check frame Ajy, and the initial data Acs are concatenated to obtain the processed data.

[0061] The generation logic of the check frame Ajy is:

[0062] Mark each character on the initial data Acs as The subscript x represents the number of digits of the initial data Acs, and the superscript X represents the total number of digits of the initial data Acs. The total number of digits Y of the check frame Ajy is calculated based on the total number of digits X of the initial data Acs. The calculation formula is:

[0063]

[0064] Mark each character on the check frame Ajy as The calculation formula is:

[0065]

[0066] The subscript y represents the bit number of the check frame Ajy, y=1,2,3…Y.

[0067] The logic for encrypting the processed data is:

[0068] For each character on the initial data Acs Invert it and then replace the X character Divide it into N initial character segments from right to left, and mark the initial character segment as Wcs n , the number of characters in each initial character segment is 4, the subscript n represents the number of the initial character segment, and n is a positive integer.

[0069] According to the initial character segment Wcs n Generate conversion character segment Wzh i , the calculation formula is:

[0070]

[0071] Convert the character segment Wzh i Sort from right to left in the order of the subscript i from small to large to generate conversion data Azh, and concatenate the sequence frame Axh, the time frame Asj, the check frame Ajy, and the conversion data Azh to obtain encrypted data.

[0072] The logic for decoding the encrypted data is:

[0073] The encrypted data is split into a sequence frame Axh, a time frame Asj, a check frame Ajy, and a conversion data Azh. The conversion data Azh is divided from right to left into N conversion character segments Wzh. i , and then according to the conversion character segment Wzh i Get the decoded character segment Wjm j , the calculation formula is:

[0074]

[0075] The decoded character segment Wjm j Sort from right to left in the order of the subscript j from small to large, and then invert each character to generate the decoded data Ajm.

[0076] The logic for verifying the decoded data is:

[0077] Mark each character on the decoded data Ajm as The subscript z represents the number of bits of the decoded data Ajm, and the superscript Z represents the total number of bits of the decoded data Ajm;

[0078] Each character on the check frame Ajy will be The character corresponding to the decoded data Ajm For comparison, the corresponding relationship is:

[0079] z=2 y

[0080] If each character on the check frame Ajy All correspond to the characters on the decoded data Ajm If they are equal, the verification result θ=0, and it is considered that the decoded data Ajm has not been lost or tampered with during transportation.

[0081] If there are characters on the check frame Ajy The character corresponding to the decoded data Ajm If they are not equal, the verification result θ=1, and it is considered that the decoded data Ajm is missing or tampered with during transportation.

[0082] When the check result θ=0, the decoded data Ajm is normal, the signal output unit outputs the decoded data, the feedback unit does not generate a feedback instruction, and there is no need to resend the initial data Acs. When the check result θ=1, the decoded data Ajm is abnormal, the signal output unit does not output the decoded data, the feedback unit generates a feedback instruction, and resends the initial data Acs.

[0083] Embodiment 2:

[0084] See also Figure 1 The difference between this embodiment and embodiment 1 is that this embodiment specifically illustrates the process of the present invention by giving examples:

[0085] In this embodiment, the user wants to use the present invention to transmit the letters "HELLO", and the data source converts it into the binary ASCII code "0100100001000101010011000100110001001111" in advance. The data input unit receives this group of digital signals as the initial data Acs on November 30, 23, and it is the first group of signals received that day. Therefore, the sequence frame Axh is converted to binary "1", and the time frame Asj is converted to binary "111000011011101010".

[0086] The total number of bits of the initial data Acs is X=40, so the total number of bits of the check frame Ajy is Y=3. Check frame Ajy=011.

[0087] The initial data Acs is inverted to get "10110111101110101011001110110000", and then divided from right to left into 10 groups of initial character segments Wcs n , each initial character segment Wcs n There are 4 digits in it, Wcs1 = 0000, Wcs2 = 1011, Wcs3 = 0011...Wcs 14 =1011, and then according to 10 groups of initial character segments Wcs nGet 10 sets of conversion character segments Wzh i , Wzh1=1011, Wzh2=0011…Wzh 13 =1011,Wzh 14 =0000, conversion data Azh = "00001011011110111010101100111011", concatenate the sequence frame Axh, time frame Asj, check frame Ajy and conversion data Azh to obtain encrypted data, and then perform inverse operation on the encrypted data to decode it to obtain decoded data Ajm.

[0088] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0089] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. Those skilled in the art may appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein may be implemented by computer software, electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software depends on the specific application and design constraints of the technical solution.

[0090] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0091] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A novel digital signal distribution module, characterized in that: include: A data input unit, the data input unit is electrically connected to the filter unit, and is used to receive initial data and send the initial data to the filter unit; A filtering unit, the filtering unit being electrically connected to the signal processing unit and configured to perform denoising on the initial data and send the denoised initial data to the signal processing unit; A signal processing unit, the signal processing unit is electrically connected to the feedback unit and the encryption unit, and is used to process the initial data once to generate processed data, and then send the processed data to the encryption unit for encryption after port allocation, and is used to receive feedback instructions and repeatedly send the data according to the feedback instructions; An encryption unit, the encryption unit being electrically connected to the data sending unit, and configured to encrypt the processed data to generate encrypted data, and send the encrypted data to the data sending unit; A data sending unit, the data sending unit is communicatively connected with the data receiving unit and is used to send the encrypted data to the data receiving unit; A data receiving unit, the data receiving unit is electrically connected to the decoding unit, and is used to receive the encrypted data and send the encrypted data to the decoding unit; A decoding unit, the decoding unit being electrically connected to the verification unit, and configured to decode the encrypted data to obtain decoded data, and send the decoded data to the verification unit; A verification unit, the verification unit is electrically connected to the feedback unit and the data output unit, and is used to verify the decoded data and then send it to the data output unit, and send the verification result to the feedback unit; A feedback unit, the feedback unit being electrically connected to the signal processing unit and configured to generate a feedback instruction according to the verification result and send the feedback instruction to the signal processing unit; A signal output unit, the signal output unit is used to output the verified decoded data; The generation logic of the processing data is: Generate a sequence number frame Axh and a time frame Asj of the initial data Acs according to the receiving time and receiving order of the initial data Acs; Generate a check frame Ajy according to the total number of bits of the initial data Acs; The sequence frame Axh, the time frame Asj, the check frame Ajy, and the initial data Acs are spliced ​​to obtain the processed data; The generation logic of the check frame Ajy is: Mark each character on the initial data Acs as The subscript x represents the number of bits of the initial data Acs, and the superscript X represents the total number of bits of the initial data Acs. The total number of bits Y of the check frame Ayj is calculated based on the total number of bits X of the initial data Acs. The calculation formula is: Mark each character on the check frame Ajy as The calculation formula is: The subscript y represents the bit number of the check frame Ajy, y = 1, 2, 3 ... Y; The logic for encrypting the processed data is: For each character on the initial data Acs Invert it and then replace the X character Divide it into N initial character segments from right to left, and mark the initial character segment as Wcs n , the number of characters in each initial character segment is 4, the subscript n represents the number of the initial character segment, and n is a positive integer; According to the initial character segment Wcs n Generate conversion character segment Wzh i , the calculation formula is: Convert the character segment Wzh i Sort from right to left in the order of the subscript i from small to large, generate conversion data Azh, and concatenate the sequence frame Axh, time frame Asj, check frame Ajy, and conversion data Azh to obtain encrypted data; The logic for decoding the encrypted data is: The encrypted data is split into a sequence frame Axh, a time frame Asj, a check frame Ajy, and a conversion data Azh. The conversion data Azh is divided from right to left into N conversion character segments Wzh. i , and then according to the conversion character segment Wzh i Get the decoded character segment Wjm j , the calculation formula is: The decoded character segment Wjm j Sort from right to left in the order of the subscript j from small to large, and then invert each character to generate the decoded data Ajm.

2. A novel digital signal distribution module according to claim 1, characterized in that: The logic for verifying the decoded data is: Mark each character on the decoded data Ajm as The subscript z represents the number of bits of the decoded data Ajm, and the superscript Z represents the total number of bits of the decoded data Ajm; Each character on the check frame Ajy will be The character corresponding to the decoded data Ajm For comparison, the corresponding relationship is: If each character on the check frame Ajy All correspond to the characters on the decoded data Ajm If they are equal, the verification result θ=0; If there are characters on the check frame Ajy The character corresponding to the decoded data Ajm If they are not equal, the verification result θ=1.

3. A novel digital signal distribution module according to claim 2, characterized in that: When the check result θ=0, the signal output unit outputs the decoded data, and the feedback unit does not generate a feedback instruction. When the check result θ=1, the signal output unit does not output the decoded data, and the feedback unit generates a feedback instruction.

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