Programming techniques for polarity-based memory cells

Abstract

This application relates to programming techniques for polarity-based memory cells. A method can include writing a memory cell to an intermediate state based on receiving a write command. Writing the intermediate state can include applying a first pulse having a first polarity to the memory cell. The method can include isolating a first access line coupled with the memory cell from a voltage source based on applying the first pulse. The method can also include applying a second pulse to a second access line coupled with the memory cell based on isolating the first access line.

Description

[0001] Cross-reference

[0002] This patent application is a national stage application of International Patent Application No. PCT / US2022 / 073032, filed June 17, 2022, titled “PROGRAMMING TECHNIQUES FOR POLARITY-BASED MEMORY CELLS,” by Sebastiani et al., which claims the benefit of U.S. Provisional Patent Application No. 17 / 361,194, filed June 28, 2021, titled “PROGRAMMING TECHNIQUES FOR POLARITY-BASED MEMORY CELLS,” by Sebastiani et al., each of which is assigned to the assignee hereof and the entire contents of each of which are hereby expressly incorporated by reference herein. TECHNICAL FIELD

[0003] The technical field relates to programming techniques for polarity-based memory cells. BACKGROUND

[0004] Memory devices are widely used in electronic systems to store information. Information is stored by programming memory cells within the memory device into various states. For example, binary memory cells can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state in the memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selecting memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. SUMMARY

[0006] A method is described. The method can include receiving, at a memory device, a command to write information to a memory cell that includes a chalcogenide material and is configured to store a set state, a reset state, and an intermediate state; and writing, based at least in part on receiving the command, a memory cell of the memory device to the intermediate state, wherein writing the memory cell to the intermediate state comprises applying a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell; isolating, based at least in part on applying the first pulse having the first polarity, a first access line coupled with the memory cell from a voltage source; and applying, based at least in part on isolating the first access line coupled with the memory cell, a second pulse to a second access line coupled with the memory cell.

[0007] Another method is described. The method can include receiving, at a memory device, a command to write information to a memory cell configured to store three or more states; and writing, based at least in part on receiving the command, a memory cell of the memory device to an intermediate state of the three or more states, wherein writing the memory cell to the intermediate state comprises applying a first pulse having a first polarity to the memory cell; applying, based at least in part on applying the first pulse, a second pulse having a second polarity to the memory cell; isolating, based at least in part on applying the second pulse having the second polarity, a first access line coupled with the memory cell from a voltage source; and applying, based at least in part on isolating the first access line coupled with the memory cell, a third pulse to a second access line coupled with the memory cell to write the memory cell to the intermediate state.

[0008] A device is described. The device can include a memory array comprising memory cells, the memory cells including a chalcogenide material and configured to store a set state, a reset state, and an intermediate state; and a controller coupled with the memory array and configured to cause the device to receive a command to write information to the memory cells; and write, based at least in part on receiving the command, a memory cell of the memory cells to the intermediate state, wherein to write the memory cell to the intermediate state, the controller is further configured to apply a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell; isolate, based at least in part on applying the first pulse having the first polarity, a first access line coupled with the memory cell from a voltage source; and apply, based at least in part on isolating the first access line coupled with the memory cell, a second pulse to a second access line coupled with the memory cell.

[0009] Another apparatus is described. The apparatus can include a memory array comprising memory cells configured to store three or more states; and a controller coupled with the memory array and configured to cause the apparatus to receive a write command to write information to the memory cells; and write a memory cell of the memory cells to an intermediate state of the three or more states based at least in part on receiving the command, wherein to write the memory cell to the intermediate state, the controller is further configured to apply a first pulse having a first polarity to the memory cell; apply a second pulse having a second polarity to the memory cell based at least in part on applying the first pulse; isolate a first access line coupled with the memory cell from a voltage source based at least in part on applying the second pulse having the second polarity; and apply a third pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 Examples of systems that support programming techniques for polarity-based memory cells according to examples as disclosed herein are described.

[0011] Figure 2 Examples of memory dies that support programming techniques for polarity-based memory cells according to examples as disclosed herein are described.

[0012] Figure 3 Examples of memory cells that support programming techniques for polarity-based memory cells according to examples as disclosed herein are described.

[0013] Figure 4A , 4B And 4C examples of plots that support programming techniques for polarity-based memory cells according to examples as disclosed herein are described.

[0014] Figure 5 Examples of plots that support programming techniques for polarity-based memory cells according to examples as disclosed herein are described.

[0015] Figure 6 Examples of process diagrams that support programming techniques for polarity-based memory cells according to examples as disclosed herein are described.

[0016] Figure 7 A block diagram of a memory device that supports programming techniques for polarity-based memory cells according to examples as disclosed herein is shown.

[0017] Figure 8 And9 A flow diagram illustrating one or more methods supporting programming techniques for polarity-based memory cells in accordance with examples as disclosed herein is shown. DETAILED DESCRIPTION

[0018] Some types of memory cells, such as memory cells including a chalcogenide material, which can be referred to as polarity-based memory cells, can be written to different logic states using voltage pulses or current pulses having different polarities. For example, a memory cell can be written to a first logic state using a pulse of a first polarity or a second logic state using a pulse of a second polarity. In some cases, detecting a logic state stored in a memory cell can also be based on a polarity of a read pulse used to read the memory cell. For example, if a memory cell is read using a read pulse having a first polarity, applying a write pulse having the first polarity can store a first logic state in the memory cell and applying a write pulse having a second polarity can store a second logic state in the memory cell. In other examples, if a memory cell is read using a read pulse having a second polarity, applying a write pulse having a first polarity can store a second logic state in the memory cell and applying a write pulse having the second polarity can store a first logic state in the memory cell. In writing a first logic state or a second logic state, current across the memory cell can be managed by a current mirror to reduce the effects of current spikes. In some examples, the memory cell can be a multi-level cell configured to store three or more logic states. In such examples, programming techniques for programming a first logic state or a second logic state can not effectively program a third logic state (e.g., an intermediate state).

[0019] Systems, techniques, and apparatuses are described herein to program a memory cell to one of three states including an intermediate state between a first state and a second state. In some cases, a memory cell can be written to the intermediate state using a current spike generated by a discharge of a capacitance of an access line coupled to the memory cell. For example, to program a memory cell to the intermediate state, a memory device can apply a first pulse to a first access line coupled to an unselected memory cell, e.g., pre-charge the first access line to a negative voltage. Then, the memory device can isolate the first access line from the memory cell, e.g., float the first access line. To write the intermediate state, the memory device can apply a second pulse to a second access line coupled to the memory cell, e.g., apply a positive voltage pulse to the second access line. In such examples, a current across the memory cell can spike and program the memory cell to the intermediate state. The memory cell can be deselected, e.g., turned off, based on the first access line and the second access line equalizing, e.g., current can flow from the second access line through the memory cell to charge the first access line until both sides of the memory cell equalize. In some examples, by programming the memory cell with a current spike, the duration of the second pulse to the second access line can be shorter than a program pulse applied to program the memory cell to store the first state or the second state. Having a shorter pulse duration can save power for the memory device. Moreover, the programming techniques described herein can reduce interference that can occur on a memory cell after a read operation and enable a memory cell storing the intermediate state to be read when using a read pulse having a first polarity or a second polarity, e.g., a memory cell storing the intermediate state can have a voltage threshold that is distinguishable from the first state and the second state, whether using a read pulse having a positive polarity or using a read pulse having a negative polarity.

[0020] Features of the disclosure are initially described in the context of a memory system, die, and array as described with reference to Figures 1 to 3 Features of the disclosure are described in the context of plots and process flows as described with reference to FIGS. 4-6. These and other features of the disclosure are further illustrated by, and described with reference to, apparatus diagrams and flowcharts related to programming techniques for polarity-based memory cells, as described with reference to Figures 7 to 9

[0021] Figure 1 ​Examples are described that support systems 100 for programming techniques for polarity-based memory cells as disclosed herein. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 and the memory device 110. The system 100 can include one or more memory devices, but aspects of the one or more memory devices 110 can be described in the context of a single memory device, such as the memory device 110.

[0022] The system 100 can include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 can illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. The memory device 110 can be a component of the system that is operable to store data for one or more other components of the system 100.

[0023] At least portions of the system 100 can be an example of the host device 105. The host device 105 can be an example of a processor or other circuitry within a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, the host device 105 can refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 120. In some examples, the external memory controller 120 can be referred to as a host or host device 105.

[0024] The memory device 110 can be a standalone device or component that is operable to provide physical memory addresses / space that can be used or referenced by the system 100. In some examples, the memory device 110 can be configured to work with one or more different types of host devices 105. Signaling between the host device 105 and the memory device 110 can be operable to support one or more of: a modulation scheme to modulate signals; various pin configurations for communicating signals; various form factors of physical packaging of the host device 105 and the memory device 110; clock signaling and synchronization between the host device 105 and the memory device 110; timing conventions; or other factors.

[0025] Memory device 110 can be operable to store data for components of host device 105. In some examples, memory device 110 can act as a secondary or slave device (e.g., respond to and execute commands provided by host device 105 through external memory controller 120) of host device 105. Such commands can include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0026] Host device 105 can include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components (e.g., one or more peripheral components or one or more input / output controllers). Components of host device 105 can be coupled with each other using bus 135.

[0027] Processor 125 can be operable to provide control or other functionality for at least portions of system 100 or at least portions of host device 105. Processor 125 can be a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 can be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, external memory controller 120 can be implemented by or be a part of processor 125.

[0028] BIOS component 130 can be a software component that includes a BIOS that operates as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 can also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 can include a program or software stored in one or more of read-only memory (ROM), flash memory, or other nonvolatile storage.

[0029] Memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 can be a set of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) where each memory cell is operable to store at least one bit of data. A memory device 110 including two or more memory dies 160 can be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0030] Device memory controller 155 can include circuitry, logic, or components operable to control operations of memory device 110. Device memory controller 155 can include hardware, firmware, or instructions that enable memory device 110 to perform various operations and can be operable to receive, transmit, or execute commands, data, or control information related to components of memory device 110. Device memory controller 155 can be operable to communicate with one or more of external memory controller 120, one or more memory dies 160, or processor 125. In some examples, device memory controller 155 can control operations of memory device 110 described herein in connection with local memory controllers 165 of memory dies 160.

[0031] In some examples, the memory device 110 can receive data or commands, or both, from the host device 105. For example, the memory device 110 can receive a write command instructing the memory device 110 to store data for the host device 105 or a read command instructing the memory device 110 to provide data stored in the memory die 160 to the host device. In some examples, the memory device 110 can receive a write command to write information to a memory cell configured to store a set state, a reset state, and an intermediate state. In such examples, to write some memory cells to the intermediate state, the memory device 110 can generate a current spike across the memory cell. For example, the memory device 110 can apply a first pulse to condition the memory cell, apply a second pulse to a first access line coupled with the memory cell, and isolate the first access line based on applying the second pulse. In such examples, the memory device 110 can then apply a third pulse to a second access line coupled with the memory cell (while the memory cell is isolated from the first access line) to generate a current spike through the memory cell by discharging capacitively through the memory cell via the second access line. The memory cell can be deselected based on the first access line and second access line equalization. In some examples, the memory device 110 can apply an additional conditioning pulse before applying the second pulse to the first access line.

[0032] The local memory controller 165 (e.g., local to the memory die 160) can include circuitry, logic, or components operable to control operations of the memory die 160. In some examples, the local memory controller 165 can be operable to communicate (e.g., receive or transmit data or commands, or both) with the device memory controller 155. In some examples, the memory device 110 can not include the device memory controller 155 and the local memory controller 165, or the external memory controller 120 can perform various functions described herein. As such, the local memory controller 165 can be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that can be included in the device memory controller 155 or the local memory controller 165, or both, can include a receiver to receive signals (e.g., from the external memory controller 120), a transmitter to transmit signals (e.g., to the external memory controller 120), a decoder to decode or demodulate received signals, an encoder to encode or modulate signals to be transmitted, or various other circuitry or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0033] The external memory controller 120 can be operable to enable transfer of one or more of information, data, or commands between components of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 can translate or interpret communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105 or their functions described herein can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software implemented by the processor 125 or other components of the system 100 or host device 105 or some combination thereof. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or its functions described herein can be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0034] Components of the host device 105 can exchange information with the memory device 110 using one or more channels 115. The channels 115 can be operable to support communications between the external memory controller 120 and the memory device 110. Each channel 115 can be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. A signal path can be an example of an electrically conductive path that is operable to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin can be an example of an electrically conductive input or output point of a device of the system 100, and a pin can be operable to act as part of a channel.

[0035] The channels 115 (and associated signal paths and terminals) can be dedicated to transferring one or more types of information. For example, the channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling can be transferred via the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., a signal level) of a signal can be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0036] Figure 2 Examples of a memory die 200 that support programming techniques for polarity-based memory cells are described in accordance with examples as disclosed herein. The memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory apparatus with reference to Figure 1 Examples of a memory die 160 are described. In some examples, the memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 can include one or more memory cells 205, which can each be programmed to store different logical states (e.g., a set of two or more possible states of a programmed state). For example, the memory cells 205 can be operable to store one bit of information (e.g., a logical 0 or a logical 1) at a time. In some examples, the memory cells 205 (e.g., multi-bit-level memory cells 205) can be operable to store more than one bit of information (e.g., logical 00, logical 01, logical 10, logical 11) at a time. In some examples, the memory cells 205 can be configured to store one and a half (1.5) bits of information, for example, using a set state, a reset state, and an intermediate state. In some examples, the memory cells 205 can be arranged in an array, for example, with reference to Figure 1 A memory array 170 is described.

[0037] The memory cells 205 can use a configurable material (which can be referred to as a memory element, a memory storage element, a material element, a material memory element, a material portion, or a polarity- write material portion, among others) to store a logical state. The configurable material of the memory cells 205 can refer to a chalcogenide-based storage component, as described with reference to Figure 3 are described in greater detail. For example, chalcogenide storage elements can be used in phase change memory (PCM) cells, thresholding memory cells, or self-selecting memory cells.

[0038] The memory die 200 can include access lines (e.g., row lines 210 and column lines 215) arranged in a pattern (e.g., a grid-like pattern). The access lines can be formed of one or more conductive materials. In some examples, the row lines 210 can be referred to as word lines. In some examples, the column lines 215 can be referred to as digit lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or the like, can be interchangeable without loss of understanding or operation. The memory cells 205 can be positioned at intersections of the row lines 210 and the column lines 215.

[0039] Operations such as reads and writes can be performed on memory cells 205 by activating or selecting an access line, such as one or more of row lines 210 or column lines 215. A single memory cell 205 can be accessed at the intersection of a row line 210 and a column line 215 by biasing the row line 210 and the column line 215, such as by applying a voltage to the row line 210 or the column line 215. The intersection of a row line 210 and a column line 215 in a two-dimensional or three-dimensional configuration can be referred to as an address of a memory cell 205. An access line can be an electrically conductive line coupled with a memory cell 205 and can be used to perform an access operation on the memory cell 205.

[0040] Accessing memory cells 205 can be controlled by a row decoder 220 or a column decoder 225. For example, a row decoder 220 can receive a row address from a local memory controller 245 and activate a row line 210 based on the received row address. A column decoder 225 can receive a column address from the local memory controller 245 and can activate a column line 215 based on the received column address.

[0041] A sense component 230 can operate to detect a state of a memory cell 205 (e.g., material state, resistance, threshold state) and determine a logic state of the memory cell 205 based on the stored state. The sense component 230 can include one or more sense amplifiers to amplify or otherwise convert a signal generated by an accessed memory cell 205. The sense component 230 can compare a signal detected from a memory cell 205 to a reference 235 (e.g., a reference voltage). The detected logic state of a memory cell 205 can be provided as an output of the sense component 230 (e.g., to an input / output 240) and can indicate the detected logic state to another component of a memory device including the memory die 200.

[0042] A local memory controller 245 can control access of memory cells 205 through various components, such as a row decoder 220, a column decoder 225, a sense component 230. The local memory controller 245 can be a reference Figure 1An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 230 can be co-located with the local memory controller 245. The local memory controller 245 can be operable to receive one or more of commands or data from one or more different memory controllers (e.g., the external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and pass data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 245 can generate row signals and column address signals to activate a target row line 210 and a target column line 215. The local memory controller 245 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitudes, shapes, or durations of the voltages or currents applied discussed herein can vary and can differ for the various operations discussed in operating the memory die 200.

[0043] The local memory controller 245 can be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations can include write operations, read operations, refresh operations, precharge operations, or activate operations, among others. In some examples, the access operations can be performed or otherwise coordinated by the local memory controller 245 in response to various access commands (e.g., from the host device 105). The local memory controller 245 can be operable to perform other access operations not listed here or other operations related to operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0044] The local memory controller 245 is operable to perform a write operation (e.g., a program operation) on one or more memory cells 205 of the memory die 200. During a write operation, a memory cell 205 of the memory die 200 can be programmed to store a desired logic state. The local memory controller 245 can identify a target memory cell 205 on which to perform the write operation. The local memory controller 245 can identify a target row line 210 and a target column line 215 coupled with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 245 can activate the target row line 210 and the target column line 215 (e.g., apply a voltage to the row line 210 or the column line 215) to access the target memory cell 205. The local memory controller 245 can apply a particular signal (e.g., a write pulse) to the column line 215 during the write operation to store a particular state in a storage element of the memory cell 205. A pulse used as part of a write operation can include one or more voltage levels for a duration of time. In some examples, the local memory controller 245 can be configured to write the memory cell 205 to three or more states. For example, the local memory controller 245 can write a set state, a reset state, or an intermediate state to the memory cell 205. For example, the local controller 245 can select a memory cell 205 to write to an intermediate state. In such examples, the local controller 245 can apply a first pulse to condition the memory cell 205. In some examples, the local controller 245 can also apply an additional pulse to condition the memory cell 205, the additional pulse having a polarity opposite to a polarity of the first pulse. The local controller 245 can then apply a second pulse to a first access line (e.g., apply a negative voltage to a word line 210 or digit line 215). While the first access line is pre-charged, the local memory controller 245 can isolate the first access line from a voltage source and apply a third pulse to a second access line (e.g., to a word line 210 or digit line 215 that was not charged by the first pulse). In such examples, a current can peak across the memory cell 205 and write the memory cell 205 to the intermediate state.

[0045] The local memory controller 245 can be operable to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logical state stored in a memory cell 205 of the memory die 200 can be determined. The local memory controller 245 can identify a target memory cell 205 on which to perform the read operation. The local memory controller 245 can identify a target row line 210 and a target column line 215 coupled with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 245 can activate the target row line 210 and the target column line 215 (e.g., apply a voltage to the row line 210 or the column line 215) to access the target memory cell 205. The sense component 230 can detect a signal received from the memory cell 205 based on a pulse applied to the row line 210, a pulse applied to the column line, and / or a resistance or threshold characteristic of the memory cell 205. The sense component 230 can amplify the signal. The local memory controller 245 can activate the sense component 230 (e.g., latch the sense component) and thereby compare the signal received from the memory cell 205 to a reference signal 235. Based on the comparison, the sense component 230 can determine the logical state stored on the memory cell 205. The pulses used as part of a read operation can include one or more voltage levels for a duration of time. In some examples, the local memory controller 245 can perform a read operation by applying two read pulses (e.g., a pulse having a first polarity and a pulse having a second polarity, the first polarity opposite the second polarity). In such examples, the sense component 230 can determine the logical state of the memory cell 205 based on whether the threshold voltage of the memory cell 205 is high at the first read pulse, the second read pulse, or both, as described with reference to FIG. 4.

[0046] Figure 3 An example of a memory array 300 is described in accordance with examples as disclosed herein. The memory array 300 can be an example of the memory array or portion of the memory die described with reference to FIGS. 1-3. The memory array 300 can include a first tier 305 of memory cells positioned above a substrate (not shown) and a second tier 310 of memory cells on top of the first array or tier 305. Although the example of the memory array 300 includes two tiers 305, 310, the memory array 300 can include any number of tiers (e.g., one or more than two). Figure 1 and 2 An example of a memory array 300 is described in accordance with examples as disclosed herein. The memory array 300 can be an example of the memory array or portion of the memory die described with reference to FIGS. 1-3. The memory array 300 can include a first tier 305 of memory cells positioned above a substrate (not shown) and a second tier 310 of memory cells on top of the first array or tier 305. Although the example of the memory array 300 includes two tiers 305, 310, the memory array 300 can include any number of tiers (e.g., one or more than two).

[0047] The memory array 300 can also include a row line 210-a, a row line 210-b, a row line 210-c, a row line 210-d, a column line 215-a, and a column line 215-b, which can be examples of the row lines 210 and the column lines 215, as described with reference to FIGS. 1-3. The memory array 300 can also include a sense component 230-a, a sense component 230-b, a sense component 230-c, a sense component 230-d, a reference signal 235-a, and a reference signal 235-b, which can be examples of the sense components 230 and the reference signals 235, as described with reference to FIGS. 1-3. Figure 2Description. One or more memory cells of the first tier 305 and the second tier 310 can include one or more chalcogenide materials in a pillar between access lines. For example, a single stack between access lines can include one or more of a first electrode, a first chalcogenide material (e.g., a selector component), a second electrode, a second chalcogenide material (e.g., a storage element), or a third electrode. Although some elements included in Figure 3 While some elements included in the figures are labeled with numerical designators, other corresponding elements are not labeled, but are identical or will be understood to be similar, in an attempt to increase the visibility and clarity of the depicted features.

[0048] One or more memory cells of the first tier 305 can include one or more of the electrode 325-a, the storage element 320-a, or the electrode 325-b. One or more memory cells of the second tier 310 can include the electrode 325-c, the storage element 320-b, and the electrode 325-d. The storage element 320 can be an example of a chalcogenide material, such as a phase change storage element, a thresholding storage element, or a self-selecting storage element. In some examples, the memory cells of the first tier 305 and the second tier 310 can have a common conductive line such that corresponding memory cells of the one or more tiers 305 and the one or more tiers 310 can share a column line 215 or a row line 210. For example, the first electrode 325-c of the second tier 310 and the second electrode 325-b of the first tier 305 can be coupled with the column line 215-a such that the column line 215-a can be shared by vertically adjacent memory cells.

[0049] In some examples, the material of the storage element 320 can include a chalcogenide material or other alloy, including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) can be referred to as a SAG alloy. In some examples, a SAG alloy can also include silicon (Si) and such a chalcogenide material can be referred to as a SiSAG alloy. In some examples, a SAG alloy can include silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials can be referred to as a SiSAG alloy or an InSAG alloy, respectively, or combinations thereof. In some examples, a chalcogenide glass can include additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F).

[0050] In some examples, storage element 320 can be an example of a phase change memory cell. In such examples, the material used in storage element 320 can be alloy-based (e.g., the alloys listed above) and can be operated so as to undergo a phase change or become a different physical state during normal operation of the memory cell. For example, a phase change memory cell can have an amorphous state (e.g., a relatively disordered atomic configuration) and a crystalline state (e.g., a relatively ordered atomic configuration).

[0051] In some examples, such as for thresholding memory cells or self-selecting memory cells, some or all of the set of logic states supported by the memory cell can be associated with an amorphous state of a chalcogenide material (e.g., the material in a single state can be operable to store different logic states). In some examples, storage element 320 can be an example of a self-selecting memory cell. In such examples, the material used in storage element 320 can be alloy-based (e.g., the alloys listed above) and can be operated so as to undergo a change to a different physical state during normal operation of the memory cell. For example, a self-selecting memory cell can have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state can correspond to a first logic state (e.g., a reset state) and the low threshold voltage state can correspond to a second logic state (e.g., a set state). In some examples, a self-selecting memory cell can be configured to store three or more states. For example, a self-selecting memory cell can store a third logic state (e.g., an intermediate state) having a threshold voltage between the first logic state and the second logic state. In some examples, a self-selecting memory cell can be configured to store the first logic state or the second logic state based on a polarity used to write the memory cell (e.g., a first polarity for the first logic state and a second polarity for the second logic state). In some examples, a self-selecting memory cell can be configured to store the third logic state based on a current spike during a write operation. That is, the third logic state can be programmed using the first polarity or the second polarity. In such examples, a first pulse configured to condition the memory cell can be applied to the self-selecting memory cell. In some examples, an additional pulse having a polarity opposite the polarity of the first pulse can also be applied to the self-selecting memory cell to further condition the memory cell. Then, a second pulse can be applied to the first access line (e.g., a negative voltage applied to the row line 210 or the column line 215). While the first access line is pre-charged, the first access line can be isolated from the voltage source and a third pulse can be applied to the second access line (e.g., to the row line 210 or the column line 215 that was not charged by the first pulse). In such examples, a current can peak across the self-selecting memory cell and write the memory cell to the intermediate state.

[0052] During a program (write) operation of a self-selecting memory cell (e.g., including electrode 325-a, storage element 320-a, and electrode 325-b), the polarity used for the write operation can affect (determine, set, program) a particular behavior or characteristic of the material of storage element 320, such as a threshold voltage of the material. The difference in threshold voltage of the material of storage element 320 depending on the logical state stored by the material of storage element 320 (e.g., the difference between the threshold voltage when the material stores a logical state '0' and the threshold voltage when the material stores a logical state '1') can correspond to a read window for storage element 320. In other examples, the threshold voltage of a memory cell storing a first logical state can be high at a first polarity and low at a second, opposite polarity. The threshold voltage of a memory cell storing a second logical state can be low at the first polarity and high at the opposite polarity. The threshold voltage of a memory cell storing a third logical state can be high at the first polarity and the second polarity. Thus, the logical state of a memory cell can be determined by applying two read pulses.

[0053] In some examples, the architecture of memory array 300 can be referred to as a cross-point architecture, in which memory cells are formed at topological cross-points between row lines 210 and column lines 215. This cross-point architecture can provide relatively high density data storage at lower production cost than other memory architectures. For example, a cross-point architecture can have memory cells with a reduced area and thus increased memory cell density compared to other architectures. For example, the architecture can have a 4F2 memory cell area compared to other architectures (e.g., architectures with three-terminal selector elements) that have a 6F2 memory cell area, where F is the minimum feature size. For example, DRAM can use transistors (which are three-terminal devices) as selector elements for each memory cell and can have a larger memory cell area compared to a cross-point architecture.

[0054] While Figure 3 Examples of Figure 3 may be configured in a three-dimensional cross-point architecture in a similar manner. Furthermore, in some cases, the memory cells of Figure 3 The elements described in

[0055] Figure 4A , 4Band 4C illustrate examples of plots 400, 401, and 402 that support write operations for programming techniques for memory cells based on polarity as disclosed herein. For example, Figure 4A A plot 400 of a write operation that writes a memory cell (e.g., a memory cell 205 as described with reference to Figure 2 FIG. 4A) to a set state can be illustrated. For example, Figure 4B A plot 401 of a write operation that writes a memory cell to a reset state can be illustrated, and Figure 4C A plot 402 of a write operation that writes a memory cell to an intermediate state can be illustrated. The write operations depicted in Figure 1 Figure 4A 4B FIGS. 4A, 4B, and 4C can be performed by a system (e.g., a system 100 as described with reference to Figure 1 FIG. 4A). For example, a memory device (e.g., a memory device 110 as described with reference to Figure 1 FIG. 4A) can perform a write operation on a memory cell in a memory array (e.g., a memory array 170 as described with reference to Figure 2 FIG. 4A). The memory cell can be configured to store three or more logic states as described with reference to 3 FIGS. 4A, 4B, and 4C.

[0056] The X-axis of the plots 400, 401, and 402 can represent time and the Y-axis of the plots 400, 401, and 402 can represent a voltage of a pulse applied to a given memory cell or a given access line (e.g., a word line 210 or a digit line 215 as described with reference to Figure 2 FIG. 4A). In some examples, applying a pulse to a memory cell can refer to applying a pulse to both a first access line and a second access line. In other examples, applying a pulse to an access line can refer to a voltage applied to bias a first access line or a second access line.

[0057] With reference to Figure 4A In some examples, a memory device can receive a write command from a host device (e.g., a host device 105 as described with reference to Figure 1 FIG. 4A) to write information or data to one or more memory cells. In some examples, the write command can include data or information associated with a first logic state (e.g., a set state) to be stored at the memory cell. In such examples, the memory device can perform a write operation as illustrated in plot 400. For example, the memory device (e.g., or a local memory controller 245 as described with reference to Figure 2 FIG. 4A). That is, the memory device can apply a pulse 405 to bias a first access line to a first voltage and apply a pulse 410 to bias a second access line to a second voltage.

[0058] ​​In some examples, pulse 405 can be a negative voltage and pulse 410 can be a positive voltage. In such examples, the polarity of the voltage across the memory cell can be based on whether the first access line is a digit line or a word line, e.g., the voltage across the memory cell can be the difference between the voltage of the digit line and the word line. For example, a memory cell can be programmed to a positive polarity when the first access line is a word line and the second access line is a digit line and to a negative polarity when the first access line is a digit line and the second access line is a word line. In some examples, the first pulse to the memory cell can also be associated with conditioning the memory cell to prevent drift. That is, the voltage threshold of the memory cell can change due to time, temperature, or other factors and the first pulse illustrated in plot 400 can mitigate drift, e.g., cause the threshold voltage of the memory cell to return to the original threshold voltage.

[0059] Further, the memory device can use a current mirror when applying pulse 405 and pulse 410. That is, applying pulse 405 or pulse 410 can cause a current to rapidly increase across the memory cell. A current mirror can be utilized to stabilize the current and prevent the current from dropping, e.g., the current mirror can maintain the current across the memory cell. Thus, a first pulse (e.g., pulse 405 to the first access line and pulse 410 to the second access line) across the memory cell can be applied for a first duration to program the memory cell to a set state.

[0060] Referring to Figure 4B In some examples, the write command can include data or information associated with a second logical state (e.g., a reset state) to be stored at the memory cell. In such examples, the memory device can perform a write operation as illustrated in plot 401. For example, the memory device can apply a first pulse to the memory cell, e.g., apply pulse 415-a to the first access line and pulse 420-a to the second access line. The first pulse can be the same as the first pulse illustrated in plot 400. That is, the memory device can apply the first pulse to some or all of the memory cells in the memory array. In such examples, the memory cell can initially be written to a first logical state (e.g., a set state). The first pulse can also condition the memory cell, e.g., mitigate any drift in a given threshold voltage of the memory cell.

[0061] After applying the first pulse, the memory device can apply a second pulse having an opposite polarity to program a subset of memory cells including the memory cell in the memory cell to a second logic state (e.g., a reset state). That is, the first logic state and the second logic state can be associated with voltages of opposite polarities. In some examples, the first logic state can be associated with a positive polarity and the second logic state can be associated with a negative polarity or the first logic state can be associated with a negative polarity and the second logic state can be associated with a positive polarity. For example, the memory device can apply a pulse 415-b to bias the first access line to a third voltage and apply a pulse 420-b to bias the second access line to a fourth voltage. In some examples, the pulse 415-b can be a positive voltage and the pulse 420-b can be a negative voltage. In such examples, the polarity of the voltage across the memory cell can be based on whether the first access line is a digit line or a word line, e.g., the voltage across the memory cell can be the difference between the voltage of the digit line and the voltage of the word line. For example, the memory cell can be programmed to a negative polarity when the first access line is a word line and the second access line is a digit line and the memory cell can be programmed to a positive polarity when the first access line is a digit line and the second access line is a word line. As described with reference to plot 400, the memory device can use a current mirror to limit current spikes across the memory cell while applying the first pulse (e.g., pulse 415-a and pulse 415-b) and the second pulse (e.g., pulse 415-b and pulse 420-b).

[0062] Reference Figure 4C In some examples, the write command can include data or information associated with a third logic state (e.g., an intermediate state) to be stored at the memory cell. That is, a memory cell storing a set state can have a first threshold voltage and a memory cell storing a reset state can have a second threshold voltage different from the first threshold voltage. In such examples, a memory cell storing an intermediate state can have a third threshold voltage between the first threshold voltage and the second threshold voltage. The level of the threshold voltage detected in the memory cell can be different based on the polarity of the read pulse used. For example, if the memory cell is read using a read pulse having a first polarity, the set state can exhibit a threshold voltage higher than the threshold voltage of the reset state. In some examples, if the memory cell is read using a read pulse having a second polarity, the set state can exhibit a threshold voltage lower than the threshold voltage of the reset state. The intermediate state can be configured such that it can be distinguished from the set state and the reset state in response to using a read voltage having the first polarity and in response to using a read voltage having the second polarity. In some examples, the third threshold voltage can be the same as the second threshold voltage.

[0063] To program the memory cells to the intermediate state, the memory device can perform a write operation as illustrated in plot 402. For example, the memory device can apply a first pulse to the memory cells, e.g., apply pulse 425-a to the first access line and pulse 430-a to the second access line. The first pulse can be the same as the first pulse illustrated in plot 400. That is, the memory device can apply the first pulse to some or all of the memory cells in the memory array. In such examples, the memory cells can initially be written to a first logical state (e.g., a set state). The first pulse can also condition the memory cells, e.g., mitigate any drift in a given threshold voltage of the memory cells.

[0064] After applying the first pulse, the memory device can apply a second pulse 430-b to bias the second access line. For example, the second pulse 430-b can be a negative pulse. In such examples, the memory device can bias (e.g., pre-charge) the second access line to a fifth voltage, e.g., a negative voltage. In some cases, at time 435, the voltage of the second access line can be at the fifth voltage. In such examples, the memory device can isolate the second access line from a voltage source (e.g., a negative voltage source or a negative decoder). For example, the memory device can de-activate the voltage source such that the second access line is not coupled to any voltage and the node of the second access line and the memory cells is floating. In other examples, the memory device can de-activate a switch that couples the voltage source to the second access line. For example, the memory array can include a transistor (e.g., an n-type metal-oxide-semiconductor (nMOS) transistor) coupled with a voltage (e.g., a signal or a mitigation signal). In some examples, the voltage (e.g., the signal) can be applied at the gate of the transistor. Based on the timing (e.g., a predetermined timing) of the write operation, the voltage at the gate can be de-activated or lowered at time 435. Thus, the transistor can be de-activated and isolate the second access line from the voltage source. Isolating the transistor can also isolate the current mirror from the second access line and the memory cells, as described with reference to plots 400 and 401, e.g., the current mirror can not have an effect on the memory cells during the write operation illustrated in plot 402.

[0065] After isolating the second access line from the memory cell at 435, the memory device can apply a third pulse 425-b to bias the first access line to a sixth voltage. The third pulse 425-b can be applied to the first access line while the second access line is floating (e.g., isolated from a voltage source). Although shown at a time after 435, in some examples, the memory device can apply the pulse 425-b immediately after or concurrently with the isolation, e.g., based on a small duration between isolating the second access line and applying the third pulse 425-b to the first access line, less current can leak. In some examples, applying the third pulse 425-b can cause a current across the memory cell to quickly reach a peak. In addition, the current spike can also bias the second access line, e.g., a node coupled to the second access line and the memory cell can be charged up until it is equalized with a second node coupled to the first access line and the memory cell. Thus, when the application of the third pulse 425-b is complete, the current across the memory cell can quickly drop to 0 (e.g., approximately 0). That is, the positive voltage of the third pulse 425-b and the negative voltage of the second pulse 430-b can be equalized at 0. In such examples, the quick drop in current can deselect (e.g., turn off) the memory cell.

[0066] In some examples, the quick current spike and drop across the memory cell can program the memory cell to an intermediate state. As the memory cell is programmed to the intermediate state based on the quick current spike and drop, the third pulse 425-b can be applied for a second duration that is shorter than the first duration (e.g., shorter than the duration of the first pulse or the second pulse that programs the memory cell to the first logical state or the second logical state). Thus, the memory device can save power when programming the intermediate state. Utilizing the write operation illustrated in plot 402 can also result in better read disturb immunity to high voltage threshold states, e.g., voltage threshold or logical state changes based on a large number of read operations can be reduced or mitigated. In addition, the first polarity or the second polarity can be utilized to program the memory cell storing the intermediate state. That is, the polarity of the voltage across the memory cell can be based on whether the first access line is a word line or a digit line. For example, the memory cell can be programmed to a negative polarity when the first access line is a word line and the second access line is a digit line and the memory cell can be programmed to a positive polarity when the first access line is a digit line and the second access line is a word line.

[0067] In some instances, after a memory cell is programmed to a first, second, or third logic state, the memory device may perform a read operation to determine the logic state of a given memory cell. In some instances, when a memory cell is configured to store a set state, a reset state, or an intermediate state, the memory device may use two read pulses. For example, the memory device may use a first read pulse with a first polarity and a second read pulse with a second polarity (e.g., opposite polarity). When the memory device applies the first read pulse, the memory cell storing the first or third logic state may exhibit a high threshold voltage, and the memory cell storing the second logic state may exhibit a low threshold voltage. When the memory device applies the second read pulse, the memory cell storing the second or third logic state may exhibit a high threshold voltage, and the memory cell storing the first logic state may exhibit a low threshold voltage. That is, the memory cells storing the first and second logic states may be at a high or low threshold voltage based on the applied polarity. The memory cell storing the third logic state may be at a high threshold voltage regardless of the applied polarity. Therefore, the memory device can determine whether a memory cell stores a first logic state, a second logic state, or a third logic state by applying first and second read pulses with opposite polarities.

[0068] Figure 5 This illustrates an example of a plot 500 that supports write operations for polarity-based memory cell programming techniques, as disclosed herein. For example, Figure 5 The description refers to memory cells (e.g., as referenced). Figure 2 A plot 500 depicts a write operation where memory cell 205 is written to an intermediate state. In some instances, Figure 5 The write operation described herein can be an alternative example of the write operation described in diagram 402 to write a memory cell to an intermediate state. This can be achieved through a system (e.g., as referenced in the documentation). Figure 1 The described system 100) executes Figure 5 The write operation described in the text. For example, a memory device (e.g., as referenced) Figure 1 The described memory device 110) can be used with memory arrays (e.g., as referenced). Figure 1 Write operations are performed on memory cells in the described memory array 170.

[0069] The X-axis of plot 500 can represent time, and the Y-axis of plot 500 can represent the time applied to a given memory cell or a given access line (e.g., as referenced). Figure 2the voltage of a pulse described for the word line 210 or the digit line 215. In some examples, a pulse to a memory cell can refer to applying a pulse to both the first and second access lines. In other examples, a pulse to an access line can refer to a voltage applied to either the first access line or the second access line that is coupled to a memory cell to bias.

[0070] In some examples, a memory device can receive a write command from a host device (e.g., as described with reference to the host device 105) to write information or data to one or more memory cells (e.g., to a first logical state, a second logical state, or a third logical state). To write a memory cell to a third logical state, the memory device can utilize a write operation illustrated in the plot 500. Figure 1

[0071] For example, the memory device can apply a first pulse (e.g., pulse 510-a and pulse 505-a) to a given memory cell. In some examples, the first pulse can be the same as the first pulse illustrated in the plots 400, 401, and 402 as described with reference to FIG. 4. That is, the first pulse can condition the memory cell and mitigate drift. After applying the first pulse, the memory device can apply a second pulse (e.g., pulse 505-b and pulse 510-b) to the memory cell. In some examples, the second pulse can have an opposite polarity than the first pulse. In some cases, the polarity of the first and second pulses can depend on whether the first access line is a digit line or a word line. For example, the memory device can apply a first pulse having a positive polarity when the first access line is a word line and the second access line is a digit line and the memory device can apply a first pulse having a negative polarity when the first access line is a digit line and the second access line is a word line. The second pulse can have a polarity opposite the polarity of the first pulse, e.g., negative if the first polarity is positive and positive if the first polarity is negative. In some examples, the second pulse can be the same as the second pulse illustrated in plot 401, e.g., the memory cell can be in a reset state after the first and second pulses. In some examples, e.g., compared to plot 402, an additional pulse can further condition the memory cell. Compared to the write operation illustrated in plot 402, the write operation illustrated in plot 500 can consume additional power but also result in a current spike that is greater than the current spike generated by the write operation illustrated in plot 402. This can enable additional read disturb prevention.

[0072] After applying the second pulse, the memory device can apply a third pulse 505-c to bias the first access line to a first voltage, e.g., a negative voltage. In some examples, at time 515, the first access line can be at the first voltage. In such examples, the memory device can isolate the first access line from a voltage source, e.g., by deactivating a transistor or a voltage supplier, as described with reference to​Figure 4C and plot 402. After isolating the first access line, the memory device can apply a fourth pulse 510-c to bias the second access line to a second voltage, e.g., a positive voltage. As described with reference to Figure 4C To reduce current leakage, the fourth pulse 510-c can be applied concurrently with isolating the first access line or immediately after isolating the first access line. In some examples, applying the fourth pulse 510-c can cause the current across the memory cell to quickly reach a peak. In addition, the current spike can also bias the first access line, e.g., a node coupled with the first access line and the memory cell can be charged until equalized with a second node coupled with the second access line and the memory cell. Thus, when the application of the fourth pulse 510-c is complete, the current across the memory cell can quickly drop to 0 (e.g., approximately 0). That is, the positive voltage of the fourth pulse 510-c and the negative voltage of the third pulse 505-c can be equalized at 0. In such examples, the quick drop in current can deselect (e.g., turn off) the memory cell and program the memory cell to an intermediate state. Since the memory cell is programmed to the intermediate state based on the quick current spike and the drop in current, the fourth pulse 510-c can be applied for a duration that is shorter than the duration of the first pulse or the second pulse. The memory cell storing the intermediate state can be programmed using the first polarity or the second polarity. That is, the polarity of the voltage across the memory cell can be based on whether the first access line is a word line or a digit line. For example, the memory cell can be programmed to a positive polarity when the first access line is a word line and the second access line is a digit line and the memory cell can be programmed to a negative polarity when the first access line is a digit line and the second access line is a word line.

[0073] Figure 6 An example of a process diagram 600 that supports programming techniques for polarity-based memory cells according to examples as disclosed herein is illustrated. The operations of the process diagram can be implemented by a system or components thereof as described herein. For example, the process diagram 600 can be performed by a system or device (e.g., system 100, memory die 200, or memory array 300) as described with reference to Figures 1 to 3 The process diagram 600 can illustrate a write operation that programs a memory cell to an intermediate state as described with reference to FIGS. 4 and 5.

[0074] At 605, a memory device (e.g., memory device 110 as described with reference to Figure 1 Figure 2 At 605, a memory device (e.g., memory device 110 as described with reference to Figure 1 ​The host device 105 described receives a write command. In some examples, the write command can indicate to write information to a memory cell including a chalcogenide material. For example, the write command can indicate to write a set state, a reset state, or an intermediate state to the memory cell. The memory device can select a subset of memory cells in a memory array to program to the intermediate state based on receiving the write command.

[0075] At 610, the memory device can apply a first pulse to the memory cell to condition the memory cell. For example, the memory device can apply a pulse to bias a first access line and apply a pulse to bias a second access line, as illustrated in plots 402 and 500. In some examples, the first pulse can mitigate drift at the memory cell. In some examples, the pulse to the first access line can be a negative voltage and the pulse to the second access line can be a positive voltage. In such examples, the polarity of the voltage across the memory cell can depend on whether the first access line is a word line or a digit line, for example, negative polarity when the first access line is a digit line (e.g., as referenced to Figure 2 the digit line 215 described) and positive polarity when the first access line is a word line (e.g., as referenced to Figure 2 the word line 210 described).

[0076] At 615, the memory device can apply an optional second pulse to the memory cell to further condition the memory cell, for example, as illustrated in plot 500. For example, the memory device can apply a pulse to bias a first access line and apply a pulse to bias a second access line, as illustrated in plot 500. In some examples, the second pulse can have an opposite polarity to the first pulse, for example, the second pulse can have a negative polarity if the first pulse has a positive polarity and the second pulse can have a positive polarity if the first pulse has a negative polarity. At 630, the optional second pulse can improve read disturbance immunity and result in a larger current spike.

[0077] At 620, the memory device can apply a third pulse to the first access line or the second access line based on whether an optional second pulse is applied. For example, if the second pulse is not applied, the memory device can apply the third pulse to the second access line, for example, as illustrated in plot 402. In other examples, if the second pulse is applied, the memory device can apply the third pulse to the first access line, as illustrated in plot 500. In some examples, the third pulse can bias the respective access line to a negative voltage.

[0078] At 625, the memory device can isolate the respective access line (e.g., the access line) to which the third pulse is applied. In some examples, when the access line is biased to a negative voltage, the memory device can isolate the access line by decoupling the access line from the voltage source. For example, the memory device can deactivate a switch, a transistor coupled with the voltage source and the access line, or the voltage source as described with reference to FIG. 4. For example, the memory device can deactivate a transistor by deactivating a mitigation signal applied to a gate of the transistor. Isolating the access line can cause a node coupled with the access line and the memory cell to float, e.g., uncoupled to any voltage source.

[0079] At 630, the memory device can apply a fourth pulse to an access line (e.g., another access line) to which the third pulse is not applied. In some examples, the memory device can apply the fourth pulse concurrently with or immediately after isolating the access line. In some examples, the memory device can apply the fourth pulse to bias the other access line to a positive voltage. Applying the fourth pulse can also generate a current spike across the memory cell. Since the access line can be isolated from the voltage source, the memory cell can be isolated from the current mirror and the current can drop across the memory cell quickly after completing the application of the fourth pulse, e.g., until both sides of the memory cell equalize as described with reference to FIG. 4. Thus, the memory cell can be programmed to an intermediate state. In some examples, the fourth pulse can be applied for a duration that is less than the first, second, and third pulses. This can reduce power consumption. Further, the memory device can program the memory cell to the intermediate state using a positive or negative polarity. Programming the memory cell with the current spike can also reduce read disturbance.

[0080] At 635, the memory device can apply a first read pulse to the memory cell. In some examples, after programming the memory cell to the intermediate state, the memory device can receive a read command from the host device. In such examples, the memory device can perform a read operation to determine a logical state of the memory cell based on receiving the read command. In some cases, the memory device can perform the read operation with a first read pulse and a second read pulse to determine the logical state of the memory cell. For example, the memory device can apply the first read pulse to a given memory cell. The first read pulse can be a pulse having a first polarity (e.g., a positive polarity). The first read pulse can cause a first set of memory cells to exhibit a high voltage threshold and a second set of memory cells to exhibit a low threshold voltage.

[0081] At 640, the memory device can apply a second read pulse to the memory cell. In some examples, the second read pulse can have a second polarity (e.g., a negative polarity) that is opposite the first polarity. The second read pulse can cause a third set of memory cells to exhibit a high threshold voltage and a fourth set of cells to exhibit a low threshold voltage.

[0082] At 645, the memory device can determine the logical state of the memory cells in the memory array based at least in part on applying the first pulse and the second pulse. For example, memory cells having a first logical state (e.g., a set state) can exhibit a high voltage threshold based on applying the first read pulse and a low threshold voltage based on applying the second read pulse, e.g., memory cells having the first logical state can be in the first set of memory cells. Memory cells having a second logical state can exhibit a high voltage threshold based on applying the second read pulse and a low threshold voltage based on applying the first read pulse, e.g., memory cells having the second logical state (e.g., a reset state) can be in the second set and the third set of memory cells. Memory cells having a third logical state (e.g., an intermediate state) can exhibit a high threshold voltage based on applying the first pulse or the second pulse, e.g., memory cells having the third logical state can be in the first set of memory cells and the third set of memory cells. Thus, the memory device can determine that the memory cells in the second set are associated with the second logical state, the memory cells in the fourth set are associated with the first logical state, and the remaining memory cells in the first set and the third set are associated with the third logical state, e.g., memory cells that exhibit a high threshold voltage at the first read pulse and the second read pulse can store the third logical state. Memory cells storing the third logical state can exhibit a high threshold voltage at both the first read pulse and the second read pulse based on being programmable by either the first polarity or the second polarity.

[0083] Figure 7 A block diagram 700 showing a memory device 720 supporting programming techniques for polarity-based memory cells according to examples as disclosed herein is shown. The memory device 720 can be an example of aspects of the memory device described with reference to Figures 1 to 6 Examples of aspects of the memory device are described. The memory device 720, or various components thereof, can be examples of means for performing various aspects of programming techniques for polarity-based memory cells as described herein. For example, the memory device 720 can include a receiving component 725, an access operation component 730, an isolation component 735, or any combination thereof. Each of these components can be in communication, directly or indirectly, with one another (e.g., via one or more buses).

[0084] The receiving component 725 can be configured as or otherwise support a means for receiving, at a memory device, a command to write information to a memory cell including a chalcogenide material and configured to store a set state, a reset state, and an intermediate state.

[0085] The access operation component 730 can be configured as or otherwise support means for writing a memory cell of a memory device to an intermediate state based at least in part on receiving a command, where writing the memory cell to the intermediate state includes applying a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell, isolating a first access line coupled with the memory cell from a voltage source based at least in part on applying the first pulse having the first polarity, and applying a second pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell. In some examples, the access operation component 730 can be configured as or otherwise support means for applying a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell.

[0086] The isolation component 735 can be configured as or otherwise support means for isolating a first access line coupled with a memory cell from a voltage source based at least in part on applying a first pulse having a first polarity. In some cases, the access operation component 730 can be configured as or otherwise support means for applying a second pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell.

[0087] In some examples, to support writing a memory cell to an intermediate state, the access operation component 730 can be configured as or otherwise support means for biasing a first access line to a first voltage, where isolating the first access line is based at least in part on biasing the first access line to the first voltage. In some examples, the access operation component 730 can be configured as or otherwise support means for applying a first pulse to the memory cell for a first duration and applying a second pulse to the memory cell for a second duration, the first duration greater than the second duration.

[0088] In some examples, to support writing a memory cell to an intermediate state, the access operation component 730 can be configured as or otherwise support means for applying a third pulse having a second polarity to the memory cell prior to isolating a first access line, the third pulse configured to condition the memory cell.

[0089] In some cases, the access operation component 730 can be configured as or otherwise support means for applying a first polarity (positive polarity) and a second polarity (negative polarity).

[0090] In some examples, the access operation component 730 can be configured as or otherwise support a means for applying a first pulse to mitigate a shift in a threshold voltage associated with a memory cell.

[0091] In some examples, to support applying a second pulse to a second access line, the access operation component 730 can be configured as or otherwise support a means for biasing the second access line to a first voltage. In some examples, to support applying a first pulse to a memory cell having a first polarity, the access operation component 730 can be configured as or otherwise support a means for biasing a first access line to a first voltage. In some cases, to support applying a first pulse to a memory cell having a first polarity, the access operation component 730 can be configured as or otherwise support a means for biasing a second access line to a second voltage. In some examples, the first access line includes a word line and the second access line includes a digit line. In some examples, the first access line includes a digit line and the second access line includes a word line.

[0092] In some examples, to support isolating a first access line from a voltage source, the isolation component 735 can be configured as or otherwise support a means for biasing a gate of a transistor coupled with the voltage source and the first access line to a first voltage, where the transistor is deactivated based at least in part on the gate of the transistor being biased. In some cases, to support isolating a first access line from a voltage source, the isolation component 735 can be configured as or otherwise support a means for deactivating a voltage source based at least in part on not receiving a signal.

[0093] In some examples, the receiving component 725 can be configured as or otherwise support a means for receiving, at a memory device, a command to write information to a memory cell configured to store three or more states.

[0094] In some examples, the access operation component 730 can be configured as or otherwise support means for writing a memory cell of the memory device to an intermediate state of three or more states based at least in part on receiving a command, where writing the memory cell to the intermediate state includes applying a first pulse to the memory cell having a first polarity, applying a second pulse to the memory cell having a second polarity based at least in part on applying the first pulse, isolating a first access line coupled with the memory cell from a voltage source based at least in part on applying the second pulse having the second polarity, and applying a third pulse to a second access line coupled with the memory cell to write the memory cell to the intermediate state based at least in part on isolating the first access line coupled with the memory cell. In some instances, the access operation component 730 can be configured as or otherwise support means for applying a first pulse to a memory cell having a first polarity.

[0095] In some cases, the access operation component 730 can be configured as or otherwise support means for applying a second pulse to the memory cell having a second polarity based at least in part on applying a first pulse. In some examples, the access operation component 730 can be configured as or otherwise support means for applying a third pulse to a second access line coupled with the memory cell to write the memory cell to an intermediate state based at least in part on isolating a first access line coupled with the memory cell.

[0096] In some examples, to support writing a memory cell to an intermediate state, the access operation component 730 can be configured as or otherwise support means for biasing a first access line to a first voltage based at least in part on applying a second pulse, where isolating the first access line is based at least in part on biasing the first access line to the first voltage. In some cases, the access operation component 730 can be configured as or otherwise support means for applying a first pulse for a first duration and applying a third pulse for a second duration, the first duration being greater than the second duration. In some instances, to support applying a first pulse to a memory cell having a first polarity, the access operation component 730 can be configured as or otherwise support means for biasing a first access line to a first voltage. In some instances, to support applying a first pulse to a memory cell having a first polarity, the access operation component 730 can be configured as or otherwise support means for biasing a second access line to a second voltage.

[0097] In some cases, to support applying the second pulse to the memory cell having the second polarity, the access operation component 730 can be configured as or otherwise support means for biasing the first access line to a second voltage. In some examples, to support applying the second pulse to the memory cell having the second polarity, the access operation component 730 can be configured as or otherwise support means for biasing the second access line to the first voltage.

[0098] In some cases, the isolation component 735 can be configured as or otherwise support means for isolating the first access line coupled with the memory cell from the voltage source based at least in part on applying the second pulse having the second polarity.

[0099] In some examples, to support isolating the first access line, the isolation component 735 can be configured as or otherwise support means for biasing a gate of a transistor coupled with the voltage source and the first access line to a first voltage, where the transistor is deactivated based at least in part on the gate of the transistor being biased. In some cases, to support isolating the first access line, the isolation component 735 can be configured as or otherwise support means for deactivating the voltage source based at least in part on not receiving a signal.

[0100] Figure 8 A flow diagram illustrating a method 800 of supporting programming techniques for memory cells on a polarity basis in accordance with examples as disclosed herein is shown. The operations of method 800 can be implemented by a memory device or its components as described herein. For example, the operations of method 800 can be performed by a memory device as described with reference to Figures 1 to 7 The operations of method 800 can be performed by a memory device as described with reference to FIGS. 1-6. In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0101] At 805, the method can include receiving, at a memory device, a command to write information to a memory cell including a chalcogenide material and configured to store a set state, a reset state, and an intermediate state. The operations of 805 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 805 can be performed by a receiving component 725 as described with reference to Figure 7

[0102] At 810, the method can include writing, based at least in part on receiving the command, a memory cell of the memory device to an intermediate state, where writing the memory cell to the intermediate state can include features described with reference to 815 and 820. The operations of 810 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 810 can be performed by a writing component 730 as described with reference to Figure 7 ​Aspects of the operations performed by access operation component 730 described at 810 can be performed.

[0103] At 815, the method can include applying a first pulse having a first polarity to a memory cell, the first pulse configured to condition the memory cell. The operations of 815 can be performed according to examples as disclosed herein. In some examples, the operations of 815 can be performed by an apply component as Figure 7 Aspects of the operations performed by access operation component 730 described at 815 can be performed.

[0104] At 820, the method can include isolating a first access line coupled with a memory cell from a voltage source based at least in part on applying a first pulse having a first polarity. The operations of 820 can be performed according to examples as disclosed herein. In some examples, the operations of 820 can be performed by an isolation component as Figure 7 Aspects of the operations performed by isolation component 735 described at 820 can be performed.

[0105] At 825, the method can include applying a second pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell. The operations of 825 can be performed according to examples as disclosed herein. In some examples, the operations of 825 can be performed by an apply component as Figure 7 Aspects of the operations performed by access operation component 730 described at 825 can be performed.

[0106] In some examples, an apparatus as described herein can perform one or more methods, such as method 800. An apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions that are executable by a processor) for receiving, at a memory device, a command to write information to a memory cell including a chalcogenide material and configured to store a set state, a reset state, and an intermediate state; writing, based at least in part on receiving the command, a memory cell of the memory device to the intermediate state, wherein writing the memory cell to the intermediate state includes applying a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell; isolating, based at least in part on applying the first pulse having the first polarity, a first access line coupled with the memory cell from a voltage source; and applying, based at least in part on isolating the first access line coupled with the memory cell, a second pulse to a second access line coupled with the memory cell.

[0107] In some examples of the method 800 and apparatus described herein, writing a memory cell to an intermediate state can include operations, features, circuitry, logic, means, or instructions for biasing a first access line to a first voltage, wherein isolating the first access line can be based at least in part on biasing the first access line to the first voltage.

[0108] In some examples of the method 800 and apparatus described herein, a first pulse can be applied to a memory cell for a first duration, a second pulse can be applied for a second duration, the first duration being greater than the second duration.

[0109] In some cases of the method 800 and apparatus described herein, writing the memory cell to the intermediate state can include operations, features, circuitry, logic, means, or instructions for applying a third pulse having a second polarity to the memory cell prior to isolating the first access line, the third pulse configured to condition the memory cell.

[0110] In some examples of the method 800 and apparatus described herein, the first polarity can be a positive polarity and the second polarity can be a negative polarity.

[0111] In some examples of the method 800 and apparatus described herein, the first pulse can be configured to mitigate a shift in a threshold voltage associated with the memory cell.

[0112] In some cases of the method 800 and apparatus described herein, isolating the first access line from the voltage source can include operations, features, circuitry, logic, means, or instructions for biasing a gate of a transistor coupled with the voltage source and the first access line to a first voltage, where the transistor can be deactivated based at least in part on the gate of the transistor being biased.

[0113] In some examples of the method 800 and apparatus described herein, isolating the first access line from the voltage source can include operations, features, circuitry, logic, means, or instructions for deactivating the voltage source based at least in part on not receiving a signal.

[0114] In some examples of the method 800 and apparatus described herein, applying the second pulse to the second access line can include operations, features, circuitry, logic, means, or instructions for biasing the second access line to a first voltage.

[0115] In some cases of the method 800 and apparatus described herein, applying the first pulse to the memory cell can include operations, features, circuitry, logic, means, or instructions for biasing a first access line to a first voltage and biasing a second access line to a second voltage.

[0116] In some examples of the method 800 and apparatus described herein, the first access line includes a word line and the second access line includes a digit line.

[0117] In some examples of the method 800 and apparatus described herein, the first access line includes a digit line and the second access line includes a word line.

[0118] Figure 9 A flow diagram illustrating a method 900 that supports programming techniques for polarity-based memory cells in accordance with examples as disclosed herein is shown. The operations of method 900 can be implemented by a memory device or its components as described herein. For example, the operations of method 900 can be performed by a memory device as described with reference to Figures 1 to 7 The operations of method 900 can be implemented by a memory device or its components as described herein. For example, the operations of method 900 can be performed by a memory device as described with reference to

[0119] At 905, the method can include receiving, at a memory device, a command to write information to a memory cell configured to store three or more states. The operations of 905 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 905 can be performed by a receiving component 725 as described with reference to Figure 7 The operations of 905 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 905 can be performed by a receiving component 725 as described with reference to

[0120] At 910, the method can include writing, based at least in part on receiving the command, a memory cell of the memory device to an intermediate state of the three or more states, where writing the memory cell to the intermediate state can include features described with reference to 915, 920, 925, and 930. The operations of 910 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 910 can be performed by an access operation component 730 as described with reference to Figure 7 The operations of 910 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 910 can be performed by an access operation component 730 as described with reference to

[0121] At 915, the method can include applying a first pulse having a first polarity to the memory cell. The operations of 915 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 915 can be performed by an access operation component 730 as described with reference to Figure 7 The operations of 915 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 915 can be performed by an access operation component 730 as described with reference to

[0122] At 920, the method can include applying, based at least in part on applying the first pulse, a second pulse having a second polarity to the memory cell. The operations of 920 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 920 can be performed by an access operation component 730 as described with reference to Figure 7 The operations of 920 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 920 can be performed by an access operation component 730 as described with reference to

[0123] At 925, the method can include isolating, based at least in part on applying the second pulse having the second polarity, a first access line coupled with the memory cell from a voltage source. The operations of 925 can be performed according to the examples as disclosed herein. In some examples, aspects of the operations of 925 can be performed by an access operation component 730 as described with reference toFigure 7 Aspects of the operations performed by the isolation component 735 described are executed 925.

[0124] At 930, the method can include applying a third pulse to a second access line coupled with the memory cell to write the memory cell to an intermediate state based at least in part on isolating a first access line coupled with the memory cell. The operations of 930 can be performed according to examples as disclosed herein. In some examples, 930 can be performed by an isolation component as Figure 7 Aspects of the operations of 930 can be performed by the access operation component 730 described.

[0125] In some examples, an apparatus as described herein can perform one or several methods, such as the method 900. An apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions that are executable by a processor) for receiving, at a memory device, a command to write information to a memory cell configured to store three or more states; writing, based at least in part on receiving the command, a memory cell of the memory device to an intermediate state of the three or more states, where writing the memory cell to the intermediate state includes applying a first pulse having a first polarity to the memory cell, applying a second pulse having a second polarity to the memory cell based at least in part on applying the first pulse, isolating a first access line coupled with the memory cell from a voltage source based at least in part on applying the second pulse having the second polarity, and applying a third pulse to a second access line coupled with the memory cell to write the memory cell to the intermediate state based at least in part on isolating the first access line coupled with the memory cell.

[0126] In some cases of the method 900 and apparatus described herein, writing the memory cell to the intermediate state can include operations, features, circuitry, logic, means, or instructions for biasing a first access line to a first voltage based at least in part on applying the second pulse, where isolating the first access line can be based at least in part on biasing the first access line to the first voltage.

[0127] In some examples of the method 900 and apparatus described herein, the first pulse can be applied to the memory cell for a first duration and the third pulse can be applied for a second duration, the first duration being greater than the second duration.

[0128] In some examples of the method 900 and apparatus described herein, isolating the first access line can include operations, features, circuitry, logic, means, or instructions for biasing a gate of a transistor coupled with the voltage source and the first access line to a first voltage, where deactivating the transistor can be undone based at least in part on the gate of the transistor being biased.

[0129] In some examples of the method 900 and apparatus described herein, isolating the first access line can include operations, features, circuitry, logic, means, or instructions for deactivating the voltage source based at least in part on not receiving a signal.

[0130] In some examples of the method 900 and apparatus described herein, applying the first pulse to the memory cell that can have a first polarity can include operations, features, circuitry, logic, means, or instructions for biasing the first access line to a first voltage and biasing the second access line to a second voltage.

[0131] In some cases of the method 900 and apparatus described herein, applying the second pulse to the memory cell that can have a second polarity can include operations, features, circuitry, logic, means, or instructions for biasing the first access line to a second voltage and biasing the second access line to a first voltage.

[0132] In some examples of the method 900 and apparatus described herein, the first access line includes a word line and the second access line includes a digit line.

[0133] In some examples of the method 900 and apparatus described herein, the first access line includes a digit line and the second access line includes a word line.

[0134] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more methods can be combined.

[0135] Another device is described. The device can include a memory array including memory cells including a chalcogenide material and configured to store a set state, a reset state, and an intermediate state; a controller coupled with the memory array and configured to cause the device to receive a command to write information to the memory cells and to write a memory cell of the memory cells to the intermediate state based at least in part on receiving the command, where to write the memory cell to the intermediate state, the controller is further configured to apply a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell, isolate a first access line coupled with the memory cell from a voltage source based at least in part on applying the first pulse having the first polarity, and apply a second pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell.

[0136] In some examples, the device can include biasing a first access line to a first voltage, where the controller can be configured to isolate the first access line based at least in part on biasing the first access line to the first voltage.

[0137] Another device is described. The device can include a memory array including memory cells configured to store three or more states; a controller coupled with the memory array and configured to cause the device to receive a write command to write information to the memory cells and to write a memory cell of the memory cells to an intermediate state of the three or more states based at least in part on receiving the command, where to write the memory cell to the intermediate state, the controller is further configured to apply a first pulse having a first polarity to the memory cell, apply a second pulse having a second polarity to the memory cell based at least in part on applying the first pulse, isolate a first access line coupled with the memory cell from a voltage source based at least in part on applying the second pulse having the second polarity, and apply a third pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell.

[0138] In some cases, the device can include biasing a first access line to a first voltage based at least in part on applying a second pulse, where the controller can be configured to isolate the first access line based at least in part on biasing the first access line to the first voltage.

[0139] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by those skilled in the art that the signals can represent a bus of signals, where buses can have a variety of bit widths.

[0140] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which the relationship supports the flow of signals between the components. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if there exists any conductive path between the components that can support the flow of signals between the components at some time. The conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other can be open or closed at any given time based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time using one or more intervening components such as switches or transistors, for example.

[0141] The term "coupled" refers to the condition of components that are in an open circuit relationship between the components from which signals cannot currently pass via a conductive path between the components to a closed circuit relationship between the components that are capable of passing signals via a conductive path between the components. When a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path through which signals were not previously allowed to flow.

[0142] The term "isolated" refers to a relationship between components from which signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, two components that are separated by a switch positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller implements a change that prevents signals from flowing between the components using a conductive path through which signals were previously allowed to flow.

[0143] The devices (including memory arrays) discussed herein can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be an epitaxial layer of semiconductor material on an insulator (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate by ion implantation or by any other doping means.

[0144] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include one three-terminal device including a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive material (e.g., metal). The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor can be "turned off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

[0145] The description set forth herein, in connection with the appended drawings and description, describes exemplary configurations and does not represent all of the instances that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" over other examples. The implementations

[0146] In the drawings, like reference numerals can be used to denote like components throughout the several views. Additionally, components of the same type can be distinguished by the use of a lettered suffix, e.g., 102a, 102b, etc. If only the first reference numeral is used in the specification, the description is applicable to any one of the similarly designated components having the same first reference numeral irrespective of the suffix.

[0147] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0148] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein can be employed. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0149] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0150] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0151] The description herein is presented to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operations, comprising: receiving, at a memory device, a command to write information to a memory cell comprising a chalcogenide material and configured to store a set state, a reset state, and an intermediate state; and writing, based at least in part on receiving the command, a memory cell of the memory device to the intermediate state, wherein writing the memory cell to the intermediate state comprises: applying a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell; biasing a first access line to a first voltage; isolating, based at least in part on applying the first pulse having the first polarity and biasing the first access line to the first voltage, the first access line coupled with the memory cell from a voltage source; and applying a second pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell.

2. The method of claim 1, wherein isolating the first access line from the voltage source further comprises: biasing a gate of a transistor coupled with the voltage source and the first access line to a second voltage, wherein deactivating the transistor is revoked based at least in part on biasing the gate of the transistor.

3. The method of claim 1, wherein isolating the first access line from the voltage source further comprises: deactivating the voltage source based at least in part on not receiving a signal.

4. The method of claim 1, wherein applying the second pulse to the second access line further comprises: biasing the second access line to a second voltage.

5. The method of claim 1, wherein applying the first pulse to the memory cell having the first polarity further comprises: biasing the first access line to the first voltage; and biasing the second access line to a second voltage.

6. The method of claim 1, wherein the first access line comprises a word line and the second access line comprises a digit line.

7. The method of claim 1, wherein the first access line comprises a digit line and the second access line comprises a word line.

8. A method for memory operations, comprising: receiving, at a memory device, a command to write information to a memory cell comprising a chalcogenide material and configured to store a set state, a reset state, and an intermediate state; and writing, based at least in part on receiving the command, a memory cell of the memory device to the intermediate state, wherein writing the memory cell to the intermediate state comprises: applying a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell; isolating, based at least in part on applying the first pulse having the first polarity, a first access line coupled with the memory cell from a voltage source; and applying a second pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell. applying a second pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell, wherein the first pulse is applied to the memory cell for a first duration and the second pulse is applied for a second duration, the first duration being greater than the second duration.

9. A method for memory operations, comprising: receiving, at a memory device, a command to write information to a memory cell comprising a chalcogenide material and configured to store a set state, a reset state, and an intermediate state; and writing, based at least in part on receiving the command, a memory cell of the memory device to the intermediate state, wherein writing the memory cell to the intermediate state comprises: applying a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell; applying a second pulse having a second polarity to the memory cell prior to isolating a first access line, the second pulse configured to condition the memory cell; isolating, based at least in part on applying the first pulse having the first polarity, the first access line coupled with the memory cell from a voltage source; and applying a third pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell.

10. The method of claim 9, wherein the first polarity is a positive polarity and the second polarity is a negative polarity.

11. The method of claim 9, wherein the first pulse is configured to mitigate a drift of a threshold voltage associated with the memory cell.

12. A method for memory operations, comprising: receiving, at a memory device, a command to write information to a memory cell configured to store three or more states; and writing, based at least in part on receiving the command, a memory cell of the memory device to an intermediate state of the three or more states, wherein writing the memory cell to the intermediate state comprises: applying a first pulse having a first polarity to the memory cell; applying a second pulse having a second polarity to the memory cell based at least in part on applying the first pulse; biasing, based at least in part on applying the second pulse, a first access line to a first voltage; isolating, based at least in part on applying the second pulse having the second polarity and biasing the first access line to the first voltage, the first access line coupled with the memory cell from a voltage source; and applying a third pulse to a second access line coupled with the memory cell to write the memory cell to the intermediate state based at least in part on isolating the first access line coupled with the memory cell.

13. The method of claim 12, wherein isolating the first access line further comprises: deactivating the voltage source based at least in part on not receiving a signal.

14. The method of claim 12, wherein applying the first pulse to the memory cell having the first polarity further comprises: biasing the first access line to the first voltage; and biasing the second access line to a second voltage.

15. The method of claim 14, wherein applying the second pulse to the memory cell having the second polarity further comprises: biasing the first access line to the second voltage; and biasing the second access line to the first voltage.

16. The method of claim 12, wherein the first access line comprises a word line and the second access line comprises a digit line.

17. The method of claim 12, wherein the first access line comprises a digit line and the second access line comprises a word line.

18. A method for memory operations, comprising: receiving, at a memory device, a command to write information to a memory cell configured to store three or more states; and writing, based at least in part on receiving the command, a memory cell of the memory device to an intermediate state of the three or more states, wherein writing the memory cell to the intermediate state comprises: applying a first pulse having a first polarity to the memory cell; applying a second pulse having a second polarity to the memory cell based at least in part on applying the first pulse; isolating, based at least in part on applying the second pulse having the second polarity, a first access line coupled with the memory cell from a voltage source; and applying a third pulse to a second access line coupled with the memory cell to write the memory cell to the intermediate state based at least in part on isolating the first access line coupled with the memory cell from the voltage source, wherein the first pulse is applied to the memory cell for a first duration and the third pulse is applied for a second duration, the first duration being greater than the second duration.

19. A method for memory operations, comprising: receiving, at a memory device, a command to write information to a memory cell configured to store three or more states; and writing, based at least in part on receiving the command, a memory cell of the memory device to an intermediate state of the three or more states, wherein writing the memory cell to the intermediate state comprises: applying a first pulse having a first polarity to the memory cell; applying a second pulse having a second polarity to the memory cell based at least in part on applying the first pulse; isolating, based at least in part on applying the second pulse having the second polarity, a first access line coupled with the memory cell from a voltage source, wherein isolating the first access line further comprises biasing a gate of a transistor coupled with the voltage source and the first access line to a first voltage, wherein deactivating the transistor is revoked based at least in part on biasing the gate of the transistor; and applying a third pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell.

20. A memory device, comprising: a memory array comprising memory cells, the memory cells comprising a chalcogenide material and configured to store a set state, a reset state, and an intermediate state; and a controller coupled with the memory array and configured to cause the memory device to: receive a command to write information to the memory cells; and write a memory cell of the memory cells to the intermediate state based at least in part on receiving the command, wherein to write the memory cell to the intermediate state, the controller is further configured to: apply a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell; bias a first access line to a first voltage; isolate the first access line coupled with the memory cell from a voltage source based at least in part on applying the first pulse having the first polarity and biasing the first access line to the first voltage; and apply a second pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell.

21. A memory device, comprising: a memory array comprising memory cells, the memory cells configured to store three or more states; and a controller coupled with the memory array and configured to cause the memory device to: receive a command to write information to the memory cells; and write a memory cell of the memory cells to an intermediate state of the three or more states based at least in part on receiving the command, wherein to write the memory cell to the intermediate state, the controller is further configured to: apply a first pulse having a first polarity to the memory cell; apply a second pulse having a second polarity to the memory cell based at least in part on applying the first pulse; bias a first access line to a first voltage based at least in part on applying the second pulse; isolate the first access line coupled with the memory cell from a voltage source based at least in part on applying the second pulse having the second polarity and biasing the first access line to the first voltage; and apply a third pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell. ​ ​

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