Multi-input low voltage drop linear voltage regulator circuit and control method thereof

Abstract

The present invention discloses a multi-input low-voltage dropout linear voltage regulator circuit, comprising: an LDO unit, comprising a first low-voltage dropout linear voltage regulator and a second low-voltage dropout linear voltage regulator connected to the same output node, the first low-voltage dropout linear voltage regulator comprising a first operational amplifier and a first power device, and its input voltage is a first input voltage, the second low-voltage dropout linear voltage regulator comprising a second operational amplifier and a second power device, and its input voltage is a second input voltage; a reference voltage selection unit, used for selecting the reference voltage of the first operational amplifier as the second reference voltage and the reference voltage of the second operational amplifier as the first reference voltage when the first low-voltage dropout linear voltage regulator is switched to the second low-voltage dropout linear voltage regulator, wherein the first reference voltage is greater than the second reference voltage. In the present invention, by optimizing the structure and working sequence of the multi-input LDO circuit, the smooth switching of different LDOs can be realized, the power supply fluctuation amplitude of the internal analog circuit is greatly reduced, and the output voltage of the LDO will not erroneously trigger the UVLO during different switching processes, thereby ensuring the normal working state and good performance of the circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of low voltage difference linear voltage regulators, and in particular relates to a multi-input low voltage difference linear voltage regulator circuit. Background Art

[0002] In a DC-DC power conversion chip, in order to reduce the static power consumption drawn by the chip from the power supply to improve the transmission efficiency from the power supply to the output, one approach is to switch the power supply of the low dropout regulator (LDO) to another power supply. This requires the LDO to have the ability to detect multiple power inputs and switch power supplies.

[0003] There are two main problems in the prior art: First, considering the voltage difference between multiple input power supplies, it is necessary to add an anti-backflow circuit to the power supply path. In the prior art, diodes are generally used as anti-backflow devices, and their unidirectional conductivity is used to achieve the anti-backflow function. However, since there is a voltage drop of about 0.7V when the diode is turned on, the power consumption is further increased, limiting the voltage margin of the LDO internal circuit. Secondly, if the traditional detection hard switching timing is used, during the input power switching process, the output voltage of the LDO is at risk of being pulled down, resulting in the false triggering of the undervoltage lockout (UVLO) voltage.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a multi-input low voltage difference linear voltage regulator circuit. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a multi-input low voltage dropout linear voltage regulator circuit to prevent the output voltage from erroneously triggering UVLO during the input power switching process.

[0006] In order to achieve the above object, the present invention provides a multi-input low voltage drop linear voltage regulator circuit, the low voltage drop linear regulator comprising:

[0007] The LDO unit includes a first low-voltage dropout linear regulator and a second low-voltage dropout linear regulator connected to the same output node, the first low-voltage dropout linear regulator includes a first operational amplifier and a first power device, the first power device receives a first input voltage, and the second low-voltage dropout linear regulator includes a second operational amplifier and a second power device, and its input voltage is a second input voltage;

[0008] The reference voltage selection unit is used to select the reference voltage of the first operational amplifier as the second reference voltage and the reference voltage of the second operational amplifier as the first reference voltage when the first low-voltage difference linear regulator is switched to the second low-voltage difference linear regulator, wherein the first reference voltage is greater than the second reference voltage.

[0009] The present invention can realize smooth switching of different LDOs by optimizing the structure and working sequence of the multi-input LDO circuit, greatly reducing the power supply fluctuation amplitude of the internal analog circuit, and the output voltage of the LDO will not erroneously trigger the UVLO during different switching processes, thereby ensuring the normal working state and good performance of the circuit;

[0010] In addition, MOS tubes are used as anti-backflow devices. They have unidirectional conductivity when turned off and reduce voltage drop when turned on, which has the advantages of reducing power consumption and increasing voltage margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0012] Figure 1 It is a circuit diagram of a multi-input low voltage difference linear voltage regulator circuit in the prior art;

[0013] Figure 2 It is a working timing diagram of a multi-input low voltage difference linear voltage regulator circuit in the prior art;

[0014] Figure 3a A circuit diagram of a multi-input low voltage difference linear voltage regulator circuit in one embodiment of the present invention;

[0015] Figure 3b is a circuit diagram of a signal generating circuit in one embodiment of the present invention;

[0016] Figure 4 for Figure 3a Working timing diagram of the multi-input low voltage difference linear voltage regulator circuit in the embodiment;

[0017] Figure 5 A circuit diagram of a multi-input low voltage difference linear voltage regulator circuit in another embodiment of the present invention;

[0018] Figure 6 A circuit diagram of a multi-input low voltage difference linear voltage regulator circuit in another embodiment of the present invention;

[0019] Figure 7 A circuit diagram of a multi-input low voltage difference linear voltage regulator circuit in another embodiment of the present invention;

[0020] Figure 8 FIG. 4 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit in another embodiment of the present invention.

[0021] Fig. 9This is a flow chart of a control method for a multi-input low voltage dropout linear voltage regulator circuit in another embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the technical scheme in the present invention better understood by the personnel in the technical field, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work should belong to the scope of protection of the present invention. The embodiments described here are only for illustration and are not intended to limit the present invention. Throughout the specification, the reference to "one embodiment", "an embodiment", "an example" or "an example" means that the specific features, structures or characteristics described in conjunction with the embodiment or example are included in at least one embodiment of the present invention. The phrases "in an embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example, and specific features, structures or specific combinations can be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination.

[0023] In the description herein, unless otherwise specified and limited, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances. In addition, it should be understood by those skilled in the art that the drawings provided herein are for illustrative purposes and the drawings are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" includes any and all combinations of one or more related listed items.

[0024] It should be understood that although the terms first, second, third, etc. may be used herein to describe various devices, elements, components, or parts, this should not be limited by these terms. These terms are used to distinguish one from another. For example, a first device may also be called a second device without departing from the essential technical solution of the embodiments of the present application.

[0025] Figure 1 The circuit diagram of the multi-input low voltage difference linear voltage regulator circuit in the prior art is shown, which includes:

[0026] A feedback unit, comprising a first resistor R1 connected between the output node and the feedback node, and a second resistor R2 connected between the feedback node and a reference potential;

[0027] A first operational amplifier AMP1, a first power device MP1 and a first diode D1, wherein a first input terminal of the first operational amplifier AMP1 is connected to a reference voltage VREF, a second input terminal is connected to a feedback node in a voltage divider unit, an enable terminal of the first operational amplifier AMP1 receives a first enable signal VIN_LDO_EN, the first power device MP1 is a PMOS tube, a source terminal is connected to a first input voltage VIN, a drain terminal is connected to a positive electrode of the first diode D1, a gate terminal is connected to an output terminal of the first operational amplifier AMP1, and a cathode of the first diode D1 is connected to an output node;

[0028] A second operational amplifier AMP2, a second power device MP2 and a second diode D2, wherein a first input terminal of the second operational amplifier AMP2 is connected to a reference voltage VREF, a second input terminal is connected to a feedback node in a feedback unit, an enable terminal of the second operational amplifier AMP2 receives a second enable signal VBIAS_LDO_EN, the second power device MP2 is a PMOS tube, a source terminal is connected to a second input voltage BIAS, a drain terminal is connected to a positive electrode of the second diode D2, a gate terminal is connected to an output terminal of the second operational amplifier AMP2, and a cathode of the second diode D2 is connected to an output node;

[0029] The first low-dropout linear regulator LDO1 includes a first operational amplifier AMP1, a first power device MP1, a first diode D1 and a feedback unit. The second low-dropout linear regulator LDO2 includes a second operational amplifier AMP2, a second power device MP2, a second diode D2 and a feedback unit. The voltage outputted by the output node is the output voltage VCC.

[0030] Ginseng Figure 2 Shown Figure 1 The working timing diagram of the multi-input low voltage difference linear voltage regulator circuit in the prior art is shown, and its working principle is specifically as follows:

[0031] When it is detected that the second input voltage BIAS exceeds the first threshold voltage VTH1, BIAS_UV_BUF becomes a low level, the first enable signal VIN_LDO_EN received by LDO1 becomes a low level, LDO1 is turned off, and VCC is pulled low; the second enable signal VBIAS_LDO_EN received by LDO2 becomes a high level, LDO2 is turned on, and the LDO2 operating point begins to be established, and its rate is related to the bias current and parasitic capacitance.

[0032] Before LDO2 is fully established, VCC will continue to lose power. At this time, the voltage margin of the analog circuit working in the VCC domain will decrease rapidly, which may cause abnormal circuit performance. The worst case is that it drops below the UVLO voltage VCC_UV to trigger the UVLO protection, which is an incorrect state for a normally operating circuit. Similarly, when the BIAS voltage drops below the second threshold voltage VTH2, causing the multi-input low-dropout linear regulator circuit to switch back to LDO1, the VCC will also lose power too much. When the BIAS voltage is higher than VIN, due to the reverse bias of D1, there will be no phenomenon of BIAS to VIN current injection, and vice versa. BIAS_UV_BUF is used to characterize whether BIAS is greater than the first threshold or less than the second threshold.

[0033] Figure 3a The circuit diagram of the multi-input low voltage drop linear voltage regulator circuit according to an embodiment of the present invention is shown. The multi-input low voltage drop linear voltage regulator circuit includes:

[0034] The LDO unit includes a first low-voltage dropout linear regulator LDO1 and a second low-voltage dropout linear regulator LDO2 connected to the same output node; the first low-voltage dropout linear regulator LDO1 includes a first operational amplifier AMP1 and a first power device 201, and the input voltage of the first low-voltage dropout linear regulator LDO1 is a first input voltage VIN; the second low-voltage dropout linear regulator LDO2 includes a second operational amplifier AMP2 and a second power device 202, and the input voltage of the second low-voltage dropout linear regulator LDO2 is a second input voltage BIAS.

[0035] The reference voltage selection unit 10 is used to select the reference voltage of the first operational amplifier AMP1 as the second reference voltage VREFb and the reference voltage of the second operational amplifier AMP2 as the first reference voltage VREFa when the first low-voltage dropout linear regulator LDO1 is switched to the second low-voltage dropout linear regulator LDO2. The first reference voltage VREFa is greater than the second reference voltage VREFb. The first input terminal of the first operational amplifier AMP1 and the first input terminal of the second operational amplifier AMP2 are input terminals of the reference voltage.

[0036] In one embodiment of the present invention, the first power device 201 and / or the second power device 202 include a P-type MOS tube, but those skilled in the art should realize that the first power device 201 and / or the second power device 202 may also include an N-type MOS tube, or other types of power devices, such as BJT (bipolar transistor), IGBT (insulated gate bipolar transistor), etc.

[0037] In one embodiment of the present invention, the reference voltage selection unit 10 selects the reference voltage of the first operational amplifier AMP1 based on the first reference voltage selection signal VREF1_SEL, and selects the reference voltage of the second operational amplifier AMP2 based on the second reference voltage selection signal VREF2_SEL.

[0038] The LDO unit also includes:

[0039] The feedback unit 30 is connected between the output node and the reference potential; the feedback unit 30 is configured to provide a feedback signal to the second input terminal of the first operational amplifier AMP1 and / or the second input terminal of the second operational amplifier AMP2.

[0040] The first input terminal of the first operational amplifier AMP1 is connected to the reference voltage selection unit 10, the second input terminal is connected to the feedback node in the feedback unit 30, the first terminal of the first power device 201 is connected to the first input voltage VIN, the second terminal is connected to the output node, and the control terminal is connected to the output terminal of the first operational amplifier AMP1;

[0041] The first input terminal of the second operational amplifier AMP2 is connected to the reference voltage selection unit 10, the second input terminal is connected to the feedback node in the feedback unit, the first terminal of the second power device 202 is connected to the second input voltage BIAS, the second terminal is connected to the output node, and the control terminal is connected to the output terminal of the second operational amplifier AMP2.

[0042] The first low dropout linear regulator LDO1 includes a first operational amplifier AMP1 , a first power device 201 and a feedback unit 30 , and the second low dropout linear regulator LDO2 includes a second operational amplifier AMP2 , a second power device 202 and a feedback unit 30 .

[0043] In one embodiment of the present invention, the feedback unit includes a first resistor R1 connected between the output node and the feedback node, and a second resistor R2 connected between the feedback node and a reference potential.

[0044] In one embodiment of the present invention, the reference voltage selection unit 10 may select a voltage selector, and output a corresponding reference voltage by respectively inputting a first reference voltage selection signal VREF1_SEL and / or a second reference voltage selection signal VREF2_SEL, and the output reference voltage includes a first reference voltage VREFa and a second reference voltage VREFb, satisfying VREFa>VREFb.

[0045] In one embodiment of the present invention, the reference voltage selection unit 10 includes a first reference voltage selector 101 and a second reference voltage selector 102. The first reference voltage selector 101 is used to select the first reference voltage VREFa or the second reference voltage VREFb for the first operational amplifier AMP1. The second reference voltage selector 102 is used to select the first reference voltage VREFa or the second reference voltage VREFb for the second operational amplifier.

[0046] The first reference voltage selector 101 has a first input terminal connected to the first reference voltage VREFa, a second input terminal connected to the second reference voltage VREFb, an output terminal connected to the first input terminal of the first operational amplifier AMP1, and a control terminal connected to the first reference voltage selection signal VREF1_SEL. The second reference voltage selector 102 has a first input terminal connected to the first reference voltage VREFa, a second input terminal connected to the second reference voltage VREFb, an output terminal connected to the first input terminal of the second operational amplifier AM2, and a control terminal connected to the second reference voltage selection signal VREF2_SEL.

[0047] In one embodiment of the present invention, when the first reference selection signal VREF1_SEL / the second reference voltage selection signal VREF2_SEL is at a low level, the first reference voltage VREFa is selected, and when it is at a high level, the second reference voltage VREFb is selected. However, those skilled in the art should appreciate that in other implementations, when the first reference selection signal VREF1_SEL / the second reference voltage selection signal VREF2_SEL is at a high level, the first reference voltage VREFa is selected, and when it is at a low level, the second reference voltage VREFb is selected.

[0048] In one embodiment of the present invention, the first op amp AMP1 and the second op amp AMP2 are enabled and controlled by the first op amp enable signal VIN_LDO_EN and the second op amp enable signal VBIAS_LDO_EN, respectively. For example, when the first op amp enable signal VIN_LDO_EN and / or the second op amp enable signal VBIAS_LDO_EN are valid, the first op amp AMP1 and / or the second op amp AMP2 are enabled to work; when the first op amp enable signal VIN_LDO_EN and / or the second op amp enable signal VBIAS_LDO_EN are invalid, the first op amp AMP1 and / or the second op amp AMP2 do not work. The valid level can be a high level or a low level; the invalid level can be a low level or a high level.

[0049] In one embodiment of the present invention, a first backflow prevention device is provided between the second end of the first power device 201 and the output node, and a second backflow prevention device is provided between the second end of the second power device 202 and the output node.

[0050] In one embodiment of the present invention, the first anti-backflow device is a first switch tube 203, which can be a PMOS tube, whose source is connected to the output node, whose drain is connected to the drain of the first power device 201, and whose gate is connected to the first op amp enable signal VIN_LDO_EN of the first op amp AMP1; the second anti-backflow device is a second switch tube 204, which can be a PMOS tube, whose source is connected to the output node, whose drain is connected to the drain of the second power device 202, and whose gate is connected to the second op amp enable signal VBIAS_LDO_EN of the second op amp AMP2.

[0051] In one embodiment of the present invention, the first operational amplifier enable signal VIN_LDO_EN is inverted by an inverter and then output to the gate of the first switch tube 203 to drive the first switch tube 203. The second operational amplifier enable signal VBIAS_LDO_EN is inverted by another inverter and then output to the gate of the second switch tube 204 to drive the second switch tube 204.

[0052] Figure 3b The signal generating circuit 40 of one embodiment of the present invention is shown. The signal generating circuit 40 is configured to generate a control signal to control the reference voltage selection unit and the LDO unit. The signal generating circuit 40 includes a detection circuit 401, an operational amplifier enable signal generating circuit 402, and a reference voltage selection signal generating circuit 403.

[0053] The detection circuit 401 is configured to compare the second input voltage BIAS with the first threshold voltage VTH1 / the second threshold voltage VTH2, and output a detection signal BIAS_UV_BUF based on the comparison result. The signal generation circuit 40 generates a first reference voltage selection signal VREF1_SEL, a second reference voltage selection signal VREF2_SEL, a first op amp enable signal VIN_LDO_EN, and a second op amp enable signal VBIAS_LDO_EN based on the detection signal BIAS_UV_BUF.

[0054] In one embodiment of the present invention, the reference voltage selection signal generating circuit 403 generates a first reference voltage selection signal VREF1_SEL and a second reference voltage selection signal VREF2_SEL based on the detection signal BIAS_UV_BUF. The reference voltage selection signal generating circuit 403 includes an inverter and a follower. The detection signal BIAS_UV_BUF generates a first reference voltage selection signal VREF1_SEL and a second reference voltage selection signal VREF2_SEL after passing through a plurality of inverters and followers. The number of inverters and followers can be set accordingly according to the actual needs of the effective potential of the first reference voltage selection signal VREF1_SEL and the second reference voltage selection signal VREF2_SEL. Figure 3bIn the example, the second reference voltage selection signal VREF2_SEL is generated after passing through two serially connected inverters, and the first reference voltage selection signal VREF1_SEL is generated after passing through an inverter and a follower.

[0055] In one embodiment of the present invention, the operational amplifier enable signal generating circuit 402 generates a first operational amplifier enable signal VIN_LDO_EN and a second operational amplifier enable signal VBIAS_LDO_EN based on the detection signal BIAS_UV_BUF.

[0056] In one embodiment of the present invention, the detection signal BIAS_UV_BUF generates a second op amp enable signal VBIAS_LDO_EN after passing through a NAND gate 4022 and a follower 4023. A first input terminal of the NAND gate 4022 is connected to the detection signal BIAS_UV_BUF, and a second input terminal is connected to the output terminal of the hysteresis inverting unit 4020. The detection signal BIAS_UV_BUF generates a first op amp enable signal VIN_LDO_EN after passing through the hysteresis inverting unit 4020 and a follower 4024, and the hysteresis inverting unit 4020 includes a Schmitt trigger 4021.

[0057] Ginseng Figure 4 Shown Figure 3a The working timing diagram of the multi-input low voltage difference linear voltage regulator circuit in the embodiment, the working principle is as follows:

[0058] 1. In the first time period (the time period before TD1), the second input voltage BIAS is less than the first threshold voltage VTH1, the first op amp enable signal VIN_LDO_EN of the first op amp AMP1 is high, the second op amp enable signal VBIAS_LDO_EN of the second op amp AMP2 is low, the first reference voltage selection signal VREF1_SEL is low, the second reference voltage selection signal VREF2_SEL is high, the first reference voltage selector 101 outputs the first reference voltage VREFa, and the first low voltage difference linear regulator LDO1 modulates the output voltage VCC of the output node based on the first reference voltage VREFa.

[0059] 2. In the second time period, i.e., the TD1 period, TD1 is the first delay period, the second input voltage BIAS is greater than the first threshold voltage VTH1, the first operational amplifier enable signal VIN_LDO_EN of the first operational amplifier AMP1 remains at a high level, the second operational amplifier enable signal VBIAS_LDO_EN of the second operational amplifier AMP2 jumps and remains at a high level, the first reference voltage selection signal VREF1_SEL jumps to a high level, the first reference voltage selector 101 outputs the second reference voltage VREFb; the second reference voltage selection signal VREF2_SEL jumps to a low level, the second reference voltage selector 102 outputs the first reference voltage VREFa, the second low voltage difference linear regulator LDO2 modulates the output voltage VCC based on the first reference voltage VREFa, and the first low voltage difference linear regulator LDO1 modulates the output voltage VCC based on the second reference voltage VREFb. △V2 is the VCC power loss during this period.

[0060] 3. In the third time period (the time period between TD1 and TD2), the first op amp enable signal VIN_LDO_EN of the first op amp AMP1 jumps and remains at a low level, the second op amp enable signal VBIAS_LDO_EN of the second op amp AMP2 remains at a high level, and the second low dropout linear regulator LDO2 modulates the output voltage VCC based on the first reference voltage VREFa.

[0061] 4. In the fourth time period, i.e., the TD2 time period, TD2 is the second delay time period, the second input voltage BIAS decreases to less than the second threshold voltage VTH2, the first op amp enable signal VIN_LDO_EN of the first op amp AMP1 jumps and remains at a high level, the second op amp enable signal VBIAS_LDO_EN of the second op amp AMP2 remains at a high level, the first reference voltage selection signal VREF1_SEL jumps to a low level, the first reference voltage selector 101 outputs the first reference voltage VREFa, the second reference voltage selection signal VREF2_SEL jumps to a high level, the second reference voltage selector 102 outputs the second reference voltage VREFb, the first low dropout linear regulator LDO1 modulates the output voltage VCC based on the first reference voltage VREFa, and the second low dropout linear regulator LDO2 modulates the output voltage VCC based on the second reference voltage VREFb.

[0062] The first threshold voltage VTH1 and the second threshold voltage VTH2 are the same threshold voltage or different threshold voltages, and the duration of the second period is equal to or different from the duration of the fourth period, which can be set according to the LDO loop establishment time. Preferably, in this embodiment, the first threshold voltage VTH1 is greater than the second threshold voltage VTH2, and the duration of the TD1 period is equal to the duration of the TD2 period.

[0063] This embodiment optimizes the circuit structure and working sequence. When LDO1 and LDO2 switch, there is always a loop modulating VCC, which can achieve a small amount of power loss of VCC and ensure the normal working state and good performance of the circuit.

[0064] In addition, in one embodiment of the present invention, an anti-backflow PMOS switch tube is used as the first switch tube 203 and the second switch tube 204, and an anti-backflow PMOS switch tube controlled by the inverted signal of VIN_LDO_EN and VBIAS_LDO_EN is used to replace the diodes D1 and D2. In particular, the source potential of the PMOS switch tube is lower than the drain potential in the connection method, thereby realizing the anti-backflow function. In addition, since there is a voltage drop of about 0.7V when the diode is turned on, and the reduction of the on-state voltage drop of the PMOS switch tube is compared with using a diode as an anti-backflow device, lower power consumption and higher voltage margin can be obtained.

[0065] like Figure 3a , Figure 4 As shown, when the BIAS voltage rises to exceed VTH1, the second op amp enable signal VBIAS_LDO_EN jumps to a high level, immediately turns on the second switch tube 102, reduces its voltage drop to the minimum, and enables the second op amp AMP2 at the same time, while the first op amp enable signal VIN_LDO_EN remains at a high level, and the first op amp AMP1 is still enabled; at the same time, the first reference voltage selection signal VREF1_SEL jumps to a high level, selects the reference voltage of LDO1 as VREFb, and the second reference voltage selection signal VREF2_SEL jumps to a low level, selects the reference voltage of LDO2 as VREFa, and VREFa is greater than VREFb. Compared with the prior art, when LDO1 is turned off, LDO2 has not yet been established, and VCC power is too much off, see Figure 1 △V1 in the middle causes the risk of UVLO false triggering. The technical solution of the present invention ensures that during the TD1 period, there is always a loop in LDO1 and LDO2 that modulates VCC, thereby ensuring that VCC will not drop too much. Specifically, when the BIAS voltage rises to exceed VTH1, LDO2 begins to establish. At this time, if the establishment is too slow, the existence of the LDO1 loop ensures that the minimum VCC will not be lower than VREFb / R2*(R1+R2); if the LDO2 loop is established before VCC drops to VREFb / R2*(R1+R2), the LDO2 loop will pull down the gate of the second power device 202, and the LDO2 loop will modulate VCC alone. In this case, the LDO1 loop operates in an open-loop state, and the first power device 201 is turned off by the loop, reducing the risk of two loops controlling one voltage at the same time.

[0066] For example, VREFa=3V, VREFb=2.7V, R2 / (R1+R2)=3 / 5, then the VCC voltage of LDO1 / LDO2 is 5V when the reference voltage is 3V, and the VCC voltage is 4.5V when the reference voltage is 2.7V. When the BIAS voltage exceeds VTH1, the reference voltage of LDO1 is immediately switched from 3V to 2.7V, LDO2 is immediately turned on, and the reference voltage of LDO2 is switched from 2.7V to 3V, the steady-state VCC modulated by LDO1 changes from 5V to 4.5V, and the steady-state VCC modulated by LDO2 changes from 4.5V to 5V. During the establishment time of LDO2, the current of the second power device 202 is small, and VCC starts to drop from 5V under the power draw of the load current. Before dropping to 4.5V, the current of the first power device 201 gradually decreases, and the current of the second power device 202 gradually increases. VCC is slowly increased under the current of the second power device 202, causing the first power device 201 to be completely turned off, and LDO1 enters an open-loop state. At this time, the loop is completely taken over by LDO2.

[0067] After working together for a period of time TD1, VIN_LDO_EN jumps to a low level, the first switch tube 203 is turned off and LDO1 is completely turned off. When BIAS is powered down to below the second threshold voltage VTH2, the power switching is similar.

[0068] It can be seen that through the optimized working timing, the VCC power-off is significantly less than the existing technology, and VCC will not drop below the UVLO voltage (VCC_UV), ensuring the correct working state and good performance of the circuit.

[0069] Figure 5 FIG. 1 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to an embodiment of the present invention. Figure 3a The difference from the illustrated embodiment is that the present embodiment includes N+1 low voltage dropout linear regulators LDO1, LDO2, ..., LDON+1, and the nth low voltage dropout linear regulator LDOn (n=1, 2, ..., N+1) includes the nth operational amplifier AMPn and the nth power device.

[0070] In one embodiment of the present invention, the n-th low voltage dropout linear regulator LDOn (n=1, 2, ..., N+1) further includes an n-th switch tube.

[0071] The working principle of this embodiment is Figure 3aThe embodiment shown is similar. When the switching condition is detected and LDO1 needs to be switched to LDO X (X is between 2 and N+1), the reference voltage of LDO1 is immediately adjusted to VREFb, the reference voltage of LDO X is adjusted to VREFa, and the Xth switch tube is immediately turned on. The Xth switch tube is an anti-backflow device connected between the Xth power device of LDOX and VCC; so that the voltage drop of the Xth switch tube is reduced, and after LDO1 and LDOX both work for a period of TD1, the gate voltage of the first switch tube is lowered to completely shut down LDO1. The logic of switching from LDOX to LDO1 and LDO X to another LDOX is the same, and will not be repeated here.

[0072] Figure 6 FIG. 1 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to an embodiment of the present invention. Figure 3a The difference between the illustrated embodiment and the embodiment is that the first power device 201 and the second power device 202 in this embodiment are both NMOS transistors, wherein:

[0073] The drain of the first power device 201 is connected to the first input voltage VIN, the source is connected to the drain of the first switch tube 203, and the gate is connected to the output terminal of the first operational amplifier AMP1;

[0074] The drain of the second power device 202 is connected to the second input voltage BIAS, the source is connected to the drain of the second switch tube 204, and the gate is connected to the output terminal of the second operational amplifier AMP2.

[0075] Figure 7 FIG. 1 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to an embodiment of the present invention. Figure 3a The difference between the illustrated embodiment and the embodiment is that the first switch tube 203 and the second switch tube 204 in this embodiment are both NMOS tubes, wherein:

[0076] The source of the first switch tube 203 is connected to the drain of the first power device 201 , the drain is connected to the output node, and the gate is connected to the first operational amplifier enable signal VIN_LDO_EN;

[0077] The source of the second switch tube 204 is connected to the drain of the second power device 202 , the drain is connected to the output node, and the gate is connected to the second operational amplifier enable signal VBIAS_LDO_EN.

[0078] Figure 8 FIG. 1 is a circuit diagram of a multi-input low voltage dropout linear voltage regulator circuit according to an embodiment of the present invention. Figure 3a The difference between the illustrated embodiment and the embodiment is that the first power device 201 and the second power device 202, the first switch tube 203 and the second switch tube 204 in the embodiment are all NMOS tubes, wherein:

[0079] The drain of the first power device 201 is connected to the first input voltage VIN, the gate is connected to the output terminal of the first operational amplifier AMP1, the source is connected to the source of the first switch tube 203, the drain of the first switch tube 203 is connected to the output node, and the gate is connected to the first operational amplifier enable signal VIN_LDO_EN;

[0080] The drain of the second power device 202 is connected to the second input voltage BIAS, the gate is connected to the output end of the second operational amplifier AMP1, the source is connected to the source of the second switch tube 204, the drain of the second switch tube 204 is connected to the output node, and the gate is directly connected to the second operational amplifier enable signal VBIAS_LDO_EN.

[0081] Fig. 9 This is a flow chart of a control method for a multi-input low voltage difference linear voltage regulator circuit in another embodiment of the present invention, specifically: when it is detected that the second input voltage is greater than the first threshold voltage, the second operational amplifier enable signal is flipped and maintained at a valid level, and the first operational amplifier enable signal is maintained at a valid level; the first input terminal of the second operational amplifier inputs the first reference voltage, and the first input terminal of the first operational amplifier inputs the second reference voltage;

[0082] After the first delay period TD1, the first operational amplifier enable signal is flipped and maintained at an invalid level, the second operational amplifier enable signal is maintained at a valid level, the first input terminal of the first operational amplifier is maintained at the second reference voltage, and the first input terminal of the second operational amplifier is maintained at the second reference voltage;

[0083] When it is detected that the second input voltage is less than the second threshold, the first operational amplifier enable signal is flipped and maintained at a valid level, the second operational amplifier enable signal is maintained at a valid level, the first input terminal of the first operational amplifier inputs the first reference voltage, and the first input terminal of the second operational amplifier inputs the second reference signal;

[0084] After the second delay period TD2, the first op amp enable signal remains at a valid level, the second op amp enable signal is flipped and remains at an invalid level, the first input terminal of the first op amp remains at the first reference voltage, and the first input terminal of the second op amp remains at the second reference voltage.

[0085] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0086] In the present invention, by optimizing the structure and working sequence of the multi-input LDO circuit, the smooth switching of different LDOs can be achieved, which greatly reduces the power supply fluctuation amplitude of the internal analog circuit. The output voltage of the LDO will not erroneously trigger the UVLO during different switching processes, thereby ensuring the normal working state and good performance of the circuit.

[0087] In addition, MOS tubes are used as anti-backflow devices. They have unidirectional conductivity when turned off and reduce voltage drop when turned on, which has the advantages of reducing power consumption and increasing voltage margin.

[0088] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0089] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A multi-input low voltage drop linear voltage regulator circuit, characterized in that: The multi-input low voltage drop linear voltage regulator circuit comprises: The LDO unit includes a first low-voltage difference linear regulator and a second low-voltage difference linear regulator connected to the same output node, the first low-voltage difference linear regulator includes a first operational amplifier and a first power device, a first end of the first power device receives a first input voltage, a control end of the first power device is connected to an output end of the first operational amplifier, and a second end of the first power device is connected to the output node; the second low-voltage difference linear regulator includes a second operational amplifier and a second power device, a first end of the second power device receives a second input voltage, a control end of the second power device is connected to an output end of the second operational amplifier, and a second end of the second power device is connected to the output end; The reference voltage selection unit is used to select the reference voltage of the first operational amplifier as the second reference voltage and the reference voltage of the second operational amplifier as the first reference voltage when the first low-voltage difference linear regulator is switched to the second low-voltage difference linear regulator, wherein the first reference voltage is greater than the second reference voltage.

2. The multi-input low voltage drop linear voltage regulator circuit according to claim 1, characterized in that: The LDO unit further includes a feedback unit connected between the output node and a reference potential; the feedback unit is configured to provide a feedback signal to the second input terminal of the first operational amplifier and the second input terminal of the second operational amplifier through the feedback node.

3. The multi-input low voltage dropout linear voltage regulator circuit according to claim 2, characterized in that: The first input terminal of the first operational amplifier is connected to the reference voltage selection unit, the second input terminal is connected to the feedback node, the first terminal of the first power device is connected to the first input voltage, the second terminal is connected to the output node, and the control terminal is connected to the output terminal of the first operational amplifier; The first input terminal of the second operational amplifier is connected to the reference voltage selection unit, the second input terminal is connected to the feedback node, the first terminal of the second power device is connected to the second input voltage, the second terminal is connected to the output node, and the control terminal is connected to the output terminal of the second operational amplifier.

4. The multi-input low voltage dropout linear voltage regulator circuit according to claim 2, characterized in that: The feedback unit includes: a first resistor connected between the output node and the feedback node; and a second resistor connected between the feedback node and a reference potential.

5. The multi-input low voltage dropout linear voltage regulator circuit according to any one of claims 1 to 3, characterized in that: The reference voltage selection unit includes a first reference voltage selector and a second reference voltage selector; The output end of the first reference voltage selector is connected to the first input end of the first operational amplifier; the first end is connected to the first reference voltage, the second end is connected to the second reference voltage, and the control end is connected to the first reference voltage selection signal; The first reference voltage selector outputs the first reference voltage or the second reference voltage under the control of the first reference voltage selection signal; The output end of the second reference voltage selector is connected to the first input end of the second operational amplifier; the first end is connected to the first reference voltage, the second end is connected to the second reference voltage, and the control end is connected to the second reference voltage selection signal; the second reference voltage selector outputs the first reference voltage or the second reference voltage under the control of the second reference voltage selection signal.

6. The multi-input low voltage dropout linear voltage regulator circuit according to any one of claims 1 to 3, characterized in that: The first power device and the second power device are both PMOS tubes, the first end is the source, the second end is the drain, and the control end is the gate; or, The first power device and the second power device are both NMOS tubes, with a first end being a drain, a second end being a source, and a control end being a gate.

7. The multi-input low voltage drop linear voltage regulator circuit according to claim 1, characterized in that: The LDO unit also includes: A first switch tube, a first end of which is connected to the output node, a second end of which is connected to the second end of the first power device, and a control end of which is connected to the first operational amplifier enable signal; A second switch tube, a first end of which is connected to the output node, a second end of which is connected to the second end of the second power device, and a control end of which is connected to the second operational amplifier enable signal; The first operational amplifier is enabled when the first operational amplifier enable signal is at a valid level, and the second operational amplifier is enabled when the second operational amplifier enable signal is at a valid level.

8. The multi-input low voltage drop linear voltage regulator circuit according to claim 7, characterized in that: The first operational amplifier enable signal is connected to the control end of the first switch tube via an inverter; The second operational amplifier enable signal is connected to the control end of the second switch tube via an inverter.

9. The multi-input low voltage dropout linear voltage regulator circuit according to claim 1, characterized in that: The detection unit detects and compares the second input voltage with the first threshold voltage, the second input voltage with the second threshold voltage, and outputs a detection signal based on the comparison result; the first threshold voltage and the second threshold voltage are the same threshold voltage or different threshold voltages.

10. The multi-input low voltage dropout linear voltage regulator circuit according to claim 9, characterized in that: The reference voltage selection signal generating circuit generates a first reference voltage selection signal and / or a second reference voltage selection signal based on the detection signal; The first reference voltage selection signal is input to the reference voltage selection unit to select the first reference voltage or the second reference voltage for the first operational amplifier; The second reference voltage selection signal is input to the reference voltage selection unit to select the first reference voltage or the second reference voltage for the second operational amplifier.

11. The multi-input low voltage dropout linear voltage regulator circuit according to claim 9, characterized in that: The operational amplifier enable signal generating circuit generates a first operational amplifier enable signal and / or a second operational amplifier enable signal based on the detection signal; The first operational amplifier is enabled when the first operational amplifier enable signal is at a valid level, and the second operational amplifier is enabled when the second operational amplifier enable signal is at a valid level.

12. A control method for a multi-input low voltage dropout linear voltage regulator circuit, characterized in that: The multi-input low voltage difference linear voltage regulator circuit comprises: a first low voltage difference linear voltage regulator and a second low voltage difference linear voltage regulator connected to the same output node, the first low voltage difference linear voltage regulator comprises a first operational amplifier and a first power device, the first end of the first power device receives a first input voltage, the second end of the first power device is connected to the output node, the second low voltage difference linear voltage regulator comprises a second operational amplifier and a second power device, the first end of the second power device receives a second input voltage, the second end of the second power device is connected to the output node; the output end of the first operational amplifier is connected to the control end of the first power device; the output end of the second operational amplifier is connected to the control end of the second power device; The control method comprises: When it is detected that the second input voltage is greater than the first threshold voltage, the second operational amplifier enable signal is flipped and maintained at a valid level, and the first operational amplifier enable signal is maintained at a valid level; the first input terminal of the second operational amplifier inputs the first reference voltage, and the first input terminal of the first operational amplifier inputs the second reference voltage; After the first delay period TD1, the first operational amplifier enable signal is flipped and maintained at an invalid level, the second operational amplifier enable signal is maintained at a valid level, the first input terminal of the first operational amplifier is maintained at the second reference voltage, and the first input terminal of the second operational amplifier is maintained at the second reference voltage; When it is detected that the second input voltage is less than the second threshold, the first operational amplifier enable signal is flipped and maintained at a valid level, the second operational amplifier enable signal is maintained at a valid level, the first input terminal of the first operational amplifier inputs the first reference voltage, and the first input terminal of the second operational amplifier inputs the second reference signal; After the second delay period TD2, the first operational amplifier enable signal remains at a valid level, the second operational amplifier enable signal is flipped and remains at an invalid level, the first input terminal of the first operational amplifier remains at the first reference voltage, and the first input terminal of the second operational amplifier remains at the second reference voltage; The first reference voltage is greater than the second reference voltage; When the first operational amplifier enable signal is at a valid level, the first operational amplifier is enabled; when the second operational amplifier enable signal is at a valid level, the second operational amplifier is enabled.

13. The control method of the multi-input low voltage dropout linear voltage regulator circuit according to claim 12, characterized in that: The first threshold voltage and the second threshold voltage are the same threshold voltage or different threshold voltages; and / or, The first delay period is equal to or different from the second delay period.

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