High-efficiency peak suppression quick response LDO voltage stabilizing circuit and device based on FVF architecture

Abstract

The invention relates to the technical field of low dropout linear regulator optimization, and discloses an FVF architecture-based efficient peak suppression quick response LDO voltage stabilizing circuit, which comprises an LDO module comprising an operational amplifier OPA, a PMOS tube MP, a resistor R1, a resistor R2, a capacitor Cm, a capacitor C1, a reference input voltage VREF and a bias voltage Vb1, an FVF module comprising error amplifiers M1 and M2, a switch tube M3 and a resistor RP, the circuit is switched on, and when the circuit is switched off, the FVF architecture-based efficient peak suppression quick response LDO voltage stabilizing circuit is switched on, the FVF architecture-based efficient peak suppression quick response LDO voltage stabilizing circuit is switched off. The output VOUTLDO of the LDO module, the switching tubes M1 and M2 and the power tube MP form a fast feedback path, if the output Iload of the LDO module changes rapidly, the output of the LDO module without the output capacitor generates large signal response, if the output Iload of the LDO module increases or decreases suddenly, the voltage of an output node VOUTLDO responds to current change rapidly through a voltage stabilizing circuit, and the output of the output node VOUTLDO generates large signal response. The change of the load current Iload is quickly responded, so that the output voltage is adjusted and kept stable.

Description

Technical Field

[0001] The invention relates to the technical field of proportional flow detection and control, and discloses an LDO voltage stabilization circuit and a device with high efficiency peak suppression and fast response based on a FVF architecture. Background Art

[0002] With the increasing development of the electronic materials industry and changes in technology, there are more and more types of manufacturing processes, which are mainly used in the electronic materials equipment end. During the manufacturing process, continuous variable liquid supply is required. At present, the process end cannot achieve continuous variable liquid supply, and can only supply liquid or cut off liquid, but cannot achieve continuous variable liquid supply. The purpose of this solution is to meet the needs of the electronic materials equipment end and to be able to provide continuous variable liquid supply to the equipment end.

[0003] For example, the existing Chinese patent with the authorization publication number CN115268548A discloses that the present invention belongs to the field of analog integrated circuit technology, and specifically relates to a low-power Class AB output FVF structure LDO. The circuit of the present invention includes a stable reference voltage generation circuit, a fast response circuit, and a Class AB power stage. The present invention adopts the FVF structure to achieve high-speed transient response, and designs the power tube into a CLASSAB structure on the basis of the traditional FVF-LDO to achieve higher loop gain and lower quiescent current through a reasonable bias voltage. At the same time, the CLASSAB structure can well meet the two application scenarios of instantaneously providing large current and instantaneously absorbing large current in the ADC driving scenario.

[0004] The above patent may introduce additional complexity and potential stability issues, especially in the high frequency band. The bias control in the CLASSAB structure needs to be precisely adjusted to avoid crossover distortion, which increases the design difficulty. In addition, the above patent uses a specific reference voltage and a fixed bias scheme, which may limit the flexibility of output voltage adjustment.

[0005] For example, the existing Chinese patent with the authorization publication number CN118244831A discloses that the present invention discloses a low voltage difference linear regulator. In order to enable the LDO to work in an application scenario with a large voltage difference, the low voltage difference linear regulator of the present invention includes an FVF circuit, and the FVF circuit includes a switch tube M1, a switch tube M2, a switch tube M3, a switch tube M7 and a second bias current source; the input voltage of the low voltage difference linear regulator is connected to one end of the second bias current source, and the other end of the second bias current source is connected to the gate of the switch tube M1 and the drain of the switch tube M7, and the source of the switch tube M7 is grounded; the gate of the switch tube M7 is connected to the drain of the switch tube M2 and the drain of the switch tube M3, and the source of the switch tube M3 is grounded; the source of the switch tube M2 is connected to the source of the switch tube M1, and the input voltage of the low voltage difference linear regulator is connected to the drain of the switch tube M1, and the source of the switch tube M1 outputs the output voltage of the low voltage difference linear regulator. The present invention can improve the working power conversion range and supply power to power-sensitive circuits. The present invention is suitable for the field of integrated circuits.

[0006] However, the above patent uses an NMOS tube as a power tube (M1), and its gate end is controlled by a switch tube M7, which increases the number of nodes in the signal path, which may introduce additional delay or noise, and form a high resistance point when viewed from the drain end of the switch tube M2, which is not conducive to the stability of the overall loop. Summary of the invention

[0007] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0008] In order to solve the above technical problems, the main purpose of the present invention is to provide a high-efficiency peak suppression and fast response LDO voltage regulator circuit based on FVF architecture, comprising:

[0009] The LDO module includes an operational amplifier OPA, a PMOS tube MP, a resistor R1, a resistor R2, a capacitor Cm, a capacitor C1, a reference input voltage VREF and a bias voltage Vb1;

[0010] The FVF module includes error amplifiers M1 and M2, a switch tube M3 and a resistor RP.

[0011] As a preferred solution of the present invention, the FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage stabilizing circuit, wherein:

[0012] The positive input terminal of the operational amplifier OPA is connected to a reference voltage VREF;

[0013] The negative input terminal of the operational amplifier OPA is connected to the feedback point Vfb;

[0014] The output of the operational amplifier OPA is connected to the gate of the MOS tube M2;

[0015] The source of the PMOS tube MP is connected to the power supply AVDD;

[0016] The drain of the PMOS tube MP is connected to the resistor R1;

[0017] The gate of the PMOS transistor MP is connected to the drain of the MOS transistor M1.

[0018] As a preferred solution of the present invention, the FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage stabilizing circuit, wherein:

[0019] One end of the resistor R1 is connected to the output node VOUT_LDO of the LDO, and the other end is connected to the resistor R2;

[0020] The other end of the resistor R2 is connected to GND;

[0021] One end of the capacitor Cm is connected to the output node VOUT_LDO, and the other end is connected to the drain end of M2;

[0022] One end of the capacitor C1 is connected to the output node VOUT_LDO, and the other end is connected to the feedback node Vfb.

[0023] As a preferred solution of the present invention, the FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage stabilizing circuit, wherein:

[0024] The drain of the MOS tube M1 is connected to the gate of the PMOS tube MP;

[0025] The gate of the MOS transistor M1 is connected to a bias voltage Vb1.

[0026] As a preferred solution of the present invention, the FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage stabilizing circuit, wherein:

[0027] The gate of the MOS tube M2 is connected to the output end of the amplifier OPA;

[0028] The source of the MOS tube M2 is connected to the output node VOUT_LDO of the LDO;

[0029] The source of the MOS tube M2 is connected to AVDD.

[0030] As a preferred solution of the present invention, the FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage stabilizing circuit, wherein:

[0031] The gate of the MOS tube M3 is connected to the bias voltage Vb2;

[0032] The source of the MOS tube M3 is connected to GND;

[0033] The drain of the MOS tube M3 is connected to the source of M1 and the drain of M2;

[0034] One end of the resistor RP is connected to the power supply AVDD, and the other end of the resistor RP is connected to the gate of the PMOS transistor MP.

[0035] As a preferred solution of the present invention, the FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage stabilizing circuit, wherein:

[0036] The LDO module includes an operational amplifier OPA and a power tube MP. The feedback voltage is formed by the voltage division of resistors R1 and R2. The feedback voltage calculation expression is as follows:

[0037]

[0038] Among them, VREF is the input voltage of the positive input terminal of the operational amplifier OPA, R1 is the resistance value of the resistor R1, R2 is the resistance value of the resistor R2, and VOUT_LDO is the feedback voltage value;

[0039] The positive input terminal of the amplifier OPA is connected to VREF, and the negative input terminal is connected to the output VOUT_LDO, forming a unity gain amplifier, so that the voltage at the Vfb point is equal to VREF, and the output of the amplifier OPA is connected to the gate of the MOS tube M2 to generate a third branch current IBIAS3;

[0040] The gate of the MOS tube M3 is connected to the bias voltage Vb2 to generate a first branch current IBIAS1;

[0041] The resistor RP generates a second branch current IBIAS2.

[0042] As a preferred solution of the present invention, the FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage stabilizing circuit, wherein:

[0043] The calculation expressions satisfied by each branch current are as follows:

[0044] I BIAS1 =I BIAS2 +I BIAS3

[0045]

[0046] I BIAS2 =(AVDD-V P ) / R P

[0047] Among them, I D is the current generated by the PMOS tube MP, AVDD is the source power supply value of the PMOS tube MP, μ p is the electron mobility of the PMOS tube, W is the length of the PMOS tube, L is the width of the PMOS tube, V P is the voltage at the capacitor Cpair terminal, V THP is the threshold voltage of the PMOS tube, λ is the channel length modulation parameter, which affects the saturation current, V SD is the drain voltage of the PMOS tube MP, C ox is the gate oxide capacitance per unit area.

[0048] As a preferred solution of the present invention, the FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage stabilizing circuit, wherein:

[0049] The FVF module working method includes:

[0050] S1, the circuit is turned on, and the output VOUT_LDO of the LDO module, the switch tubes M1, M2 and the power tube MP form a fast feedback path;

[0051] S2. If the LDO module output Iload changes rapidly, the output of the LDO module without output capacitor responds with a large signal;

[0052] S3. If the output Iload of the LDO module suddenly increases, the voltage of the output node VOUT_LDO decreases, and the VSG of the PMOS tube MP is reduced through the fast response loop to restore the voltage of the output node VOUT_LDO.

[0053] S4. If the output Iload of the LDO module suddenly decreases, the voltage of the output node VOUT_LDO increases, and the VSG of the PMOS tube MP is reduced through the fast response loop to restore the voltage of the output node VOUT_LDO.

[0054] Beneficial effects of the present invention: The FVF architecture-based high-efficiency peak suppression fast-response LDO voltage regulator circuit of the present invention has better transient characteristics and relatively small undershoot, which is mainly due to its internal fast response loop, which can quickly respond to changes in the load current Iload, thereby adjusting the output voltage to keep it stable;

[0055] The FVF architecture-based high-efficiency spike suppression and fast-response LDO voltage stabilization circuit of the present invention can be implemented by using small-size transistors, and a resistor RP is used to generate a bias current IBIAS2, thereby reducing the chip area.

[0056] This application is trained based on historical data and uses a multi-layer traffic perception layer to calculate the weight of hidden information to predict traffic changes, so that the system can prepare in advance to deal with possible traffic fluctuations, ensure that the system's predictive ability always remains at a high level, and adjust in time to adapt to new traffic trends. The judgment unit, transient unit, steady-state unit and adjustment unit work together to respond quickly according to the actual state of the traffic and maintain efficient operation of the network. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0058] Figure 1 This is a schematic diagram of the structure of a high-efficiency spike suppression and fast-response LDO voltage stabilization circuit based on the FVF architecture provided by the present invention.

[0059] Figure 2 It is a structural schematic diagram of the fast transient response loop of the FVF architecture-based high-efficiency spike suppression and fast-response LDO voltage regulator circuit of the present invention. DETAILED DESCRIPTION

[0060] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0061] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0062] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0063] Embodiment 1:

[0064] like Figure 1 As shown, the FVF architecture-based high-efficiency peak suppression fast-response LDO voltage regulator circuit includes:

[0065] LDO module, fast response loop; the LDO module includes an operational amplifier OPA, a PMOS tube MP, a resistor R1, a resistor R2, a capacitor Cm, a capacitor C1, a reference input voltage VREF and a bias voltage Vb1; the positive input terminal of the operational amplifier OPA is connected to the reference voltage VREF, the negative input terminal of the operational amplifier OPA is connected to the feedback point Vfb, and the output of the operational amplifier OPA is connected to the gate of the MOS tube M2; the source of the PMOS tube MP is connected to the power supply AVDD, the drain of the PMOS tube MP is connected to the resistor R1, and the gate of the PMOS tube MP is connected to the drain of the MOS tube M1; one end of the resistor R1 is connected to the output node VOUT_LDO of the LDO, and the other end is connected to the resistor R2, and the other end of the resistor R2 is connected to GND; one end of the capacitor Cm is connected to the output node VOUT_LDO, and the other end is connected to the drain of M2; one end of the capacitor C1 is connected to the output node VOUT_LDO, and the other end is connected to the feedback node Vfb.

[0066] The FVF module includes error amplifiers M1 and M2, a switch tube M3 and a resistor RP; wherein the drain of the MOS tube M1 is connected to the gate of the PMOS tube MP, and the gate of the MOS tube M1 is connected to the bias voltage Vb1; the gate of the MOS tube M2 is connected to the output end of the amplifier OPA, the source of the MOS tube M2 is connected to the output node VOUT_LDO of the LDO, and the source of the MOS tube M2 is connected to AVDD; the gate of the MOS tube M3 is connected to the bias voltage Vb2, the source of the MOS tube M3 is connected to GND, and the drain of the MOS tube M3 is connected to the source of M1 and the drain of M2; one end of the resistor RP is connected to the power supply AVDD, and the other end is connected to the gate of the PMOS tube MP.

[0067] By using the PMOS tube MP as a power tube and connecting its source to the power supply AVDD, the driving mechanism is simplified and the efficiency is improved. Through reasonable capacitor configuration (such as Cm and C1), good loop stability is ensured, which is crucial to maintaining the stability of the output voltage. The resistor divider network allows the user to adjust the output voltage according to specific needs, enhancing the application range of the design. The design of the FVF module particularly emphasizes the response capability to rapid load changes and can quickly recover to a stable state, which is suitable for application scenarios with high requirements for dynamic performance.

[0068] Embodiment 2:

[0069] like Figure 2 As shown, a proportional flow control device comprises:

[0070] The LDO module includes an operational amplifier OPA and a power tube MP. The feedback voltage is formed by the voltage division of resistors R1 and R2. The calculation expression of the feedback voltage is as follows:

[0071]

[0072] Among them, VREF is the input voltage of the positive input terminal of the operational amplifier OPA, R1 is the resistance value of the resistor R1, R2 is the resistance value of the resistor R2, and VOUT_LDO is the feedback voltage value;

[0073] The positive input terminal of the amplifier OPA is connected to VREF, and the negative input terminal is connected to the output VOUT_LDO, forming a unity gain amplifier, so that the voltage at the Vfb point is equal to VREF, and the output of the amplifier OPA is connected to the gate of the MOS tube M2, generating a third branch current IBIAS3;

[0074] The gate of the MOS tube M3 is connected to the bias voltage Vb2 to generate a first branch current IBIAS1;

[0075] The resistor RP generates a second branch current IBIAS2;

[0076] The calculation expressions satisfied by each branch current are as follows:

[0077] I BIAS1 =I BIAS2 +I BIAS3

[0078]

[0079] I BIAS2 =(AVDD-V P ) / R P

[0080] Among them, I D is the current generated by the PMOS tube MP, AVDD is the source power supply value of the PMOS tube MP, μ p is the electron mobility, W is the length of the PMOS tube, L is the width of the PMOS tube, V P is the voltage at the capacitor Cpair terminal, V THP is the threshold voltage of the PMOS tube, λ is the channel length modulation parameter, which affects the saturation current, V SD is the drain voltage of the PMOS tube MP, C ox is the gate oxide capacitance per unit area;

[0081] The capacitors Cm and C1 are used to compensate for the stability of the circuit; RP not only provides the current IBIAS2, but is also connected in parallel with the gate resistance of the power tube Vp to reduce the resistance. Because the gate capacitance of the power tube Vp is large, the large capacitance and resistance make this point a high-frequency point, maintaining the stability of the entire loop. The introduction of RP avoids the use of current mirrors to provide current, reduces the area and saves power consumption.

[0082] Figure 2FIG. 1 is a schematic diagram of a fast response loop of the present invention. When the LDO output Iload changes rapidly, the output of the LDO without output capacitor responds with a large signal.

[0083] When the LDO output Iload suddenly increases, since Cpair is too large, the LDO cannot immediately increase the VSG of the PMOS tube MP to provide current, and the output node VOUT_LDO voltage decreases. Now the VSG of the PMOS tube MP can be reduced through the fast response loop to provide current, thereby restoring the output node VOUT_LDO voltage.

[0084] When the LDO output Iload suddenly decreases, the LDO cannot immediately reduce the VSG of the PMOS tube MP to provide current, and the voltage of the output node VOUT_LDO increases. Now the VSG of the PMOS tube MP can be reduced through the fast response loop to provide current, thereby restoring the voltage of the output node VOUT_LDO.

[0085] The FVF module working method includes:

[0086] S1, the circuit is turned on, the output VOUT_LDO of the LDO module, the switch tubes M1, M2 and the power tube MP form a fast feedback path;

[0087] S2. If the LDO module output Iload changes rapidly, the output of the LDO module without output capacitor will respond with a large signal;

[0088] S3. If the output Iload of the LDO module suddenly increases, the voltage of the output node VOUT_LDO decreases, and the VSG of the PMOS tube MP is reduced through the fast response loop to restore the voltage of the output node VOUT_LDO.

[0089] S4. If the output Iload of the LDO module suddenly decreases, the voltage of the output node VOUT_LDO increases, and the VSG of the PMOS tube MP is reduced through the fast response loop to restore the voltage of the output node VOUT_LDO.

[0090] It is important to note that the construction and arrangement of the present application shown in a plurality of different exemplary embodiments are only exemplary. Although only two embodiments are described in detail in this disclosure, it should be easily understood by the personnel referring to this disclosure that many modifications are possible, for example, the size, scale, structure, shape and ratio of various elements, and parameter values ​​(e.g., temperature, pressure, etc.), installation arrangement, use of materials, color, directional changes, etc., without departing substantially from the novel teachings and advantages of the subject matter described in the application. For example, the element shown as integrally formed can be composed of multiple parts or elements, the position of the element can be inverted or otherwise changed, and the nature or number or position of the discrete element can be changed or changed. Therefore, all such modifications are intended to be included in the scope of the present invention. The order or sequence of any process or method step can be changed or reordered according to the alternative embodiment. Any "device plus function" clause is intended to cover the structure of the execution function described in this article, and is not only structurally equivalent but also equivalent structure. Without departing from the scope of the present invention, other replacements, modifications, changes and omissions can be made in the design, operating conditions and arrangement of the exemplary embodiment. Therefore, the invention is not limited to a specific embodiment, but extends to numerous modifications still falling within the scope of the appended claims.

[0091] Additionally, in order to provide a concise description of exemplary embodiments, all features of an actual embodiment (ie, those features that are not relevant to the best mode presently contemplated for carrying out the invention or those that are not relevant to implementing the invention) may not be described.

[0092] It should be understood that in the development of any actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort may be complex and time-consuming, but for those of ordinary skill having the benefit of this disclosure, the development effort will be a routine task of design, fabrication, and production without undue experimentation.

[0093] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. Based on FVF architecture, efficient spike suppression and fast response LDO voltage regulator circuit, including: The LDO module includes an operational amplifier OPA, a PMOS tube MP, a resistor R1, a resistor R2, a capacitor Cm, a capacitor C1, a reference input voltage VREF and a bias voltage Vb1; The FVF module includes error amplifiers M1 and M2, a switch tube M3 and a resistor RP.

2. The FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage regulator circuit according to claim 1, characterized in that: The positive input terminal of the operational amplifier OPA is connected to a reference voltage VREF; The negative input terminal of the operational amplifier OPA is connected to the feedback point Vfb; The output of the operational amplifier OPA is connected to the gate of the MOS tube M2; The source of the PMOS tube MP is connected to the power supply AVDD; The drain of the PMOS tube MP is connected to the resistor R1; The gate of the PMOS transistor MP is connected to the drain of the MOS transistor M1.

3. The FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage regulator circuit according to claim 1, characterized in that: One end of the resistor R1 is connected to the output node VOUT_LDO of the LDO, and the other end is connected to the resistor R2; The other end of the resistor R2 is connected to GND; One end of the capacitor Cm is connected to the output node VOUT_LDO, and the other end is connected to the drain end of M2; One end of the capacitor C1 is connected to the output node VOUT_LDO, and the other end is connected to the feedback node Vfb.

4. The FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage regulator circuit according to claim 3 is characterized in that: The drain of the MOS tube M1 is connected to the gate of the PMOS tube MP; The gate of the MOS transistor M1 is connected to a bias voltage Vb1.

5. The FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage regulator circuit according to claim 4 is characterized in that: The gate of the MOS tube M2 is connected to the output end of the amplifier OPA; The source of the MOS tube M2 is connected to the output node VOUT_LDO of the LDO; The source of the MOS tube M2 is connected to AVDD.

6. The FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage regulator circuit according to claim 5, characterized in that: The gate of the MOS tube M3 is connected to the bias voltage Vb2; The source of the MOS tube M3 is connected to GND; The drain of the MOS tube M3 is connected to the source of M1 and the drain of M2; One end of the resistor RP is connected to the power supply AVDD, and the other end of the resistor RP is connected to the gate of the PMOS transistor MP.

7. The FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage regulator circuit according to claim 6, characterized in that: The LDO module includes an operational amplifier OPA and a power tube MP. The feedback voltage is formed by the voltage division of resistors R1 and R2. The feedback voltage calculation expression is as follows: Among them, VREF is the input voltage of the positive input terminal of the operational amplifier OPA, R1 is the resistance value of the resistor R1, R2 is the resistance value of the resistor R2, and VOUT_LDO is the feedback voltage value; The positive input terminal of the amplifier OPA is connected to VREF, and the negative input terminal is connected to the output VOUT_LDO, forming a unity gain amplifier, so that the voltage at the Vfb point is equal to VREF, and the output of the amplifier OPA is connected to the gate of the MOS tube M2 to generate a third branch current IBIAS3; The gate of the MOS tube M3 is connected to the bias voltage Vb2 to generate a first branch current IBIAS1; The resistor RP generates a second branch current IBIAS2.

8. The FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage regulator circuit according to claim 7, characterized in that: The calculation expressions satisfied by each branch current are as follows: I BIAS1 =I BIAS2 +I BIAS3 I BIAS2 =(AVDD-V P ) / R P Among them, I D is the current generated by the PMOS tube MP, AVDD is the source power supply value of the PMOS tube MP, μ P is the electron mobility of the PMOS tube, W is the length of the PMOS tube, L is the width of the PMOS tube, V P is the voltage at the capacitor Cpair terminal, V THP is the threshold voltage of the PMOS tube, λ is the channel length modulation parameter, which affects the saturation current, V SD is the drain voltage of the PMOS tube MP, C ox is the gate oxide capacitance per unit area.

9. The FVF architecture-based high-efficiency peak suppression and fast-response LDO voltage regulator circuit according to claim 8, characterized in that: The FVF module working method includes: S1, the circuit is turned on, and the output VOUT_LDO of the LDO module, the switch tubes M1, M2 and the power tube MP form a fast feedback path; S2. If the LDO module output Iload changes rapidly, the output of the LDO module without output capacitor responds with a large signal; S3. If the output Iload of the LDO module suddenly increases, the voltage of the output node VOUT_LDO decreases, and the VSG of the PMOS tube MP is reduced through the fast response loop to restore the voltage of the output node VOUT_LDO. S4. If the output Iload of the LDO module suddenly decreases, the voltage of the output node VOUT_LDO increases, and the VSG of the PMOS tube MP is reduced through the fast response loop to restore the voltage of the output node VOUT_LDO.

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