Storage arrays, content-addressable memory, electronic devices

Abstract

The application provides a storage array, a content addressing memory and an electronic device, relates to the technical field of memories, and aims to reduce the area of the storage array and improve the PPA of the device. The storage array comprises a first active layer, a second active layer, a first data line and a second data line, and the first active layer and the second active layer are arranged along a first direction. The first data line overlaps the second active layer, and the second data line overlaps the first active layer. The storage subunit further comprises a first connecting line and a second connecting line, the first connecting line is connected with the first active layer through a first contact column and connected with the first data line through a second contact column. The second connecting line is connected with the second data line through a third contact column and connected with the second active layer through a fourth contact column. The connection lines of the second contact column and the third contact column are perpendicular to the first direction. The storage array can be applied to a content addressing memory and can realize reading, writing and searching of data.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a storage array, a content addressable memory and an electronic device. BACKGROUND

[0002] A ternary content addressable memory (TCAM) is a memory with functions of reading, writing and searching, and its storage content includes three states of "0", "1" and "X", and it can be addressed according to its storage content.

[0003] In the related art, the architecture of the ternary content addressable memory is based on a static random addressable memory (SRAM), and the ternary content addressable memory includes a plurality of storage units, each of which is composed of 16 transistors, and there are problems of excessive device area and low storage density.

[0004] In addition, with the increase of the amount of stored data, the ternary content addressable memory has problems of increased power consumption, reduced working frequency and increased delay. Therefore, the field is committed to designing a ternary content addressable memory with low power consumption, small delay and small area, so as to achieve better PPA (Power Performance Area). SUMMARY

[0005] Embodiments of the present application provide a storage array, a content addressable memory and an electronic device, which are aimed at reducing the area of the storage array and improving the PPA of the device.

[0006] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a storage array is provided, which can be applied to a ternary content addressable memory and can realize reading, writing and searching of data.

[0008] The storage array includes a plurality of storage units arranged in an array, each of which includes an addressing subunit and a storage subunit arranged along a first direction, and the storage subunit includes a P-well region and an N-well region, and the N-well region is located on opposite sides of the P-well region along the first direction.

[0009] Each storage subunit includes a first active layer, a second active layer, a first data line and a second data line, the first active layer and the second active layer are arranged along the first direction and located in the P-well region, the first data line overlaps the second active layer, and the second data line overlaps the first active layer.

[0010] It can be understood that the first data line overlaps the second active layer to form a sixth transistor, and the sixth transistor is a P-type transistor. The part of the first data line overlapping the second active layer is a gate of the sixth transistor, the part of the second active layer overlapping the first data line is a channel of the sixth transistor, and the parts of the second active layer located on both sides of the channel are a source and a drain of the sixth transistor.

[0011] Similarly, the second data line overlaps the first active layer to form an eighth transistor, and the eighth transistor is a P-type transistor. The part of the second data line overlapping the first active layer is a gate of the eighth transistor, the part of the first active layer overlapping the second data line is a channel of the eighth transistor, and the parts of the first active layer located on both sides of the channel are a source and a drain of the eighth transistor.

[0012] Each storage subunit further includes a first contact pillar, a second contact pillar, a third contact pillar, a fourth contact pillar, a first connection line and a second connection line. The first connection line is connected with the first active layer through the first contact pillar and connected with the first data line through the second contact pillar, so as to realize the connection of the second electrode of the eighth transistor and the first data line. The second connection line is connected with the second data line through the third contact pillar and connected with the second active layer through the fourth contact pillar, so as to realize the connection of the second electrode of the sixth transistor and the second data line. Wherein, along the first direction, the second contact pillar and the third contact pillar are both located between the first contact pillar and the fourth contact pillar, and the connection line of the second contact pillar and the third contact pillar is perpendicular to the first direction.

[0013] The connection line of the second contact pillar and the third contact pillar is perpendicular to the first direction, the connection line of the second contact pillar and the third contact pillar is parallel to the second direction (for example, the second direction is perpendicular to the first direction), the second contact pillar and the third contact pillar are on the same horizontal line along the second direction, which is beneficial to reduce the size of the storage unit along the first direction, thereby reducing the area of the storage array and improving the storage density, so as to improve the PPA of the device.

[0014] In some embodiments, the storage subunit further includes a first voltage line, a fifth contact pillar and a sixth contact pillar. The first voltage line overlaps the first active layer and overlaps the second active layer. The first voltage line is connected with the first active layer through the fifth contact pillar, so as to realize the connection of the first electrode of the eighth transistor and the first voltage line. The first voltage line is further connected with the second active layer through the sixth contact pillar, so as to realize the connection of the first electrode of the sixth transistor and the first voltage line.

[0015] In the above embodiment, the size of the storage unit along the first direction is reduced, so that the first voltage line can overlap the first active layer, and the connection line is not arranged, the first voltage line can be directly connected with the first active layer through the fifth contact pillar, the layout design of the storage unit is simplified, the arrangement compactness of the structure is improved, and the storage density of the device can be improved.

[0016] In some embodiments, the connection between the fifth contact pillar and the first contact pillar is perpendicular to the first direction.

[0017] In the above embodiment, the connection between the fifth contact pillar and the first contact pillar is perpendicular to the first direction, and the connection between the fifth contact pillar and the first contact pillar is parallel to the second direction, so that the fifth contact pillar and the first contact pillar are in the same horizontal line along the second direction, which is beneficial to reduce the size of the storage unit along the first direction, thereby reducing the area of the storage array and improving the storage density, and improving the PPA of the device.

[0018] In some embodiments, the first connection line and the second connection line are both bent twice, the first connection line includes a first bending segment, a second bending segment and a third bending segment connected in sequence, the connection between the first bending segment and the second bending segment is connected with the first contact pillar, and the third bending segment is connected with the second contact pillar. The second connection line includes a fourth bending segment, a fifth bending segment and a sixth bending segment connected in sequence, the fourth bending segment is connected with the third contact pillar, and the connection between the fifth bending segment and the sixth bending segment is connected with the fourth contact pillar. The bending direction of the connection between the second bending segment and the third bending segment is away from the bending direction of the connection between the fourth bending segment and the fifth bending segment. For example, the bending direction of the connection between the second bending segment and the third bending segment is on the same straight line as the bending direction of the connection between the fourth bending segment and the fifth bending segment, and they are arranged away from each other.

[0019] In the above embodiment, since the second contact pillar and the third contact pillar are in the same horizontal line, the arrangement of the first contact pillar, the second contact pillar, the third contact pillar and the fourth contact pillar is more compact. Moreover, the first connection line and the second connection line are both located in the first conductive layer, the first connection line is connected with the first contact pillar and the second contact pillar, and the second connection line is connected with the third contact pillar and the fourth contact pillar.

[0020] By arranging the bending direction of the first connection line to be away from the bending direction of the second connection line, the first connection line can be connected with the first contact pillar and the second contact pillar, and the second connection line can be connected with the third contact pillar and the fourth contact pillar, and the distance between the first connection line and the second connection line can be increased to avoid the contact between the first connection line and the second connection line in the first conductive layer, thereby avoiding the short circuit between them.

[0021] In some embodiments, the N-well region includes a first sub-N-well region and a second sub-N-well region, the first sub-N-well region is located at a side of the P-well region close to the addressed sub-unit, and the second sub-N-well region is located at a side of the P-well region away from the addressed sub-unit. The storage sub-unit further includes a third active layer, a fourth active layer, a seventh contact pillar, and an eighth contact pillar, the third active layer is located at the first sub-N-well region, and the fourth active layer is located at the second sub-N-well region. The first bending segment is connected to the third active layer through the seventh contact pillar, and the sixth bending segment is connected to the fourth active layer through the eighth contact pillar.

[0022] In the above embodiments, the first bending segment of the first connection line is connected to the third active layer through the seventh contact pillar, thereby realizing the connection of the first data line to the second electrode of the ninth transistor and the second electrode of the tenth transistor. The sixth bending segment of the second connection line is connected to the fourth active layer through the eighth contact pillar, thereby realizing the connection of the second data line to the second electrode of the fifth transistor and the second electrode of the seventh transistor.

[0023] Further, by arranging the first sub-N-well region and the second sub-N-well region at opposite sides of the P-well region, according to the well proximity effect, the P-type transistors in the P-well region have balanced effects on the N-type transistors in the first sub-N-well region and the second sub-N-well region, so as to ensure that the on and off capabilities of the N-type transistors in the first sub-N-well region and the second sub-N-well region are similar, thereby facilitating the improvement of the reliability of the performance of the device.

[0024] In some embodiments, the storage sub-unit further includes a first word line, a first cut-off structure, a second word line, and a second cut-off structure, the first word line and the first data line are arranged along a first direction and are separated by the first cut-off structure to realize insulation therebetween. The first word line overlaps the third active layer, and the first data line also overlaps the fourth active layer. The second data line and the second word line are arranged along the first direction and are separated by the second cut-off structure to realize insulation therebetween. The second data line also overlaps the third active layer, and the second word line overlaps the fourth active layer.

[0025] In the above embodiments, the first word line overlaps the third active layer to form a tenth transistor, and the tenth transistor is an N-type transistor. The part of the first word line overlapping the third active layer is the gate electrode of the tenth transistor, the part of the third active layer overlapping the first word line is the channel of the tenth transistor, and the parts of the third active layer located at both sides of the channel are the source electrode and the drain electrode of the tenth transistor.

[0026] The first data line also overlaps the fourth active layer to form a seventh transistor, and the seventh transistor is an N-type transistor. The part of the first data line overlapping the fourth active layer is the gate electrode of the seventh transistor, the part of the fourth active layer overlapping the first data line is the channel of the seventh transistor, and the parts of the fourth active layer located at both sides of the channel are the source electrode and the drain electrode of the seventh transistor.

[0027] The second data line also overlaps with the third active layer to form a ninth transistor, and the ninth transistor is an N-type transistor. The part of the second data line overlapping with the third active layer is a gate of the ninth transistor, the part of the third active layer overlapping with the second data line is a channel of the ninth transistor, and the parts of the third active layer on both sides of the channel are a source and a drain of the ninth transistor.

[0028] The second word line overlaps with the fourth active layer to form a fifth transistor, and the fifth transistor is an N-type transistor. The part of the second word line overlapping with the fourth active layer is a gate of the fifth transistor, the part of the fourth active layer overlapping with the second word line is a channel of the fifth transistor, and the parts of the fourth active layer on both sides of the channel are a source and a drain of the fifth transistor.

[0029] In some embodiments, the storage subunit further includes a ninth contact column, a first bit line, a tenth contact column, and a second bit line, the first bit line passes through the first sub-N-well region and is connected to the third active layer through the ninth contact column to realize the connection between the first electrode of the tenth transistor and the first bit line. The second bit line passes through the second sub-N-well region and is connected to the fourth active layer through the tenth contact column to realize the connection between the first electrode of the fifth transistor and the second bit line.

[0030] In some embodiments, the storage subunit further includes an eleventh contact column, a twelfth contact column, and two second voltage lines, one of the two second voltage lines passes through the first sub-N-well region and is connected to the third active layer through the eleventh contact column to realize the connection between the first electrode of the ninth transistor and the second voltage line. The other of the two second voltage lines passes through the second sub-N-well region and is connected to the fourth active layer through the twelfth contact column to realize the connection between the first electrode of the seventh transistor and the second voltage line.

[0031] In some embodiments, the storage unit includes one addressing subunit and two storage subunits, and the two storage subunits are arranged along a second direction intersecting the first direction.

[0032] In some embodiments, the addressing subunit includes a fifth active layer, a first lookup gate line, and a second lookup gate line, and the first lookup gate line and the second lookup gate line overlap with the fifth active layer, respectively. In the two storage subunits, the two second data lines also overlap with the fifth active layer.

[0033] It can be understood that the first lookup gate line overlaps with the fifth active layer to form a first transistor, and the first transistor is an N-type transistor. The part of the first lookup gate line overlapping with the fifth active layer is a gate of the first transistor, the part of the fifth active layer overlapping with the first lookup gate line is a channel of the first transistor, and the parts of the fifth active layer on both sides of the channel are a source and a drain of the first transistor.

[0034] The second search gate line overlaps the fifth active layer to form a third transistor, and the third transistor is an N-type transistor. The part of the second search gate line overlapping the fifth active layer is a gate of the third transistor, the part of the fifth active layer overlapping the second search gate line is a channel of the third transistor, and the parts of the fifth active layer located on both sides of the channel are a source and a drain of the third transistor.

[0035] In the two storage subunits, the second data line in the first storage subunit overlaps the fifth active layer to form a second transistor, and the second transistor is an N-type transistor. The part of the second data line overlapping the fifth active layer is a gate of the second transistor, the part of the fifth active layer overlapping the second data line is a channel of the second transistor, and the parts of the fifth active layer located on both sides of the channel are a source and a drain of the second transistor.

[0036] The second data line in the second storage subunit overlaps the fifth active layer to form a fourth transistor, and the fourth transistor is an N-type transistor. The part of the second data line overlapping the fifth active layer is a gate of the fourth transistor, the part of the fifth active layer overlapping the second data line is a channel of the fourth transistor, and the parts of the fifth active layer located on both sides of the channel are a source and a drain of the fourth transistor.

[0037] The addressing subunit further includes a first search line, a third voltage line and a second search line arranged in sequence along the first direction, and a thirteenth contact column, a fourteenth contact column and a third connection line. The third connection line is connected with the first search gate line through the thirteenth contact column and connected with the first search line through the fourteenth contact column, so as to realize transmission of a search signal from the first search line to the first search gate line.

[0038] The addressing subunit further includes a fifteenth contact column, a sixteenth contact column and a fourth connection line. The fourth connection line is connected with the second search gate line through the fifteenth contact column and connected with the second search line through the sixteenth contact column, so as to realize transmission of a search signal from the second search line to the second search gate line. The thirteenth contact column and the fourteenth contact column are located on a side of the third voltage line away from the second search line, the fifteenth contact column is located on a side of the third voltage line away from the second search line, and the sixteenth contact column is located on a side of the third voltage line away from the first search line.

[0039] In the above embodiment, the fifteenth contact column is located on the side of the third voltage line away from the second search line, and the sixteenth contact column is located on the side of the third voltage line away from the first search line, i.e., the fifteenth contact column and the sixteenth contact column are located on opposite sides of the third voltage line along the first direction, and the fifteenth contact column can be located in the same horizontal track as the thirteenth contact column and the fourteenth contact column. In this way, the space of one horizontal track can be saved, the size of the addressing sub-unit along the first direction is reduced, and thus the size of the storage unit along the first direction is reduced, thereby facilitating the reduction of the area of the storage array and the improvement of the storage density, and the PPA of the device is improved.

[0040] In some embodiments, the fourth connection line crosses the third voltage line, and the fifteenth contact column does not overlap the fifth active layer.

[0041] In the above embodiment, since the fifteenth contact column and the sixteenth contact column are located on opposite sides of the third voltage line along the first direction, the fourth connection line needs to cross the third voltage line and be connected with the fifteenth contact column and the sixteenth contact column, respectively. Moreover, the fifteenth contact column does not overlap the fifth active layer, which can avoid over-etching of the contact hole in which the fifteenth contact column is located and avoid short circuiting of the fifteenth contact column connecting the second search gate line and the fifth active layer.

[0042] In some embodiments, the third connection line and the fourth connection line are both bent once, the third connection line includes a seventh bent segment and an eighth bent segment connected in sequence, the seventh bent segment is connected with the thirteenth contact column, and the connection position of the seventh bent segment and the eighth bent segment is connected with the fourteenth contact column. The fourth connection line includes a ninth bent segment and a tenth bent segment connected in sequence, the ninth bent segment is connected with the fifteenth contact column, and the tenth bent segment crosses the third voltage line and is connected with the sixteenth contact column. The bending direction of the connection position of the seventh bent segment and the eighth bent segment and the bending direction of the connection position of the ninth bent segment and the tenth bent segment are close to each other. For example, the bending direction of the connection position of the seventh bent segment and the eighth bent segment and the bending direction of the connection position of the ninth bent segment and the tenth bent segment are located on the same straight line, and are arranged opposite to each other.

[0043] In some embodiments, the eighth bent segment of the third connection line crosses the third voltage line, and the thirteenth contact column does not overlap the fifth active layer, which can avoid over-etching of the contact hole in which the thirteenth contact column is located and avoid short circuiting of the thirteenth contact column connecting the first search gate line and the fifth active layer.

[0044] In some embodiments, the storage unit further includes a match line extending along the first direction, the match line being connected with the fifth active layer to realize connection of the second electrode of the second transistor and the match line and connection of the second electrode of the fourth transistor and the match line, so as to transmit the match signal output by the addressing subunit to the match line. The third connection line and the fourth connection line are symmetrically arranged with the match line as a symmetric axis, so as to improve compactness of arrangement of the third connection line and the fourth connection line.

[0045] In some embodiments, the addressing subunit further includes a seventeenth contact pillar, an eighteenth contact pillar and a fifth connection line, the fifth connection line crossing the first search line. The match line is connected with one end of the fifth connection line through the seventeenth contact pillar, and the other end of the fifth connection line is connected with the fifth active layer through the eighteenth contact pillar, so as to realize connection of the match line and the fifth active layer.

[0046] In some embodiments, the third connection lines of the addressing subunits of the two adjacent storage units are disconnected with each other, and the fourth connection lines of the addressing subunits of the two adjacent storage units are disconnected with each other.

[0047] In the above embodiments, the third connection lines of the addressing subunits of the two adjacent storage units are not shared, and the fourth connection lines of the addressing subunits of the two adjacent storage units are not shared, so that in the second direction, the two adjacent storage units are not limited to be arranged in mirror symmetry, and the arrangement diversity of the plurality of storage units in the storage array can be improved, thereby facilitating optimization of arrangement design of the storage array.

[0048] In some embodiments, the addressing subunit further includes a third cut-off structure and a fourth cut-off structure, the first search gate line and the first word line of one storage subunit are arranged along the first direction and are insulated from each other by the third cut-off structure. The second search gate line and the first word line of another storage subunit are arranged along the first direction and are insulated from each other by the fourth cut-off structure.

[0049] In some embodiments, the third cut-off structure is spaced apart from the fifth active layer and no contact pillar is arranged therebetween. The fourth cut-off structure is spaced apart from the fifth active layer and no contact pillar is arranged therebetween, so as to save space of one horizontal line, reduce the size of the addressing subunit along the first direction, and thereby reduce the size of the storage unit along the first direction, thereby facilitating reduction of the area of the storage array, improvement of the storage density and improvement of the PPA of the device.

[0050] In some embodiments, the two storage subunits are symmetrically arranged with the match line as a symmetric axis.

[0051] In some embodiments, the first storage subunit and the second storage subunit share the first voltage line and the two second voltage lines, and the first storage subunit and the second storage subunit each include the first word line and the second word line.

[0052] The storage unit further includes a fourth voltage line, a third word line, a match line, a fourth word line and a fifth voltage line arranged in sequence along the second direction, and each line extends along the first direction. The fourth voltage line is connected with the two second voltage lines and the third voltage line, the third word line is connected with the first word line and the second word line of the first storage subunit, the fourth word line is connected with the first word line and the second word line of the second storage subunit, and the fifth voltage line is connected with the first voltage line.

[0053] In a second aspect, a content addressable memory is provided, which includes the storage array of any of the above embodiments and a controller electrically connected with the storage array to control the storage array to read, write and search data.

[0054] In a third aspect, an electronic device is provided, which can be a network device such as a base station, a switch or a router. The electronic device includes a circuit board and the content addressable memory of the above embodiments. The content addressable memory is arranged on the circuit board and electrically connected with the circuit.

[0055] It can be understood that the content addressable memory and the electronic device provided by the above embodiments of the present application can achieve the beneficial effects as described above for the storage array, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings needed to be used in some embodiments of the present application. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the products involved in the embodiments of the present application.

[0057] Figure 1 is an architecture diagram of an electronic device according to some embodiments;

[0058] Figure 2 is an architecture diagram of a ternary content addressable memory according to some embodiments;

[0059] Figure 3 is a circuit diagram of a storage unit according to some embodiments;

[0060] Figure 4 is a top view of a storage unit according to some embodiments;

[0061] Figure 5 is a top view of the active layer of the memory cell in Figure 4

[0062] Figure 6 is a top view of the active layer and the gate conductive layer of the memory cell in Figure 4

[0063] Figure 7 is a top view of the active layer, the gate conductive layer and the first conductive layer of the memory cell in Figure 4

[0064] Figure 8 is a top view of the active layer, the gate conductive layer, the first conductive layer and the second conductive layer of the memory cell in Figure 4

[0065] Figure 9 is a top view of the active layer, the gate conductive layer and the first conductive layer of the memory cell in Figure 4

[0066] Figure 10 is a top view of the active layer, the gate conductive layer, the first conductive layer and the second conductive layer of the memory cell in Figure 4

[0067] Figure 11 is a top view of the active layer, the gate conductive layer, the first conductive layer, the second conductive layer and the third conductive layer of the memory cell in Figure 4 DETAILED DESCRIPTION

[0068] The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present application.

[0069] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to has a particular orientation, is constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0070] ​​​​​​​Unless otherwise required by context, the term "including" as used herein is to be interpreted as open-ended, i.e. the term "including" is to be interpreted as "including, but not limited to". In describing the embodiments, the term "one embodiment," "some embodiments," "an exemplary embodiment," "an example embodiment," "exemplary embodiments," or "some examples" are used. The phrase "for example" is used to introduce an example. The phrase "for instance" is used to introduce an example. The phrase "such as" is used to introduce a non-limiting list of one or more examples. Other permutations of these phrases are also used to introduce a non-limiting examples. The specific features, structures, materials, or characteristics described in the specification, examples, and claims are optionally included in at least one embodiment. The description herein, in addition to specifying the various embodiments, also describes the best modes known to the applicant of practicing them.

[0071] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description and are not to be construed as indicating or implying relative importance or an indicated number of technical features. Thus, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0072] In describing some embodiments, the use of "coupled" or variations thereof can be used. For example, the term "coupled" can be used to indicate that two or more components are in direct physical or electrical contact with one another. The present embodiments are not necessarily limited in this regard.

[0073] In addition, the use of "based on" means open and inclusive, as the process, step, calculation, or other action based on one or more recited condition or value can be based on additional condition or values beyond those recited.

[0074] In the content of the present application, the meanings of "on", "over", and "above" should be interpreted in the broadest possible way, such that "on" means not only "directly on" but also "on" with intervening features or layers therebetween, and "over" or "above" means not only "over" or "above" but also "over" or "above" with no intervening features or layers therebetween (i.e., directly on).

[0075] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have jagged edges when etched due to the fact that the etching process often does not proceed vertically down to the substrate. Thus, the regions illustrated in the figures are schematic and not drawn to scale. As used herein, the term "schematic" means that the drawings are not drawn to scale and are intended to be illustrative only.

[0076] Some embodiments of the present application provide an electronic device, which can be different types of user devices or terminal devices such as a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging household small appliance (e.g., a soybean milk machine, a sweeping robot), a drone, a radar, an aerospace device, and a vehicle-mounted device, etc.; or a network device such as a base station, a switch, and a router. The specific form of the electronic device is not specially limited in the embodiments of the present application.

[0077] Figure 1 Architecture diagram of an electronic device according to some embodiments.

[0078] Referring to Figure 1 , the electronic device 1 includes components such as a storage device 11, a processor 12, a communication interface 13, and a bus 14, and communicates between the storage device 11, the processor 12, and the communication interface 13 through the bus 14. Those skilled in the art can understand that Figure 1 The architecture of the electronic device 1 shown in Figure 1 may include more or fewer components than those shown in Figure 1 may combine some of the components shown in Figure 1 may be arranged differently from the components shown in

[0079] The storage device 11 is configured to store software programs and modules. The storage device 11 mainly includes a program storage area and a data storage area, wherein the program storage area can store and backup an operating system, application programs (such as a sound playing function, an image playing function, etc.) required by at least one function, etc.; and the data storage area can store data (such as audio data, image data, a phonebook, etc.) created according to the use of the electronic device 1, etc.

[0080] The processor 12 is the control center of the electronic device 1, connects various parts of the electronic device 1 by various interfaces and lines, performs various functions of the electronic device 1 and processes data by running or executing software programs and / or modules stored in the storage device 11 and calling data stored in the storage device 11, thereby monitoring the whole electronic device 1. Optionally, the processor 12 can include one or more processing units. For example, the processor 12 can include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. Different processing units can be independent devices or integrated in one or more processors. For example, the processor 12 can integrate an application processor and a modem processor, wherein the application processor mainly processes operating systems, user interfaces, and applications, and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 12. The above-mentioned application processor can be a central processing unit (CPU), for example.

[0081] The communication interface 13 can be used for communication between the electronic device 1 and other devices. For example, the communication interface 13 can be used to receive messages sent by other devices or send messages to other devices. The communication interface 13 can include an ingress media access control (MAC) chip and an egress MAC chip, for example. The electronic device 1 can receive messages through the ingress MAC chip and send messages through the egress MAC chip.

[0082] The bus 14 can be an industry standard architecture (ISA) bus, a peripheral component (PCI) bus, an extended industry standard architecture (EISA) bus, etc. The bus 14 can include an address bus, a data bus, a control bus, etc. Figure 1 The bus 14 is represented by a thick arrow line, which does not mean that there is only one bus or one type of bus in the electronic device 1.

[0083] Continuing to refer to Figure 1The storage device 11 includes a first memory 111 and a second memory 112. The first memory 111 is configured to store executable program code including computer operation instructions. The first memory 111 can include a random access memory (RAM), a read-only memory (ROM), or the like.

[0084] The second memory 112 can include a content addressable memory (CAM). The content addressable memory can be disposed on a circuit board of the electronic device 1 and electrically connected to the circuit board. A typical content addressable memory is a ternary content addressable memory. The ternary content addressable memory is a memory having functions of reading, writing, and searching, and has three states of "0", "1", and "X" for storage. The ternary content addressable memory can be addressed according to the stored content. The "X" state is a "don't care" state, also referred to as a "fuzzy state". The ternary content addressable memory can perform both exact match searching and fuzzy match searching.

[0085] The ternary content addressable memory can perform functions of packet classification and route searching together with the processor 12, and serve as a search engine unit. The processor 12 is configured to extract information from a message and arrange the information into a data format consistent with a table to be searched in the ternary content addressable memory. The data is referred to as a key. In a searching stage, the key is sent to the ternary content addressable memory to be compared with all entries in the table to be searched, so as to find a storage address matching the data.

[0086] The following embodiments take the ternary content addressable memory as an example. Figure 2 FIG. 1 is a schematic diagram of a ternary content addressable memory according to some embodiments.

[0087] Referring to FIG. 1, Figure 2 The ternary content addressable memory includes a storage array 210, a decoder 220, a driver 230, a controller 240, a buffer 250, and an input / output interface 260, and can be integrated in one chip or in multiple chips. The storage array 210 includes a plurality of storage units 200 arranged in an array.

[0088] Figure 3 FIG. 2 is a circuit diagram of a storage unit according to some embodiments.

[0089] Referring to FIG. 2, Figure 3The architecture of the storage unit 200 is implemented based on the architecture of a static random-access memory (SRAM). The storage unit 200 comprises an addressing subunit S and two storage subunits D, wherein the storage subunit D is a static random-access memory.

[0090] Continuing to refer to Figure 3 The two storage subunits D comprise a first storage subunit D1 and a second storage subunit D2. The addressing subunit S comprises first to fourth transistors M1-M4. The control electrode of the first transistor M1 is connected with a first search line SL1, the first electrode of the first transistor M1 is grounded, and the second electrode of the first transistor M1 is connected with the first electrode of the second transistor M2. The control electrode of the second transistor M2 is connected with the first storage subunit D1, and the second electrode of the second transistor M2 is connected with a matching line ML.

[0091] The control electrode of the third transistor M3 is connected with a second search line SL2, the first electrode of the third transistor M3 is grounded, and the second electrode of the third transistor M3 is connected with the first electrode of the fourth transistor M4. The control electrode of the fourth transistor M4 is connected with the second storage subunit D2, and the second electrode of the fourth transistor M4 is connected with the matching line ML.

[0092] It should be noted that the first search line SL1 and the second search line SL2 are used to transmit search signals, and the matching line ML is used to output a signal indicating whether the data stored in the storage unit 200 matches the key.

[0093] For example, it is pre-set that a high-level signal indicates that the data stored in the storage unit 200 matches the key. When the addressing operation is performed, the first search line SL1 and the second search line SL2 transmit search signals to address the storage unit 200, i.e., to search for the storage unit 200 in which the stored data matches the key. If the matching line ML connected with the storage unit 200 outputs a high-level signal, it indicates that the data stored in the storage unit 200 matches the key; if the matching line ML connected with the storage unit 200 outputs a low-level signal, it indicates that the data stored in the storage unit 200 does not match the key.

[0094] As Figure 3As shown in the figure, the first storage subunit D1 includes the fifth transistor M5 to the tenth transistor M10, wherein the control electrode of the fifth transistor M5 is connected with the word line WLX, the first electrode of the fifth transistor M5 is connected with the second bit line BL, and the second electrode of the fifth transistor M5 is connected with the node QX. The control electrode of the sixth transistor M6 is connected with the node QBX, the first electrode of the sixth transistor M6 is connected with the VDD line, and the second electrode of the sixth transistor M6 is connected with the node QX. The control electrode of the seventh transistor M7 is connected with the node QBX, the first electrode of the seventh transistor M7 is connected with the VSS line, and the second electrode of the seventh transistor M7 is connected with the node QX. The control electrode of the eighth transistor M8 is connected with the node QX, the first electrode of the eighth transistor M8 is connected with the VDD line, and the second electrode of the eighth transistor M8 is connected with the node QBX. The control electrode of the ninth transistor M9 is connected with the node QX, the first electrode of the ninth transistor M9 is connected with the VSS line, and the second electrode of the ninth transistor M9 is connected with the node QBX. The control electrode of the tenth transistor M10 is connected with the word line WLX, the first electrode of the tenth transistor M10 is connected with the first bit line BLB, and the second electrode of the tenth transistor M10 is connected with the node QBX.

[0095] It can be understood that, under the control of the signal transmitted by the word line WLX, the first storage subunit D1 can read and write data.

[0096] Reference Figure 3 , the structure of the second storage subunit D2 can be the same as that of the first storage subunit D1.

[0097] As Figure 3 shown in the figure, the second storage subunit D2 includes the eleventh transistor M11 to the sixteenth transistor M16, wherein the control electrode of the eleventh transistor M11 is connected with the word line WLY, the first electrode of the eleventh transistor M11 is also connected with the second bit line BL, and the second electrode of the eleventh transistor M11 is connected with the node QY. The control electrode of the twelfth transistor M12 is connected with the node QBY, the first electrode of the twelfth transistor M12 is connected with the VDD line, and the second electrode of the twelfth transistor M12 is connected with the node QY. The control electrode of the thirteenth transistor M13 is connected with the node QBY, the first electrode of the thirteenth transistor M13 is connected with the VSS line, and the second electrode of the thirteenth transistor M13 is connected with the node QY. The control electrode of the fourteenth transistor M14 is connected with the node QY, the first electrode of the fourteenth transistor M14 is connected with the VDD line, and the second electrode of the fourteenth transistor M14 is connected with the node QBY. The control electrode of the fifteenth transistor M15 is connected with the node QY, the first electrode of the fifteenth transistor M15 is connected with the VSS line, and the second electrode of the fifteenth transistor M15 is connected with the node QBY. The control electrode of the sixteenth transistor M16 is connected with the word line WLY, the first electrode of the sixteenth transistor M16 is connected with the first bit line BLB, and the second electrode of the sixteenth transistor M16 is connected with the node QBY.

[0098] It can be understood that the second storage sub-unit D2 can perform data reading and writing under the control of the signal transmitted by the word line WLY.

[0099] In the embodiments of the present application, the transistor can be a metal-oxide semiconductor field effect transistor (MOSFET), and the transistor can be divided into two types of N-type transistor and P-type transistor. The transistor includes a gate, a source, and a drain, the gate is a control electrode of the transistor, one of the source and the drain is a first electrode of the transistor, and the other is a second electrode of the transistor.

[0100] In addition, the N-type transistor is turned on under the control of a high-level signal of the control electrode, and the P-type transistor is turned on under the control of a low-level signal of the control electrode.

[0101] Exemplarily, Figure 3 In the embodiments of the present application, the first transistor M1 to the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the ninth transistor M9 to the eleventh transistor M11, the thirteenth transistor M13, the fifteenth transistor M15, and the sixteenth transistor M16 are N-type transistors. The sixth transistor M6, the eighth transistor M8, the twelfth transistor M12, and the fourteenth transistor M14 are P-type transistors, and the embodiments of the present application are not limited thereto.

[0102] As shown in Table 1, the combination of the data stored by the first storage sub-unit D1 and the second storage sub-unit D2 can be used to represent three states of the storage unit 200, i.e., “0”, “1”, and “X”.

[0103] D1 D2 State 1 0 0 0 1 1 1 1 "X0” 0 0 "X1”

[0104] Table 1

[0105] As shown in Table 1, the "1" (high level signal) stored in the first storage subunit D1 and the "0" (low level signal) stored in the second storage subunit D2 are combined, indicating that the storage unit 200 is in a "0" state, matching the key value "0"; the "0" stored in the first storage subunit D1 and the "1" stored in the second storage subunit D2 are combined, indicating that the storage unit 200 is in a "1" state, matching the key value "1"; the combination of the "1" stored in the first storage subunit D1 and the "1" stored in the second storage subunit D2 indicates that the storage unit 200 is in a first ambiguous state (also referred to as "X" type 0, abbreviated as "X0"), and "X0" does not match the key value "0" or "1"; the combination of the "0" stored in the first storage subunit D1 and the "0" stored in the second storage subunit D2 indicates that the storage unit 200 is in a second ambiguous state (also referred to as "X" type 1, abbreviated as "X1"), and "X1" matches the key value "0" or "1". This matching state is referred to as "ambiguous matching".

[0106] The ternary content addressable memory can search and match the key value with the state of the storage unit 200. In the case where the state of the storage unit 200 matches the key value, the corresponding matching signal is output through the matching line ML, which is referred to as addressing. As shown in Table 2, before addressing, the correspondence between the key value and the voltages of the search signals transmitted by the first search line SL1 and the second search line SL2 is set in advance.

[0107] Key value SL1 voltage SL2 voltage 0 0 1 1 1 0

[0108] Table 2

[0109] As shown in Table 2, in the case where the key value is "0", the SL1 voltage is "0" and the SL2 voltage is "1", i.e., the first search line SL1 transmits a low level signal and the second search line SL2 transmits a high level signal. In the case where the key value is "1", the SL1 voltage is "1" and the SL2 voltage is "0", i.e., the first search line SL1 transmits a high level signal and the second search line SL2 transmits a low level signal.

[0110] As shown in Table 3, the data matching protocol of the storage unit 200 of the ternary content addressable memory also needs to be defined.

[0111] State Key value = 1 Key value = 0 Matching protocol 0 ML = 0 ML = 1 Data match when ML = 1 1 ML = 1 ML = 0 Data match when ML = 1 "X0” ML = 0 ML = 0 No match when ML = 0 "X1” ML = 1 ML = 1 Fuzzy match

[0112] Table 3

[0113] As shown in Table 3, when the storage unit 200 is in the "0" state, if the key value is "1", the match line ML outputs a low-level signal "0", indicating that the data of the storage unit 200 does not match the key value; if the key value is "0", the match line ML outputs a high-level signal "1", indicating that the data of the storage unit 200 matches the key value.

[0114] When the storage unit 200 is in the "1" state, if the key value is "1", the match line ML outputs a high-level signal "1", indicating that the data of the storage unit 200 matches the key value; if the key value is "0", the match line ML outputs a low-level signal "0", indicating that the data of the storage unit 200 does not match the key value.

[0115] When the storage unit 200 is in the "X0" state, no matter whether the key value is "1" or "0", the match line ML outputs a low-level signal "0", indicating that the data of the storage unit 200 does not match the key value.

[0116] When the storage unit 200 is in the "X1" state, no matter whether the key value is "1" or "0", the match line ML outputs a high-level signal "1", indicating that the data of the storage unit 200 ambiguously matches the key value.

[0117] In combination with Table 1-Table 3, and Figure 3 When addressing, a high-level signal "1" is transmitted to the match line ML in advance.

[0118] Referring to Table 1 and Figure 3 When the storage unit 200 is in the "0" state, the first storage subunit D1 stores "1" (i.e., the node QX outputs a high-level signal), and the second storage subunit D2 stores "0" (i.e., the node QY outputs a low-level signal). The second transistor M2 is turned on under the control of the high-level signal of the node QX, and the fourth transistor M4 is turned off under the control of the low-level signal of the node QY.

[0119] Based on this, referring to Table 2, Table 3 and Figure 3 When the key value is "1", the first search line SL1 transmits a high-level signal, and the second search line SL2 transmits a low-level signal. The first transistor M1 is turned on under the control of the high-level signal, and the third transistor M3 is turned off under the control of the low-level signal. The first transistor M1 and the second transistor M2 form a series path, grounding the match line ML, and pulling down the high-level signal "1" of the match line ML to a low-level signal "0". At this time, the data of the storage unit 200 does not match the key value.

[0120] In the case of the key value being "0", the first search line SL1 transmits a low level signal, the second search line SL2 transmits a high level signal, the first transistor M1 is turned off under the control of the low level signal, and the third transistor M3 is turned on under the control of the high level signal. Since the first transistor M1 and the fourth transistor M4 are both turned off, the match line ML is not grounded and keeps a high level signal "1", and at this time the data of the storage unit 200 matches the key value.

[0121] Referring to Table 1 and Figure 3 In the case of the storage unit 200 being in the "1" state, the first storage subunit D1 stores "0" (i.e. the node QX outputs a low level signal), and the second storage subunit D2 stores "1" (i.e. the node QY outputs a high level signal). The second transistor M2 is turned off under the control of the low level signal of the node QX, and the fourth transistor M4 is turned on under the control of the high level signal of the node QY.

[0122] Based on this, referring to Table 2, Table 3 and Figure 3 In the case of the key value being "1", the first search line SL1 transmits a high level signal, the second search line SL2 transmits a low level signal, the first transistor M1 is turned on under the control of the high level signal, and the third transistor M3 is turned off under the control of the low level signal. Since the second transistor M2 and the third transistor M3 are both turned off, the match line ML is not grounded and keeps a high level signal "1", and at this time the data of the storage unit 200 matches the key value.

[0123] In the case of the key value being "0", the first search line SL1 transmits a low level signal, the second search line SL2 transmits a high level signal, the first transistor M1 is turned off under the control of the low level signal, and the third transistor M3 is turned on under the control of the high level signal. The third transistor M3 and the fourth transistor M4 form a series connection, so that the match line ML is grounded, and the high level signal "1" of the match line ML is pulled down to a low level signal "0", and at this time the data of the storage unit 200 does not match the key value.

[0124] Referring to Table 1 and Figure 3 In the case of the storage unit 200 being in the "X0" state, the first storage subunit D1 and the second storage subunit D2 both store "1" (i.e. the node QX and the node QY both output a high level signal), the second transistor M2 is turned on under the control of the high level signal of the node QX, and the fourth transistor M4 is turned on under the control of the high level signal of the node QY.

[0125] Based on this, referring to Table 2, Table 3 and Figure 3In the case of the key value being "1", the first search line SL1 transmits a high-level signal, the second search line SL2 transmits a low-level signal, the first transistor M1 is turned on under the control of the high-level signal, and the third transistor M3 is turned off under the control of the low-level signal. The first transistor M1 and the second transistor M2 form a series path, so that the match line ML is grounded, and the high-level signal "1" of the match line ML is pulled down to a low-level signal "0", at this time, the data of the storage unit 200 does not match the key value.

[0126] In the case of the key value being "0", the first search line SL1 transmits a low-level signal, the second search line SL2 transmits a high-level signal, the first transistor M1 is turned off under the control of the low-level signal, and the third transistor M3 is turned on under the control of the high-level signal. The third transistor M3 and the fourth transistor M4 form a series path, so that the match line ML is grounded, and the high-level signal "1" of the match line ML is pulled down to a low-level signal "0", at this time, the data of the storage unit 200 does not match the key value.

[0127] Therefore, in the case of the storage unit 200 being in the "X0" state, no matter whether the key value is "1" or "0", the match line ML outputs a low-level signal "0", indicating that the data of the storage unit 200 does not match the key value.

[0128] Referring to Table 1 and Figure 3 In the case of the storage unit 200 being in the "X1" state, the first storage subunit D1 and the second storage subunit D2 both store "0" (i.e., the node QX and the node QY both output low-level signals), the second transistor M2 is turned off under the control of the low-level signal of the node QX, and the fourth transistor M4 is turned off under the control of the low-level signal of the node QY.

[0129] Based on this, referring to Table 2, Table 3 and Figure 3 In the case of the storage unit 200 being in the "X1" state, no matter whether the key value is "1" or "0", the match line ML cannot be grounded and remains high ("1"), at this time, the data of the storage unit 200 is ambiguously matched with the key value.

[0130] The ternary content-addressable memory based on the static random access memory architecture has fast search address speed and simple operation, but each storage unit 200 includes one addressing subunit S and two storage subunits D, a total of 16 transistors, which has problems of large power consumption, large device area, and low storage density, etc. Therefore, the field is committed to designing a ternary content-addressable memory with low power consumption and small area to achieve better PPA.

[0131] Some embodiments of the present application provide a storage unit 200 of a ternary content-addressable memory, Figure 4a plan view of the storage unit according to some embodiments; Figures 5-11 respectively Figure 4 a plan view of each film layer of the storage unit in

[0132] Referring to Figure 4 , the storage unit 200 includes an addressing subunit S and a storage subunit D arranged along a first direction X, the storage subunit D including a P-well region 3 and an N-well region 4, and the N-well region 4 being located on opposite sides of the P-well region 3 along the first direction X.

[0133] Exemplarily, the storage unit 200 includes one addressing subunit S and two storage subunits D, the two storage subunits D being a first storage subunit D1 and a second storage subunit D2 respectively, the first storage subunit D1 and the second storage subunit D2 being arranged along a second direction Y, the second direction Y intersecting the first direction X, for example, the second direction Y being perpendicular to the first direction X.

[0134] Exemplarily, the storage unit 200 further includes a matching line ML, the matching line ML extending along the first direction X, the two storage subunits D being symmetrically arranged with the matching line ML as a symmetric axis.

[0135] Continuing to refer to Figure 4 , the storage unit 200 includes, from bottom to top, an active layer 21, a gate conductive layer 22, a first conductive layer 23, a second conductive layer 24, and a third conductive layer 25, all of which are conductive film layers.

[0136] Exemplarily, the material of the active layer 21 can include metal oxide, and the material of the gate conductive layer 22 can include polycrystalline silicon doped with ions.

[0137] It can be understood that, in addition to the above-mentioned conductive film layers, the storage unit 200 further includes a plurality of insulating layers, an insulating layer being arranged between adjacent two conductive film layers to realize insulation between the conductive film layers.

[0138] Referring to Figure 5 , the storage subunit D includes a first active layer 211 and a second active layer 212, the first active layer 211 and the second active layer 212 being arranged along the first direction X and both being located within the P-well region 3.

[0139] Referring to Figure 6 , the storage subunit D further includes a first data line QBX and a second data line QX, wherein the first data line QBX overlaps the second active layer 212, and the second data line QX overlaps the first active layer 211.

[0140] It can be understood that after the active layer 21 and the gate conductive layer 22 are formed, the active layer 21 is ion doped with the gate conductive layer 22 as a mask. The first active layer 211 and the second active layer 212 are both located in the P-well region 3, and both are doped with P-type ions.

[0141] Furthermore, the first data line QBX overlaps with the second active layer 212 to form a sixth transistor M6, and the sixth transistor M6 is a P-type transistor. The part of the first data line QBX overlapping with the second active layer 212 is the gate of the sixth transistor M6, the part of the second active layer 212 overlapping with the first data line QBX is the channel of the sixth transistor M6, and the parts of the second active layer 212 located on both sides of the channel are the source and the drain of the sixth transistor M6.

[0142] Similarly, the second data line QX overlaps with the first active layer 211 to form an eighth transistor M8, and the eighth transistor M8 is a P-type transistor. The part of the second data line QX overlapping with the first active layer 211 is the gate of the eighth transistor M8, the part of the first active layer 211 overlapping with the second data line QX is the channel of the eighth transistor M8, and the parts of the first active layer 211 located on both sides of the channel are the source and the drain of the eighth transistor M8.

[0143] Referring to Figure 7 , the storage subunit D further includes a first contact pillar 51, a second contact pillar 52, and a first connection line 61. The first connection line 61 is connected with the first active layer 211 through the first contact pillar 51 and connected with the first data line QBX through the second contact pillar 52, so as to realize the connection between the second electrode (the source or the drain) of the eighth transistor M8 and the first data line QBX.

[0144] Continuously referring to Figure 7 , the storage subunit D further includes a third contact pillar 53, a fourth contact pillar 54, and a second connection line 62. The second connection line 62 is connected with the second data line QX through the third contact pillar 53 and connected with the second active layer 212 through the fourth contact pillar 54, so as to realize the connection between the second electrode (the source or the drain) of the sixth transistor M6 and the second data line QX.

[0145] Again referring to Figure 7 , along the first direction X, the second contact pillar 52 and the third contact pillar 53 are both located between the first contact pillar 51 and the fourth contact pillar 54, and the line L1 connecting the second contact pillar 52 and the third contact pillar 53 is perpendicular to the first direction X.

[0146] Exemplarily, the line L1 connecting the second contact pillar 52 and the third contact pillar 53 is also parallel to the second direction Y.

[0147] The storage unit 200 provided by the above embodiments of the present application has the following advantages. The line L1 between the second contact pillar 52 and the third contact pillar 53 is perpendicular to the first direction X and parallel to the second direction Y, so that the second contact pillar 52 and the third contact pillar 53 are on the same horizontal line along the second direction Y. This advantageously reduces the size of the storage unit 200 along the first direction X, thereby advantageously reducing the area of the storage array 210 and improving the storage density, so as to improve the PPA of the device.

[0148] In some embodiments, referring to Figure 7 and Figure 8 , the storage subunit D further includes a first voltage line V1, a fifth contact pillar 55, and a sixth contact pillar 56. The first voltage line V1 overlaps the first active layer 211 and overlaps the second active layer 212. The first voltage line V1 is connected to the first active layer 211 through the fifth contact pillar 55, so as to realize the connection between the first electrode (source electrode or drain electrode) of the eighth transistor M8 and the first voltage line V1. The first voltage line V1 is further connected to the second active layer 212 through the sixth contact pillar 56, so as to realize the connection between the first electrode (source electrode or drain electrode) of the sixth transistor M6 and the first voltage line V1.

[0149] In the related art, the first voltage line of the storage subunit does not overlap the first active layer but overlaps the second active layer, so that there is a distance between the first voltage line and the first active layer along the first direction X. Therefore, a connection line needs to be arranged in the first conductive layer, and the two ends of the connection line overlap the first voltage line and the first active layer respectively, so as to connect the first voltage line and the first active layer through the connection line.

[0150] In the above embodiments of the present application, the size of the storage unit 200 along the first direction X is reduced, so that the first voltage line V1 can overlap the first active layer 211. In this way, no connection line is needed, and the first voltage line V1 can be directly connected to the first active layer 211 through the fifth contact pillar 55. This simplifies the layout design of the storage unit 200 and improves the arrangement compactness of the structure, thereby improving the storage density of the device.

[0151] In some embodiments, referring to Figure 8 , the line L2 between the fifth contact pillar 55 and the first contact pillar 51 is perpendicular to the first direction X.

[0152] In the above embodiments, the line L2 connecting the fifth contact pillar 55 and the first contact pillar 51 is perpendicular to the first direction X and parallel to the second direction Y, so that the fifth contact pillar 55 and the first contact pillar 51 are on the same horizontal line in the second direction Y, which is beneficial to reduce the size of the memory cell 200 in the first direction X, thereby reducing the area of the memory array 210 and improving the storage density, and improving the PPA of the device.

[0153] Figure 9 The structures shown are the same, and the difference is that, Figure 7 The structures shown are the same, and the difference is that, Figure 7 The structures shown are the same, and the difference is that, Figure 9 The structures shown are the same, and the difference is that,

[0154] In some embodiments, referring to Figure 9 The first connection line 61 and the second connection line 62 are both bent twice, the first connection line 61 includes a first bending section 611, a second bending section 612 and a third bending section 613 connected in sequence, the first bending section 611 is connected with the second bending section 612, and the third bending section 613 is connected with the second contact pillar 52.

[0155] Continuing to refer to Figure 9 The second connection line 62 includes a fourth bending section 621, a fifth bending section 622 and a sixth bending section 623 connected in sequence, the fourth bending section 621 is connected with the third contact pillar 53, and the fifth bending section 622 is connected with the sixth bending section 623.

[0156] The connection between the second bending section 612 and the third bending section 613 is in a direction U1, the connection between the fourth bending section 621 and the fifth bending section 622 is in a direction U2, and the directions U1 and U2 are away from each other.

[0157] Exemplarily, the directions U1 and U2 are on the same straight line and are arranged opposite to each other.

[0158] It can be understood that, since the second contact pillar 52 and the third contact pillar 53 are on the same horizontal line, the arrangement of the first contact pillar 51, the second contact pillar 52, the third contact pillar 53 and the fourth contact pillar 54 is more compact.

[0159] In addition, the first connection line 61 and the second connection line 62 are both located in the first conductive layer 23, the first connection line 61 is connected with the first contact pillar 51 and the second contact pillar 52, and the second connection line 62 is connected with the third contact pillar 53 and the fourth contact pillar 54.

[0160] By setting the bending direction U1 of the first connecting line 61 and the bending direction U2 of the second connecting line 62 to be away from each other, the first connecting line 61 can be connected with the first contact column 51 and the second contact column 52, and the second connecting line 62 can be connected with the third contact column 53 and the fourth contact column 54, and the distance between the first connecting line 61 and the second connecting line 62 can be increased to avoid the first connecting line 61 and the second connecting line 62 from contacting in the first conductive layer 23, thereby avoiding short circuit between the first connecting line 61 and the second connecting line 62.

[0161] In some embodiments, referring to Figure 5 , the N well region 4 includes a first sub-N well region 41 and a second sub-N well region 42, the first sub-N well region 41 is located on the side of the P well region 3 close to the addressing sub-unit S, and the second sub-N well region 42 is located on the side of the P well region 3 away from the addressing sub-unit S.

[0162] Continuing to refer to Figure 5 , the storage sub-unit D further includes a third active layer 213 and a fourth active layer 214, the third active layer 213 is located in the first sub-N well region 41, and the fourth active layer 214 is located in the second sub-N well region 42.

[0163] Referring to Figure 9 , the storage sub-unit D further includes a first word line WL1 and a first cut-off structure C1, the first word line WL1 and the first data line QBX are arranged along the first direction X and are separated by the first cut-off structure C1 to achieve insulation between the two. The first word line WL1 overlaps the third active layer 213, and the first data line QBX also overlaps the fourth active layer 214.

[0164] It can be understood that the third active layer 213 is located in the first sub-N well region 41, and the fourth active layer 214 is located in the second sub-N well region 42, both the third active layer 213 and the fourth active layer 214 are located in the N well region 4, and both are doped with N-type ions.

[0165] Furthermore, the first word line WL1 overlaps the third active layer 213 to form a tenth transistor M10, the tenth transistor M10 is an N-type transistor. The part of the first word line WL1 overlapping the third active layer 213 is the gate of the tenth transistor M10, the part of the third active layer 213 overlapping the first word line WL1 is the channel of the tenth transistor M10, and the parts of the third active layer 213 on both sides of the channel are the source and the drain of the tenth transistor M10.

[0166] Similarly, the first data line QBX also overlaps with the fourth active layer 214 to form a seventh transistor M7, and the seventh transistor M7 is an N-type transistor. The part of the first data line QBX overlapping with the fourth active layer 214 is the gate of the seventh transistor M7, the part of the fourth active layer 214 overlapping with the first data line QBX is the channel of the seventh transistor M7, and the parts of the fourth active layer 214 located on both sides of the channel are the source and the drain of the seventh transistor M7.

[0167] By arranging the first and second sub-N-well regions 41 and 42 on opposite sides of the P-well region 3, according to the well proximity effect (WPE), the influence of the P-type transistor in the P-well region 3 on the N-type transistor in the first and second sub-N-well regions 41 and 42 is balanced, which can ensure that the on and off capabilities of the N-type transistor in the first and second sub-N-well regions 41 and 42 are similar, thereby facilitating the improvement of the reliability of the performance of the device.

[0168] Continuing to refer to Figure 9 The storage subunit D further includes a second word line WL2 and a second cut-off structure C2. The second data line QX and the second word line WL2 are arranged along the first direction X and are separated by the second cut-off structure C2 to achieve insulation therebetween. The second data line QX also overlaps with the third active layer 213, and the second word line WL2 overlaps with the fourth active layer 214.

[0169] It can be understood that the second data line QX also overlaps with the third active layer 213 to form a ninth transistor M9, and the ninth transistor M9 is an N-type transistor. The part of the second data line QX overlapping with the third active layer 213 is the gate of the ninth transistor M9, the part of the third active layer 213 overlapping with the second data line QX is the channel of the ninth transistor M9, and the parts of the third active layer 213 located on both sides of the channel are the source and the drain of the ninth transistor M9.

[0170] Similarly, the second word line WL2 overlaps with the fourth active layer 214 to form a fifth transistor M5, and the fifth transistor M5 is an N-type transistor. The part of the second word line WL2 overlapping with the fourth active layer 214 is the gate of the fifth transistor M5, the part of the fourth active layer 214 overlapping with the second word line WL2 is the channel of the fifth transistor M5, and the parts of the fourth active layer 214 located on both sides of the channel are the source and the drain of the fifth transistor M5.

[0171] In some embodiments, referring to Figure 9The storage subunit D further includes a seventh contact column 57 and an eighth contact column 58, and the first bending section 611 of the first connection line 61 is further connected with the third active layer 213 through the seventh contact column 57, so as to realize the connection of the first data line QBX with the second electrode (source electrode or drain electrode) of the ninth transistor M9 and the second electrode (source electrode or drain electrode) of the tenth transistor M10.

[0172] Continuing to refer to Figure 9 The sixth bending section 623 of the second connection line 62 is further connected with the fourth active layer 214 through the eighth contact column 58, and the second data line QX is connected with the second electrode (source electrode or drain electrode) of the fifth transistor M5 and the second electrode (source electrode or drain electrode) of the seventh transistor M7 through the second connection line 62.

[0173] Figure 10 The structures shown are the same, and the difference lies in that Figure 8 The structures are labeled differently, so as to clearly show the structures and their labels. Figure 8 And Figure 10 The structures are labeled differently, so as to clearly show the structures and their labels.

[0174] In some embodiments, referring to Figure 10 The storage subunit D further includes a ninth contact column 59 and a first bit line BLB, the first bit line BLB passes through the first sub-N-well region 41 and is connected with the third active layer 213 through the ninth contact column 59, so as to realize the connection of the first electrode (source electrode or drain electrode) of the tenth transistor M10 with the first bit line BLB.

[0175] Continuing to refer to Figure 10 The storage subunit D further includes a tenth contact column 510 and a second bit line BL, the second bit line BL passes through the second sub-N-well region 42 and is connected with the fourth active layer 214 through the tenth contact column 510, so as to realize the connection of the first electrode (source electrode or drain electrode) of the fifth transistor M5 with the second bit line BL.

[0176] In some embodiments, referring to Figure 10 The storage subunit D further includes an eleventh contact column 511, a twelfth contact column 512 and two second voltage lines V2, one of the two second voltage lines V2 passes through the first sub-N-well region 41 and is connected with the third active layer 213 through the eleventh contact column 511, so as to realize the connection of the first electrode (source electrode or drain electrode) of the ninth transistor M9 with the second voltage line V2 (VSS line).

[0177] Continuing to refer to Figure 10 The other of the two second voltage lines V2 passes through the second sub-N-well region 42 and is connected with the fourth active layer 214 through the twelfth contact column 512, so as to realize the connection of the first electrode (source electrode or drain electrode) of the seventh transistor M7 with the second voltage line V2 (VSS line).

[0178] In some embodiments, referring to Figure 5 , the addressing subunit S includes a fifth active layer 215, which is also doped with N-type ions.

[0179] Referring to Figure 6 , the addressing subunit S further includes a first lookup gate line HBLX and a second lookup gate line HBLY, which respectively overlap with the fifth active layer 215.

[0180] It can be understood that the first lookup gate line HBLX overlaps with the fifth active layer 215 to form a first transistor M1, which is an N-type transistor. The part of the first lookup gate line HBLX overlapping with the fifth active layer 215 is the gate of the first transistor M1, the part of the fifth active layer 215 overlapping with the first lookup gate line HBLX is the channel of the first transistor M1, and the parts of the fifth active layer 215 located on both sides of the channel are the source and the drain of the first transistor M1.

[0181] Similarly, the second lookup gate line HBLY overlaps with the fifth active layer 215 to form a third transistor M3, which is an N-type transistor. The part of the second lookup gate line HBLY overlapping with the fifth active layer 215 is the gate of the third transistor M3, the part of the fifth active layer 215 overlapping with the second lookup gate line HBLY is the channel of the third transistor M3, and the parts of the fifth active layer 215 located on both sides of the channel are the source and the drain of the third transistor M3.

[0182] Continuing to refer to Figure 6 , in the two storage subunits D, the two second data lines QX also overlap with the fifth active layer 215.

[0183] It can be understood that the second data line QX in the first storage subunit D1 overlaps with the fifth active layer 215 to form a second transistor M2, which is an N-type transistor. The part of the second data line QX overlapping with the fifth active layer 215 is the gate of the second transistor M2, the part of the fifth active layer 215 overlapping with the second data line QX is the channel of the second transistor M2, and the parts of the fifth active layer 215 located on both sides of the channel are the source and the drain of the second transistor M2.

[0184] Similarly, the second data line QX in the second storage subunit D2 overlaps with the fifth active layer 215 to form a fourth transistor M4, which is an N-type transistor. The part of the second data line QX overlapping with the fifth active layer 215 is the gate of the fourth transistor M4, the part of the fifth active layer 215 overlapping with the second data line QX is the channel of the fourth transistor M4, and the parts of the fifth active layer 215 located on both sides of the channel are the source and the drain of the fourth transistor M4.

[0185] Referring to Figure 8 , the addressing subunit S further includes a first search line SL1, a third voltage line V3, and a second search line SL2, which are arranged in sequence along the first direction X.

[0186] Continuing to refer to Figure 8 , the addressing subunit S further includes a thirteenth contact column 513, a fourteenth contact column 514, and a third connection line 63, the third connection line 63 is connected with the first search gate line HBLX through the thirteenth contact column 513, and is connected with the first search line SL1 through the fourteenth contact column 514, so as to realize the transmission of the search signal from the first search line SL1 to the first search gate line HBLX.

[0187] Again referring to Figure 8 , the addressing subunit S further includes a fifteenth contact column 515, a sixteenth contact column 516, and a fourth connection line 64, the fourth connection line 64 is connected with the second search gate line HBLY through the fifteenth contact column 515, and is connected with the second search line SL2 through the sixteenth contact column 516, so as to realize the transmission of the search signal from the second search line SL2 to the second search gate line HBLY.

[0188] Among them, the thirteenth contact column 513 and the fourteenth contact column 514 are located on the side of the third voltage line V3 away from the second search line SL2. The fifteenth contact column 515 is located on the side of the third voltage line V3 away from the second search line SL2, and the sixteenth contact column 516 is located on the side of the third voltage line V3 away from the first search line SL1.

[0189] In the related art, the fifteenth contact column and the sixteenth contact column are both located on the side of the third voltage line away from the first search line, and since the fourth connection line is connected with the second search gate line through the fifteenth contact column, that is, the contact hole where the fifteenth contact column is located communicates the first conductive layer with the gate conductive layer, the contact hole where the fifteenth contact column is located is marked as "23-22".

[0190] In the storage unit, there are also some contact columns whose contact holes communicate the first conductive layer with the active layer, these contact columns are marked as "23-21", the contact hole "23-22" and the contact hole "23-21" are formed in the same etching process, but the depth of the contact hole "23-22" is different from that of the contact hole "23-21", the depth of the contact hole "23-21" is greater than that of the contact hole "23-22", in the case of ensuring that the contact hole "23-21" is etched to the active layer, the contact hole "23-22" may be over-etched, resulting in that the gate conductive layer is etched through.

[0191] Therefore, by arranging the fifteenth contact pillar not to overlap with the fifth active layer, over-etching of the contact hole "23-22" where the fifteenth contact pillar is located is avoided, and thus short circuit of the fifteenth contact pillar connecting the second lookup gate line and the fifth active layer is avoided.

[0192] However, in the case where the fifteenth contact pillar does not overlap with the fifth active layer, the fifteenth contact pillar occupies the space of one horizontal line, resulting in an increase in the size of the addressing subunit along the first direction X, and thus an increase in the size of the memory cell along the first direction X.

[0193] In the above embodiments of the present application, the fifteenth contact pillar 515 is located on the side of the third voltage line V3 away from the second lookup line SL2, and the sixteenth contact pillar 516 is located on the side of the third voltage line V3 away from the first lookup line SL1, i.e., the fifteenth contact pillar 515 and the sixteenth contact pillar 516 are located on opposite sides of the third voltage line V3 along the first direction X, and the fifteenth contact pillar 515 can be located in the same horizontal line as the thirteenth contact pillar 513 and the fourteenth contact pillar 514. In this way, the space of one horizontal line can be saved, the size of the addressing subunit S along the first direction X is reduced, and thus the size of the memory cell 200 along the first direction X is reduced, thereby facilitating reduction in the area of the memory array 210 and improvement in the storage density, and thus improvement in the PPA of the device.

[0194] In some embodiments, referring to Figure 7 and Figure 8 , the third voltage line V3 is connected with the fifth active layer 215 through the contact pillar 50 to realize connection of the first electrode (source or drain) of the first transistor M1 with the third voltage line V3 and connection of the first electrode (source or drain) of the third transistor M3 with the third voltage line V3.

[0195] In some embodiments, referring to Figure 8 , the fourth connection line 64 crosses the third voltage line V3. It can be understood that, since the fifteenth contact pillar 515 and the sixteenth contact pillar 516 are located on opposite sides of the third voltage line V3 along the first direction X, the fourth connection line 64 needs to cross the third voltage line V3 and be connected with the fifteenth contact pillar 515 and the sixteenth contact pillar 516, respectively.

[0196] In addition, the fifteenth contact pillar 515 does not overlap with the fifth active layer 215. According to the foregoing, over-etching of the contact hole "23-22" where the fifteenth contact pillar 515 is located is avoided, and thus short circuit of the fifteenth contact pillar 515 connecting the second lookup gate line HBLY and the fifth active layer 215 is avoided.

[0197] In some embodiments, referring to Figure 10The third connection line 63 and the fourth connection line 64 are each bent once. The third connection line 63 comprises a seventh bent segment 631 and an eighth bent segment 632 connected in sequence. The seventh bent segment 631 is connected with the thirteenth contact pillar 513. The connection position of the seventh bent segment 631 and the eighth bent segment 632 is connected with the fourteenth contact pillar 514.

[0198] Continuing to refer to Figure 10 The fourth connection line 64 comprises a ninth bent segment 641 and a tenth bent segment 642 connected in sequence. The ninth bent segment 641 is connected with the fifteenth contact pillar 515. The tenth bent segment 642 crosses the third voltage line V3 and is connected with the sixteenth contact pillar 516.

[0199] The bending direction of the connection position of the seventh bent segment 631 and the eighth bent segment 632 is U3. The bending direction of the connection position of the ninth bent segment 641 and the tenth bent segment 642 is U4. The direction U3 and the direction U4 are close to each other.

[0200] Exemplarily, the direction U3 and the direction U4 are located on the same straight line and are arranged oppositely.

[0201] Exemplarily, referring to Figure 10 The eighth bent segment 632 of the third connection line 63 crosses the third voltage line V3. The thirteenth contact pillar 513 does not overlap with the fifth active layer 215, which can avoid over-etching of the contact hole “23-22” where the thirteenth contact pillar 513 is located, and can avoid short circuit of the thirteenth contact pillar 513 connecting the first lookup gate line HBLX and the fifth active layer 215.

[0202] Figure 11 The structure shown is the same, and the difference is that Figure 4 The structures are marked differently to clearly show the structures and their markings. Figure 4 Figure 11 In some embodiments, referring to The third connection line 63 of the addressing subunit S of the adjacent two storage units 200 is disconnected with each other. The fourth connection line 64 of the addressing subunit S of the adjacent two storage units 200 is disconnected with each other.

[0203] Figure 11 In the related art, along the second direction Y, the adjacent two storage units need to be arranged in mirror symmetry, so that the addressing subunits of the adjacent two storage units can share one third connection line and can share one fourth connection line.

[0204] In the related art, along the second direction Y, the adjacent two storage units need to be arranged in mirror symmetry, so that the addressing subunits of the adjacent two storage units can share one third connection line and can share one fourth connection line.

[0205] ​In the above embodiments of the application, the addressing sub-units S of the two adjacent memory units 200 do not share the third connection line 63, and the addressing sub-units S of the two adjacent memory units 200 do not share the fourth connection line 64. Therefore, in the second direction Y, the two adjacent memory units 200 can not be limited to be arranged in a mirror symmetry, and the diversity of arrangement of the plurality of memory units 200 in the memory array 210 can be improved, thereby facilitating the optimization of the arrangement design of the memory array 210.

[0206] In some embodiments, referring to Figure 11 , the matching line ML is connected with the fifth active layer 215 to realize the connection of the second electrode (source or drain) of the second transistor M2 and the matching line ML and the connection of the second electrode (source or drain) of the fourth transistor M4 and the matching line ML, so as to transmit the matching signal output by the addressing sub-unit S to the matching line ML.

[0207] Continuing to refer to Figure 11 , the third connection line 63 and the fourth connection line 64 are symmetrically arranged with the matching line ML as the axis, so as to improve the compactness of the arrangement of the third connection line 63 and the fourth connection line 64.

[0208] In some embodiments, referring to Figure 11 , the addressing sub-unit S further includes a seventeenth contact column 517, an eighteenth contact column 518, and a fifth connection line 65, and the fifth connection line 65 crosses the first search line SL1. The matching line ML is connected with one end of the fifth connection line 65 through the seventeenth contact column 517, and the other end of the fifth connection line 65 is connected with the fifth active layer 215 through the eighteenth contact column 518 to realize the connection of the matching line ML and the fifth active layer 215.

[0209] In some embodiments, referring to Figure 6 , the addressing sub-unit S further includes a third cut-off structure C3 and a fourth cut-off structure C4, and the first search gate line HBLX and the first word line WL1 of one memory sub-unit D are arranged along the first direction X and are separated by the third cut-off structure C3 to realize the insulation therebetween.

[0210] Continuing to refer to Figure 6 , the second search gate line HBLY and the first word line WL1 of the other memory sub-unit D are arranged along the first direction X and are separated by the fourth cut-off structure C4 to realize the insulation therebetween.

[0211] Exemplarily, the third cut-off structure C3 is spaced apart from the fifth active layer 215, and no contact column is arranged between the third cut-off structure C3 and the fifth active layer 215. The fourth cut-off structure C4 is spaced apart from the fifth active layer 215, and no contact column is arranged between the fourth cut-off structure C4 and the fifth active layer 215. The space of one horizontal line can be saved, the size of the addressing sub-unit S along the first direction X is reduced, and thus the size of the storage unit 200 along the first direction X is reduced, thereby facilitating the reduction of the area of the storage array 210, the improvement of the storage density, and the improvement of the PPA of the device.

[0212] In some embodiments, referring to Figure 11 , the first storage sub-unit D1 and the second storage sub-unit D2 share one first voltage line V1 and two second voltage lines V2, and the first storage sub-unit D1 and the second storage sub-unit D2 each include a first word line WL1 and a second word line WL2. The addressing sub-unit S includes a third voltage line V3.

[0213] Referring to Figure 11 , the storage unit 200 includes, in sequence along the second direction Y, a fourth voltage line V4, a third word line WL3, a match line ML, a fourth word line WL4, and a fifth voltage line V5, and each line extends along the first direction X.

[0214] It should be noted that the fourth voltage line V4 is the “VSS line”, and the fifth voltage line V5 is the “VDD line”. The third word line WL3 is the “word line WLX”, and the fourth word line WL4 is the “word line WLY”.

[0215] Continuing to refer to Figure 11 , the fourth voltage line V4 is connected to the two second voltage lines V2 and the third voltage line V3, for example, the fourth voltage line V4 is connected to the two second voltage lines V2 through the nineteenth contact column 519 and the twentieth contact column 520, and is connected to the third voltage line V3 through the twenty-first contact column 521.

[0216] Continuing to refer to Figure 11 , the third word line WL3 is connected to the first word line WL1 and the second word line WL2 of the first storage sub-unit D1.

[0217] Exemplarily, the first storage sub-unit D1 includes a twenty-second contact column 522, a twenty-third contact column 523, and a sixth connection line 66. The sixth connection line 66 is connected to the third word line WL3 through the twenty-second contact column 522, and is connected to the first word line WL1 through the twenty-third contact column 523, so as to realize the connection between the first word line WL1 and the third word line WL3.

[0218] The first storage subunit D1 further includes a twenty-fourth contact column 524, a twenty-fifth contact column 525, and a seventh connection line 67. The seventh connection line 67 is connected with the third word line WL3 through the twenty-fourth contact column 524, and is connected with the second word line WL2 through the twenty-fifth contact column 525, so as to realize the connection between the second word line WL2 and the third word line WL3.

[0219] With reference back to Figure 11 , the fourth word line WL4 is connected with the first word line WL1 and the second word line WL2 of the second storage subunit D2.

[0220] Exemplarily, the second storage subunit D2 includes a twenty-sixth contact column 526, a twenty-seventh contact column 527, and an eighth connection line 68. The eighth connection line 68 is connected with the fourth word line WL4 through the twenty-sixth contact column 526, and is connected with the first word line WL1 through the twenty-seventh contact column 527, so as to realize the connection between the first word line WL1 and the fourth word line WL4.

[0221] The second storage subunit D2 further includes a twenty-eighth contact column 528, a twenty-ninth contact column 529, and a ninth connection line 69. The ninth connection line 69 is connected with the fourth word line WL4 through the twenty-eighth contact column 528, and is connected with the second word line WL2 through the twenty-ninth contact column 529, so as to realize the connection between the second word line WL2 and the fourth word line WL4.

[0222] With reference back to Figure 11 , the fifth voltage line V5 is connected with the first voltage line V1. For example, the fifth voltage line V5 is connected with the first voltage line V1 through a thirtieth contact column 530.

[0223] The storage array, the content-addressable memory, and the electronic device provided by some embodiments of the present application include the storage unit provided by any of the above embodiments, and can achieve the beneficial effects of the storage unit, which will not be described herein again.

[0224] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any changes or replacements within the technical scope disclosed by the present application can be easily conceived by those skilled in the art, and shall be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A memory array comprising: The memory cell includes an addressing subunit and a memory subunit arranged along a first direction; The memory subunit includes a P-well region and an N-well region, the N-well region is located on opposite sides of the P-well region along the first direction; The memory subunit includes: A first active layer and a second active layer arranged along the first direction and located in the P-well region; A first data line and a second data line, the first data line overlaps the second active layer, and the second data line overlaps the first active layer; A first contact pillar, a second contact pillar, and a first connection line, the first connection line is connected to the first active layer through the first contact pillar and connected to the first data line through the second contact pillar; A third contact pillar, a fourth contact pillar, and a second connection line, the second connection line is connected to the second data line through the third contact pillar and connected to the second active layer through the fourth contact pillar; Wherein, along the first direction, the second contact pillar and the third contact pillar are both located between the first contact pillar and the fourth contact pillar; the connection line between the second contact pillar and the third contact pillar is perpendicular to the first direction.

2. The storage array of claim 1, wherein, The memory subunit further includes: A first voltage line overlapping the first active layer and the second active layer; A fifth contact pillar and a sixth contact pillar, the first voltage line is connected to the first active layer through the fifth contact pillar and connected to the second active layer through the sixth contact pillar.

3. The storage array of claim 2, wherein, The connection line between the fifth contact pillar and the first contact pillar is perpendicular to the first direction.

4. The storage array of any of claims 1-3, wherein, Both the first connection line and the second connection line are bent twice; The first connection line includes a first bending segment, a second bending segment, and a third bending segment connected in sequence; the connection between the first bending segment and the second bending segment is connected to the first contact pillar; the third bending segment is connected to the second contact pillar; The second connection line includes a fourth bending segment, a fifth bending segment, and a sixth bending segment connected in sequence; the fourth bending segment is connected to the third contact pillar; the connection between the fifth bending segment and the sixth bending segment is connected to the fourth contact pillar; Wherein, the bending direction of the connection between the second bending segment and the third bending segment is away from the bending direction of the connection between the fourth bending segment and the fifth bending segment.

5. The storage array of claim 4, wherein, The N-well region includes a first sub-N-well region and a second sub-N-well region, the first sub-N-well region is located on the side of the P-well region close to the addressing subunit, and the second sub-N-well region is located on the side of the P-well region away from the addressing subunit; The memory subunit further includes: A third active layer and a fourth active layer, the third active layer is located in the first sub-N-well region, and the fourth active layer is located in the second sub-N-well region; A seventh contact pillar and an eighth contact pillar, the first bending segment is connected to the third active layer through the seventh contact pillar, and the sixth bending segment is connected to the fourth active layer through the eighth contact pillar.

6. The storage array of claim 5, wherein, The memory subunit further includes: a first word line and a first cut-off structure, the first word line and the first data line are arranged along the first direction and are separated by the first cut-off structure; the first word line overlaps the third active layer, and the first data line also overlaps the fourth active layer; a second word line and a second cut-off structure, the second data line and the second word line are arranged along the first direction and are separated by the second cut-off structure; the second data line also overlaps the third active layer, and the second word line overlaps the fourth active layer.

7. The storage array of claim 5 or 6, wherein, The storage subunit further comprises: a ninth contact column and a first bit line, the first bit line passes through the first sub-N well region and is connected with the third active layer through the ninth contact column; a tenth contact column and a second bit line, the second bit line passes through the second sub-N well region and is connected with the fourth active layer through the tenth contact column.

8. The storage array of any of claims 5-7, wherein, The storage subunit further comprises an eleventh contact column, a twelfth contact column and two second voltage lines; one of the two second voltage lines passes through the first sub-N well region and is connected with the third active layer through the eleventh contact column; the other of the two second voltage lines passes through the second sub-N well region and is connected with the fourth active layer through the twelfth contact column.

9. The storage array of any of claims 1-8, wherein, The storage unit comprises one addressing subunit and two storage subunits; The two storage subunits are arranged along a second direction intersecting the first direction.

10. The storage array of claim 9, wherein, The addressing subunit comprises: a fifth active layer; a first search gate line and a second search gate line, respectively overlapping the fifth active layer; among the two storage subunits, two second data lines also overlap the fifth active layer; a first search line, a third voltage line and a second search line, arranged in sequence along the first direction; a thirteenth contact column, a fourteenth contact column and a third connection line, the third connection line is connected with the first search gate line through the thirteenth contact column and is connected with the first search line through the fourteenth contact column; a fifteenth contact column, a sixteenth contact column and a fourth connection line, the fourth connection line is connected with the second search gate line through the fifteenth contact column and is connected with the second search line through the sixteenth contact column; wherein the thirteenth contact column and the fourteenth contact column are located on the side of the third voltage line away from the second search line; the fifteenth contact column is located on the side of the third voltage line away from the second search line, and the sixteenth contact column is located on the side of the third voltage line away from the first search line.

11. The storage array of claim 10, wherein, The fourth connection line spans the third voltage line, and the fifteenth contact column does not overlap the fifth active layer.

12. The storage array of claim 10 or 11, wherein, The third connection line and the fourth connection line are both bent once; The third connection line comprises a seventh bending segment and an eighth bending segment connected in sequence; the seventh bending segment is connected with the thirteenth contact column; the connection between the seventh bending segment and the eighth bending segment is connected with the fourteenth contact column; the fourth connection line comprises a ninth bending segment and a tenth bending segment connected in sequence; the ninth bending segment is connected with the fifteenth contact column; the connection between the ninth bending segment and the tenth bending segment is connected with the sixteenth contact column. The fourth connecting line comprises a ninth bending segment and a tenth bending segment connected in sequence; the ninth bending segment is connected with the fifteenth contact column; The tenth bending segment crosses the third voltage line and is connected with the sixteenth contact column; The bending direction of the connection between the seventh bending segment and the eighth bending segment is close to the bending direction of the connection between the ninth bending segment and the tenth bending segment.

13. The storage array of claim 12, wherein, The eighth bending segment of the third connecting line crosses the third voltage line, and the thirteenth contact column does not overlap with the fifth active layer.

14. The storage array of any of claims 10-13, wherein, The storage unit further comprises a matching line extending along the first direction, and the matching line is connected with the fifth active layer; The third connecting line and the fourth connecting line are symmetrically arranged with the matching line as the symmetric axis.

15. The memory array of claim 14, wherein, The addressing subunit further comprises a seventeenth contact column, an eighteenth contact column and a fifth connecting line crossing the first search line; The matching line is connected with one end of the fifth connecting line through the seventeenth contact column, and the other end of the fifth connecting line is connected with the fifth active layer through the eighteenth contact column.

16. The storage array of any of claims 10-15, wherein, The third connecting lines of the addressing subunits of two adjacent storage units are disconnected with each other, and the fourth connecting lines of the addressing subunits of two adjacent storage units are disconnected with each other.

17. The storage array of any of claims 10-16, wherein, The storage subunit comprises a first word line; The addressing subunit further comprises a third cut-off structure and a fourth cut-off structure; the first search gate line and the first word line of one storage subunit are arranged along the first direction and are separated by the third cut-off structure; the second search gate line and the first word line of another storage subunit are arranged along the first direction and are separated by the fourth cut-off structure.

18. The memory array of claim 17, wherein, The third cut-off structure is arranged apart from the fifth active layer, and no contact column is arranged between the third cut-off structure and the fifth active layer; The fourth cut-off structure is arranged apart from the fifth active layer, and no contact column is arranged between the fourth cut-off structure and the fifth active layer.

19. The storage array of any of claims 9-18, wherein, The storage unit further comprises a matching line extending along the first direction; The two storage subunits are symmetrically arranged with the matching line as the symmetric axis.

20. The storage array of any of claims 9-19, wherein, The two storage subunits comprise a first storage subunit and a second storage subunit, the first storage subunit and the second storage subunit share one first voltage line and two second voltage lines, and the first storage subunit and the second storage subunit each comprise a first word line and a second word line; the addressing subunit comprises a third voltage line; The storage unit further comprises a fourth voltage line, a third word line, a matching line, a fourth word line and a fifth voltage line arranged in sequence along the second direction, and all extending along the first direction; The fourth voltage line is connected with the two second voltage lines and the third voltage line, the third word line is connected with the first word line and the second word line of the first storage subunit, the fourth word line is connected with the first word line and the second word line of the second storage subunit, and the fifth voltage line is connected with the first voltage line.

21. A content-addressable memory, comprising: Comprise: The storage array according to any one of claims 1-20; A controller electrically connected with the storage array.

22. An electronic device, comprising: Comprise: A circuit board; The content addressable memory of claim 21, disposed on and electrically connected to the circuit board.

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