A data processing method based on a chaotic iterative sequence reconfigurable processor

Abstract

This invention proposes a data processing method based on a reconfigurable processor with out-of-order iterative execution. The method includes: constructing a dynamically reconfigurable processor based on out-of-order iterative execution; annotating the memory access operators L0, L1, and L2 in the application pseudocode; where L0 represents the load operator A[i][j], L1 represents the load operator A[k][i], and L2 represents the load operator A[k][j]; executing the three operators L0, L1, and L2 serially and respectively deploying them on the memory access units LSU0, LSU1, and LSU2 of the dynamically reconfigurable processor; and performing out-of-order iteration based on the dynamically reconfigurable processor, wherein the out-of-order iteration operates in a pipelined manner, including four stages: fetch iteration, issue, execute, and write back. This method solves the problem of memory partitioning in non-template computation at its source, thereby improving the parallel data memory access capability of the reconfigurable processor.

Description

Technical Field

[0001] This invention belongs to the field of dynamically reconfigurable processors. Background Technology

[0002] In recent years, with the decline of Moore's Law, improving the performance of general-purpose processors (GPPs) by scaling up integration is unsustainable, yet modern applications still demand high-performance and energy-efficient platforms. Application-specific integrated circuits (ASICs) can achieve maximum performance and efficiency for specific applications but lack flexibility. Ideally, this invention aims to create an architecture that approaches the efficiency of ASICs while maintaining the flexibility of GPPs. Coarse-grained reconfigurable arrays (CGRAs) are a promising solution to achieve this goal. CGRAs feature dozens of dynamically configurable and interconnected distributed processing elements (PEs), providing high throughput and flexible data paths, thus offering energy-efficient solutions for a wide range of applications.

[0003] To unlock the potential of CGRA, modular scheduling is widely used to pipeline loop execution, with the Initiation Interval (II) between adjacent loop iterations being a primary concern. A smaller II indicates higher performance, but also requires parallel data access to serve multiple PEs. Furthermore, CGRA's on-chip memory is typically organized across multiple memory blocks for parallel access. In data arrays involving multiple references, memory partitioning is often used to divide the original data array into multiple memory blocks for storage. However, memory partitioning is limited to regular memory references with fixed access patterns, which is common in template computations. For non-template computations, because they contain array references with variable distances, the access pattern changes with the iteration variable. Therefore, in non-template computations, it is difficult to perform static memory partitioning for irregular array references, leading to access conflicts and performance penalties.

[0004] To avoid access violations in non-template computations, the simplest approach is to increase the II to the number of array references and statically separate these irregular array references so that only one array reference exists in the control step. This workaround can be easily implemented on statically scheduled CGRAs with only compiler modifications, but it results in a significant performance penalty. Another approach is to dynamically schedule these array references at the operator granularity. By actively pipelined on dynamically scheduled CGRAs, access violations are dynamically detected and resolved, thus improving performance. Ideally, there are no violations, and I II is achieved. However, in most cases, violations are detected, and the pipeline must stop. Therefore, dynamically scheduled CGRAs can improve the performance of non-template programs to some extent, but it incurs significant hardware overhead due to the need for a complex scheduler for each PE. In FPGA High-level Synthesis (HLS), there are also works that convert non-template loops into graphs by traversing the entire iterative domain and then leveraging data parallelism at the graph level, resulting in considerable data parallelism; however, these works not only require significant compilation work but also incur expensive hardware overhead. Therefore, leveraging intra-iterative data parallelism (e.g., static and dynamic CGRA) in non-template computation is difficult, while leveraging graph-level data parallelism (e.g., graph-based memory partitioning) is also costly. Leveraging inter-iterative data parallelism seems like a good option, but it's difficult to reap the benefits from traditional static compilation techniques (such as loop transformations). Summary of the Invention

[0005] The present invention aims to at least partially solve one of the technical problems in the related art.

[0006] Therefore, the purpose of this invention is to propose a data processing method based on a randomized iterative reconfigurable processor to improve the parallel data memory access capability of the reconfigurable processor.

[0007] To achieve the above objectives, a first aspect of the present invention proposes a data processing method based on a randomized iterative reconfigurable processor, comprising:

[0008] Construct a dynamically reconfigurable processor based on out-of-order iterative execution;

[0009] The memory access operators L0, L1, and L2 in the application pseudocode are labeled; where L0 represents the load operator A[i][j], L1 represents the load operator A[k][i], and L2 represents the load operator A[k][j]. The three operators L0, L1, and L2 are executed serially and are respectively located on the memory access units LSU0, LSU1, and LSU2 of the dynamically reconfigurable processor.

[0010] The out-of-order iteration is performed based on the dynamically reconfigurable processor, wherein the out-of-order iteration operates in a pipelined manner and includes four stages: fetch iteration, issue, execute, and write back.

[0011] In addition, a data processing method based on a randomized iterative reconfigurable processor according to the above embodiments of the present invention may also have the following additional technical features:

[0012] Furthermore, in one embodiment of the present invention, the construction of a dynamically reconfigurable processor based on out-of-order iterative execution includes:

[0013] Construct an iterative generation engine, an iterative reordering engine, and a reconfigurable computing engine; among them,

[0014] The iterative generation engine consists of an iterative variable generator and N address generators, where N represents the maximum number of simultaneous memory access operators supported. By configuring the step size, initial value, and end value of the accumulator, the address generator can generate addresses for various memory access operators.

[0015] The iterative reordering engine includes an iterative cache, a planned memory access table, an iterative selection unit, and a reordering cache.

[0016] The reconfigurable computing engine includes multiple sets of high-speed temporary storage and a PE array with mesh interconnection.

[0017] Furthermore, in one embodiment of the present invention, the method further includes eliminating read-after-write (WAR) and write-after-write (WAW) hazards generated by out-of-order iterative execution by reordering the cached ROB, and dynamically detecting access conflicts and write-after-read (RAW) hazards by using an iterative selection unit (ISU).

[0018] The ROB includes a randomly accessible FIFO of depth M, a demultiplexer, an M×N-1 crossbar switch, and N-1 RAW reuse buffers, where M and N represent the IB size and the maximum number of memory references supported. Each element of the randomly accessible FIFO includes three segments: storage address S, result ready flag R, and result data D.

[0019] The ISU contains M access conflict detection modules (ACDM), M RAW detection modules (RAMDM), and N buffer queues.

[0020] Furthermore, in one embodiment of the present invention, the step of eliminating read-after-write WAR and write-after-write WAW hazards generated by out-of-order iterative execution by reordering the cached ROB includes:

[0021] During iteration, if RaFIFO is not full, the iteration is obtained from IRG to IB; at the same time, a new element containing the iteration storage address is sent to RaFIFO, where the ready flag is set to false.

[0022] Once RCE completes its iteration, it writes the data back to the corresponding element's data segment in ROB via random access and sets the ready flag to true. If the ready flag of the element preceding RaFIFO is true, the corresponding data will be written back to the SPM's storage block.

[0023] Furthermore, in one embodiment of the present invention, the step of dynamically detecting access conflicts and read-after-write RAW hazards through the Iterative Selection Unit (ISU) includes:

[0024] In ACDM, read-after-read RAR data reuse is detected by comparing the addresses of all memory load operators iterated in IB with the address of the last iteration issued in PMAT; once RAR exists, the corresponding memory load operator will not cause access conflicts.

[0025] By comparing the first N-1 memory load addresses of the iteration in IB with the memory load addresses executed in the pipeline and stored in PMAT, there are (N-1)(N-2) / 2 comparators in between to detect access violations from pipeline execution.

[0026] Access conflicts in ordered storage are detected by comparing the first N-1 memory load addresses of the iterations in IB with the ordered memory storage addresses in PMAT; if an access conflict exists at a load address from an iteration in IB, the problem for that iteration is not considered.

[0027] In addition to access conflict detection, each iteration also sends data to the RAWDM to detect RAW hazards. The RAWDM takes the ready flag and storage address in the ROB's RaFIFO as input and determines whether the current iteration has a RAW hazard that would allow the iteration to proceed.

[0028] Furthermore, in one embodiment of the present invention, the execution of out-of-order iteration based on the dynamically reconfigurable processor includes:

[0029] During the iteration phase, if the space of both the iteration cache and the reorder cache is not full, the iteration is retrieved from the iteration and reordering engine, stored in the iteration cache, and its storage address is recorded in the reorder cache.

[0030] During the launch phase, if a conflict-free iteration exists, it will be selected and launched to the reconfigurable computing engine;

[0031] During the execution phase, the reconfigurable computing engine requires a fixed latency to complete the computation and write the results to the reordering cache;

[0032] During the write-back phase, the reordered cache checks the fetch order and result readiness status, and then writes the results back to the high-speed temporary storage.

[0033] Furthermore, in one embodiment of the present invention, the execution of out-of-order iteration based on the dynamically reconfigurable processor includes:

[0034] At time CS0, iteration 1 is available for emission in the iteration buffer, while iteration 2 is being fetched and iteration 1 is emitted. At time CS1, iteration 2 is available for emission in the iteration buffer, while iteration 3 is being fetched and an empty iteration is emitted. At time CS2, iteration 2 and iteration 3 are available for emission in the iteration buffer, while iteration 4 is being fetched and iteration 2 is emitted. At time CS3, iteration 3 and iteration 4 are available for emission in the iteration buffer, while iteration 5 is being fetched and iteration 4 is emitted. At time CS4, an empty iteration is emitted. In CS5 and CS6, iteration 5 and iteration 3 are emitted respectively.

[0035] To achieve the above objectives, a second aspect of the present invention provides a data processing apparatus based on a randomized iterative reconfigurable processor, comprising the following modules:

[0036] Build modules are used to construct dynamically reconfigurable processors based on out-of-order iterative execution;

[0037] The annotation module is used to annotate the memory access operators L0, L1, and L2 in the application pseudocode; where L0 represents the load operator A[i][j], L1 represents the load operator A[k][i], and L2 represents the load operator A[k][j]; the three operators L0, L1, and L2 are executed serially and are respectively arranged on the memory access units LSU0, LSU1, and LSU2 of the dynamically reconfigurable processor;

[0038] An iteration module is used to perform out-of-order iterations based on the dynamically reconfigurable processor, wherein the out-of-order iterations operate in a pipelined manner and include four stages: fetch iteration, issue, execute, and write back.

[0039] The data processing method based on a reconfigurable processor with out-of-order iteration proposed in this invention is designed for data-intensive applications. It uses out-of-order iterative execution technology to support non-template computation with irregular access, which can solve the problem of memory partitioning for non-template computation from the source, thereby improving the parallel data memory access capability of the reconfigurable processor. Attached Figure Description

[0040] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0041] Figure 1 This is a flowchart illustrating a data processing method based on a randomly iteratively reconfigurable processor, as provided in an embodiment of the present invention.

[0042] Figure 2 A schematic diagram of a dynamically reconfigurable processor for non-template memory access conflicts provided in an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of a dynamic access conflict detection design provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of out-of-order iterative execution provided in an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of the structure of a data processing device based on a randomized iterative reconfigurable processor, provided in an embodiment of the present invention. Detailed Implementation

[0046] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0047] The following describes a data processing method based on a randomly iteratively reconfigurable processor according to an embodiment of the present invention, with reference to the accompanying drawings.

[0048] Figure 1 This is a flowchart illustrating a data processing method based on a randomly iteratively reconfigurable processor, as provided in an embodiment of the present invention.

[0049] like Figure 1 As shown, the data processing method based on a randomized iterative reconfigurable processor includes the following steps:

[0050] S101: Construct a dynamically reconfigurable processor based on out-of-order iterative execution;

[0051] S102: Label the memory access operators L0, L1, and L2 in the application pseudocode; where L0 represents the load operator A[i][j], L1 represents the load operator A[k][i], and L2 represents the load operator A[k][j]; the three operators L0, L1, and L2 are executed serially and are respectively arranged on the memory access units LSU0, LSU1, and LSU2 of the dynamically reconfigurable processor;

[0052] S103: Execute out-of-order iteration based on the dynamically reconfigurable processor, wherein the out-of-order iteration operates in a pipeline manner and includes four stages: fetch iteration, issue, execute, and write back.

[0053] like Figure 2 The diagram shown is a schematic of a dynamically reconfigurable processor for non-template memory access conflicts provided in an embodiment of the present invention.

[0054] Furthermore, in one embodiment of the present invention, the construction of a dynamically reconfigurable processor based on out-of-order iterative execution includes:

[0055] An iterative generation engine (IGE), an iterative reordering engine (IRE), and a reconfigurable computation engine (RCE) are constructed; among them...

[0056] The iterative generation engine consists of an iterative variable generator (IVG) and N address generators (AG), where N represents the maximum number of simultaneous memory access operators supported. By configuring the step size, initial value, and end value of the accumulator, the address generator can generate addresses for various memory access operators.

[0057] The iterative reordering engine includes an iterative cache IB, a planned memory access table PMAT, an iterative selection unit ISU, and a reordering cache ROB.

[0058] The reconfigurable computing engine includes multiple sets of high-speed temporary storage (SPM) and a PE array with mesh interconnection.

[0059] The left-hand PEs can read data from each block in the SPM using the load register (LR) and read crossbar switch. These PEs can also write data to each block in the SPM using the storage register (SR), ROB, and write crossbar switch.

[0060] like Figure 3 The diagram shown is a schematic diagram of a dynamic access conflict detection design provided by an embodiment of the present invention.

[0061] Furthermore, in one embodiment of the present invention, the method further includes eliminating read-after-write (WAR) and write-after-write (WAW) hazards generated by out-of-order iterative execution by reordering the cached ROB, and dynamically detecting access conflicts and write-after-read (RAW) hazards by using an iterative selection unit (ISU).

[0062] The ROB includes a randomly accessible FIFO of depth M, a demultiplexer, an M×N-1 crossbar switch, and N-1 RAW reuse buffers, where M and N represent the IB size and the maximum number of memory references supported. Each element of the randomly accessible FIFO includes three segments: storage address S, result ready flag R, and result data D.

[0063] The ISU contains M access conflict detection modules (ACDM), M RAW detection modules (RAMDM), and N buffer queues.

[0064] Furthermore, in one embodiment of the present invention, the step of eliminating read-after-write WAR and write-after-write WAW hazards generated by out-of-order iterative execution by reordering the cached ROB includes:

[0065] During iteration, if RaFIFO is not full, the iteration is obtained from IRG to IB; at the same time, a new element containing the iteration storage address is sent to RaFIFO, where the ready flag is set to false.

[0066] Once RCE completes its iteration, it writes the data back to the corresponding element's data segment in ROB via random access and sets the ready flag to true. If the ready flag of the element preceding RaFIFO is true, the corresponding data will be written back to the SPM's storage block.

[0067] Because ROBs (Resource Blocks) have the characteristics of iterative sequential reads and iterative sequential writes to memory blocks, WAW (Wasteful Explosions) and WAR (Warning Explosions) can be resolved naturally. Furthermore, ROBs facilitate the reuse of RAW data. When a result is written back to the ROB, if the issued iteration has a RAW dependency on that result, the result will be sent to the reuse buffer via a crossbar switch for RAW data reuse. Therefore, the issued iteration does not need to wait for the dependent data to be written back to the SPM (Site Module Buffer).

[0068] Furthermore, in one embodiment of the present invention, the step of dynamically detecting access conflicts and read-after-write RAW hazards through the Iterative Selection Unit (ISU) includes:

[0069] In ACDM, read-after-read RAR data reuse is detected by comparing the addresses of all memory load operators iterated in IB with the address of the last iteration issued in PMAT; once RAR exists, the corresponding memory load operator will not cause access conflicts.

[0070] By comparing the first N-1 memory load addresses of the iteration in IB with the memory load addresses executed in the pipeline and stored in PMAT, there are (N-1)(N-2) / 2 comparators in between to detect access violations from pipeline execution.

[0071] Access conflicts in ordered storage are detected by comparing the first N-1 memory load addresses of the iterations in IB with the ordered memory storage addresses in PMAT; if an access conflict exists at a load address from an iteration in IB, the problem for that iteration is not considered.

[0072] In addition to access conflict detection, each iteration also sends data to the RAWDM to detect RAW hazards. The RAWDM takes the ready flag and storage address in the ROB's RaFIFO as input and determines whether the current iteration has a RAW hazard that would allow the iteration to proceed.

[0073] Because RaFIFO operates in iteration order, if the current iteration has a RAW dependency, its memory address is recorded earlier in RaFIFO, and its ready flag is false, it indicates a RAW hazard exists. An iteration with neither access conflicts nor RAW hazards (see the AND gate in the diagram) becomes one of the candidates for emission. If at least one emission candidate is found (see the output OR gate), ISU selects a candidate iteration and emits it to RCE for execution. Otherwise, an empty iteration with a specific address is emitted. Since memory access operators in the selected iteration are scheduled sequentially, the corresponding access addresses should be sent to N buffer queues for data synchronization.

[0074] Furthermore, in one embodiment of the present invention, the execution of out-of-order iteration based on the dynamically reconfigurable processor includes:

[0075] During the iteration phase, if the space of both the iteration cache and the reorder cache is not full, the iteration is retrieved from the iteration and reordering engine, stored in the iteration cache, and its storage address is recorded in the reorder cache.

[0076] During the launch phase, if a conflict-free iteration exists, it will be selected and launched to the reconfigurable computing engine;

[0077] During the execution phase, the reconfigurable computing engine requires a fixed latency to complete the computation and write the results to the reordering cache;

[0078] During the write-back phase, the reordered cache checks the fetch order and result readiness status, and then writes the results back to the high-speed temporary storage.

[0079] From the pipeline control, it can be seen that the performance improvement of out-of-order iterative CGRA actually benefits from out-of-order iterative issuance. After the issuance iteration, it will execute within a fixed latency because the IRE eliminates its memory load conflicts.

[0080] like Figure 4 The diagram shown illustrates out-of-order iterative execution according to an embodiment of the present invention. Since memory access operators are a performance bottleneck in non-template computation applications, this invention primarily focuses on memory access operators within the program.

[0081] Furthermore, in one embodiment of the present invention, the execution of out-of-order iteration based on the dynamically reconfigurable processor includes:

[0082] At time CS0, iteration 1 is available for emission in the iteration buffer, while iteration 2 is being fetched and iteration 1 is emitted. At time CS1, iteration 2 is available for emission in the iteration buffer, while iteration 3 is being fetched and an empty iteration is emitted. At time CS2, iteration 2 and iteration 3 are available for emission in the iteration buffer, while iteration 4 is being fetched and iteration 2 is emitted. At time CS3, iteration 3 and iteration 4 are available for emission in the iteration buffer, while iteration 5 is being fetched and iteration 4 is emitted. At time CS4, an empty iteration is emitted. In CS5 and CS6, iteration 5 and iteration 3 are emitted respectively.

[0083] This completes the execution of a full loop code example.

[0084] Because the above operations are executed in a pipelined manner, there are only two cycles (CS1 and CS4) where conflicts occur. Therefore, out-of-order iterative execution only requires 9 cycles to complete 5 iterations, while traditional CGRA requires 15 cycles to avoid conflicts. Thus, out-of-order iterative CGRA helps improve the performance of non-template kernels.

[0085] The data processing method based on a reconfigurable processor with out-of-order iteration proposed in this invention is designed for data-intensive applications. It uses out-of-order iterative execution technology to support non-template computation with irregular access, which can solve the problem of memory partitioning for non-template computation from the source, thereby improving the parallel data memory access capability of the reconfigurable processor.

[0086] To implement the above embodiments, the present invention also proposes a data processing device based on a randomized iterative reconfigurable processor.

[0087] Figure 5 This is a schematic diagram of the structure of a data processing device based on a randomized iterative reconfigurable processor, provided in an embodiment of the present invention.

[0088] like Figure 5 As shown, the data processing device based on a randomized iterative reconfigurable processor includes: a construction module 100, a labeling module 200, and an iteration module 300, wherein...

[0089] Build modules are used to construct dynamically reconfigurable processors based on out-of-order iterative execution;

[0090] The annotation module is used to annotate the memory access operators L0, L1, and L2 in the application pseudocode; where L0 represents the load operator A[i][j], L1 represents the load operator A[k][i], and L2 represents the load operator A[k][j]; the three operators L0, L1, and L2 are executed serially and are respectively arranged on the memory access units LSU0, LSU1, and LSU2 of the dynamically reconfigurable processor;

[0091] An iteration module is used to perform out-of-order iterations based on the dynamically reconfigurable processor, wherein the out-of-order iterations operate in a pipelined manner and include four stages: fetch iteration, issue, execute, and write back.

[0092] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0093] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0094] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A data processing method based on a chaotic iterative sequence reconfigurable processor, characterized in that, Includes the following steps: Construct a dynamically reconfigurable processor based on out-of-order iterative execution; The memory access operators L0, L1, and L2 in the application pseudocode are labeled; where L0 represents the load operator A[i][j], L1 represents the load operator A[k][i], and L2 represents the load operator A[k][j]. The three operators L0, L1, and L2 are executed serially and are respectively located on the memory access units LSU0, LSU1, and LSU2 of the dynamically reconfigurable processor. The out-of-order iteration is performed based on the dynamically reconfigurable processor, wherein the out-of-order iteration operates in a pipelined manner and includes four stages: fetch iteration, issue, execute, and write back; The construction of a dynamically reconfigurable processor based on out-of-order iterative execution includes: An iterative generation engine, an iterative reordering engine, and a reconfigurable computing engine are constructed. The iterative generation engine consists of an iterative variable generator and N address generators, where N represents the maximum number of simultaneous memory access operators supported. By configuring the accumulator's step size, initial value, and end value, the address generators can generate addresses for various memory access operators. The iterative reordering engine includes an iterative cache, a planned memory access table, an iterative selection unit, and a reordering cache. The reconfigurable computing engine includes multiple sets of high-speed temporary storage memories and a PE array with mesh interconnection. Reordering the cached ROBs eliminates read-after-write (WAR) and write-after-write (WAW) hazards caused by out-of-order iterative execution. Iterative selection of ISU units dynamically detects access conflicts and write-after-read (RAW) hazards. The ROB includes a random-accessable FIFO with a depth of a demultiplexer, a crossbar and RAW reuse buffers, wherein and denote the IB size and the maximum number of memory references supported, each element of the random-accessable FIFO includes three segments: a store address S, a result ready flag R and a result data D; the ISU contains M access conflict detection modules ACDM, M RAW detection modules RAMDM and N buffer queues; The method of dynamically detecting access conflicts and read-after-write RAW hazards through iterative selection unit (ISU) includes: In ACDM, read-after-read RAR data reuse is detected by comparing the addresses of all memory load operators iterated in IB with the address of the last iteration issued in PMAT; once RAR exists, the corresponding memory load operator will not cause access conflicts. By comparing the first N-1 memory load addresses iterated in the IB with the memory load addresses executed in the pipeline saved by the PMAT, there are (N 1) (N 2) / 2 comparators for detecting access conflicts from the pipeline execution; Access conflicts in ordered storage are detected by comparing the first N-1 memory load addresses of the iterations in IB with the ordered memory storage addresses in PMAT; if an access conflict exists at a load address from an iteration in IB, the problem for that iteration is not considered. In addition to access conflict detection, each iteration also sends data to the RAWDM to detect RAW hazards. The RAWDM takes the ready flag and storage address in the ROB's RaFIFO as input and determines whether the current iteration has a RAW hazard that would allow the iteration to proceed.

2. The method of claim 1, wherein, The method of eliminating read-after-write WAR and write-after-write WAW hazards caused by out-of-order iterative execution by reordering cached ROBs includes: During iteration, if RaFIFO is not full, the iteration is obtained from IRG to IB; at the same time, a new element containing the iteration storage address is sent to RaFIFO, where the ready flag is set to false. Once RCE completes its iteration, it writes the data back to the corresponding element's data segment in ROB via random access and sets the ready flag to true. If the ready flag of the element preceding RaFIFO is true, the corresponding data will be written back to the SPM's storage block.

3. The method according to claim 1, characterized in that, The method of dynamically detecting access conflicts and read-after-write RAW hazards through iterative selection unit (ISU) includes: In ACDM, read-after-read RAR data reuse is detected by comparing the addresses of all memory load operators iterated in IB with the address of the last iteration issued in PMAT; once RAR exists, the corresponding memory load operator will not cause access conflicts. By comparing the first N-1 memory load addresses of the iterations in IB with the memory load addresses executed in the pipeline stored in PMAT, the intermediate (N) 1)(N 2) Two comparators are used to detect access violations from pipeline execution; Access conflicts in ordered storage are detected by comparing the first N-1 memory load addresses of the iterations in IB with the ordered memory storage addresses in PMAT; if an access conflict exists at a load address from an iteration in IB, the problem for that iteration is not considered. In addition to access conflict detection, each iteration also sends data to the RAWDM to detect RAW hazards. The RAWDM takes the ready flag and storage address in the ROB's RaFIFO as input and determines whether the current iteration has a RAW hazard that would allow the iteration to proceed.

4. The method according to claim 1, characterized in that, The execution of out-of-order iteration based on the dynamically reconfigurable processor includes: At time CS0, iteration 1 is available for emission in the iteration buffer, while iteration 2 is being fetched and iteration 1 is emitted. At time CS1, iteration 2 is available for emission in the iteration buffer, while iteration 3 is being fetched and an empty iteration is emitted. At time CS2, iteration 2 and iteration 3 are available for emission in the iteration buffer, while iteration 4 is being fetched and iteration 2 is emitted. At time CS3, iteration 3 and iteration 4 are available for emission in the iteration buffer, while iteration 5 is being fetched and iteration 4 is emitted. At time CS4, an empty iteration is emitted. In CS5 and CS6, iteration 5 and iteration 3 are emitted respectively.

5. A data processing device based on a randomized iterative reconfigurable processor, characterized in that, Includes the following modules: Build modules are used to construct dynamically reconfigurable processors based on out-of-order iterative execution; The annotation module is used to annotate the memory access operators L0, L1, and L2 in the application pseudocode; where L0 represents the load operator A[i][j], L1 represents the load operator A[k][i], and L2 represents the load operator A[k][j]; the three operators L0, L1, and L2 are executed serially and are respectively arranged on the memory access units LSU0, LSU1, and LSU2 of the dynamically reconfigurable processor; An iteration module is used to perform out-of-order iteration based on the dynamically reconfigurable processor, wherein the out-of-order iteration operates in a pipelined manner and includes four stages: fetch iteration, issue, execute, and write back; The construction of a dynamically reconfigurable processor based on out-of-order iterative execution includes: An iterative generation engine, an iterative reordering engine, and a reconfigurable computing engine are constructed. The iterative generation engine consists of an iterative variable generator and N address generators, where N represents the maximum number of simultaneous memory access operators supported. By configuring the accumulator's step size, initial value, and end value, the address generators can generate addresses for various memory access operators. The iterative reordering engine includes an iterative cache, a planned memory access table, an iterative selection unit, and a reordering cache. The reconfigurable computing engine includes multiple sets of high-speed temporary storage memories and a PE array with mesh interconnection. Reordering the cached ROBs eliminates read-after-write (WAR) and write-after-write (WAW) hazards caused by out-of-order iterative execution. Iterative selection of ISU units dynamically detects access conflicts and write-after-read (RAW) hazards. The ROB includes a depth of Random access FIFO, demultiplexer, cross switches and One RAW reuse buffer, of which and The IB size and the maximum number of memory references supported are indicated. Each element of the randomly accessible FIFO includes three segments: storage address S, result ready flag R, and result data D. The ISU contains M access conflict detection modules ACDM, M RAW detection modules RAMDM, and N buffer queues. The method of dynamically detecting access conflicts and read-after-write RAW hazards through iterative selection unit (ISU) includes: In ACDM, read-after-read RAR data reuse is detected by comparing the addresses of all memory load operators iterated in IB with the address of the last iteration issued in PMAT; once RAR exists, the corresponding memory load operator will not cause access conflicts. By comparing the first N-1 memory load addresses of the iterations in IB with the memory load addresses executed in the pipeline stored in PMAT, the intermediate (N) 1)(N 2) Two comparators are used to detect access violations from pipeline execution; Access conflicts in ordered storage are detected by comparing the first N-1 memory load addresses of the iterations in IB with the ordered memory storage addresses in PMAT; if an access conflict exists at a load address from an iteration in IB, the problem for that iteration is not considered. In addition to access conflict detection, each iteration also sends data to the RAWDM to detect RAW hazards. The RAWDM takes the ready flag and storage address in the ROB's RaFIFO as input and determines whether the current iteration has a RAW hazard that would allow the iteration to proceed.

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