Multivalued transistor and multivalued logic circuit
By introducing an electronic filtering structure and filtering band gap into the transistor, the problem that a single transistor can only express two states is solved, realizing the circuit design of multiple states, reducing power consumption and simplifying the circuit structure.
Patent Information
- Application Number
- CN202311627591.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-30
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2043-11-30
AI Technical Summary
In existing technologies, a single transistor can only represent two states, resulting in complex circuit design, high power consumption and interconnection delay, making it difficult to implement multi-valued logic systems.
By introducing an electron filtering structure into the transistor and setting at least one filtering band gap, the electron flow is filtered within the potential barrier variation range of the channel layer using the filtering band gap, forming a current plateau and realizing a multi-valued state.
It achieves multiple states without extending the transistor voltage range, reduces power consumption, is suitable for low-voltage operating environments, and simplifies circuit design.
Smart Images
Figure CN117855274B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of multi-valued transistor technology, and more particularly to multi-valued transistors and multi-valued logic circuits. Background Technology
[0002] The miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs) under Moore's Law has enabled the continuous development of information technology over the past few decades. By reducing the channel length of transistors, switching speeds have become faster, transistor density has become higher, and circuits have become more powerful and efficient.
[0003] However, there are physical limits to transistor miniaturization, necessitating new solutions to further improve computer performance. The traditional von Neumann architecture is based on binary logic systems, while multi-valued systems offer higher information density, fewer operations, and reduced system complexity. Ternary logic, as a typical multi-valued logic system, is the most promising approach due to its simplicity, efficiency, and similarity to current binary logic. As early as the 1970s, attempts were made to implement ternary logic using binary field-effect transistors (FETs), but because a single FET can only represent two values (only on and off states), the circuit design became complex, inevitably leading to high power consumption and interconnect delays.
[0004] Constructing a ternary logic system, where a single transistor can implement multiple values, such as three values (three states), is necessary to simplify the system. Summary of the Invention
[0005] This invention provides a multi-valued transistor and a multi-valued logic circuit to solve the problem in the prior art that a single transistor needs to have multiple states to achieve multiple values.
[0006] This invention provides a multi-valued transistor, characterized in that it comprises: a channel layer and a gate, a source, and a drain disposed on the channel layer; an electron filtering structure having at least one filtering band gap, the electron filtering structure being connected to the source to filter electrons flowing to the source within the range of the filtering band gap, or the electron filtering structure being connected to the drain to filter electrons flowing to the drain within the range of the filtering band gap; at least one of the filtering band gaps being located within the potential barrier variation range of the channel layer, so that when the bottom energy level of the barrier conduction band of the channel layer falls within the range of the filtering band gap, the current of the channel layer remains unchanged, forming a current plateau; wherein, the potential barrier variation range of the channel layer characterizes the variation range of the bottom energy level of the barrier conduction band of the channel layer with the applied voltage of the gate.
[0007] According to the multi-value transistor provided by the present invention, the electron filtering structure comprises at least one material selected from carbon nanoribbons, carbon nanotubes, black phosphorus, titanium chloride, and indium arsenide.
[0008] According to the multi-value transistor provided by the present invention, the electronic filtering structure has at least two of the filtering band gaps, and the bottom energy level of the barrier conduction band of the channel layer is located within one of the filtering band gaps when no voltage is applied to the gate.
[0009] The present invention also provides a method for constructing a multi-valued transistor, the multi-valued transistor comprising: obtaining the barrier variation range of the channel layer and target multi-valued platform information, wherein the target multi-valued platform information characterizes the target voltage value and duration range corresponding to the required multi-valued state; and adjusting the doping type and doping concentration of the electronic filter structure according to the barrier variation range and the target multi-valued platform information, so as to adjust the filtering bandgap range of the electronic filter structure.
[0010] The present invention also provides a multi-valued logic circuit, including at least one of the multi-valued transistors described above.
[0011] The present invention also provides a ternary inverter, comprising: a P-type ternary transistor, including a first channel layer and a first gate, a first source, a first drain, and a first electron filter structure disposed on the first channel layer, wherein the first electron filter structure is connected to the first drain and has a first filtering band gap located within the potential barrier variation range of the first channel layer; and an N-type ternary transistor, including a second channel layer and a second gate, a second source, a second drain, and a second electron filter structure disposed on the second channel layer, wherein the second electron filter structure is connected to the second source and has a second filtering band gap located within the potential barrier variation range of the second channel layer; wherein the first gate and the second gate are connected as an inverting input terminal, and the first drain and the second drain are connected as an inverting output terminal.
[0012] According to the ternary inverter provided by the present invention, the potential barrier variation range of the first channel layer is the same as that of the second channel layer; the first filtering band gap is located in the middle of the potential barrier variation range of the first channel layer, and the range of the first filtering band gap is the same as that of the second filtering band gap; or, the first filtering band gap is located in the middle of the potential barrier variation range of the first channel layer, and the upper energy level of the first filtering band gap is the same as the lower energy level of the second filtering band gap; or, the second filtering band gap is located in the middle of the potential barrier variation range of the second channel layer, and the upper energy level of the first filtering band gap is the same as the lower energy level of the second filtering band gap.
[0013] The present invention also provides a ternary NAND gate, comprising: a first P-type ternary transistor, including a third channel layer and a third gate, a third source, a third drain, and a third electron filter structure disposed on the third channel layer, the third electron filter structure being connected to the third drain, the third electron filter structure having a third filtering band gap located within the potential barrier variation range of the third channel layer; a second P-type ternary transistor, including a fourth channel layer and a fourth gate, a fourth source, a fourth drain, and a fourth electron filter structure disposed on the fourth channel layer, the fourth electron filter structure being connected to the fourth drain, the fourth electron filter structure having a fourth filtering band gap located within the potential barrier variation range of the fourth channel layer; the range of the third filtering band gap being the same as the range of the fourth filtering band gap; the third gate serving as the input terminal of a first NAND gate, the fourth gate serving as the input terminal of a second NAND gate, the third source being connected to the fourth source and used for connection to a power supply terminal, and the third drain being connected to the fourth drain serving as the output terminal of a NAND gate and used for grounding through a resistor.
[0014] The present invention also provides a ternary NOR gate, comprising: a first N-type ternary transistor, including a fifth channel layer and a fifth gate, a fifth source, a fifth drain, and a fifth electron filter structure disposed on the fifth channel layer, the fifth electron filter structure being connected to the fifth source, the fifth electron filter structure having a fifth filtering band gap located within the potential barrier variation range of the fifth channel layer; a second N-type ternary transistor, including a sixth channel layer and a sixth gate, a sixth source, a sixth drain, and a sixth electron filter structure disposed on the sixth channel layer, the sixth electron filter structure being connected to the sixth source, the sixth electron filter structure having a sixth filtering band gap located within the potential barrier variation range of the sixth channel layer; the range of the fifth filtering band gap being the same as the range of the sixth filtering band gap; the fifth gate serving as the input terminal of a first NOR gate, the sixth gate serving as the input terminal of a second NOR gate, the fifth drain being connected to the sixth drain serving as the output terminal of the NOR gate and used for connection to a power supply terminal through a resistor, and the fifth source being connected to the sixth source and grounded.
[0015] The present invention also provides a ternary decoder, comprising three ternary inverters as described above: a first ternary inverter, a second ternary inverter, and a third ternary inverter. It also includes a ternary NOR gate as described above. The input terminals of the first ternary inverter and the second ternary inverter are connected as decoding input terminals. The output terminals of the second ternary inverter and the third ternary inverter are connected as input terminals of the ternary NOR gate. The output terminal of the first ternary inverter serves as the first decoding output terminal. The output of the ternary NOR gate serves as the second decoding output, and the output of the third ternary inverter serves as the third decoding output. Specifically, for the first and third ternary inverters, the first filtering bandgap is located in the middle of the potential barrier variation range of the first channel layer, and the upper energy level of the first filtering bandgap is the same as the lower energy level of the second filtering bandgap. For the second ternary inverter, the second filtering bandgap is located in the middle of the potential barrier variation range of the second channel layer, and the upper energy level of the first filtering bandgap is the same as the lower energy level of the second filtering bandgap.
[0016] The multi-valued transistor and multi-valued logic circuit provided by this invention have at least the following beneficial effects: By providing an electron filtering structure connected to the source or drain, the electron filtering structure has at least one filtering band gap within the potential barrier variation range of the channel layer. When electrons flow to the source or drain through the electron filtering structure, since there is no corresponding energy level within the range of the filtering band gap, electrons cannot exist within the range of the filtering band gap, thus achieving the filtering of electrons flowing to the source or drain within the range of the filtering band gap. When a voltage is applied to the gate, as the gate voltage increases, the barrier of the channel layer decreases, allowing electrons with energy levels higher than the bottom of the conduction band to pass through, forming a current. When the bottom of the conduction band decreases and falls into the range of the filtering band gap, the electron flow rate through the barrier remains unchanged, i.e., the current in the channel layer remains unchanged, because the filtering band gap filters electrons within that range (i.e., there are no electrons in that range). This continues until, as the gate voltage increases, the bottom of the conduction band decreases to a level lower than the lower energy level of the filtering band gap, meaning it escapes the range of the filtering band gap. Electrons below the lower energy level of the filtering band gap are not filtered, allowing the current in the channel layer to continue increasing. Thus, by incorporating an electron filtering structure and utilizing the filtering band gap to filter electrons flowing into the channel layer, the current change curve of the channel layer exhibits a current plateau, forming an intermediate state, as the gate voltage increases. Within the range of the filtering bandgap, even if the gate voltage increases, the current in the channel layer remains unchanged, forming a current plateau, i.e. a stable intermediate state as the third state, thus achieving the effect of a ternary transistor. Similarly, when the electronic filtering structure has two or more filtering bandgap locations within the range of potential barrier changes, the corresponding multi-valued transistor effect can be achieved. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the structure of one embodiment of the multi-valued transistor provided by the present invention;
[0019] Figure 2 This is a transfer characteristic curve of one embodiment of the multi-valued transistor provided by the present invention;
[0020] Figure 3 This is one of the schematic diagrams illustrating the barrier change process of one embodiment of the multi-valued transistor provided by the present invention;
[0021] Figure 4 This is the second schematic diagram of the barrier change process in one embodiment of the multi-valued transistor provided by the present invention;
[0022] Figure 5 This is the third schematic diagram of the barrier change process in one embodiment of the multi-valued transistor provided by the present invention;
[0023] Figure 6 This is the fourth schematic diagram of the barrier change process in one embodiment of the multi-valued transistor provided by the present invention;
[0024] Figure 7 This is a circuit diagram of one embodiment of the ternary inverter provided by the present invention;
[0025] Figure 8 This is the truth table of STI, NTI, and PTI in the ternary inverter provided by the present invention;
[0026] Figure 9 This is a graph showing the transfer characteristics of STI, NTI, and PTI in the ternary inverter provided by this invention.
[0027] Figure 10 This is a schematic diagram illustrating the formation of the NTI transfer characteristic curve in the ternary inverter provided by the present invention;
[0028] Figure 11 This is a schematic diagram illustrating the formation of the PTI transfer characteristic curve in the ternary inverter provided by the present invention;
[0029] Figure 12 This is a circuit diagram of one embodiment of the ternary NAND gate provided by the present invention;
[0030] Figure 13 This is the truth table of the ternary NAND gate provided by the present invention;
[0031] Figure 14 This is a circuit diagram of one embodiment of the ternary NOR gate provided by the present invention.
[0032] Figure 15 This is the truth table of the ternary NOR gate provided by the present invention;
[0033] Figure 16 This is a circuit diagram of one embodiment of the ternary decoder provided by the present invention;
[0034] Figure 17 This is a circuit diagram of one embodiment of the ternary half-adder provided by the present invention;
[0035] Figure 18 This is a circuit diagram of one embodiment of the ternary full adder provided by the present invention. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0037] According to band gap theory, electronic energy levels in a solid can be divided into a conduction band and a valence band. A band gap is formed between the bottom energy level of the conduction band and the top energy level of the valence band. Since there are no electronic energy levels in the band gap, the corresponding energy level range has no electrons. This invention relates to the case of multiple band gaps. For ease of description, for a single band gap, the bottom energy level of the conduction band is called the upper energy level, and the top energy level of the valence band is called the lower energy level.
[0038] The following is combined Figures 1-6 The multi-valued transistor of the present invention includes:
[0039] The channel layer and the gate, source and drain disposed on the channel layer;
[0040] An electron filtering structure having at least one filtering band gap, the electron filtering structure being connected to the source electrode to filter electrons flowing towards the source electrode within the filtering band gap, or the electron filtering structure being connected to the drain electrode to filter electrons flowing towards the drain electrode within the filtering band gap. c electrons;
[0041] At least one of the filtering band gaps is located within the potential barrier variation range of the channel layer, so that when the energy level at the bottom of the potential barrier conduction band of the channel layer falls into the range of the filtering band gap, the current of the channel layer remains unchanged, forming a current plateau.
[0042] The potential barrier variation range of the channel layer characterizes the variation range of the bottom energy level of the channel layer's potential conduction band as the gate voltage is applied.
[0043] By incorporating an electron filtering structure connected to the source or drain, the electron filtering structure has at least one filtering band gap within the potential barrier variation range of the channel layer. When electrons flow to the source or drain through the electron filtering structure, since there is no corresponding energy level within the filtering band gap, the electrons cannot exist within the filtering band gap range, thus achieving the filtering of electrons flowing to the source or drain within the filtering band gap range. When a voltage is applied to the gate, as the gate voltage increases, the barrier of the channel layer decreases, allowing electrons with energy levels higher than the bottom of the conduction band to pass through, forming a current. When the bottom of the conduction band decreases and falls into the range of the filtering band gap, the electron flow rate through the barrier remains unchanged because the filtering band gap filters electrons within the corresponding range, meaning there are no electrons in that range. Thus, even if the bottom of the conduction band continues to decrease, the current in the channel layer remains unchanged, forming a current. This continues until, as the gate voltage increases, the bottom of the conduction band decreases to a level lower than the lower energy level of the filtering band gap, meaning it escapes from the range of the filtering band gap. Electrons below the lower energy level of the filtering band gap are not filtered, allowing the current in the channel layer to continue to increase.
[0044] Therefore, by incorporating an electron filtering structure, electrons flowing to the channel layer are filtered through the filtering band gap. This causes a current plateau to appear in the channel layer current change curve as the gate voltage increases, forming an intermediate state. Within the range of the filtering band gap, even if the gate voltage increases, the current in the channel layer remains constant, forming a current plateau, i.e., a stable intermediate state, which serves as the third state, achieving the effect of a ternary transistor. Similarly, when the electron filtering structure has two or more filtering band gaps located within the potential barrier change range, the corresponding multi-valued transistor effect can be achieved.
[0045] To make it more intuitive, let's take the three-valued case as an example, refer to... Figure 2 and Figure 3 When no voltage is applied to the gate, the corresponding Figure 2 At point V0, the upper energy level Eco of the filtering band gap Egap is lower than the bottom energy level Etop of the conduction band barrier of the channel layer. (Reference) Figure 4 When a first threshold voltage is applied to the gate, the corresponding Figure 2 At point V1, the upper energy level Eco of the filtering band gap Egap is equal to the bottom energy level Etop of the conduction band barrier of the channel layer. (Reference) Figure 5When a voltage greater than the first threshold and less than the second threshold is applied to the gate, the corresponding Figure 2 In the range of V1 to V3, the upper energy level Eco of the filtering band gap Egap is greater than the bottom energy level Etop of the channel layer's conduction band barrier, while the lower energy level Evo of the filtering band gap Egap is less than the bottom energy level Etop of the channel layer's conduction band barrier. That is, the bottom energy level Etop of the conduction band barrier is located within the range of the filtering band gap Egap. At this point, due to the filtering effect of the filtering band gap Egap, the change in the channel layer's barrier does not affect the electron flux, resulting in a constant current in the channel layer, forming a current plateau in the range of V1 to V3. (Reference) Figure 6 When a voltage greater than the second threshold is applied to the gate, the corresponding Figure 2 After point V3, the lower energy level Evo of the filtering band gap Egap is greater than the bottom energy level Etop of the channel layer's conduction band barrier. This means that the bottom energy level Etop of the channel layer's conduction band barrier exits the filtering band gap Egap. As the gate voltage increases, the bottom energy level Etop of the channel layer's conduction band barrier further decreases, and the current in the channel layer also increases accordingly. When the gate voltage is greater than or equal to the third threshold voltage, the corresponding... Figure 2 After point V4, the corresponding transistor is in saturation conduction state.
[0046] It is understandable that the current of the current plateau remains constant, and fluctuations within the error range can be considered constant. In the actual environment, there is no absolute constant. The lower energy level of the filter band gap is greater than the bottom energy level of the conduction band of the source and drain electrodes connected to the electronic filter structure.
[0047] In the multi-valued case, there are two or more filtering band gaps within the potential barrier variation range of the channel layer. The working principle is the same as in the three-valued case described above. Each filtering band gap forms a current plateau, achieving the multi-valued effect. Specifically, two filtering band gaps within the potential barrier variation range of the channel layer correspond to the four-valued function; three filtering band gaps correspond to the five-valued function, and so on.
[0048] By adding a suitable filtering bandgap through an electronic filtering structure, a current plateau corresponding to the filtering bandgap appears as the channel layer current changes with the gate voltage. The position (energy level size) of the filtering bandgap affects the gate voltage corresponding to the appearance of the current plateau, while the width of the filtering bandgap affects the duration of the current plateau, i.e., the range of gate voltage changes when the current remains constant. By adjusting the type and concentration of doping materials in the electronic filtering structure, the position and width of the filtering bandgap, i.e., the range of the filtering bandgap, can be adjusted, thereby regulating the gate voltage corresponding to the appearance and termination of the current plateau, thus meeting the transistor performance design requirements.
[0049] It should be noted that the multi-value transistor provided by this invention achieves a multi-value effect by filtering the band gap through an electronic filtering structure and adding an intermediate state between the on and off states. Compared to multi-value implementations that create a third state by increasing the voltage above the on state, the newly added current plateau, i.e., the intermediate state, lies between the original on and off voltages of the transistor. This eliminates the need to expand the transistor's voltage range, making it suitable for low-voltage environments, such as operating voltage environments from 0.6V to 1.2V, and also offering the significant advantage of low power consumption.
[0050] Whether the electron filter structure is connected to the source or drain of the transistor depends on the type of doping. In the case of an N-type transistor, the current flows from the drain to the source. Since the electron flow is opposite to the current, that is, electrons flow in from the source, the electron filter structure is connected to the source of an N-type transistor to achieve the function of electron filtering. Similarly, in the case of a P-type transistor, electrons flow in from the drain, and the electron filter structure is connected to the drain of a P-type transistor.
[0051] In some embodiments of the multivalued transistor of the present invention, the electron filtering structure comprises at least one material selected from carbon nanoribbons, carbon nanotubes, black phosphorus, titanium chloride, and indium arsenide.
[0052] Semiconductor materials used to fabricate electron filter structures can include one-dimensional (linear), two-dimensional (planar), and three-dimensional (bulk) materials such as carbon nanoribbons, carbon nanotubes, black phosphorus, titanium chloride, and indium arsenide. Using carbon nanoribbons, carbon nanotubes, black phosphorus, titanium chloride, and indium arsenide facilitates doping to form a suitable filter band gap.
[0053] It should be noted that since multi-valued transistors achieve multi-valued functions by relying on the band gap of the electron filtering structure, which is not closely related to the shape of the electron filtering structure, they can be compatible with one-dimensional, two-dimensional, and three-dimensional materials without limitations, thus expanding the range of material choices. Compared to schemes that can only achieve multi-valued functions using two-dimensional materials, this approach offers the advantages of flexible and wide-ranging material selection.
[0054] In some embodiments of the multi-valued transistor of the present invention, the electron filtering structure has at least two of the filtering band gaps, wherein the bottom energy level of the barrier conduction band of the channel layer is located within one of the filtering band gaps when no voltage is applied to the gate.
[0055] When no voltage is applied to the gate, the bottom energy level of the conduction band barrier in the channel layer is at its highest point and lies within the filtering band gap A. At this time, the transistor is in an off state. The filtering effect of band gap A reduces the number of high-energy electrons above the barrier passing through the channel layer, which helps reduce leakage current when the transistor is off, reduces power consumption and heat generation at low voltages, and improves transistor performance. Simultaneously, when a voltage is applied to the gate, causing the bottom energy level of the conduction band barrier to decrease and move out of band gap A, the current in the channel layer changes significantly. Within the subthreshold (transistor off-state) voltage range, the gate voltage change required for a tenfold current change is smaller, meaning the subthreshold swing is smaller. This helps improve the transistor's low-voltage sensitivity and reduce low-voltage power consumption. After the bottom energy level of the conduction band barrier in the channel layer moves out of band gap A, it enters band gap B, forming a corresponding level plateau, achieving a multi-valued effect.
[0056] The present invention also provides a method for constructing a multi-valued transistor, applicable to the above-mentioned multi-valued transistor, comprising:
[0057] Obtain the potential barrier variation range and target multi-value plateau information of the channel layer. The target multi-value plateau information represents the target voltage value and duration range corresponding to the required multi-value state.
[0058] Based on the potential barrier variation range and the target multi-value platform information, the doping type and doping concentration of the electronic filter structure are adjusted to adjust the filtering band gap range of the electronic filter structure.
[0059] By obtaining the potential barrier variation range of the channel layer, the size and width of the bottom energy level of the conduction band of the barrier changing with the gate voltage are determined, facilitating the subsequent generation of the corresponding filtering bandgap. Based on the target multi-valued plateau information, which may include the gate voltage triggered and terminated by the current plateau, the doping type and concentration of the electronic filtering structure are adjusted to generate a filtering bandgap within the potential barrier variation range. Furthermore, the size and width of the filtering bandgap's energy level meet the requirements. The upper energy level of the filtering bandgap corresponds to the trigger voltage of the current plateau, and the lower energy level corresponds to the termination voltage of the current plateau. Thus, by adjusting the doping type and concentration of the electronic filtering structure, the trigger voltage and duration range of the current plateau meet the design requirements, achieving the effect of multi-valued operation in a single transistor.
[0060] The present invention also provides a multi-valued logic circuit, including at least one of the aforementioned multi-valued transistors. The multi-valued logic circuit employs the multi-valued transistors provided by the present invention, enabling a single transistor to achieve multiple values, which simplifies the design of the multi-valued logic circuit. Furthermore, the multi-valued transistors provided by the present invention have the advantage of low power consumption, which helps reduce the power consumption and heat generation of the multi-valued logic circuit, thereby improving overall performance.
[0061] refer to Figures 7 to 11The present invention also provides a ternary inverter, comprising:
[0062] A P-type ternary transistor includes a first channel layer and a first gate, a first source, a first drain, and a first electron filter structure disposed on the first channel layer. The first electron filter structure is connected to the first drain and has a first filtering band gap. The first filtering band gap is located within the potential barrier variation range of the first channel layer.
[0063] An N-type ternary transistor includes a second channel layer and a second gate, a second source, a second drain, and a second electron filter structure disposed on the second channel layer. The second electron filter structure is connected to the second source and has a second filtering band gap. The second filtering band gap is located within the potential barrier variation range of the second channel layer.
[0064] The first gate and the second gate are connected as an inverting input terminal, and the first drain and the second drain are connected as an inverting output terminal.
[0065] Both P-type and N-type ternary transistors can achieve the function of ternary operation with a single transistor. Based on the above connection structure, the inversion function in the ternary case can be realized, and only three P-type transistors and two N-type ternary transistors are needed, which is beneficial to simplifying the circuit structure.
[0066] It is understood that the above-mentioned P-type ternary transistor and N-type ternary transistor are essentially the implementation of the ternary transistor on the P-type and N-type transistors of the above-mentioned multi-valued transistor. The working principle is the same as that of the multi-valued transistor provided in this invention. Please refer to the description of the multi-valued transistor, which will not be repeated here.
[0067] In the ternary inverter case, there are three types: standard ternary inverter (STI), negative ternary inverter (NTI), and positive ternary inverter (PTI). The truth tables for these three types of ternary inverters are as follows: Figure 8 As shown.
[0068] refer to Figure 9 In some embodiments of the ternary inverter of the present invention, the potential barrier variation range of the first channel layer is the same as that of the second channel layer, the first filtering band gap is located in the middle of the potential barrier variation range of the first channel layer, and the range of the first filtering band gap is the same as that of the second filtering band gap.
[0069] The P-type ternary transistor and the N-type ternary transistor have the same current plateau position in the intermediate state, allowing both to be in the intermediate state simultaneously. The output of the ternary inverter also includes the intermediate state, so that the inverted output satisfies the truth table of STI. The ternary inverter is used as an STI.
[0070] refer to Figure 9 and Figure 10 In some embodiments of the ternary inverter of the present invention, the range of the first filtering band gap is the same as the range of the second filtering band gap, the first filtering band gap is located in the middle of the potential barrier change range of the first channel layer, and the upper energy level of the first filtering band gap is the same as the lower energy level of the second filtering band gap.
[0071] The current plateau of the P-type ternary transistor is located in the middle, and it is located after the current plateau of the N-type ternary transistor. During the increase of the gate voltage, when the P-type ternary transistor is in the intermediate state, the N-type ternary transistor is in the on state, which pulls down the level of the inverting output terminal, so that the inverting output satisfies the truth table of NTI. The ternary inverter is used as NTI.
[0072] refer to Figure 9 and Figure 11 In some embodiments of the ternary inverter of the present invention, the range of the first filtering band gap is the same as the range of the second filtering band gap, the second filtering band gap is located in the middle of the potential barrier change range of the second channel layer, and the upper energy level of the first filtering band gap is the same as the lower energy level of the second filtering band gap.
[0073] The current plateau of the N-type ternary transistor is located in the middle, and the current plateau of the P-type ternary transistor is located after the N-type ternary transistor. When the N-type ternary transistor is in the intermediate state, the P-type ternary transistor is in the conducting state, and the inverting output terminal outputs a high level, so that the inverting output satisfies the truth table of PTI. The ternary inverter is used as a PTI.
[0074] refer to Figure 12 The present invention also provides a ternary NAND gate, comprising:
[0075] The first P-type ternary transistor includes a third channel layer and a third gate, a third source, a third drain and a third electron filter structure disposed on the third channel layer. The third electron filter structure is connected to the third drain and has a third filtering band gap. The third filtering band gap is located within the potential barrier variation range of the third channel layer.
[0076] The second P-type ternary transistor includes a fourth channel layer and a fourth gate, a fourth source, a fourth drain and a fourth electron filter structure disposed on the fourth channel layer. The fourth electron filter structure is connected to the fourth drain and has a fourth filtering band gap. The fourth filtering band gap is located within the potential barrier variation range of the fourth channel layer.
[0077] The range of the third filtration band gap is the same as the range of the fourth filtration band gap;
[0078] The third gate serves as the input terminal of the first NAND gate, the fourth gate serves as the input terminal of the second NAND gate, the third source is connected to the fourth source and is used to connect to the power supply terminal, and the third drain is connected to the fourth drain as the output terminal of the NAND gate and is used to ground through a resistor.
[0079] The first P-type ternary transistor and the second P-type ternary transistor have the same potential barrier range, and the range of the third filtering bandgap is the same as that of the fourth filtering bandgap and is located in the middle. Based on the above connection structure, the input voltages of the third and fourth gates, which serve as the input terminals of the NAND gate, and the output voltage of the NAND gate satisfy the following conditions: Figure 13 The truth table for a ternary NAND gate is shown below. Thus, the function of a ternary NAND gate can be implemented using only two P-type ternary transistors, resulting in a simple circuit structure that is easy to design and apply.
[0080] It is understood that the first P-type ternary transistor and the second P-type ternary transistor mentioned above are essentially the implementation of the ternary transistor on the P-type transistor in the above-mentioned multi-valued transistor. Their working principle is the same as that of the multi-valued transistor provided in this invention. Please refer to the description of the multi-valued transistor, which will not be repeated here.
[0081] refer to Figure 14 The present invention also provides a ternary NOR gate, comprising:
[0082] The first N-type ternary transistor includes a fifth channel layer and a fifth gate, a fifth source, a fifth drain and a fifth electron filter structure disposed on the fifth channel layer. The fifth electron filter structure is connected to the fifth source and has a fifth filtering band gap. The fifth filtering band gap is located within the potential barrier variation range of the fifth channel layer.
[0083] The second N-type ternary transistor includes a sixth channel layer and a sixth gate, a sixth source, a sixth drain and a sixth electron filter structure disposed on the sixth channel layer. The sixth electron filter structure is connected to the sixth source and has a sixth filtering band gap. The sixth filtering band gap is located within the potential barrier variation range of the sixth channel layer.
[0084] The range of the fifth filtration band gap is the same as the range of the sixth filtration band gap;
[0085] The fifth gate serves as the input terminal of the first NOR gate, the sixth gate serves as the input terminal of the second NOR gate, the fifth drain is connected to the sixth drain as the output terminal of the NOR gate and is used to connect to the power supply terminal through a resistor, and the fifth source is connected to the sixth source and grounded.
[0086] The first N-type ternary transistor and the second N-type ternary transistor have the same potential barrier variation range, and the range of the fifth filtering bandgap is the same as that of the sixth filtering bandgap and is located in the middle. Based on the above connection structure, the input voltages of the fifth and sixth gates, which are the input terminals of the NOR gate, and the output voltage of the NOR gate, satisfy the following conditions: Figure 15 The truth table for a ternary NOR gate is shown below. Thus, the function of a ternary NOR gate can be implemented using only two N-type ternary transistors, resulting in a simple circuit structure that is easy to design and apply.
[0087] It is understood that the first N-type ternary transistor and the second N-type ternary transistor mentioned above are essentially the implementation of ternary transistors on N-type transistors in the context of the multi-valued transistors mentioned above. Their working principle is the same as that of the multi-valued transistors provided in this invention. Please refer to the description of the multi-valued transistors for further details.
[0088] refer to Figure 16 The present invention also provides a ternary decoder, comprising three ternary inverters as described above, namely a first ternary inverter, a second ternary inverter, and a third ternary inverter, and further comprising a ternary NOR gate as described above. The input terminal of the first ternary inverter is connected to the input terminal of the second ternary inverter as a decoding input terminal. The output terminal of the second ternary inverter is connected to the input terminal of the third ternary inverter. The output terminals of the first ternary inverter and the third ternary inverter are connected to the input terminal of the ternary NOR gate. The output terminal of the first ternary inverter serves as a first decoding output terminal, the output terminal of the ternary NOR gate serves as a second decoding output terminal, and the output terminal of the third ternary inverter serves as a third decoding output terminal.
[0089] The first and third ternary inverters are NTIs, and the second ternary inverter is a PTI. Based on this connection structure, when the input voltage X is 0, the output voltage of the first decoder output terminal X0 is 2, and the output voltages of the second decoder output terminal X1 and the third decoder output terminal X2 are both 0. When the input voltage is 1, the output voltage of the second decoder output terminal X1 is 2, and the output voltages of the first decoder output terminal X0 and the third decoder output terminal X2 are both 0. When the input voltage is 2, the output voltage of the third decoder output terminal X2 is 2, and the output voltages of the first decoder output terminal X0 and the second decoder output terminal X1 are both 0. Therefore, only three ternary inverters and one ternary NOR gate are needed to implement the function of a ternary decoder, resulting in a simple circuit structure that is easy to design and apply.
[0090] The ternary inverter, ternary NAND gate, ternary NOR gate, and ternary decoder provided by this invention do not include binary devices; that is, they are all implemented based on ternary transistors, and the number of ternary transistors used is minimal. Compared with other schemes that use binary devices to implement ternary logic functions, they have the advantage of simplifying the circuit structure and reducing the number of devices.
[0091] refer to Figure 17 and Figure 18 This invention also provides a ternary half-adder and a ternary full-adder. Based on the ternary decoder, ternary NAND gate, and ternary inverter provided by this invention, combined with existing binary NAND gates, the functions of a ternary half-adder and a ternary full-adder in ternary mode can be realized. The specific connection structure of the ternary half-adder is as follows... Figure 17 As shown, the connection structure of the ternary full adder is as follows: Figure 18 As shown in the figure, the "Decoder" device is the ternary decoder provided by the present invention. Devices marked with "B" represent binary devices, and devices marked with "T" represent ternary devices, namely the ternary NAND gate and ternary inverter provided by this application.
[0092] The multi-valued transistor of this invention, by incorporating an electronic filtering structure, achieves multi-valued functionality from a single transistor, simplifying logic circuit design and reducing the number of components required to implement logic circuit functions. The ternary inverter, ternary NAND gate, ternary NOR gate, ternary decoder, ternary half-adder, and ternary full adder provided by this invention all utilize the multi-valued transistor of this invention, enabling the implementation of corresponding logic functions with a simple circuit structure. Furthermore, the multi-valued transistor provided by this invention has the advantages of being suitable for low-voltage environments and exhibiting significant low power consumption, which helps to ensure that the aforementioned logic circuits also possess low power consumption advantages.
[0093] In the description of this invention, it should be understood that the terms "first," "second,"..."sixth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A multi-valued transistor, characterized in that, include: The channel layer and the gate, source and drain disposed on the channel layer; An electronic filtering structure having at least one filtering band gap, the electronic filtering structure being connected to the source electrode to filter electrons flowing toward the source electrode within the filtering band gap, or the electronic filtering structure being connected to the drain electrode to filter electrons flowing toward the drain electrode within the filtering band gap. At least one of the filtering band gaps is located within the potential barrier variation range of the channel layer, so that when the energy level at the bottom of the potential barrier conduction band of the channel layer falls into the range of the filtering band gap, the current of the channel layer remains unchanged, forming a current plateau. The potential barrier variation range of the channel layer characterizes the variation range of the bottom energy level of the channel layer's potential conduction band as the gate voltage is applied.
2. The multi-valued transistor according to claim 1, characterized in that, The electron filter structure comprises at least one material selected from carbon nanoribbons, carbon nanotubes, black phosphorus, titanium chloride, and indium arsenide.
3. The multi-valued transistor according to claim 1, characterized in that: The electronic filtering structure has at least two of the filtering band gaps, and the bottom energy level of the barrier conduction band of the channel layer is located within one of the filtering band gaps when no voltage is applied to the gate.
4. A method for constructing a multi-valued transistor, characterized in that, Applied to the multi-value transistor as described in any one of claims 1 to 3, comprising: Obtain the potential barrier variation range and target multi-value plateau information of the channel layer. The target multi-value plateau information represents the target voltage value and duration range corresponding to the required multi-value state. Based on the potential barrier variation range and the target multi-value platform information, the doping type and doping concentration of the electronic filter structure are adjusted to adjust the filtering band gap range of the electronic filter structure.
5. A multi-valued logic circuit, characterized in that, It includes at least one multi-value transistor as described in any one of claims 1 to 3.
6. A ternary inverter, characterized in that, include: A P-type ternary transistor includes a first channel layer and a first gate, a first source, a first drain, and a first electron filter structure disposed on the first channel layer. The first electron filter structure is connected to the first drain and has a first filtering band gap. The first filtering band gap is located within the potential barrier variation range of the first channel layer. An N-type ternary transistor includes a second channel layer and a second gate, a second source, a second drain, and a second electron filter structure disposed on the second channel layer. The second electron filter structure is connected to the second source and has a second filtering band gap. The second filtering band gap is located within the potential barrier variation range of the second channel layer. The first gate and the second gate are connected as an inverting input terminal, and the first drain and the second drain are connected as an inverting output terminal.
7. The ternary inverter according to claim 6, characterized in that, The potential barrier variation range of the first channel layer is the same as that of the second channel layer; The first filtering band gap is located in the middle of the potential barrier variation range of the first channel layer, and the range of the first filtering band gap is the same as the range of the second filtering band gap; Alternatively, the first filtering band gap is located in the middle of the potential barrier variation range of the first channel layer, and the upper energy level of the first filtering band gap is the same as the lower energy level of the second filtering band gap. Alternatively, the second filtering band gap is located in the middle of the potential barrier variation range of the second channel layer, and the upper energy level of the first filtering band gap is the same as the lower energy level of the second filtering band gap.
8. A ternary NAND gate, characterized in that, include: The first P-type ternary transistor includes a third channel layer and a third gate, a third source, a third drain and a third electron filter structure disposed on the third channel layer. The third electron filter structure is connected to the third drain and has a third filtering band gap. The third filtering band gap is located within the potential barrier variation range of the third channel layer. The second P-type ternary transistor includes a fourth channel layer and a fourth gate, a fourth source, a fourth drain and a fourth electron filter structure disposed on the fourth channel layer. The fourth electron filter structure is connected to the fourth drain and has a fourth filtering band gap. The fourth filtering band gap is located within the potential barrier variation range of the fourth channel layer. The range of the third filtration band gap is the same as the range of the fourth filtration band gap; The third gate serves as the input terminal of the first NAND gate, the fourth gate serves as the input terminal of the second NAND gate, the third source is connected to the fourth source and is used to connect to the power supply terminal, and the third drain is connected to the fourth drain as the output terminal of the NAND gate and is used to ground through a resistor.
9. A ternary NOR gate, characterized in that, include: The first N-type ternary transistor includes a fifth channel layer and a fifth gate, a fifth source, a fifth drain and a fifth electron filter structure disposed on the fifth channel layer. The fifth electron filter structure is connected to the fifth source and has a fifth filtering band gap. The fifth filtering band gap is located within the potential barrier variation range of the fifth channel layer. The second N-type ternary transistor includes a sixth channel layer and a sixth gate, a sixth source, a sixth drain and a sixth electron filter structure disposed on the sixth channel layer. The sixth electron filter structure is connected to the sixth source and has a sixth filtering band gap. The sixth filtering band gap is located within the potential barrier variation range of the sixth channel layer. The range of the fifth filtration band gap is the same as the range of the sixth filtration band gap; The fifth gate serves as the input terminal of the first NOR gate, the sixth gate serves as the input terminal of the second NOR gate, the fifth drain is connected to the sixth drain as the output terminal of the NOR gate and is used to connect to the power supply terminal through a resistor, and the fifth source is connected to the sixth source and grounded.
10. A ternary decoder, characterized in that, The device includes three ternary inverters as described in claim 7, namely a first ternary inverter, a second ternary inverter, and a third ternary inverter, and also includes a ternary NOR gate as described in claim 9. The input terminals of the first ternary inverter and the second ternary inverter are connected as decoding input terminals, the output terminals of the second ternary inverter and the third ternary inverter are connected as input terminals of the ternary NOR gate, the output terminal of the first ternary inverter serves as a first decoding output terminal, the output terminal of the ternary NOR gate serves as a second decoding output terminal, and the output terminal of the third ternary inverter serves as a third decoding output terminal. Wherein, for the first ternary inverter and the third ternary inverter, the first filtering band gap is located in the middle of the potential barrier variation range of the first channel layer, and the upper energy level of the first filtering band gap is the same as the lower energy level of the second filtering band gap. For the second ternary inverter, the second filtering bandgap is located in the middle of the potential barrier variation range of the second channel layer, and the upper energy level of the first filtering bandgap is the same as the lower energy level of the second filtering bandgap.