Method, device, equipment and computer storage medium for adjusting wafer parameters

Abstract

The embodiments of the present disclosure disclose a method, apparatus, device, and computer storage medium for adjusting wafer parameters. The method comprises: collecting multiple sampling points on the surface of a wafer to be tested according to a set sampling method; obtaining height change data corresponding to each of the multiple sampling points based on a reference height of the wafer to be tested; obtaining a height gradient at each sampling point based on the height change data corresponding to each sampling point; and rotating the wafer to be tested by a set angle based on the height gradients at all sampling points.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor manufacturing technology, and more particularly, to a method, apparatus, device, and computer storage medium for adjusting wafer parameters. Background Art

[0002] Wafers are essential materials for the production of integrated circuits. Through processes like photolithography and ion implantation, various semiconductor devices can be fabricated from wafers. It's no secret that semiconductor devices made from wafers possess astonishing computing power. With the rapid advancement of automation and computer technology, the application range of semiconductor devices made from wafers has expanded significantly, and they are now widely used in a wide range of fields, including aerospace, industry, agriculture, and national defense. Naturally, with the widespread use of wafers across various industries, the quality requirements for wafers are becoming increasingly stringent. Understandably, any slight variation in the wafers will affect their quality, and in turn, the functionality of the semiconductor devices made from them.

[0003] With the development of advanced processes, wafers that are considered flat under current specifications may not appear flat under higher specifications. Instead, the wafer surface exhibits topographical variations. In this case, material and energy transfer within the wafer surface is uneven, which in turn restricts the wafer's application in advanced processes with smaller line widths. Therefore, in practice, it is necessary to adjust the wafer surface topography to improve the uniformity of material and energy transfer within the wafer surface by increasing its flatness, thereby reducing yield loss. Summary of the Invention

[0004] In view of this, the embodiments of the present disclosure hope to provide a method, apparatus, device and computer storage medium for adjusting wafer parameters, which can improve the flatness of the wafer surface and reduce yield loss.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for adjusting parameters of a wafer, the method comprising:

[0007] Collect multiple sampling points on the surface of the wafer to be tested according to the set sampling method;

[0008] Based on the reference height of the wafer to be measured, obtaining height change data corresponding to each sampling point of the plurality of sampling points;

[0009] Based on the height change data corresponding to each sampling point, obtaining the height gradient at each sampling point;

[0010] Based on the height gradients at all sampling points, the wafer to be tested is rotated by a set angle.

[0011] In a second aspect, an embodiment of the present disclosure provides a device for adjusting wafer parameters, the device comprising: a collection unit, a first acquisition unit, a second acquisition unit, and a rotation unit; wherein,

[0012] The collecting unit is configured to collect a plurality of sampling points on the surface of the wafer to be tested according to a set sampling method;

[0013] The first acquiring unit is configured to acquire height change data corresponding to each of the plurality of sampling points based on a reference height of the wafer to be measured;

[0014] The second acquiring unit is configured to acquire the height gradient at each sampling point based on the height change data corresponding to each sampling point;

[0015] The rotating part is configured to rotate the wafer to be tested by a set angle based on the height gradients at all sampling points.

[0016] In a third aspect, an embodiment of the present disclosure provides a computing device comprising a processor and a memory; the processor is configured to execute instructions stored in the memory to implement the method for adjusting wafer parameters according to the first aspect.

[0017] In a fourth aspect, an embodiment of the present disclosure provides a computer storage medium, wherein the storage medium stores at least one instruction, and the at least one instruction is used to be executed by a processor to implement the method for adjusting wafer parameters according to the first aspect.

[0018] The embodiments of the present disclosure provide a method, apparatus, device, and computer storage medium for adjusting wafer parameters; multiple sampling points are selected on the surface of a wafer to be tested according to a set selection method; based on a reference height of the wafer to be tested, height change data corresponding to each of the multiple sampling points is obtained, and the height gradients at all sampling points are obtained, and the wafer to be tested is rotated by a set angle, thereby improving the flatness of the surface of the wafer to be tested, thereby improving the uniformity and controllability of material and energy transfer from the surface of the wafer to be tested to the inside, and reducing the yield loss of the wafer to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic flow chart of a method for adjusting wafer parameters provided in an embodiment of the present disclosure;

[0020] Figure 2 A topographic change map of a surface of one side of a wafer to be tested provided in an embodiment of the present disclosure;

[0021] Figure 3A schematic diagram of using height gradient to eliminate the effects of shadow effects and crystal plane transformations provided by an embodiment of the present disclosure;

[0022] Figure 4 A schematic diagram of another embodiment of the present disclosure for eliminating the shadow effect and the influence of crystal plane transformation by using height gradient;

[0023] Figure 5 A schematic diagram of a sampling method provided in an embodiment of the present disclosure;

[0024] Figure 6 A schematic diagram of the height of various positions on the surface of a wafer to be measured with a small step size according to an embodiment of the present disclosure;

[0025] Figure 7 A schematic diagram of the height of various positions on the surface of a wafer to be measured with a large step length according to an embodiment of the present disclosure;

[0026] Figure 8 A schematic diagram of the composition of a device for adjusting wafer parameters provided by an embodiment of the present disclosure;

[0027] Figure 9 A structural block diagram of a computing device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present disclosure.

[0029] See also Figure 1 , which shows a method for adjusting wafer parameters provided by an embodiment of the present disclosure, and the method specifically includes the following steps.

[0030] In step S101 , a plurality of sampling points are collected on the surface of a wafer to be tested according to a set sampling method.

[0031] The surface of the wafer to be tested includes the front side of the wafer to be tested and the back side of the wafer to be tested. Generally, the front side of the wafer to be tested refers to the side surface on which integrated circuits can be manufactured, and the back side of the wafer to be tested refers to the side surface opposite to the front side of the wafer to be tested. It is understood that in order to obtain the topographic changes on the surface of the wafer to be tested, it is necessary to collect multiple sampling points on the front side and the back side of the wafer to be tested during the specific implementation process.

[0032] In some examples, the number of the sampling points is not specifically limited. Generally speaking, the greater the number of sampling points, the closer the degree of topographic variation of the wafer surface to be measured is to the actual situation.

[0033] In step S102 , height variation data corresponding to each of the plurality of sampling points is obtained based on the reference height of the wafer to be measured.

[0034] In some examples, the above-mentioned reference height is a pre-measured height of a sampling point or a position on the surface of the wafer to be measured, and then the height change data of the remaining sampling points or remaining positions on the surface of the wafer to be measured are obtained based on the reference height.

[0035] Understandably, when the surface of the wafer under test is uneven, height fluctuations will occur on both the front and back sides of the wafer under test, reducing the uniformity and controllability of material and energy transfer from the surface of the wafer under test. Therefore, in the disclosed embodiment, multiple sampling points are collected on both the front and back sides of the wafer under test to obtain height variation data for each sampling point relative to the reference height.

[0036] Specifically, by measuring the height change data of multiple sampling points on the front side and back side of the wafer to be tested relative to the reference height, a topographic change map of the surface of the wafer to be tested can be obtained by fitting. Figure 2 As shown in FIG, it shows the topographic deformation map of one side surface of the wafer to be tested. Figure 2 It can be seen that Figure 2 The height fluctuations of one side surface of the wafer to be tested shown in FIG. 1 indicate that the one side surface of the wafer to be tested is not uniform and flat.

[0037] In step S103, the height gradient at each sampling point is obtained based on the height change data corresponding to each sampling point.

[0038] In the embodiment of the present disclosure, in order to be able to control the height fluctuation changes on the surface of the wafer to be tested in advance and avoid the wafer to be tested with uneven surface from being transported to the next process or entering the market, the embodiment of the present disclosure obtains the height gradient corresponding to the height change data obtained above, so as to characterize the uniformity of the surface of the wafer to be tested by the height gradient.

[0039] In step S104 , the wafer to be tested is rotated by a set angle based on the height gradients at all sampling points.

[0040] It is understood that the height gradient at each sampling point is a vector and has a direction. The direction of the height gradient represents the direction in which the actual height of the corresponding sampling point changes most rapidly. In a specific implementation, the speed of the actual height change of the sampling point represents the degree to which the ideal plane (such as the (001) crystal plane) shifts to other crystal planes or deviates in other directions.

[0041] like Figure 3 and Figure 4 As shown, different crystal planes have anisotropic mass and energy transfer coefficients, resulting in different mass and energy transfer fluxes on different crystal planes. This can cause non-uniform transmission inward from the surface of the wafer under test. In specific implementations, the processing angle of the wafer under test, the concentration or power of the transmission source, and the height gradient at all sampling points are adjusted during different processes (such as ion implantation) to maintain equal flux transmission, thereby eliminating shadow effects caused by surface topography and the influence of crystal plane transformations.

[0042] In some examples, when the crystal plane at the sampling point is offset in other directions so as to cause a deviation in the angle of material transfer or energy transfer of the offset crystal plane, the wafer to be tested is rotated at a location with a large height gradient based on the height gradient at the sampling point so that the wafer to be tested maintains a preset processing angle, thereby eliminating the shadow effect and the impact of crystal plane transformation.

[0043] for Figure 1 The technical solution shown in FIG. 1 selects multiple sampling points on the surface of the wafer to be tested according to a set selection method; based on the reference height of the wafer to be tested, the height change data corresponding to each of the multiple sampling points is obtained, and the height gradients at all the sampling points are obtained. The wafer to be tested is rotated by a set angle, thereby improving the flatness of the surface of the wafer to be tested, thereby improving the uniformity and controllability of material and energy transfer from the surface of the wafer to be tested, and reducing the yield loss of the wafer to be tested.

[0044] for Figure 1 In some possible implementations of the technical solution shown, the above sampling method includes:

[0045] Establish a Cartesian coordinate system;

[0046] Establish a corresponding polar coordinate system based on the above Cartesian coordinate system;

[0047] The plurality of sampling points are collected with a sampling interval of 0.1 mm to 0.5 mm corresponding to the polar diameter of the polar coordinate system and a sampling interval of 0° to 180° corresponding to the polar angle of the polar coordinate system.

[0048] In the embodiment of the present disclosure, Figure 2 As shown, a Cartesian coordinate system is established with the center of the wafer to be tested as the origin, the direction of the notch on the wafer to be tested as the x-axis, the direction perpendicular to the direction of the notch on the wafer to be tested as the y-axis, and the vertical direction as the z-axis. Of course, in the specific implementation process, the method for establishing the Cartesian coordinate system is not limited to the above-mentioned establishment method.

[0049] After the Cartesian coordinate system is established, a polar coordinate system is established with the origin of the Cartesian coordinate system as the origin of the polar coordinate system. It can be understood that x = r cos θ, y = rs in θ, where r represents the polar diameter of the polar coordinate system and θ represents the polar angle of the polar coordinate system.

[0050] In some examples, based on the polar coordinate system, the sampling interval corresponding to the polar diameter of the polar coordinate system is 0.1 mm to 0.5 mm, and the sampling interval corresponding to the polar angle of the polar coordinate system is 0° to 180°, and multiple sampling points are selected on the front side and the back side of the wafer to be tested, respectively. Figure 5 shown.

[0051] for Figure 1 In some possible implementations of the technical solution shown, Fizeau phase-shift interferometry, infrared method or capacitance method are used to obtain the height change data at each sampling point.

[0052] It should be noted that, in the specific implementation process, the method for obtaining the height change data at each sampling point in the embodiment of the present disclosure is not limited to the above-mentioned Fizeau phase shift interferometry method, infrared method or capacitance method. Other methods that can obtain the height change data at each of the above-mentioned sampling points based on the technical solution of the present disclosure are also within the scope of protection of the present disclosure.

[0053] for Figure 1 In some possible implementations of the technical solution shown, obtaining the height gradient at each sampling point based on the height change data corresponding to each sampling point includes:

[0054] Based on the set step size, the height gradient at each sampling point is obtained according to the following formula:

[0055]

[0056] in, represents the height gradient corresponding to the t-th sampling point, and 1≤t≤N, N represents the number of sampling points; s represents the step size, and the range of s is 1 to 10; Δz t (x, y) represents the height change data corresponding to the t-th sampling point at the starting point and the end point of the step length under the set step length; represents a unit vector with the same positive direction as the x-axis; represents a unit vector in the same direction as the positive direction of the y-axis; Δx represents the change in the height change data at the t-th sampling point in the x-direction; Δy represents the change in the height change data at the t-th sampling point in the y-direction.

[0057] In the embodiment of the present disclosure, the height gradient under different step lengths s can be calculated to more accurately reflect the surface uniformity of the wafer to be tested. It can be understood that, if Figure 6 As shown, when the step size s is smaller, it can better reflect the smaller area on the surface of the wafer to be tested ( Figure 6 The morphology of point A in the figure. Figure 7 As shown, when the step length s is larger, it can reflect a larger area on the surface of the wafer to be measured ( Figure 7 The morphology of point B in the figure.

[0058] for Figure 1 In some possible implementations of the technical solution shown, the above-mentioned rotating the wafer to be tested by a set angle based on the height gradient at all sampling points includes:

[0059] Determining whether a crystal plane transition occurs on the surface of the wafer to be tested based on the height gradients at all sampling points;

[0060] When a crystal plane transition occurs on the surface of the wafer to be tested, the wafer to be tested is rotated by a set angle.

[0061] It is understandable that when the morphology of the surface of the wafer to be tested changes, such as the appearance of pits, a shadow effect will occur. Of course, the above-mentioned changes in the morphology of the surface of the wafer to be tested may also lead to crystal plane transformation. It should be noted that, depending on the cause of the damage, mechanical damage such as deep pits will usually lead to crystal plane transformation. However, shallow pits in a larger range, such as uneven removal in the polishing process, will not lead to crystal plane transformation. It is understandable that, if Figure 7 As shown, long-range topography fluctuations on the wafer to be tested can be formed by short-range small steps.

[0062] In the specific implementation process, it is necessary to first determine whether the surface of the wafer to be tested has a crystal plane transition. If a crystal plane transition occurs, the wafer to be tested must first be rotated by a set angle to eliminate the shadow effect.

[0063] Regarding the above-mentioned embodiment, in some examples, when a crystal plane transition occurs on the surface of the wafer to be tested, rotating the wafer to be tested by a set angle includes:

[0064] Based on the wafer to be tested after being rotated by the set angle, the power or concentration of the transmission source corresponding to the wafer to be tested after being rotated by the set angle is adjusted.

[0065] In some examples, when crystal plane transformation is involved, since the physical properties of each crystal plane are anisotropic, it is necessary to adjust the power of the transmission source during the specific implementation process so that the crystal plane after the adjustment maintains the same transport depth concentration as the crystal plane before the adjustment. It is understandable that when, for example, the crystal plane transforms from the (100) crystal plane to the (110) crystal plane, since the anisotropic physical parameters corresponding to the (100) crystal plane and the (110) crystal plane can be known in advance, it is possible to determine how to adjust the power of the transmission source, such as increasing or decreasing the power of the transmission source.

[0066] Regarding the above-mentioned embodiment, in some examples, when a crystal plane transition occurs on the surface of the wafer to be tested, rotating the wafer to be tested by a set angle further includes:

[0067] When a crystal plane transformation occurs on the surface of the wafer to be tested and the transformed crystal plane is a high-index crystal plane, the wafer to be tested, which has been rotated by a set angle, is rotated again by a set angle.

[0068] In some examples, for example, the transformation of the crystal plane from the (100) crystal plane to the (110) crystal plane requires a rotation of 90°. Then, when the (100) crystal plane is rotated by 5°, the corresponding crystal plane can be calculated to be a high-index crystal plane. The atomic density of the high-index crystal plane is very small, so it can be considered that the effect on the shadow effect is very weak. Therefore, in the embodiment of the present disclosure, the above-mentioned crystal plane is transformed into a transformation between non-high-index crystal planes. In the specific implementation process, when the crystal plane of the wafer to be tested is obtained as a high-index crystal plane according to the height gradient at the sampling point and the physical performance parameters corresponding to the high-index crystal plane cannot be known, the wafer to be tested can be rotated again by a set angle to eliminate the shadow effect.

[0069] Based on the same inventive concept, see Figure 8 , which shows a device 80 for adjusting wafer parameters provided by an embodiment of the present disclosure, the device 80 includes: a collection unit 801, a first acquisition unit 802, a second acquisition unit 803 and a rotation unit 804, wherein,

[0070] The collecting unit 801 is configured to collect a plurality of sampling points on the surface of the wafer to be tested according to a set sampling method;

[0071] The first acquiring unit 802 is configured to acquire height change data corresponding to each of the plurality of sampling points based on the reference height of the wafer to be measured;

[0072] The second acquiring unit 803 is configured to acquire the height gradient at each sampling point based on the height change data corresponding to each sampling point;

[0073] The rotating unit 804 is configured to rotate the wafer to be tested by a set angle based on the height gradients at all sampling points.

[0074] Optionally, in some examples, the acquisition unit 801 is configured to:

[0075] Establish a Cartesian coordinate system;

[0076] Establish a corresponding polar coordinate system based on the above Cartesian coordinate system;

[0077] The plurality of sampling points are collected with a sampling interval of 0.1 mm to 0.5 mm corresponding to the polar diameter of the polar coordinate system and a sampling interval of 0° to 180° corresponding to the polar angle of the polar coordinate system.

[0078] Optionally, in some examples, the first acquiring unit 802 is configured to:

[0079] The height change data at each sampling point is obtained using Fizeau phase-shift interferometry, infrared method or capacitance method.

[0080] Optionally, in some examples, the second acquiring unit 803 is configured to:

[0081] Based on the set step size, the height gradient at each sampling point is obtained according to the following formula:

[0082]

[0083] in, represents the height gradient corresponding to the t-th sampling point, and 1≤t≤N, N represents the number of sampling points; s represents the step size, and the range of s is 1 to 10; Δz t (x, y) represents the height change data corresponding to the t-th sampling point at the starting point and the end point of the step length under the set step length; represents a unit vector with the same positive direction as the x-axis; represents a unit vector in the same direction as the positive direction of the y-axis; Δx represents the change in the height change data at the t-th sampling point in the x-direction; Δy represents the change in the height change data at the t-th sampling point in the y-direction.

[0084] Optionally, in some examples, the rotating unit 804 is configured as follows:

[0085] Determining whether a crystal plane transition occurs on the surface of the wafer to be tested based on the height gradients at all sampling points;

[0086] When a crystal plane transition occurs on the surface of the wafer to be tested, the wafer to be tested is rotated by a set angle.

[0087] Optionally, in some examples, the rotating unit 804 is configured as follows:

[0088] Based on the wafer to be tested after being rotated by the set angle, the power or concentration of the transmission source corresponding to the wafer to be tested after being rotated by the set angle is adjusted.

[0089] Optionally, in some examples, the rotating unit 804 is configured as follows:

[0090] When a crystal plane transformation occurs on the surface of the wafer to be tested and the transformed crystal plane is a high-index crystal plane, the wafer to be tested, which has been rotated by a set angle, is rotated again by a set angle.

[0091] Please refer to Figure 9 , which shows a structural block diagram of a computing device provided by an exemplary embodiment of the present application. In some examples, the computing device 90 can be at least one of a smart phone, a smart watch, a desktop computer, a laptop computer, a virtual reality terminal, an augmented reality terminal, a wireless terminal and a laptop portable computer. The computing device 90 has a communication function and can access a wired network or a wireless network. The computing device 90 can generally refer to one of a plurality of terminals. Those skilled in the art will appreciate that the number of the above terminals can be more or less. In some examples, the computing device 90 can receive parameter data for adjusting the wafer based on the wired network or wireless network to which it is connected. It can be understood that the computing device 90 undertakes the calculation and processing work of the technical solution of the present disclosure, and the embodiments of the present disclosure are not limited to this.

[0092] like Figure 9 As shown, the computing device in the present application may include one or more of the following components: a processor 910 and a memory 920 .

[0093] Optionally, the processor 910 uses various interfaces and lines to connect various parts of the entire computing device, and performs various functions of the computing device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 920, and calling data stored in the memory 920. Optionally, the processor 910 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 910 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), and a baseband chip. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content required to be displayed on the touch screen; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to handle wireless communications. It is understandable that the above-mentioned baseband chip may not be integrated into the processor 910, but may be implemented by a separate chip.

[0094] The memory 920 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 920 includes a non-transitory computer-readable storage medium. The memory 920 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 920 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above various method embodiments, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0095] In addition, those skilled in the art will understand that the structure of the computing device shown in the above figures does not constitute a limitation of the computing device. The computing device may include more or fewer components than shown, or a combination of certain components, or a different arrangement of components. For example, the computing device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, sensors (such as an accelerometer, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module, and other components, which will not be described in detail here.

[0096] An embodiment of the present application further provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the method for adjusting wafer parameters as described in the above embodiments.

[0097] An embodiment of the present application also provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computing device executes to implement the method for adjusting wafer parameters described in the above-mentioned embodiments.

[0098] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0099] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0100] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for adjusting wafer parameters, characterized in that: The method comprises: Collect multiple sampling points on the surface of the wafer to be tested according to the set sampling method; Based on the reference height of the wafer to be measured, obtaining height change data corresponding to each sampling point of the plurality of sampling points; Based on the height change data corresponding to each sampling point, obtaining the height gradient at each sampling point; wherein the direction of the height gradient at each sampling point represents the direction in which the actual height of the corresponding sampling point changes fastest; When it is determined based on the height gradients at all sampling points that a crystal plane transition occurs on the surface of the wafer to be tested, the wafer to be tested is rotated so that the wafer to be tested maintains a preset processing angle.

2. The method according to claim 1, characterized in that The sampling method comprises: Establish a Cartesian coordinate system; Establishing a corresponding polar coordinate system based on the Cartesian coordinate system; The plurality of sampling points are collected with a sampling interval corresponding to the polar diameter of the polar coordinate system being 0.1 mm to 0.5 mm and a sampling interval corresponding to the polar angle of the polar coordinate system being 0° to 45°.

3. The method according to claim 1, characterized in that The height change data at each sampling point is acquired using Fizeau phase-shift interferometry, infrared method or capacitance method.

4. The method according to claim 1, wherein The obtaining of the height gradient at each sampling point based on the height change data corresponding to each sampling point includes: Based on the set step size, the height gradient at each sampling point is obtained according to the following formula: in, Indicates the t The height gradient corresponding to the sampling points, and 1≤t≤N, N represents the number of sampling points; s represents the step size, and the range of s is 1 to 10; Indicates that the first t The height change data corresponding to each sampling point; Represents x A unit vector with the same positive direction as the axis; Represents y A unit vector with the same positive direction as the axis; Indicates the t The height change data at each sampling point is x The amount of change in direction; Indicates the t The height change data at each sampling point is y The change in direction.

5. The method according to claim 1, wherein When a crystal plane transition occurs on the surface of the wafer to be tested, the wafer to be tested is rotated by a set angle, comprising: Based on the wafer to be tested after being rotated by the set angle, the power or concentration of the transmission source corresponding to the wafer to be tested after being rotated by the set angle is adjusted.

6. The method according to claim 1, characterized in that When a crystal plane transition occurs on the surface of the wafer to be tested, rotating the wafer to be tested by a set angle further comprises: When a crystal plane transformation occurs on the surface of the wafer to be tested and the transformed crystal plane is a high-index crystal plane, the wafer to be tested, which has been rotated by a set angle, is rotated again by a set angle.

7. A device for adjusting wafer parameters, characterized in that: The device includes: a collection unit, a first acquisition unit, a second acquisition unit and a rotation unit; wherein, The collecting unit is configured to collect a plurality of sampling points on the surface of the wafer to be tested according to a set sampling method; The first acquiring unit is configured to acquire height change data corresponding to each of the plurality of sampling points based on a reference height of the wafer to be measured; The second acquiring unit is configured to acquire the height gradient at each sampling point based on the height change data corresponding to each sampling point; wherein the direction of the height gradient at each sampling point represents the direction in which the actual height of the corresponding sampling point changes fastest; The rotating part is configured to rotate the wafer to be tested so that the wafer to be tested maintains a preset processing angle when it is determined that a crystal plane transition occurs on the surface of the wafer to be tested based on the height gradients at all sampling points.

8. A computing device, characterized in that The computing device includes a processor and a memory; the processor is configured to execute instructions stored in the memory to implement the method for adjusting wafer parameters according to any one of claims 1 to 6.

9. A computer storage medium, characterized in that The storage medium stores at least one instruction, and the at least one instruction is used to be executed by a processor to implement the method for adjusting wafer parameters according to any one of claims 1 to 6.

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