Cross-correlation signal hardware detection circuit and automatic instrument

Abstract

This invention provides a hardware detection circuit and automated instrument for cross-correlation signals. The hardware detection circuit includes a clock generation module, a frequency division module, a first sampling-protection comparison module, a second sampling-protection comparison module, and a counting module. The counting module counts the clock signal only when the first signal is in the falling interval and the second signal is in the rising interval. The counting module only counts the clock signal during the cross-correlation time between the first and second signals. Multiplying the corresponding count code by the period of the clock signal yields the superposition result of the cross-correlation time over multiple periods. Subsequently, only simple multiplication and division operations based on the count code are needed to obtain the cross-correlation time between the first and second signals. This method involves low data computation, low processor resource consumption, and does not require a high-precision analog-to-digital converter. It achieves cross-correlation time detection simply and efficiently while reducing costs.

Description

Technical Field

[0001] This invention relates to the field of industrial automation, and in particular to a hardware detection circuit for cross-correlation signals and an automated instrument. Background Technology

[0002] Cross-correlation time between a pair of cross-correlated signals (e.g.) Figure 1 The Δt measurement shown is a commonly used measurement method in automated instruments, such as cross-correlation flow meters and ultrasonic flow meters based on cross-correlation time measurement. Taking the cross-correlation flow meter as an example: When a fluid is flowing, various "noises" related to the flow conditions exist within the fluid. This "noise" is generated by the movement of "micro-clusters" within the fluid. The noise signal generated by fluid flow is a random signal, meaning that its changes over time cannot be described by a precise mathematical formula, nor can they be accurately predicted; it can only be studied in a statistical sense.

[0003] Generally, a random signal detected in an experiment can be described by a random function that varies with time. When the value of time is any real number within a given finite or infinite interval, the random function is called a stochastic process; if the independent variable takes certain discrete values ​​within the interval, the random function is called a random sequence.

[0004] like Figure 2 As shown, the flow direction is from left to right, and the distance between cross sections aa' and bb' is L. If the time τ0 taken for the fluid to travel from cross section aa' to cross section bb' is measured, then the average flow velocity v c =L / τ0, since the pipe diameter is known, the product of the pipe cross-sectional area and the flow velocity is the average flow rate Q through the pipe.

[0005] For the above cross-correlation time measurement, an amplifier circuit is generally used to output the data to an AD converter, and then a microprocessor is used to acquire the AD data. This method consumes a lot of CPU resources, and the high-precision AD converter used is expensive.

[0006] Therefore, there is an urgent need for a simple and efficient cross-correlation time measurement technology based on hardware processing circuits. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a simple and efficient cross-correlation time measurement technology based on hardware processing circuits to solve the above-mentioned technical problems.

[0008] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0009] A hardware detection circuit for cross-correlation signals, used to measure the cross-correlation time between a first cross-correlation signal and a second cross-correlation signal, includes:

[0010] The clock generation module generates a clock signal.

[0011] The frequency division module is connected to the clock generation module and performs frequency division processing on the clock signal to obtain a sample-and-hold clock signal;

[0012] The first sampling and holding comparison module is connected to the first signal and the frequency division module. Under the control of the sampling and holding clock signal, it samples and holds the first signal to obtain a first sampling and holding signal, and compares the first signal with the first sampling and holding signal to obtain a first sampling and holding comparison signal.

[0013] The second sampling and holding comparison module is connected to the second signal and the frequency division module. Under the control of the sampling and holding clock signal, it samples and holds the second signal to obtain a second sampling and holding signal, and compares the second signal with the second sampling and holding signal to obtain a second sampling and holding comparison signal.

[0014] The counting module is connected to the clock generation module, the first sampling and protection comparison module, and the second sampling and protection comparison module. Under the joint control of the first sampling and protection comparison signal and the second sampling and protection comparison signal, it counts the clock signal to obtain a counting code.

[0015] The first signal and the second signal are sinusoidal signals with the same frequency. The first signal leads the second signal. The counting module counts the clock signal only when the first signal is in the falling interval and the second signal is in the rising interval.

[0016] Optionally, the counter code is output to a subsequent processor, which acquires the detection time of the cross-correlation signal hardware detection circuit, the frequency of the first signal, and the counter code corresponding to the detection time, and calculates the cross-correlation time between the first signal and the second signal according to the following formula:

[0017]

[0018] Wherein, Δt is the cross-correlation time between the first signal and the second signal, t0 is the detection time, f is the frequency of the first signal, D is the decimal value of the counter code corresponding to the detection time, and T is the period of the clock signal.

[0019] Optionally, the clock generation module includes a crystal oscillator, a first capacitor, a second capacitor, a first NOT gate, and a second NOT gate. The first output terminal of the crystal oscillator is connected to the input terminal of the first NOT gate, the output terminal of the first NOT gate is connected to the second output terminal of the crystal oscillator, the first terminal of the first capacitor is connected to the first output terminal of the crystal oscillator, and the second terminal of the first capacitor is grounded. The first terminal of the second capacitor is connected to the second output terminal of the crystal oscillator, and the second terminal of the second capacitor is grounded. The input terminal of the second NOT gate is connected to the output terminal of the first NOT gate, and the output terminal of the second NOT gate outputs the clock signal.

[0020] Optionally, the frequency divider module includes two cascaded D flip-flops. The clock input of the first D flip-flop is connected to the clock signal, the data input of the first D flip-flop is connected to the second output of the first D flip-flop, the first output of the first D flip-flop is connected to the clock input of the second D flip-flop, the data input of the second D flip-flop is connected to the second output of the second D flip-flop, and the first output of the second D flip-flop outputs the sample-and-hold clock signal.

[0021] Optionally, the first sample-and-hold comparison module includes a first sample-and-hold unit and a first comparison unit. The input terminal of the first sample-and-hold unit is connected to the first signal, and the control terminal of the first sample-and-hold unit is connected to the sample-and-hold clock signal. The first sample-and-hold unit samples and holds the first signal to obtain and output the first sample-and-hold signal. The non-inverting input terminal of the first comparison unit is connected to the first signal, and the inverting input terminal of the first comparison unit is connected to the first sample-and-hold signal. The first comparison unit compares the first signal with the first sample-and-hold signal to obtain and output the first sample-and-hold comparison signal.

[0022] Optionally, the first sample-and-hold unit includes a first resistor, a first NMOS transistor, a second NMOS transistor, a third capacitor, and a first operational amplifier. The source of the first NMOS transistor is connected to the first signal, the substrate of the first NMOS transistor is connected to a negative power supply, the drain of the first NMOS transistor is connected to the inverting input of the first operational amplifier via the first resistor connected in series, and the gate of the first NMOS transistor is connected to the sample-and-hold clock signal. The source of the second NMOS transistor is connected to the drain of the first NMOS transistor, the substrate of the second NMOS transistor is connected to the inverting input of the first operational amplifier, the drain of the second NMOS transistor is connected to the non-inverting input of the first operational amplifier, and the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor. The first terminal of the third capacitor is connected to the drain of the second NMOS transistor, and the second terminal of the third capacitor is grounded. The output of the first operational amplifier is connected to the inverting input of the first operational amplifier, and the output of the first operational amplifier outputs the first sample-and-hold signal.

[0023] Optionally, the first comparison unit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a fourth capacitor, and a second operational amplifier. The inverting input of the second operational amplifier is connected to the first signal, and the non-inverting input of the second operational amplifier is connected to the first sample-and-hold signal after passing through the second resistor in series. The non-inverting input of the second operational amplifier is also connected to the output of the second operational amplifier after passing through the third resistor in series. The output of the second operational amplifier is also grounded after passing through the fourth resistor and the fifth resistor in series. The fourth capacitor is connected in parallel with the fifth resistor, and the common terminal of the fourth resistor and the fifth resistor outputs the first sample-and-hold comparison signal.

[0024] Optionally, the second sample-and-hold comparison module includes a second sample-and-hold unit and a second comparison unit. The input terminal of the second sample-and-hold unit is connected to the second signal, and the control terminal of the second sample-and-hold unit is connected to the sample-and-hold clock signal. The second sample-and-hold unit samples and holds the second signal to obtain and output the second sample-and-hold signal. The non-inverting input terminal of the second comparison unit is connected to the second sample-and-hold signal, and the inverting input terminal of the second comparison unit is connected to the second signal. The second comparison unit compares the second signal with the second sample-and-hold signal to obtain and output the second sample-and-hold comparison signal.

[0025] Optionally, the counting module includes a counter input clock control unit and a counting unit. The input terminal of the counter input clock control unit is connected to the clock signal, the control terminal of the counter input clock control unit is connected to the second sample-and-hold comparison signal, and the input terminal of the counter input clock control unit is connected to the clock generation module. The counting unit includes two counters cascaded in sequence. The counting input terminal of the first counter is connected to the output terminal of the counter input clock control unit. The enable terminals of the first counter and the second counter are respectively connected to the first sample-and-hold comparison signal. The first sample-and-hold comparison signal is active low to enable counting, and the second sample-and-hold comparison signal is active low to enable the clock signal to be input to the first counter. The two counters output the counting code in parallel.

[0026] An automated instrument, characterized in that it includes a hardware detection circuit for cross-correlation signals as described in any one of the above-mentioned claims.

[0027] As described above, the cross-correlation signal hardware detection circuit and automated instrument of the present invention have the following beneficial effects:

[0028] A hardware detection circuit for cross-correlation signals is designed by combining a clock generation module, a frequency division module, a first sampling and protection comparison module, a second sampling and protection comparison module, and a counting module. Under the joint control of the first and second sampling and protection comparison signals, the counting module counts the clock signal to obtain a count code. The first and second signals are sinusoidal signals with the same frequency, and the first signal leads the second signal. The counting module only counts the clock signal when the first signal is in the falling interval and the second signal is in the rising interval. That is, the counting module only counts the clock signal during the cross-correlation time of the first and second signals in each cycle. Multiplying the corresponding count code by the period of the clock signal yields the superposition result of the cross-correlation time of the first and second signals over multiple cycles. Subsequently, only simple multiplication and division operations based on the count code are needed to obtain the cross-correlation time of the first and second signals. This method has a small data calculation volume, requires less processor resources, and does not require a high-precision analog-to-digital converter. It achieves cross-correlation time detection simply and efficiently while reducing costs. Attached Figure Description

[0029] Figure 1 This is a schematic diagram showing a set of cross-correlated signals.

[0030] Figure 2 The diagram shows the principle of a cross-correlation flow meter.

[0031] Figure 3 The diagram shown is a structural block diagram of the hardware detection circuit for cross-correlation signals in this invention.

[0032] Figure 4 The diagram shows two cross-correlated sinusoidal signals in this invention.

[0033] Figure 5 The diagram shown is a circuit diagram of the frequency division module in an optional embodiment of the present invention.

[0034] Figure 6 The diagram shown is a circuit diagram of the first sample-and-hold unit in an optional embodiment of the present invention.

[0035] Figure 7 The diagram shown is a circuit diagram of the first comparison unit in an optional embodiment of the present invention.

[0036] Figure 8 The diagram shown is a circuit diagram of the counting module in an optional embodiment of the present invention. Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0039] like Figure 3 As shown, the present invention provides a hardware detection circuit for cross-correlation signals, used to measure the cross-correlation time between a first cross-correlation signal and a second cross-correlation signal, comprising:

[0040] The clock generation module generates the clock signal CLK0.

[0041] The frequency divider module, connected to the clock generation module, divides the clock signal CLK0 to obtain the sample-and-hold clock signal CLK1.

[0042] The first sampling and holding comparison module is connected to the first signal V1 and the frequency division module. Under the control of the sampling and holding clock signal CLK1, it samples and holds the first signal V1 to obtain the first sampling and holding signal V10, and compares the first signal V1 with the first sampling and holding signal V10 to obtain the first sampling and holding comparison signal V11.

[0043] The second sampling and holding comparison module is connected to the second signal V2 and the frequency division module. Under the control of the sampling and holding clock signal CLK1, it samples and holds the second signal V2 to obtain the second sampling and holding signal V20. The second signal V2 is compared with the second sampling and holding signal V20 to obtain the second sampling and holding comparison signal V21.

[0044] The counting module is connected to the clock generation module, the first data acquisition and protection comparison module, and the second data acquisition and protection comparison module. Under the joint control of the first data acquisition and protection comparison signal V11 and the second data acquisition and protection comparison signal V21, it counts the clock signal CLK0 to obtain the counting code DN.

[0045] Among them, such as Figure 4 As shown, the first signal V1 and the second signal V2 are sinusoidal signals with the same frequency. The first signal V1 leads the second signal V2. The counting module counts the clock signal CLK0 only when the first signal V1 is in the falling interval and the second signal V2 is in the rising interval.

[0046] In detail, such as Figure 3 As shown, the clock generation module includes a crystal oscillator X1, a first capacitor C1, a second capacitor C2, a first NOT gate, and a second NOT gate. The first output terminal of the crystal oscillator X1 is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is connected to the second output terminal of the crystal oscillator X1. The first terminal of the first capacitor C1 is connected to the first output terminal of the crystal oscillator X1, and the second terminal of the first capacitor C1 is grounded to GND. The first terminal of the second capacitor C2 is connected to the second output terminal of the crystal oscillator X1, and the second terminal of the second capacitor C2 is grounded to GND. The input terminal of the second NOT gate is connected to the output terminal of the first NOT gate, and the output terminal of the second NOT gate outputs the clock signal CLK0.

[0047] Among them, crystal oscillator X1 can be a 32768 crystal oscillator or other crystal oscillators, which are not limited here. The 32768 crystal oscillator is a quartz crystal oscillator that is often used in real-time clock circuits (RTC). Its frequency is 32768Hz. This is because it can easily be obtained by dividing a standard clock frequency (such as 60 pulses per second) into 2 to the power of 15.

[0048] More in detail, such as Figure 3 As shown, in the clock generation module, the crystal oscillator X1 generates an initial clock signal, which is then inverted and shaped by the first NOT gate and the second NOT gate to output a clock signal CLK0, which serves as the counting clock for the subsequent counting module and the input clock for the frequency divider module.

[0049] In detail, in an optional embodiment of the invention, such as Figure 5 As shown, the frequency divider module includes two cascaded D flip-flops, namely flip-flops D1 and D2. The clock input terminal CLK of the first D flip-flop D1 is connected to the clock signal CLK0. The data input terminal D of the first D flip-flop D1 is connected to the second output terminal Q of the first D flip-flop D1. The first output terminal Q of the first D flip-flop D1 is connected to the clock input terminal CLK of the second D flip-flop D2. The data input terminal D of the second D flip-flop D2 is connected to the second output terminal Q of the second D flip-flop D2. The first output terminal Q of the second D flip-flop D2 outputs the sample-and-hold clock signal CLK1.

[0050] More in detail, such as Figure 5 As shown, the D flip-flops D1 and D2, cascaded in sequence, form a frequency divider circuit to divide the clock signal CLK0 by four to obtain the sample-and-hold clock signal CLK1. The sample-and-hold clock signal CLK1 is used to determine the sampling-and-hold time of the cross-correlation signal for the subsequent sampling of the first and second sample-and-hold units.

[0051] In detail, such as Figure 3 As shown, the first sample-and-hold comparison module includes a first sample-and-hold unit and a first comparison unit. The input terminal of the first sample-and-hold unit is connected to the first signal V1, and the control terminal of the first sample-and-hold unit is connected to the sample-and-hold clock signal CLK1. The first sample-and-hold unit samples and holds the first signal V1 to obtain and output the first sample-and-hold signal V10. The non-inverting input terminal of the first comparison unit is connected to the first signal V1, and the inverting input terminal of the first comparison unit is connected to the first sample-and-hold signal V10. The first comparison unit compares the first signal V1 with the first sample-and-hold signal V10 to obtain and output the first sample-and-hold comparison signal V11.

[0052] In detail, in an optional embodiment of the invention, such as Figure 6As shown, the first sample-and-hold unit includes a first resistor R1, a first NMOS transistor N1, a second NMOS transistor N2, a third capacitor C3, and a first operational amplifier Q1. The source of the first NMOS transistor N1 is connected to the first signal V1, the substrate of the first NMOS transistor N1 is connected to the negative power supply -E, the drain of the first NMOS transistor N1 is connected to the inverting input of the first operational amplifier Q1 via the first resistor R1, and the gate of the first NMOS transistor N1 is connected to the sample-and-hold clock signal CLK1. The source of the second NMOS transistor N2 is connected to the first NMOS transistor N1. The drain of the first NMOS transistor Q1 is connected to the inverting input of the second NMOS transistor N2, the drain of the second NMOS transistor N2 is connected to the non-inverting input of the first operational amplifier Q1, the gate of the second NMOS transistor N2 is connected to the gate of the first NMOS transistor N1, the first end of the third capacitor C3 is connected to the drain of the second NMOS transistor N2, the second end of the third capacitor C3 is grounded, the output of the first operational amplifier Q1 is connected to the inverting input of the first operational amplifier Q1, and the output of the first operational amplifier Q1 outputs the first sample-and-hold signal V10.

[0053] More in detail, such as Figure 6 As shown, under the control of the sample-and-hold clock signal CLK1, the first signal V1 is sampled by the first NMOS transistor N1, the second NMOS transistor N2 and the third capacitor C3, and the first sample-and-hold signal V10 is obtained by the follower formed by the first operational amplifier Q1.

[0054] In detail, in an optional embodiment of the invention, such as Figure 7 As shown, the first comparison unit includes a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a fourth capacitor C4, and a second operational amplifier Q2. The inverting input of the second operational amplifier Q2 (which serves as the non-inverting input of the first comparison unit) is connected to the first signal V1. The non-inverting input of the second operational amplifier Q2 (which serves as the inverting input of the first comparison unit) is connected to the first sample-and-hold signal V10 after passing through the second resistor R2 in series. The non-inverting input of the second operational amplifier Q2 is also connected to the output of the second operational amplifier Q2 after passing through the third resistor R3 in series. The output of the second operational amplifier Q2 is also grounded after passing through the fourth resistor R4 and the fifth resistor R5 in series. The fourth capacitor C4 is connected in parallel with the fifth resistor R5. The common terminal of the fourth resistor R4 and the fifth resistor R5 outputs the first sample-and-hold comparison signal V11.

[0055] More in detail, such as Figure 7As shown, a comparator is constructed based on the second operational amplifier Q2 and the surrounding resistors and capacitors to compare the magnitudes of the first signal V1 and the first sample-and-hold signal V10 to obtain the first sample-and-hold comparison signal V11. When the first signal V1 is in the falling range, the first sample-and-hold comparison signal V11 is at a low level, and when the first signal V1 is in the rising range, the first sample-and-hold comparison signal V11 is at a high level.

[0056] Similarly, as Figure 3 As shown, the second sample-and-hold comparison module includes a second sample-and-hold unit and a second comparison unit. The input terminal of the second sample-and-hold unit is connected to the second signal V2, and the control terminal of the second sample-and-hold unit is connected to the sample-and-hold clock signal CLK1. The second sample-and-hold unit samples and holds the second signal V2 to obtain and output the second sample-and-hold signal V20. The non-inverting input terminal of the second comparison unit is connected to the second sample-and-hold signal V20, and the inverting input terminal of the second comparison unit is connected to the second signal V2. The second comparison unit compares the second signal V2 with the second sample-and-hold signal V20 to obtain and output the second sample-and-hold comparison signal V21.

[0057] More in detail, such as Figure 3 As shown, the second comparison unit compares the second signal V2 with the second sample-and-hold signal V20 to obtain the second sample-and-hold comparison signal V21. When the second signal V2 is in the falling range, the second sample-and-hold comparison signal V21 is at a high level, and when the second signal V2 is in the rising range, the second sample-and-hold comparison signal V21 is at a low level.

[0058] The structure of the second sample-and-hold unit can be referred to Figure 6 The structures of the first sample-and-hold unit and the second comparison unit shown can be referred to Figure 7 The second sample-and-hold unit shown will not be described in detail here.

[0059] In detail, such as Figure 3 As shown, the counting module includes a counter input clock control unit and a counting unit. The input terminal of the counter input clock control unit is connected to the clock signal CLK0, the control terminal of the counter input clock control unit is connected to the second sample-and-hold comparison signal V21, and the input terminal of the counter input clock control unit is connected to the clock generation module. In an optional embodiment of the present invention, as shown... Figure 8As shown, the counting unit includes two cascaded counters Q3 and Q4. The counting input terminal of the first counter Q3 is connected to the output terminal of the counter input clock control unit. The enable terminals of the first counter Q3 and the second counter Q4 are respectively connected to the first sample-and-hold comparison signal V11. The first sample-and-hold comparison signal V11 is active low to enable counting. The second sample-and-hold comparison signal V21 is active low to enable the clock signal CLK0 to be input to the first counter Q3. The two counters Q3 to Q4 output the counting code DN in parallel.

[0060] The counting unit also includes a sixth resistor R6 and a fifth capacitor C5. For details, please refer to [link to relevant documentation]. Figure 8 This will not be elaborated upon here.

[0061] More in detail, such as Figure 3 or Figure 8 As shown, the first sample-and-hold comparison signal V11 is active low to enable counting. That is, when the first sample-and-hold comparison signal V11 is low, the counting unit composed of cascaded counters Q3 and Q4 starts counting, and when the first sample-and-hold comparison signal V11 is high, the counting unit composed of cascaded counters Q3 and Q4 stops counting and remains unchanged. The second sample-and-hold comparison signal V21 is active low to enable the clock signal CLK0 to be input to the first counter Q3. That is, when the second sample-and-hold comparison signal V21 is low, the counter input clock control unit transmits the clock signal CLK0 to the first counter Q3, and when the second sample-and-hold comparison signal V21 is high, the counter input clock control unit cuts off the transmission path of the clock signal CLK0 to the first counter Q3.

[0062] Thus, based on the dual enable control of the first data acquisition and protection comparison signal V11 and the second data acquisition and protection comparison signal V21, the counting unit in the counting module only starts working and the clock signal CLK0 is transmitted to the counting unit for counting when both the first data acquisition and protection comparison signal V11 and the second data acquisition and protection comparison signal V21 are low. A low level of the first data acquisition and protection comparison signal V11 indicates that the first signal V1 is in the falling interval, and a low level of the second data acquisition and protection comparison signal V21 indicates that the second signal V2 is in the rising interval. The overlapping area of ​​the two is exactly the same as... Figure 4 The cross-correlation time Δt between the first signal V1 and the second signal V2 shown corresponds to the counting time DN output by the counting module. This indicates that the counting time corresponding to the counting code DN is related to the cross-correlation time Δt. The counting time corresponding to the counting code DN is the cumulative superposition of the cross-correlation time Δt over multiple cycles, and thus the cross-correlation time Δt can be calculated subsequently.

[0063] In detail, such as Figure 3As shown, the counter code DN is output to the subsequent processor, which can be a microcontroller or other microprocessor. The processor acquires the detection time of the cross-correlation signal hardware detection circuit, the frequency of the first signal V1, and the counter code DN corresponding to the detection time, and calculates the cross-correlation time Δt between the first signal V1 and the second signal V2 according to the following formula:

[0064]

[0065] Where Δt is the cross-correlation time between the first signal V1 and the second signal V2, t0 is the detection time, f is the frequency of the first signal V1, D is the decimal value of the counter code DN corresponding to the detection time t0, and T is the period of the clock signal CLK0.

[0066] More specifically, before the processor performs calculations, the detection time t0 of the cross-correlation signal hardware detection circuit, the frequency f of the first signal V1, and the counting code DN corresponding to the detection time t0 are obtained. The longer the detection time t0, the more times the cross-correlation time Δt is accumulated, resulting in a larger corresponding counting code DN. During calculation, the processor first converts the binary multi-bit counting code DN into a decimal value D. The decimal value D is multiplied by the period T of the clock signal CLK0 to obtain the counting time corresponding to the counting code DN. This counting time is the result of the cumulative accumulation of the cross-correlation time Δt over multiple periods. The cumulative accumulation period is then calculated from the detection time t0 and the frequency f of the first signal V1. Finally, the counting time is divided by the number of cumulative accumulation periods to obtain the cross-correlation time Δt.

[0067] In addition, the present invention also provides an automated instrument, which includes the above-mentioned cross-correlation signal hardware detection circuit and processor. The cross-correlation time Δt between the first signal V1 and the second signal V2 is accumulated and counted by the above-mentioned cross-correlation signal hardware detection circuit, and then the cross-correlation time Δt is calculated by the processor based on the corresponding counting code DN. Thus, the cross-correlation time Δt can be measured simply, efficiently and accurately.

[0068] In summary, the cross-correlation signal hardware detection circuit and automated instrument provided by this invention combine a clock generation module, a frequency division module, a first sampling-protection comparison module, a second sampling-protection comparison module, and a counting module to design the cross-correlation signal hardware detection circuit. Under the joint enable control of the first and second sampling-protection comparison signals, the counting module counts the clock signal to obtain a counting code. The first and second signals are sinusoidal signals with the same frequency, and the first signal leads the second signal. The counting module only counts the clock signal when the first signal is in the falling interval and the second signal is in the rising interval. That is, the counting module only counts the clock signal during the cross-correlation time of the first and second signals in each cycle. The corresponding counting code multiplied by the period of the clock signal can obtain the superposition result of the cross-correlation time of the first and second signals in multiple cycles. Subsequently, only simple multiplication and division operations based on the counting code are needed to obtain the cross-correlation time of the first and second signals. The data calculation is small, the processor resource consumption is low, and a high-precision analog-to-digital converter is not required. While reducing costs, the detection of cross-correlation time is realized simply and efficiently.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A hardware detection circuit for cross-correlation signals, used to measure the cross-correlation time between a first cross-correlation signal and a second cross-correlation signal, characterized in that, include: The clock generation module generates a clock signal. The frequency division module is connected to the clock generation module and performs frequency division processing on the clock signal to obtain a sample-and-hold clock signal; The first sampling and holding comparison module is connected to the first signal and the frequency division module. Under the control of the sampling and holding clock signal, it samples and holds the first signal to obtain a first sampling and holding signal, and compares the first signal with the first sampling and holding signal to obtain a first sampling and holding comparison signal. The second sampling and holding comparison module is connected to the second signal and the frequency division module. Under the control of the sampling and holding clock signal, it samples and holds the second signal to obtain a second sampling and holding signal, and compares the second signal with the second sampling and holding signal to obtain a second sampling and holding comparison signal. The counting module is connected to the clock generation module, the first sampling and protection comparison module, and the second sampling and protection comparison module. Under the joint control of the first sampling and protection comparison signal and the second sampling and protection comparison signal, it counts the clock signal to obtain a counting code. Wherein, the first signal and the second signal are sinusoidal signals of the same frequency, the first signal leads the second signal, and the counting module counts the clock signal only when the first signal is in the falling interval and the second signal is in the rising interval; The counter code is output to the subsequent processor, which acquires the detection time of the cross-correlation signal hardware detection circuit, the frequency of the first signal, and the counter code corresponding to the detection time, and calculates the cross-correlation time between the first signal and the second signal according to the following formula: in, t0 is the cross-correlation time between the first signal and the second signal, f is the detection time, D is the decimal value of the counter code corresponding to the detection time, and T is the period of the clock signal. The counting module includes a counter input clock control unit and a counting unit. The input terminal of the counter input clock control unit is connected to the clock signal, the control terminal of the counter input clock control unit is connected to the second sample-and-hold comparison signal, and the input terminal of the counter input clock control unit is connected to the clock generation module. The counting unit includes two counters cascaded in sequence. The counting input terminal of the first counter is connected to the output terminal of the counter input clock control unit. The enable terminals of the first counter and the second counter are respectively connected to the first sample-and-hold comparison signal. The first sample-and-hold comparison signal is active low to enable counting, and the second sample-and-hold comparison signal is active low to enable the clock signal to be input to the first counter. The two counters output the counting code in parallel.

2. The hardware detection circuit for cross-correlation signals according to claim 1, characterized in that, The clock generation module includes a crystal oscillator, a first capacitor, a second capacitor, a first NOT gate, and a second NOT gate. The first output terminal of the crystal oscillator is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is connected to the second output terminal of the crystal oscillator. The first terminal of the first capacitor is connected to the first output terminal of the crystal oscillator, and the second terminal of the first capacitor is grounded. The first terminal of the second capacitor is connected to the second output terminal of the crystal oscillator, and the second terminal of the second capacitor is grounded. The input terminal of the second NOT gate is connected to the output terminal of the first NOT gate, and the output terminal of the second NOT gate outputs the clock signal.

3. The hardware detection circuit for cross-correlation signals according to claim 1, characterized in that, The frequency divider module includes two cascaded D flip-flops. The clock input of the first D flip-flop is connected to the clock signal, the data input of the first D flip-flop is connected to the second output of the first D flip-flop, the first output of the first D flip-flop is connected to the clock input of the second D flip-flop, the data input of the second D flip-flop is connected to the second output of the second D flip-flop, and the first output of the second D flip-flop outputs the sample-and-hold clock signal.

4. The hardware detection circuit for cross-correlation signals according to claim 1, characterized in that, The first sample-and-hold comparison module includes a first sample-and-hold unit and a first comparison unit. The input terminal of the first sample-and-hold unit is connected to the first signal, and the control terminal of the first sample-and-hold unit is connected to the sample-and-hold clock signal. The first sample-and-hold unit samples and holds the first signal to obtain and output the first sample-and-hold signal. The non-inverting input terminal of the first comparison unit is connected to the first signal, and the inverting input terminal of the first comparison unit is connected to the first sample-and-hold signal. The first comparison unit compares the first signal with the first sample-and-hold signal to obtain and output the first sample-and-hold comparison signal.

5. The hardware detection circuit for cross-correlation signals according to claim 4, characterized in that, The first sample-and-hold unit includes a first resistor, a first NMOS transistor, a second NMOS transistor, a third capacitor, and a first operational amplifier. The source of the first NMOS transistor is connected to the first signal, the substrate of the first NMOS transistor is connected to a negative power supply, the drain of the first NMOS transistor is connected to the inverting input of the first operational amplifier via the first resistor in series, and the gate of the first NMOS transistor is connected to the sample-and-hold clock signal. The source of the second NMOS transistor is connected to the drain of the first NMOS transistor, the substrate of the second NMOS transistor is connected to the inverting input of the first operational amplifier, the drain of the second NMOS transistor is connected to the non-inverting input of the first operational amplifier, and the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor. The first terminal of the third capacitor is connected to the drain of the second NMOS transistor, and the second terminal of the third capacitor is grounded. The output of the first operational amplifier is connected to the inverting input of the first operational amplifier, and the output of the first operational amplifier outputs the first sample-and-hold signal.

6. The hardware detection circuit for cross-correlation signals according to claim 4, characterized in that, The first comparison unit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a fourth capacitor, and a second operational amplifier. The inverting input of the second operational amplifier is connected to the first signal. The non-inverting input of the second operational amplifier is connected to the first sample-and-hold signal via the second resistor connected in series. The non-inverting input of the second operational amplifier is also connected to the output of the second operational amplifier via the third resistor connected in series. The output of the second operational amplifier is grounded via the fourth resistor and the fifth resistor connected in series. The fourth capacitor is connected in parallel with the fifth resistor. The common terminal of the fourth resistor and the fifth resistor outputs the first sample-and-hold comparison signal.

7. The hardware detection circuit for cross-correlation signals according to claim 1, characterized in that, The second sample-and-hold comparison module includes a second sample-and-hold unit and a second comparison unit. The input terminal of the second sample-and-hold unit is connected to the second signal, and the control terminal of the second sample-and-hold unit is connected to the sample-and-hold clock signal. The second sample-and-hold unit samples and holds the second signal to obtain and output the second sample-and-hold signal. The non-inverting input terminal of the second comparison unit is connected to the second sample-and-hold signal, and the inverting input terminal of the second comparison unit is connected to the second signal. The second comparison unit compares the second signal with the second sample-and-hold signal to obtain and output the second sample-and-hold comparison signal.

8. An automated instrument, characterized in that, It includes the hardware detection circuit for cross-correlation signals as described in any one of claims 1-7.

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