Semiconductor package structure
By introducing a thermally conductive layer composed of silver powder particles of different sizes into the semiconductor packaging structure, stress is offset and adhesion is improved, thus solving the problem of easy delamination of the packaging structure and achieving higher reliability and durability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- QUANZHOU SANAN INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2023-12-22
- Publication Date
- 2026-05-12
AI Technical Summary
Existing semiconductor packaging structures are prone to delamination defects, especially in high-power products, which can easily lead to performance degradation or failure. These defects mainly occur in the sidewalls, top, and bottom areas of the chip.
The design employs a structure comprising a first thermally conductive layer and a second thermally conductive layer. The first thermally conductive layer consists of small-diameter first silver powder particles, while the second thermally conductive layer consists of resin and large-diameter second silver powder particles. The chip is disposed on the second thermally conductive layer, and the molding compound covers all layers. The first thermally conductive layer counteracts the deformation stress of the lead frame, while the second thermally conductive layer counteracts the frontal stress in the chip thickness direction through the resin. The combination of these two layers improves adhesion to suppress delamination.
It effectively suppresses or avoids delamination within the semiconductor packaging structure, improves the anti-wobbling ability and adhesion of the packaging structure, extends its service life, and prevents failures caused by delamination.
Smart Images
Figure CN117894783B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit packaging technology, and more specifically to semiconductor packaging structures. Background Technology
[0002] Existing semiconductor packaging structures generally include a leadframe, die bond, chip, and molding compound. The chip is mounted to the leadframe using die bond, and the chip is bonded to the leadframe. The molding compound covers the leadframe, die bond, and chip. Existing semiconductor packaging structures are prone to delamination defects. Delamination often occurs in the areas containing the chip's sidewalls (e.g., between the chip's sidewall and the molding compound), the top area of the chip (e.g., between the top of the chip and the molding compound), and the area beneath the chip (e.g., between the leadframe and the die bond). Delamination is particularly prevalent in high-power products, leading to performance degradation or even product failure.
[0003] Therefore, it is necessary to improve the layering problem of semiconductor packaging structures to prevent packaging device failure caused by layering in chip packaging products. Summary of the Invention
[0004] In view of this, in order to solve the above-mentioned technical problems, this application provides a semiconductor packaging structure, which includes a lead frame, a first thermally conductive layer, a second thermally conductive layer, a chip, and a molding compound.
[0005] A first thermally conductive layer is disposed on one surface of the lead frame and contains first silver powder particles. A second thermally conductive layer is disposed on the first thermally conductive layer and contains resin and second silver powder particles, wherein the particle size of the first silver powder particles is smaller than the particle size of the second silver powder particles. 。 The chip is disposed on the second thermally conductive layer, and the bottom surface and at least part of the sidewalls of the chip are in contact with the second thermally conductive layer. The molding compound covers the lead frame, the first thermally conductive layer, the second thermally conductive layer, and the chip.
[0006] Beneficial Effects: Unlike existing technologies, in this application, because the particle size of the first silver powder particles in the first thermally conductive layer is smaller than that of the second silver powder particles in the second thermally conductive layer, the density of the first thermally conductive layer is superior to that of the second thermally conductive layer. Therefore, the first thermally conductive layer has good anti-wobbling ability. Thus, the first thermally conductive layer can counteract the deformation stress from the lead frame, thereby suppressing or preventing delamination in the area beneath the chip. Since the second thermally conductive layer contains resin, and the resin can partially counteract the frontal stress along the chip thickness direction, delamination caused by frontal stress in the top area of the chip can be reduced. Furthermore, compared to the first thermally conductive layer, the coefficient of thermal expansion of the resin-containing second thermally conductive layer is closer to that of the molding compound, resulting in better adhesion between the second thermally conductive layer and the molding compound. Therefore, at least a portion of the chip's sidewalls are connected to the molding compound through the second thermally conductive layer, suppressing or preventing delamination in the sidewall area of the chip. Thus, through the cooperation of the first and second thermally conductive layers, delamination within the semiconductor packaging structure can be avoided or reduced. Attached Figure Description
[0007] Figure 1 This is a schematic diagram of the semiconductor packaging structure according to the first embodiment of this application;
[0008] Figure 2 yes Figure 1 Enlarged schematic diagram of region A in the middle;
[0009] Figure 3 yes Figure 1 The diagram shows the dimensions of the structure.
[0010] Figure 4 yes Figure 2 The diagram shows the dimensions of the structure.
[0011] Figure 5 This is a schematic diagram of the semiconductor packaging structure according to the second embodiment of this application;
[0012] Figure 6 This is a schematic diagram of the semiconductor packaging structure prepared in control group 1;
[0013] Figure 7 This is a schematic diagram of the semiconductor packaging structure prepared in control group 2;
[0014] Figure 8 This is a C-type scan of the first semiconductor package structure prepared in Experimental Group 1;
[0015] Figure 9 This is a T-scan image of the first semiconductor package structure prepared in Experimental Group 1;
[0016] Figure 10 This is a slice image of the first semiconductor package structure prepared in Experimental Group 1;
[0017] Figure 11 This is a slice image of the second semiconductor package structure prepared in Experimental Group 1;
[0018] Figure 12 This is a slice image of a region of the third semiconductor package structure prepared in control group 1;
[0019] Figure 13 This is a slice image of another region of the third semiconductor package structure prepared in control group 1;
[0020] Figure 14 This is a slice image of a region of the fourth semiconductor package structure prepared in control group 1;
[0021] Figure 15 This is a slice image of another region of the fourth semiconductor package structure prepared in control group 1;
[0022] Figure 16 This is a slice image of a region of the seventh semiconductor package structure prepared in control group 1;
[0023] Figure 17 This is a slice image of another region of the seventh semiconductor package structure prepared in control group 1.
[0024] Explanation of reference numerals in the attached figures:
[0025] 100a, 100b - Semiconductor package structure; 110 - Lead frame; 120 - First thermally conductive layer; 130 - Second thermally conductive layer; 140 - Electroplated silver layer; 150 - Chip; 160 - Molded package; 170 - Lead; 111 - Base island; 112 - Pin; 113 - First region; 114 - Second region; 131 - Chip encapsulation trench; S1 - First distribution area; S2 - Second distribution area; S3 - Third distribution area; d1 - First thickness; d2 - Second thickness; d3 - Third thickness; h1 - First height; h2 - Second height;
[0026] 200 - Semiconductor package structure; 210 - Lead frame; 220 - Electroplated silver layer; 230 - First thermally conductive layer; 240 - Chip; 250 - Molding body; 231 - Chip encapsulation groove;
[0027] 300 - Semiconductor package structure; 310 - Lead frame; 320 - Electroplated silver layer; 330 - Second thermal conductive layer; 340 - Chip; 350 - Molded package; 331 - Chip encapsulation groove. Detailed Implementation
[0028] To enable those skilled in the art to better understand the technical solutions of this application, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0029] Existing semiconductor packaging structures experience internal stresses due to injection molding, changes in external ambient temperature, or heat generated during chip operation. These internal stresses can lead to delamination defects within the semiconductor packaging structure, reducing its lifespan and potentially causing failure. To address this issue, the inventors propose the following implementation method.
[0030] Please see Figures 1-2 The semiconductor packaging structure 100a of the first embodiment of this application includes a lead frame 110, a first thermally conductive layer 120, a second thermally conductive layer 130, a chip 150, and a molding compound 160.
[0031] A first thermally conductive layer 120 is disposed on one surface of the lead frame 110 and contains first silver powder particles. A second thermally conductive layer 130 is disposed on the first thermally conductive layer 120 and contains resin and second silver powder particles, wherein the particle size of the first silver powder particles is smaller than that of the second silver powder particles. A chip 150 is disposed on the second thermally conductive layer 130, and the bottom surface and at least part of the sidewalls of the chip 150 are in contact with the second thermally conductive layer 130. A molding compound 160 covers the lead frame 110, the first thermally conductive layer 120, the second thermally conductive layer 130, and the chip 150.
[0032] In this manner, because the particle size of the first silver powder particles in the first thermally conductive layer 120 is smaller than that of the second silver powder particles in the second thermally conductive layer 130, the density of the first thermally conductive layer 120 is superior to that of the second thermally conductive layer 130. Therefore, the first thermally conductive layer 120 has good anti-wobbling ability. Thus, the first thermally conductive layer 120 can counteract the deformation stress from the lead frame 110, thereby suppressing or preventing delamination in the area beneath the chip 150. Since the second thermally conductive layer 130 contains resin, and the resin can partially counteract the frontal stress along the thickness direction of the chip 150, it can reduce delamination caused by frontal stress in the top area of the chip 150. Furthermore, compared to the first thermally conductive layer 120, the coefficient of thermal expansion of the resin-containing second thermally conductive layer 130 is closer to that of the molding compound 160, resulting in better adhesion between the second thermally conductive layer 130 and the molding compound 160. Thus, at least a portion of the sidewalls of chip 150 are connected to the molding compound 160 via the second thermally conductive layer 130, which can suppress or avoid delamination in the area where the sidewalls of chip 150 are located. In this way, through the cooperation of the first thermally conductive layer 120 and the second thermally conductive layer 130, delamination inside the semiconductor package structure 100a can be avoided or reduced.
[0033] Furthermore, to achieve better density in the first thermally conductive layer 120, the first silver powder particles in the first thermally conductive layer 120 can have a high mass percentage. For example, the first thermally conductive layer 120 can be sintered from fully sintered silver paste, and the mass percentage of the first silver powder particles in the first thermally conductive layer 120 is 95% or more. For example, and not limitingly, the matrix of the fully sintered silver paste contains no resin. Preferably, the density of the first thermally conductive layer 120 is greater than that of the second thermally conductive layer 130.
[0034] Optionally, to improve the ability of the second thermally conductive layer 130 to counteract the frontal stress along the thickness direction of the chip 150, the mass percentage of the second silver powder particles in the second thermally conductive layer 130 is less than the mass percentage of the first silver powder particles in the first thermally conductive layer 120. This allows for a relatively higher resin content in the second thermally conductive layer 130, thereby improving its ability to counteract the frontal stress along the thickness direction of the chip 150. Optionally, the second thermally conductive layer 130 is sintered from semi-sintered silver paste, and the mass percentage of the second silver powder particles in the second thermally conductive layer is 85% to 98%.
[0035] Optionally, to achieve better density in the first thermally conductive layer 120, the first silver powder particles in the first thermally conductive layer 120 can have a small particle size. For example, the particle size of the first silver powder particles is less than 1 μm. 。
[0036] Optionally, to improve the ability to counteract frontal stress along the thickness direction of the chip 150, the particle size of the second silver powder particles is greater than or equal to 1 μm. Further, the particle size of the second silver powder particles is 2–20 μm (e.g., 2 μm, 5 μm, 8 μm, 15 μm, 20 μm). Thus, a particle size greater than or equal to 2 μm allows for the placement of more resin between the second silver powder particles in the second thermally conductive layer 130, thereby improving the ability to counteract frontal stress along the thickness direction of the chip 150. Even further, the particle size of the second silver powder particles is 8–12 μm (e.g., 8 μm, 9 μm, 10 μm, 12 μm).
[0037] Optionally, combined Figure 2 See Figure 1 The second thermally conductive layer 130 covers the edge of the first thermally conductive layer 120. Alternatively, in other alternative embodiments, the second thermally conductive layer 130 does not cover the edge of the first thermally conductive layer 120, that is, the second thermally conductive layer 130 is exposed at the edge of the first thermally conductive layer 120.
[0038] Furthermore, participation Figure 1 See Figure 2 The semiconductor package structure 100a includes an electroplated silver layer 140, which forms between the first thermally conductive layer 120 and the lead frame 110.
[0039] The above method has at least two beneficial effects. First, by contacting the area of the lead frame 110 used to house the chip 150 with the electroplated silver layer 140, oxidation of the area of the lead frame 110 used to house the chip 150 can be avoided. Second, the adhesion between the fully sintered silver paste and the electroplated silver layer 140 is better than the adhesion between the fully sintered silver paste and the lead frame 110. Thus, the fully sintered silver paste is connected to the lead frame 110 through the electroplated silver layer 140, which can improve the bonding strength between the first thermally conductive layer 120 and the lead frame 110.
[0040] Optionally, combined Figures 1-2 See Figure 4 The thickness of the electroplated silver layer 140 is a first thickness d1, which is 1.78 to 7.62 μm (e.g., 1.78 μm, 2 μm, 4.56 μm, 7.62 μm).
[0041] Optionally, the semi-sintered silver paste includes resin, volatile materials, and second silver powder particles. It should be noted that the volatile materials in the semi-sintered silver paste will evaporate during the sintering process, thereby forming a second thermally conductive layer 130 including resin and second silver powder particles.
[0042] In this way, because the coefficient of thermal expansion of the semi-sintered silver paste is closer to that of the molding compound 160 than that of the fully sintered silver paste, which contains resin, the semi-sintered silver paste, comprising resin, volatile materials, and second silver powder particles, can avoid or reduce thermal stress delamination with the molding compound 160 caused by the difference in coefficients of thermal expansion during the sintering process to form the second thermally conductive layer 130 comprising resin and second silver powder particles. For example, and not as a limitation, the resin is epoxy resin.
[0043] Preferably, the inventors discovered that when the mass percentage of the second silver powder particles in the second thermally conductive layer 130 is greater than 80%, the thermal conductivity of the second thermally conductive layer 130 is greater than or equal to 100 W / mK. Based on this, in the semi-sintered silver paste, the mass percentages of the resin, volatile material, and second silver powder particles are respectively 5%–12% (e.g., 5%, 10%, 12%), 5%–10% (e.g., 5%, 7%, 10%), and 80%–95% (e.g., 80%, 90%, 95%). Thus, the thermal conductivity of the second thermally conductive layer 130 can be greater than or equal to 100 W / mK.
[0044] For example, and not as a limitation, the fully sintered silver paste includes first silver powder particles, 2-ethyl-1, and 3-hexanediol. The mass percentage of the first silver powder particles in the fully sintered silver paste is 85% to 95%. Optionally, the mass percentages of the first silver powder particles, 2-ethyl-1, and 3-hexanediol in the fully sintered silver paste can be found in the content of the corresponding components in the product with model number MAX102. That is, the fully sintered silver paste can be the product with model number MAX102, but is not limited to it.
[0045] Combination Figures 1-2 See Figure 3 The distribution area of the first heat-conducting layer 120 is the first distribution area S1, the distribution area of the second heat-conducting layer 130 is the second distribution area S2, and the distribution area of the chip 150 is the third distribution area S3. The first distribution area S1, the second distribution area S2, and the third distribution area S3 satisfy the first formula, which is:
[0046]
[0047] The above method enables the semiconductor package structure 100a to have sufficient thermal conductivity and sufficient bonding strength.
[0048] Optionally, the second thermally conductive layer 130 forms a chip encapsulation groove 131, into which the chip 150 is embedded. The bottom wall of the chip encapsulation groove 131 contacts the bottom surface of the chip 150, and the sidewalls of the chip encapsulation groove 131 contact the sidewalls of the chip 150. Thus, by embedding the chip 150 in the chip encapsulation groove 131, delamination in the top and sidewall areas of the chip 150 can be more effectively suppressed or avoided.
[0049] In a better way, combined with Figures 1-2 See Figure 4 The thickness of the first thermally conductive layer 120 is a second thickness d2, which is 20–200 μm (e.g., 20 μm, 110 μm, 200 μm). It should be noted that if the thickness of the first thermally conductive layer 120 is less than 20 μm, it may cause delamination within the semiconductor package structure 100a due to the deformation stress of the lead frame 110. If the thickness of the first thermally conductive layer 120 is greater than 200 μm, it will not only significantly increase the cost but also easily cause delamination within the semiconductor package structure 100a due to frontal stress. More preferably, the second thickness d2 is 20–100 μm (e.g., 20 μm, 50 μm, 60 μm, 100 μm).
[0050] Preferably, the thickness of the portion of the second thermal conductive layer 130 located on the bottom wall of the chip covering groove 131 is a third thickness d3, which is 15 to 185 μm (e.g., 15 μm, 100 μm, 185 μm).
[0051] In the manner described above, the second thickness d2 and the third thickness d3 cooperate to reduce or suppress delamination within the semiconductor package structure 100a corresponding to the chip 150 with a larger aspect ratio. The chip 150 with a larger aspect ratio has, for example, mutually perpendicular length and width directions. Both the length and width directions are perpendicular to the thickness direction of the chip 150. The chip 150 has a first dimension in the length direction and a second dimension in the width direction. This larger aspect ratio can be expressed as: the ratio of the first dimension to the second dimension is 2:1 to 10:1 (e.g., 2:1, 5:1, 10:1). Further, the ratio of the first dimension to the second dimension is 5.5:1 to 7.5:1 (e.g., 5.5:1, 6:1, 7.5:1). Even further, the ratio of the first dimension to the second dimension is 6.4:1.
[0052] Optionally, combined Figure 1 See Figure 2The height of the sidewall of the chip covering groove 131 is a first height h1, and the height of the chip is a second height h2, with the first height h1 being lower than the second height h2. Furthermore, the first height h1 is 20%-90% (e.g., 20%, 55%, 90%) of the second height h2. This prevents delamination in the area where the bottom surface of the chip 150 or the area where the sidewall of the chip 150 is located.
[0053] contrast Figures 1-2 See Figure 5 The parts of the semiconductor packaging structure 100b in the second embodiment of this application that are the same as those of the semiconductor packaging structure 100a in the first embodiment described above will not be repeated here. The following are further limitations.
[0054] The lead frame 110 includes a base island 111 and a plurality of pins 112, with each pin 112 spaced apart on the outer periphery of the base island 111. A first thermally conductive layer 120 is disposed on the base island 111. An electrode (not shown) is provided on the upper surface of the chip 150, and the electrode is electrically connected to the pins 112 via leads 170. A molding compound 160 covers the base island 111 and part of the pins 112, and encapsulates the leads 170. Optionally, an electroplated silver layer 140 is formed between the first thermally conductive layer 120 and the base island 111.
[0055] Furthermore, such as Figure 5 As shown, pin 112 has a first region 113, which is a region encapsulated within the molding compound 160. The base island 111 has a second region 114 on the side opposite to the chip 150, which is a region exposed outside the molding compound 160. Thus, the heat dissipation efficiency of the base island 111 can be improved by exposing the second region outside the molding compound 160.
[0056] The following combination Figures 1-2 The method for preparing the semiconductor package structure 100a is described, which includes the following steps S110 to S120.
[0057] Step S110: Provide lead frame 110.
[0058] Step S120: A first thermally conductive layer 120, a second thermally conductive layer 130, a chip 150, and a molding compound 160 are formed sequentially on the lead frame 110.
[0059] The second thermally conductive layer 130 has a chip encapsulation groove 131. The bottom wall of the chip encapsulation groove 131 contacts the bottom surface of the chip 150, and the sidewalls of the chip encapsulation groove 131 contact the sidewalls of the chip 150. The molding compound 160 covers the lead frame 110, the first thermally conductive layer 120, the second thermally conductive layer 130, and the chip 150. The first thermally conductive layer 120 is formed by sintering fully sintered silver paste; the second thermally conductive layer 130 is formed by sintering semi-sintered silver paste.
[0060] For example, and not as a limitation, the semi-sintered silver paste is applied to the fully sintered silver paste when it is in a wet or dry state, and the chip 150 is attached to the semi-sintered silver paste when it is in a wet state.
[0061] In one example, the coating thickness of the fully sintered silver paste is 30–210 μm (e.g., 30 μm, 60 μm, 110 μm, 210 μm) to shrink after sintering to form a first thermally conductive layer 120 with a thickness of 20–200 μm (e.g., 20 μm, 50 μm, 100 μm, 200 μm). The coating thickness of the semi-sintered silver paste is 30–205 μm (e.g., 30 μm, 70 μm, 120 μm, 205 μm) to form a second thermally conductive layer 130 after sintering, and the thickness of the portion of the second thermally conductive layer 130 located on the bottom wall of the chip covering groove 131 is 15–185 μm (e.g., 15 μm, 50 μm, 100 μm, 185 μm).
[0062] For example, and not as a limitation, the fully sintered silver paste will shrink by about 10 μm after sintering, and the semi-sintered silver paste will shrink by 15 to 20 μm (e.g., 15 μm, 17 μm, 20 μm) after sintering.
[0063] Preferably, in order to take into account the glue aging time control and UPH (units per hour) factors, a dual-dip glue head mounting machine is used when applying fully sintered silver glue and semi-sintered silver glue.
[0064] As an example, and not a limitation, the material of chip 150 includes at least SiC (silicon carbide), or at least GaN (gallium carbide). For example, the material of chip 150 can be GaN-on-SiC (silicon carbide-based gallium carbide). Thus, chip 150 based on SiC and GaN has the advantages of high voltage resistance, high thermal conductivity, and low power consumption, making it suitable for applications in 5G base stations and the new energy industry.
[0065] The semiconductor packaging structure 100a of this application will be further described below with reference to specific embodiments.
[0066] Experimental group 1
[0067] See also Figures 1-2 The method for preparing the semiconductor packaging structure 100a in the experimental group includes the following steps S11 to S16.
[0068] Step S11: Provide a lead frame 110 and a chip 150, and provide an electroplated silver layer 140 on the lead frame 110.
[0069] The distribution area of the lead frame 110 is larger than that of the chip 150. The chip 150 has a first dimension in the length direction and a second dimension in the width direction, with the ratio of the first dimension to the second dimension being 6.4:1.
[0070] Step S12: Apply fully sintered silver paste to the electroplated silver layer 140 to form the first coating layer.
[0071] Specifically, the thickness of the first coating layer is 30–210 μm, and the fully sintered silver paste is a product with the model number MAX102.
[0072] Step S13: Apply semi-sintered silver paste to the first coating layer to form a second coating layer.
[0073] The semi-sintered silver paste comprises resin, volatile materials, and a second layer of silver powder particles. In the semi-sintered silver paste, the mass percentages of the resin, volatile materials, and second layer of silver powder particles are 5%–12%, 5%–10% (e.g., 5%, 7%, 10%), and 88%–95% (e.g., 88%, 91%, 95%), respectively. The thickness of the second coating layer is 30–205 μm.
[0074] Semi-sintered silver paste can be applied to the first coating layer when the fully sintered silver paste of the first coating layer is in a wet state or a dry state. A wet state refers to a state where it is not fully sintered and cured and remains moist. A dry state refers to a state where it is fully sintered and cured and is in a dry state.
[0075] Step S14: When the semi-sintered silver paste of the second coating layer is in a wet state, the provided chip 150 is attached to the semi-sintered silver paste, and the second coating layer forms a chip covering groove 131 with a thickness of at least covering the chip 150.
[0076] In order to form the chip encapsulation groove 131, the chip 150 is attached to the second coating layer when the semi-sintered silver paste is in a wet state, so that the chip 150 can be squeezed into the second coating layer to form the chip encapsulation groove 131 on the second coating layer.
[0077] Step S15: Sinter the first coating layer and the second coating layer to form the first thermally conductive layer 120 and the second thermally conductive layer 130.
[0078] The first coating layer shrinks after sintering to form a first thermally conductive layer 120 with a thickness of 20 to 200 μm, and the second coating layer forms a second thermally conductive layer 130 after sintering. The thickness of the portion of the second thermally conductive layer 130 located on the bottom wall of the chip coating groove 131 is 15 to 185 μm.
[0079] Step S16: A molding compound 160 is formed on the chip 150. The molding compound 160 covers the lead frame 110, the electroplated silver layer 140, the first thermal conductive layer 120, the second thermal conductive layer 130 and the chip 150 to obtain the semiconductor packaging structure 100a of Experimental Group 1.
[0080] Control group 1
[0081] contrast Figures 1-2 Referring to 6, the main difference between the semiconductor packaging structure 200 of the control group 1 and the semiconductor packaging structure 100a of the experimental group 1 is that the semiconductor packaging structure 200 of the control group 1 does not have a second heat-conducting layer 130. The preparation method of the semiconductor packaging structure 200 of the control group 1 includes the following steps S21 to S25.
[0082] Step S21: Provide a lead frame 210 and a chip 240, and provide an electroplated silver layer 220 on the lead frame 210.
[0083] The distribution area of the lead frame 210 is larger than that of the chip 240. The chip 240 has a first dimension in the length direction and a second dimension in the width direction, with the ratio of the first dimension to the second dimension being 6.4:1.
[0084] Step S22: Apply fully sintered silver paste to the electroplated silver layer 220 to form the first coating layer.
[0085] Specifically, the thickness of the first coating layer is 30–210 μm, and the fully sintered silver paste is a product with the model number MAX102.
[0086] Step S23: When the fully sintered silver paste of the first coating layer is in a wet state, the provided chip 240 is attached to the fully sintered silver paste, and the first coating layer forms a chip covering groove 231 with a thickness of at least a portion covering the chip 240.
[0087] Step S24: Sinter the first coating layer to form the first thermally conductive layer 230.
[0088] The first coating layer shrinks after sintering to form a first thermally conductive layer 230 with a thickness of 20 to 200 μm.
[0089] Step S25: A molding compound 250 is formed on the chip 240. The molding compound 250 covers the lead frame 210, the electroplated silver layer 220, the first thermal conductive layer 230 and the chip 240 to obtain the semiconductor packaging structure 200 of the control group 1.
[0090] Control group 2:
[0091] contrast Figures 1-2Referring to 7, the main difference between the semiconductor packaging structure 300 of control group 2 and the semiconductor packaging structure 100a of experimental group 1 is that the semiconductor packaging structure 300 of control group 2 does not have a first thermal conductive layer 120. The preparation method of the semiconductor packaging structure 300 of control group 2 includes the following steps S31 to S35.
[0092] Step S31: Provide a lead frame 310 and a chip 340, and provide an electroplated silver layer 320 on the lead frame 310.
[0093] The distribution area of the lead frame 310 is larger than that of the chip 340. The chip 340 has a first dimension in the length direction and a second dimension in the width direction, with the ratio of the first dimension to the second dimension being 6.4:1.
[0094] Step S32: A semi-sintered silver paste is applied to the electroplated silver layer 320 to form a second coating layer.
[0095] The semi-sintered silver paste comprises resin, volatile materials, and a second layer of silver powder particles. In the semi-sintered silver paste, the mass percentages of the resin, volatile materials, and second layer of silver powder particles are 5%–12%, 5%–10% (e.g., 5%, 7%, 10%), and 88%–95% (e.g., 88%, 91%, 95%), respectively. The thickness of the second coating layer is 30–205 μm.
[0096] Step S33: When the semi-sintered silver paste of the second coating layer is in a wet state, the provided chip 340 is attached to the semi-sintered silver paste, and the second coating layer forms a chip covering groove 331 with a thickness of at least covering the chip 340.
[0097] Step S34: Sinter the second coating layer to form the second thermally conductive layer 330.
[0098] The second coating layer forms a second thermally conductive layer 330 after sintering, and the thickness of the portion of the second thermally conductive layer 330 located on the bottom wall of the chip coating groove 331 is 15 to 185 μm.
[0099] Step S35: A molding compound 350 is formed on the chip 340. The molding compound 350 covers the lead frame 310, the electroplated silver layer 320, the second thermal conductive layer 330 and the chip 340 to obtain the semiconductor package structure 300 of the control group 2.
[0100] The semiconductor packaging structures prepared in the above embodiments were then subjected to a 500-hour temperature cycling test, referred to as TC500H. Specifically, in TC500H, each cycle included maintaining the prepared semiconductor packaging structure at 150 degrees Celsius for 15 minutes, then cooling it to -65 degrees Celsius within 15 minutes, maintaining it at -65 degrees Celsius for 15 minutes, and then raising the temperature from -65 degrees Celsius back to 150 degrees Celsius to complete one cycle.
[0101] Experiment 1
[0102] The semiconductor package structure 100a prepared in Experimental Group 1 was used as the first semiconductor package structure. After TC500H, the first semiconductor package structure was subjected to C-type scanning, T-type scanning, and slicing to obtain the desired results. Figure 8 , Figure 9 and Figure 10 Therefore, the results of Experiment 1 are as follows.
[0103] Combination Figures 1-2 See Figures 8-10 It can be seen that there is no obvious delamination between the sidewall of the chip 150 of the first semiconductor package structure and the part of the second thermal conductive layer 130 located on the sidewall of the chip covering groove 131, there is no obvious delamination in the top area of the chip 150, and there is no obvious delamination in the layers below the chip 150.
[0104] Experiment 2
[0105] A second semiconductor package structure was prepared according to the fabrication method of semiconductor package structure 100a in Experimental Group 1. The parts of the second semiconductor package structure that are the same as the first semiconductor package structure will not be described again. The difference is that the second thermally conductive layer 130 exposes the edge of the first thermally conductive layer 120. The second semiconductor package structure was sliced to obtain... Figure 11 Therefore, the results of Experiment 2 are as follows.
[0106] Comparison Figures 1-2 See Figure 11 It can be seen that there is no obvious delamination between the sidewall of the chip 150 of the second semiconductor package structure and the part of the second thermal conductive layer 130 located on the sidewall of the chip covering groove 131, there is no obvious delamination in the top area of the chip 150, and there is no obvious delamination in the layers below the chip 150.
[0107] Experiment 3
[0108] A third semiconductor package structure was prepared using the same method as the semiconductor package structure 200 in control group 1. This third semiconductor package structure is a 30 μm thick semiconductor package structure 200 in which the first thermally conductive layer 230 is located on the bottom wall of the chip encapsulation trench 231. The third semiconductor package structure was sliced to obtain... Figure 12and Figure 13 Therefore, the results of Experiment 3 are as follows.
[0109] Combination Figure 6 See Figure 12 As shown, in the third semiconductor package structure, there is a clear delamination between the sidewall of the chip 240 and the portion of the first thermally conductive layer 230 located on the sidewall of the chip encapsulation trench 231. This delamination is as follows: Figure 12 As shown within the dashed circle. Combined with... Figure 6 See Figure 13 As shown, there is a clear separation between the top of chip 240 and the molding compound 250, as follows: Figure 13 As shown inside the dashed circle.
[0110] Experiment 4
[0111] A fourth semiconductor package structure was prepared using the same method as the semiconductor package structure 200 in control group 1. This fourth semiconductor package structure is a 50 μm thick semiconductor package structure 200 in which the first thermally conductive layer 230 is located on the bottom wall of the chip encapsulation trench 231. The fourth semiconductor package structure was sliced to obtain... Figure 14 and Figure 15 Therefore, the results of Experiment 4 are as follows.
[0112] Combination Figure 6 See Figure 14 As shown, in the fourth semiconductor package structure, there is a clear delamination between the sidewall of the chip 240 and the portion of the first thermally conductive layer 230 located on the sidewall of the chip encapsulation trench 231. This delamination is as follows: Figure 14 As shown within the dashed circle. Combined with... Figure 6 See Figure 15 As shown, there is a clear separation between the top of chip 240 and the molding compound 250, as follows: Figure 15 As shown inside the dashed circle.
[0113] Experiment 5
[0114] A seventh semiconductor package structure was prepared using the same method as the semiconductor package structure 300 in control group 2. This seventh semiconductor package structure is a 50 μm thick semiconductor package structure 300 in which the second thermally conductive layer 330 is located on the bottom wall of the chip encapsulation trench 331. The seventh semiconductor package structure was sliced to obtain... Figure 16 and Figure 17 Therefore, the results of Experiment 5 are as follows.
[0115] Combination Figure 7 See Figure 16As shown, in the seventh semiconductor package structure, there is no obvious delamination between the sidewall of chip 340 and the portion of the first thermal conductive layer 330 located on the sidewall of the chip covering groove 331. However, the second thermal conductive layer 330 below chip 340 exhibits obvious delamination, as shown in the figure. Figure 16 As shown within the dashed circle. Combined with... Figure 7 See Figure 17 As shown, there is no obvious separation between the top of chip 340 and the molding compound 350.
[0116] In summary, the results of experiments 3 and 4 show that increasing the thickness of the first thermally conductive layer 230 is insufficient to solve the delamination problem between the sidewall of the chip 240 and the portion of the first thermally conductive layer 230 located on the sidewall of the chip encapsulation groove 231. The results of experiment 5 show that relying solely on the second thermally conductive layer 330 is insufficient to solve the delamination problem of the second thermally conductive layer 330. Comparing the results of experiments 3 and 5 with those of experiments 1 and 2, it is evident that the combined action of the first thermally conductive layer 120, the second thermally conductive layer 130, and the chip encapsulation groove 131 in experiments 1 and 2 can resolve the delamination problem between the sidewall of the chip 240 and the portion of the first thermally conductive layer 230 located on the sidewall of the chip encapsulation groove 231 present in experiments 3 and 4, as well as the delamination problem of the second thermally conductive layer 330 present in experiment 5.
[0117] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.
Claims
1. A semiconductor packaging structure, characterized in that, The semiconductor packaging structure includes: Lead frame; A first thermally conductive layer is disposed on one surface of the lead frame and contains first silver powder particles; The second thermally conductive layer is disposed on the first thermally conductive layer and includes resin and second silver powder particles, wherein the particle size of the first silver powder particles is smaller than the particle size of the second silver powder particles. A chip is disposed on the second thermal conductive layer, and the bottom surface and at least part of the sidewalls of the chip are in contact with the second thermal conductive layer; And a molding compound covering the lead frame, the first thermally conductive layer, the second thermally conductive layer and the chip.
2. The semiconductor packaging structure according to claim 1, characterized in that, The first thermal conductive layer is sintered from fully sintered silver paste, and the mass percentage of the first silver powder particles in the first thermal conductive layer is more than 95%.
3. The semiconductor packaging structure according to claim 1, characterized in that, The mass percentage of the second silver powder particles in the second thermal conductive layer is less than the mass percentage of the first silver powder particles in the first thermal conductive layer.
4. The semiconductor packaging structure according to claim 1, characterized in that, The first silver powder particle has a particle size of less than 1 μm, and the second silver powder particle has a particle size of greater than or equal to 1 μm.
5. The semiconductor packaging structure according to claim 1, characterized in that, The particle size of the second silver powder particles is 2~20μm.
6. The semiconductor packaging structure according to claim 1, characterized in that, The second thermal conductive layer is formed by sintering semi-sintered silver paste, and the mass percentage of the second silver powder particles in the second thermal conductive layer is 85%~98%.
7. The semiconductor packaging structure according to claim 1, characterized in that, The thickness of the first thermally conductive layer is 20~200μm.
8. The semiconductor packaging structure according to claim 1, characterized in that, The lead frame includes a base island and a plurality of pins, each pin being spaced apart on the outer periphery of the base island; a first thermally conductive layer is disposed on the base island; an electrode is provided on the upper surface of the chip, the electrode being electrically connected to the pins via leads; the molding compound covers the base island and part of the pins, and encapsulates the leads.
9. The semiconductor packaging structure according to claim 8, characterized in that, The pin has a first region, which is a region covered by the molding compound; the base island has a second region on the side opposite to the chip, which is a region exposed in the molding compound.
10. The semiconductor packaging structure according to claim 1, characterized in that, The semiconductor package structure includes an electroplated silver layer formed between the first thermally conductive layer and the lead frame.
11. The semiconductor packaging structure according to claim 10, characterized in that, The thickness of the electroplated silver layer is 1.78~7.62μm.
12. The semiconductor packaging structure according to claim 1, characterized in that, The thermal conductivity of the chip is greater than or equal to 100 W / mK.
13. The semiconductor packaging structure according to claim 1, characterized in that, The distribution area of the first thermally conductive layer is a first distribution area S1, the distribution area of the second thermally conductive layer is a second distribution area S2, and the distribution area of the chip is a third distribution area S3. The first distribution area S1, the second distribution area S2, and the third distribution area S3 satisfy a first formula, which is: 。 14. The semiconductor packaging structure according to claim 1, characterized in that, The second thermally conductive layer has a chip encapsulation groove, in which the chip is embedded. The bottom wall of the chip encapsulation groove is in contact with the bottom surface of the chip, and the side wall of the chip encapsulation groove is in contact with the side wall of the chip.
15. The semiconductor packaging structure according to claim 14, characterized in that, The thickness of the second thermal conductive layer located on the bottom wall of the chip coating groove is 15~185μm.
16. The semiconductor packaging structure according to claim 1, characterized in that, The chip has a length direction and a width direction that are perpendicular to each other; the chip has a first dimension in the length direction and a second dimension in the width direction, and the ratio of the first dimension to the second dimension is 2:1 to 10:
1.
17. The semiconductor packaging structure according to claim 16, characterized in that, The ratio of the first dimension to the second dimension is 5.5:1 to 7.5:
1.
18. The semiconductor packaging structure according to claim 14, characterized in that, The height of the sidewall of the chip covering groove is lower than the height of the chip.
19. The semiconductor packaging structure according to claim 14, characterized in that, The height of the sidewall of the chip coating groove is 20%-90% of the height of the chip.
20. The semiconductor packaging structure according to claim 1, characterized in that, The second thermally conductive layer covers or exposes the edge of the first thermally conductive layer.
21. The semiconductor packaging structure according to claim 1, characterized in that: The density of the first thermally conductive layer is greater than that of the second thermally conductive layer.