A semiconductor device terminal structure based on multi-level trenches

Abstract

The present invention provides a semiconductor device terminal structure based on multi-level trenches, belonging to the field of semiconductor device technology. The semiconductor device terminal structure includes a substrate, a drift region located on the substrate, a cathode located on the back of the substrate, and an anode. The drift region includes a main junction region and a junction termination region adjacent to the main junction region. The main junction region includes a first doped region. The junction termination region includes at least one third doped region connected to the first doped region and at least one multi-level trench having a stepped structure. The outer wall of the multi-level trench is provided with a second doped region, the interior of which is filled with a dielectric layer. The anode is electrically connected to the first doped region and the third doped region. The substrate and the drift region have the same doping type. The second doped region, the third doped region, and the first doped region have the same doping type, which is opposite to the doping type of the substrate. The semiconductor device terminal structure can achieve charge balance between the main junction region and the terminal region, thereby improving the breakdown voltage of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a semiconductor device terminal structure based on multi-level trenches. Background Art

[0002] In the blocking state, a metal-oxide-semiconductor field-effect transistor (MOSFET) primarily carries voltage through the depletion region formed by the PN junction under reverse bias. According to Poisson's equation, the peak electric field strength in the depletion region is located near the PN junction. When the peak electric field strength reaches the critical breakdown electric field strength of the semiconductor material, the device will break down. Without considering the influence of the junction termination effect, the device breakdown voltage is determined solely by device parameters such as the doping concentration and the thickness of the substrate or epitaxial layer. However, in actual semiconductor devices, due to the limited device size, the PN junction is discontinuous at the device edge, resulting in curvature at the edges and corners of the PN junction. Due to the curvature effect, the electric field on the device surface is more concentrated, resulting in severe degradation of the device's blocking performance and a breakdown voltage far lower than ideal.

[0003] Therefore, in the actual fabrication of MOSFET devices, in order to alleviate the problem of premature breakdown at the edges and corners of the PN junction due to the curvature effect, resulting in reduced device blocking capability, a junction termination structure is often formed around the PN junction (main junction). The introduced junction termination structure can disperse the electric field originally concentrated at the edge of the main junction, thereby reducing the electric field strength at the edge of the main junction and increasing the device's breakdown voltage. However, for SiC materials, due to the extremely low diffusion coefficient of impurities in SiC materials, doping of SiC materials is often performed through high-temperature ion implantation to form a shallow PN junction. This results in a smaller curvature radius of the PN junction of SiC power devices, making it easier for the electric field to concentrate, further reducing the device's blocking capability and the protection capability of the junction termination. Furthermore, for SiC superjunction devices, the formed P-pillar structure extends deep into the device's drift region, and the electric field is also concentrated deep in the drift region. However, due to the limitations of structural design and the depth of ion implantation in SiC, traditional termination structures can only alleviate the problem of the electric field near the surface of the drift region and cannot protect the PN junction deep in the drift region. Therefore, it is necessary to develop a new junction terminal structure to alleviate the problem of electric field strength concentration in the PN junction (main junction) represented by the super junction or the PN junction (main junction) deep in the drift region, and to solve the problem of charge imbalance between the main junction region and the terminal region. Summary of the Invention

[0004] To address the above issues, the present invention provides a semiconductor device junction termination structure based on multi-level trenches. This semiconductor device junction termination structure can reduce the electric field at the edge of the main junction region deep in the drift region, ensure charge balance between the main junction region and the termination region, and improve termination efficiency.

[0005] Specifically, the present invention adopts the following technical solutions:

[0006] A semiconductor device terminal structure based on multi-level trenches, comprising a substrate, a drift region located on the substrate, a cathode located on a side of the substrate facing away from the drift region, and an anode; the drift region comprises a main junction region and a junction termination region adjacent to the main junction region; the main junction region comprises a first doping region; the junction termination region comprises at least one third doping region and at least one multi-level trench having a stepped structure; the third doping region is connected to the first doping region, and the multi-level trench is located on a side of the third doping region facing away from the first doping region; the number n of the multi-level trenches is an integer ≥ 2; the multi-level trenches extend from a surface of the drift region facing away from the substrate toward the substrate; a second doping region is provided on an outer wall of the multi-level trench; a dielectric layer is filled inside the multi-level trench; at least a portion of the anode is located on a surface of the first doping region facing away from the substrate and extends to a surface of the third doping region facing away from the substrate; the substrate and the drift region have the same doping type; the second doping region, the third doping region, and the first doping region have the same doping type, and are opposite to the doping type of the drift region.

[0007] In some embodiments, the dielectric layer is an insulating dielectric layer, and the insulating dielectric layer extends from the surface of the drift region away from the substrate to the interior of the multi-level trench; the anode extends from the surface of the third doping region away from the substrate to the surface of the insulating dielectric layer away from the drift region, forming a field plate on the surface of the insulating dielectric layer.

[0008] In some embodiments, in the direction from the drift region to the substrate, a junction terminal extension structure formed by at least one fourth doping region is provided on the side of the multi-level trench away from the third doping region, and the fourth doping region is directly connected to the second doping region, and its doping type is the same as the doping type of the second doping region.

[0009] In some embodiments, a surface of the drift region facing away from the substrate forms an inclined surface on a side of the multi-level trench away from the third doping region.

[0010] In some embodiments, a plurality of floating field limiting rings formed by a plurality of fifth doping regions are provided on a side of the multi-level trench away from the third doping region, and the plurality of floating field limiting rings are arranged in sequence along the direction from the main junction region to the junction terminal region.

[0011] In some embodiments, the sidewalls on both opposite sides of the multi-level trench are stepped structures, and a second doped region is disposed around the outer wall of the multi-level trench. In other embodiments, only one sidewall of the multi-level trench is stepped, and a second doped region is disposed along the outer wall of the stepped structure to the bottom outer wall of the multi-level trench. In still other embodiments, only one sidewall of the multi-level trench is stepped, and a second doped region is disposed around the outer wall of the multi-level trench.

[0012] In some embodiments, the sidewalls on both sides of the multi-stage groove are symmetrical step structures. In other embodiments, the sidewalls on both sides of the multi-stage groove are asymmetrical step structures.

[0013] In some embodiments, the anode extends in a direction from the main junction region to the junction terminal region to cover a plurality of the multi-stage trenches and is electrically connected to a plurality of the second doping regions; or, on a side close to the first doping region, the third doping regions are alternately arranged with a portion of the multi-stage trenches and directly connected to the second doping regions, the anode is electrically connected to the third doping region between two adjacent multi-stage trenches, and the second doping regions on the outer walls of the multi-stage trenches away from the first doping region are in a floating state. In other embodiments, the second doping regions on the outer walls of all the multi-stage trenches are in a floating state.

[0014] In some embodiments, the doping concentration of at least two of the first doping region, the second doping region, and the third doping region is the same.

[0015] In some embodiments, the spacing between the multi-level trenches increases gradually along the direction from the main junction region to the junction termination region. In other embodiments, the spacing between the multi-level trenches is equal along the direction from the main junction region to the junction termination region.

[0016] In some embodiments, the number of levels of each of the multi-level trenches is the same. In other embodiments, the number of levels of the multi-level trenches gradually decreases along the direction from the main junction region to the junction termination region.

[0017] In some embodiments, each step of the multi-step trench has a different width in a direction from the main junction region to the junction termination region.

[0018] In some embodiments, each step of the multi-step trench has the same height in a direction from the substrate to the drift region.

[0019] In some embodiments, the depth of the second doped region along the direction from the drift region to the substrate is the same as the depth of the first doped region. In other embodiments, the depth of the second doped region along the direction from the drift region to the substrate is less than the depth of the first doped region. In still other embodiments, the depth of the second doped region along the direction from the drift region to the substrate is greater than the depth of the first doped region.

[0020] In some embodiments, the dielectric layer is a semiconductor layer, and the doping type of the semiconductor layer is the same as the doping type of the first doping region.

[0021] The present invention has the following beneficial effects: The semiconductor device terminal structure of the present invention provides at least one trench with a multi-step structure in the junction termination region, and a second doped region is provided on the trench sidewall. This ensures that when the device is in a reverse blocking state, the second doped region located deep within the drift region along the direction from the main junction region to the junction termination region can ensure charge balance between the main junction region and the junction termination region. The dielectric layer within the multi-step trench can disperse and bear the electric field, alleviating the problem of premature breakdown of the longitudinal or lateral PN junction at the edge of the main junction region, thereby improving the device's breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a semiconductor device terminal structure provided by an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0024] Figure 3 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0025] Figure 4 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0026] Figure 5 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0027] Figure 6 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0028] Figure 7 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0029] Figure 8 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0030] Figure 9 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0031] Figure 10 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0032] Figure 11 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0033] Figure 12 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0034] Figure 13 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0035] Figure 14 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0036] Figure 15 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0037] Figure 16 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0038] Figure 17 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0039] Figure 18 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0040] Figure 19 A schematic diagram of another semiconductor device terminal structure provided by an embodiment of the present invention;

[0041] Figure 20 It is a structural diagram of simulation structure 1;

[0042] Figure 21 Schematic diagram of doping concentration distribution of simulation structure 1;

[0043] Figure 22 Schematic diagram of the electric field intensity distribution of the simulated structure 1 at the breakdown moment;

[0044] Figure 23 It is the structural diagram of simulation structure 2;

[0045] Figure 24 Schematic diagram of doping concentration distribution of simulation structure 2;

[0046] Figure 25 Schematic diagram of the electric field intensity distribution of the simulated structure 2 at the breakdown moment;

[0047] Figure 26 It is the structural diagram of simulation structure three;

[0048] Figure 27 Schematic diagram of doping concentration distribution of simulation structure three;

[0049] Figure 28 Schematic diagram of the electric field intensity distribution of the simulated structure 3 at the breakdown moment;

[0050] Figure 29 It is the structural diagram of simulation structure 4;

[0051] Figure 30 Schematic diagram of doping concentration distribution of simulation structure 4;

[0052] Figure 31 Schematic diagram of the electric field intensity distribution of the simulated structure 4 at the breakdown moment;

[0053] Figure 32 A comparison chart of the breakdown characteristic curves of simulation structures one, two, three, and four.

[0054] In the figure: 101, substrate; 102, drift region; 103, cathode; 104, anode; 105, first doping region; 106, third doping region; 107, multi-level trench; 108, second doping region; 109, dielectric layer; 110, field plate; 111, fourth doping region; 112, inclined surface; 113, fifth doping region; A, main junction region; B, junction termination region. DETAILED DESCRIPTION

[0055] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the embodiments, so that those skilled in the art can fully understand the present invention. Obviously, the embodiments described are only some preferred embodiments of the present invention, rather than all embodiments. Any equivalent transformations or substitutions made by those skilled in the art to the following embodiments without creative work are within the scope of protection of the present invention.

[0056] Directional terms used in this disclosure, such as "upper," "lower," "inner," "outer," "bottom," and "upper surface," indicate positions or locations based on the positions or locations in the accompanying drawings or the positions or locations in which the product of this disclosure is typically placed during use. These terms are intended solely to facilitate the description and understanding of the product structure of this disclosure. Therefore, these directional terms should not be construed as limiting this disclosure. In this disclosure, unless otherwise expressly specified, expressions such as "upper," "above," "above," and "upper surface" of a first feature relative to a second feature indicate that the first and second features may be in direct contact or indirect contact through an intermediary; that the first feature may be directly above or diagonally above the second feature, or simply indicate that the first feature is at a higher level than the second feature. Expressions such as "lower," "below," "below," and "lower surface" of a first feature relative to a second feature indicate that the first and second features may be in direct contact or indirect contact through an intermediary; that the first feature may be directly below or diagonally below the second feature, or simply indicate that the first feature is at a lower level than the second feature. The ordinal numbers used in the present invention, such as "first", "second", etc., are only used for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0057] In order to better understand the present invention, Figures 1 to 19 , a specific embodiment of the semiconductor device terminal structure of the present invention is described in detail. In the figure, A is the main junction region, which also has the function of a transition region.

[0058] like Figure 1FIG2 is a schematic diagram of a semiconductor device terminal structure based on multi-level trenches provided in an embodiment of the present invention. The semiconductor device terminal structure includes a substrate 101, a drift region 102 located on the substrate 101, a cathode 103, and an anode 104. The cathode 103 is located on the side of the substrate 101 facing away from the drift region 102, that is, the cathode 103 is located on the bottom surface of the substrate 101. The drift region 102 includes a main junction region A and a terminal region B, and the terminal region B is adjacent to the main junction region A. The main junction region A includes a first doped region 105. The junction terminal region B includes a third doped region 106 and a plurality of multi-level trenches 107. The third doped region 106 is directly connected to the first doped region 105. The multi-level trenches 107 are located on the side of the third doped region 106 away from the first doped region 105. The opposite sidewalls of the multi-level trenches 107 are symmetrical step structures, and the number of trench levels n is an integer ≥ 2 (for example, n = 3). The multi-level trench 107 extends from the side of the drift region 102 facing away from the substrate 101 toward the substrate 101. Along the drift region 102 toward the substrate 101, the size of each sub-trench gradually decreases along the direction from the main junction region A to the junction termination region B. Specifically, the multi-level trench 107 extends from the top surface of the drift region 102 toward the interior of the drift region 102, with its opening located at the top surface of the drift region 102. From its opening to its bottom, the size of each sub-trench gradually decreases. A second doped region 108 is disposed around the outer wall of the multi-level trench 107. The second doped region 108 is directly connected to the third doped region 106. The second doped region 108 can be formed by homoepitaxial growth after etching the multi-level trench. The interior of the multi-level trench 107 is filled with a dielectric layer 109, which is an insulating dielectric layer. The anode 104 is located on the side of the main junction region A facing away from the substrate 101 and extends to the side of the third doped region 106 facing away from the substrate 101. Specifically, the anode 104 is located on the upper surfaces of the first doped region 105 and the third doped region 106, electrically connecting the third doped region 106 to the anode 104. This also electrically connects the second doped region 108, which is directly connected to the third doped region 106, to the anode 104. The doping type of the substrate 101 is the same as that of the drift region 102. The doping types of the second doped region 108 and the third doped region 106 are the same as that of the first doped region 105. However, the doping type of the first doped region 105 is opposite to that of the substrate 101 (or the drift region 102). That is, when the substrate 101 is n-doped, the drift region 102 is also n-doped, and the first doping region 105, the second doping region 108, and the third doping region 106 are all p-doped. Therefore, the pn junction formed by the first doping region 105 and the drift region 102 in the main junction region A is the main junction. When the substrate 101 is p-doped, the drift region 102 is also p-doped, and the first doping region 105, the second doping region 108, and the third doping region 106 are all n-doped. Therefore, the pn junction formed by the first doping region 105 and the drift region 102 in the main junction region A is the main junction.

[0059] It can be understood that the number of second doping regions 108 (or the number of multi-level trenches 107) and doping concentration, the spacing between multiple multi-level trenches 107, the size of each step of the multi-level trench 107 along the direction from the main junction region A to the junction terminal region B, the size of each step of the multi-level trench 107 along the direction from the drift region to the substrate, the number of levels of each multi-level trench 107, and the material of the filling medium inside the multi-level trench 107 can all be adjusted according to actual needs.

[0060] In the direction from the drift region 102 to the substrate 101, the doping depth of the second doping region 108 may be the same as the doping depth of the first doping region 105, or may be smaller than the doping depth of the first doping region 105 (e.g., Figure 2 ), and can also be greater than the doping depth of the first doping region 105 (as shown in Figure 3 The doping concentrations of the first doping region 105, the second doping region 108, and the third doping region 106 can be as follows: Figure 1 The same is true for Figure 4 In the direction from the main junction region A to the junction termination region B, the number of levels of each multi-level trench 107 can be as follows: Figure 1 The same as shown, can also be Figure 5 The multi-level groove 107 can be as shown. Figure 1 As shown, a symmetrical step structure is provided on the two opposite side walls, or it can be as follows Figure 6 and Figure 7 As shown, an asymmetric step structure is provided on the opposite sidewalls, and the second doping region 108 is provided around the outer wall of the multi-level trench 107; it can also be as follows Figure 8 and Figure 9 As shown, the step structure is provided on only one side of the sidewall, and the second doping region 108 is provided around the outer wall of the multi-level trench 107; it can also be as follows Figure 10 As shown, the step structure is only provided on one side of the sidewall. The second doping region 108 extends along the outer wall of the multi-level trench 107 with the step structure to its bottom and is provided around the outer wall of the first-level sub-trench at the opening of the multi-level trench 107 .

[0061] like Figure 11 As shown, in some other embodiments, in the direction along the main junction region A to the junction terminal region B, the anode 104 continues to extend and covers the multiple multi-level trenches 107, so that the multiple second doped regions 108 are in direct contact with the anode.

[0062] like Figure 12As shown, in some other embodiments, there can be multiple third doped regions 106. In the direction from the main junction region A to the junction termination region B, on the side close to the first doped region 105, the third doped regions 106 are alternately arranged with a portion (e.g., two) of the multi-level trenches 107, and the third doped regions 106 are directly connected to the second doped regions 108 on the sidewalls of the multi-level trenches 107. Another portion (one or more) of the multi-level trenches 107 on the side away from the third doped regions 106 is in a floating state. The anode 104 is in direct contact with the third doped region 106 between two adjacent multi-level trenches 107, so that the third doped region 106 and the plurality of second doped regions 108 are electrically connected to the anode 104.

[0063] like Figure 13 As shown, in some other embodiments, all the second doping regions 108 are in a floating state, that is, the second doping region 108 closest to the third doping region 106 is neither electrically connected to the third doping region 106 nor to the anode 104, and at the same time, multiple multi-level trenches 107 are spaced apart and distributed in the drift region 102.

[0064] like Figure 14 As shown, in some other embodiments, the dielectric layer 109 filling the multi-level trenches 107 is a semiconductor layer, and the doping type of the semiconductor layer is the same as the doping type of the first doped region 105. That is, when the first doped region 105 is p-type doped, the dielectric layer 109 is a p-type doped semiconductor layer; when the first doped region 105 is n-type doped, the dielectric layer 109 is an n-type doped semiconductor layer. When the dielectric layer 109 is a semiconductor layer, the semiconductor terminal structure of the present invention can be prepared in a variety of ways, for example, through trench etching-epitaxial filling, multiple epitaxial growth-ion implantation, and other process methods. The terminal structure can be prepared in the same process route as the cell region to reduce costs.

[0065] Further, if Figure 15 As shown, in some other embodiments, the dielectric layer 109 is an insulating dielectric layer. In the junction termination region B, the dielectric layer 109 extends from the surface of the drift region 102 facing away from the substrate 101 to the interior of the multi-level trench 107. The anode 104 extends from the main junction region A to the upper surface of the dielectric layer 109, forming a field plate 110 on the surface of the dielectric layer 109 facing away from the drift region 102.

[0066] Further, if Figure 16As shown in FIG. 1 , in some other embodiments, a junction terminal extension structure formed by a fourth doping region 111 is provided on a side of the multi-level trench 107 away from the third doping region 106. The fourth doping region 111 is directly connected to the second doping region 108, and its doping type is the same as that of the first doping region 105, the second doping region 108, and the third doping region 106, and its doping concentration is lower than that of the first doping region 105. Figure 17 As shown, in other embodiments, a junction termination extension structure formed by multiple fourth doping regions 111 is provided on a side of the multi-level trench 107 away from the third doping region 106. The sidewall of the multi-level trench 107 away from the third doping region 106 is a stepped structure, and the multiple fourth doping regions 111 are arranged in a direction from the drift region 102 to the substrate 101, and each fourth doping region 111 is in direct contact with the second doping region 108 on the outer wall of the stepped structure.

[0067] Further, if Figure 18 As shown, in some other embodiments, in a direction along the substrate 101 to the drift region 102, the height at the opening of the multi-level trench 107 is greater than the height of the upper surface of the drift region 102 on the side of the multi-level trench 107 away from the third doping region 106, and the surface of the drift region 102 facing away from the substrate 101 forms an inclined surface 112 on the side of the multi-level trench 107 away from the third doping region 106. An insulating dielectric layer covers the area from the upper surface of the multi-level trench 107 along the inclined surface 112 to the upper surface of the drift region 102 on the side of the multi-level trench 107 away from the third doping region 106.

[0068] Further, if Figure 19 As shown, in some other embodiments, on a side of the multi-level trench 107 away from the third doping region 106, a plurality of floating field limiting rings formed by a plurality of fifth doping regions 113 are sequentially arranged along a direction from the main junction region A to the junction termination region B. The doping type of the fifth doping region 113 is the same as that of the first doping region 105.

[0069] It is understood that in other embodiments, the number of floating field limiting rings formed by the fifth doping regions 113 can be adjusted according to actual needs. Along the direction from the main junction region A to the junction termination region B, the width of each fifth doping region 113 can be the same or different; the spacing between two adjacent fifth doping regions 113 can be equal or unequal; and the concentration of each fifth doping region 113 can be the same or different.

[0070] It should be noted that when the substrate 101 , the drift region 102 and the dielectric layer 109 in the present invention are semiconductor layers, the semiconductor material used is any one of silicon carbide, silicon, gallium nitride, gallium oxide, aluminum nitride, diamond and indium phosphide.

[0071] The performance of the semiconductor device terminal structure provided by the present invention is verified by Silvaco simulation software. Figure 20 As shown, the simulation structure 1 is an ideal multi-level trench semi-superjunction cell structure. Figure 21 Schematic diagram of doping concentration distribution of simulation structure 1. Figure 22 The diagram below shows the electric field intensity distribution of the simulated structure 1 at the breakdown moment. Figure 22 It can be seen that the breakdown voltage of the simulated structure 1 is 1915 V. In this structure, the peak value of the electric field intensity at the breakdown moment is mainly located at the bottom of the first doped region, deep into the drift region.

[0072] like Figure 23 As shown, the simulation structure 2 is the structure when no terminal structure is added to the edge of the multi-level trench semi-superjunction cell. Figure 24 Schematic diagram of doping concentration distribution of simulation structure 2. Figure 25 The diagram below is a schematic diagram of the electric field intensity distribution of the simulated structure 2 at the breakdown moment. Figure 25 It can be seen that the breakdown voltage of simulation structure 2 is 1308 V. Without a terminal structure, the electric field intensity is concentrated in the oxide layer at the edge of the cell. This phenomenon occurs because there is no terminal structure to alleviate the curvature effect. The curvature effect causes a strong electric field to concentrate at the edge of the cell, resulting in complete depletion of the first doped region. The lateral PN junction formed by the first doped region and the drift region is punched through, and the strong electric field is directly applied to the insulating medium within the multi-level trench.

[0073] like Figure 26 As shown in FIG, the simulation structure three is a terminal structure in which a JTE+field limiting ring is set at the edge of the semi-superjunction cell, specifically a JTE with a length of 3 μm and 9 floating field limiting rings. Figure 27 Schematic diagram of the doping concentration distribution of simulation structure three. Figure 28 The following diagram shows the electric field intensity distribution of simulated structure 3 at the breakdown moment. As can be seen from the figure, its breakdown voltage is 1395V, and the termination efficiency is only 73%. This shows that ordinary junction termination structures are almost incapable of mitigating the electric field concentrated at the cell edge. The lateral PN junction is punched through, and a strong electric field is applied to the insulating dielectric.

[0074] like Figure 29 As shown, the simulation structure 4 is a terminal structure provided in the present invention arranged at the edge of the semi-superjunction cell, and the terminal structure has three multi-level trenches. Figure 30 Schematic diagram of the doping concentration distribution of simulation structure four. Figure 31The following diagram shows the electric field intensity distribution of simulated structure 4 at the breakdown moment. As can be seen from the figure, the breakdown voltage of this structure is 1875V, and the termination efficiency reaches 98%. This demonstrates that the termination structure provided by the present invention not only achieves charge balance between the main junction region (or transition region) and the junction termination region through the second doped region on the outer wall of the multi-level trench, but also disperses and bears the electric field through the dielectric layer within the multi-level trench.

[0075] Figure 32 Figure 2 is the breakdown characteristic curve of simulation structures one, two, three and four. It can be seen from the figure that the breakdown characteristic curve of simulation structure four is closest to the breakdown characteristic curve of the ideal multi-level trench semi-superjunction cell structure (simulation structure one), indicating that simulation structure four has the highest efficiency.

[0076] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It will be apparent to anyone skilled in the art that various modifications and variations of the present invention are possible. Any simple equivalent variations and modifications made in accordance with the scope of protection of the present invention and the contents of the specification are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device terminal structure based on multi-level trenches, characterized in that: The device comprises a substrate, a drift region located on the substrate, a cathode located on a side of the substrate away from the drift region, and an anode; the drift region comprises a main junction region and a junction termination region adjacent to the main junction region; the main junction region comprises a first doped region; the junction termination region comprises at least one third doped region and a plurality of multi-level trenches having a stepped structure; The third doped region is connected to the first doped region; the number n of the multi-level trenches is an integer ≥ 2; the multi-level trenches extend from a surface of the drift region facing away from the substrate toward the substrate; a second doped region is provided on an outer wall of the multi-level trench; a dielectric layer is filled inside the multi-level trench; the substrate and the drift region have the same doping type; the second doped region, the third doped region, and the first doped region have the same doping type, and are opposite to the doping type of the drift region; The anode extends in the direction along the main junction region to the junction terminal region. On the side close to the first doping region, the third doping region and a portion of the multi-level grooves are alternately arranged and the third doping region is directly connected to the second doping region. The anode is in contact with the third doping region between two adjacent multi-level grooves, and the other portion of the multi-level grooves away from the first doping region is in a floating state.

2. The semiconductor device terminal structure based on multi-level trenches according to claim 1, characterized in that: In the direction from the drift region to the substrate, a junction terminal extension structure formed by at least one fourth doping region is provided on the side of the multi-level trench away from the third doping region. The fourth doping region is directly connected to the second doping region, and its doping type is the same as the doping type of the second doping region.

3. The semiconductor device terminal structure based on multi-level trenches according to claim 1, characterized in that: A surface of the drift region facing away from the substrate forms an inclined surface on a side of the multi-level trench away from the third doping region.

4. The semiconductor device terminal structure based on multi-level trenches according to claim 1, characterized in that: A plurality of floating field limiting rings formed by a plurality of fifth doping regions are provided on a side of the multi-level trench away from the third doping region, and the plurality of floating field limiting rings are arranged in sequence along a direction from the main junction region to the junction termination region.

5. The semiconductor device terminal structure based on multi-level trenches according to claim 1, characterized in that: The sidewalls on two opposite sides of the multi-level trench are both step structures, and a second doping region is arranged around the outer wall of the multi-level trench.

6. The semiconductor device terminal structure based on multi-level trenches according to claim 1, characterized in that: At least two of the first doping region, the second doping region, and the third doping region have the same doping concentration.

7. The semiconductor device terminal structure based on multi-level trenches according to claim 1, characterized in that: Along a direction from the drift region to the substrate, a depth of the second doping region is the same as a depth of the first doping region.

8. The semiconductor device terminal structure based on multi-level trenches according to claim 1, characterized in that: The dielectric layer is a semiconductor layer, and the doping type of the semiconductor layer is the same as the doping type of the first doping region.

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