Data processing device and method for operating a data processing device

Abstract

The present invention provides a data processing device for connecting to a communication bus, the data processing device comprising: an analysis logic unit; an offset circuit configured to generate an offset voltage and output it to the analysis logic unit; and a voltage amplifier configured to amplify a voltage dropped through a measurement resistor connectable to the communication bus, and output the amplified voltage obtained thereby to the analysis logic unit. The analysis logic unit is configured to adjust the height of the offset voltage output by the offset circuit based on the amplified voltage and the received offset voltage when the data processing device is running.

Description

Technical Field

[0001] The invention relates to a data processing device for connection to a communication bus and a method for operating at least the data processing device. In addition, a system for processing data using the data processing device is provided. Additionally or alternatively, a computer program is provided, which includes instructions that cause the computer to at least partially implement the method when the program is executed by the computer. Additionally or alternatively, a computer-readable medium including instructions is provided, which causes the computer to at least partially implement the method when the instructions are executed by the computer. Background Art

[0002] LIN (Local Area Network) is a serial network protocol used for communication between components in a motor vehicle. It is a serial single-wire network protocol that supports communication up to 19.2 Kbit / s over a 40 m bus length.

[0003] In this case, the LIN bus can be used for so-called slave node position detection (SNPD) or for so-called automatic addressing or for so-called automatic address allocation. These methods make it possible to detect the position of the slave nodes on the LIN bus and allow the assignment of unique node addresses. This in turn makes it possible to connect similar or identical devices to the bus without completed offline programming or connection pin programming, so that standard slaves can be connected in any way or in any order.

[0004] Various methods are known from the prior art for address assignment in LIN bus systems.

[0005] In detail, EP 1 490 772 B1 relates to a method for addressing a user of a bus system, the bus system having a control unit, a bus originating from the control unit and a plurality of addressable users connected to the bus, wherein in the method:

[0006] - each subscriber which has not yet been addressed feeds an identification current into the bus for identification, wherein all identification currents flow via the bus in the direction of the control unit,

[0007] - Each user that has not yet been addressed detects the current flowing through the bus,

[0008] - only that subscriber which has not been addressed and for which no current has been detected or only a current which is less than a predeterminable first threshold value is identified as a subscriber which has not yet been addressed,

[0009] - assigning an address to the user thus identified for addressing purposes, and

[0010] - Carry out the previous steps without the last addressed user until all users not yet addressed have been addressed.

[0011] US2021 / 0173717 A1 relates to a method for identifying bus nodes of a bus system, which method makes it possible to operate two different types of bus slaves in a mixed installation. Depending on the type of bus slave, the identification of which bus slave has not yet been assigned an address during the addressing phase is implemented in different ways. However, in all cases, the bus slave that is connected to the bus line furthest from the bus master is always identified as the bus slave to be assigned an address.

[0012] US2019 / 0173838 relates to a bus node that can implement a method for assigning a bus address to a bus node of a serial data bus system. During an allocation time period, a method for assigning a bus address to a bus node of a serial data bus system is performed by means of a bus shunt resistor in each bus node of the data bus system. After the method for distributing the bus address to the bus node of the serial data bus system is performed in the allocation time period, an operating time period follows. The bus node has such a bus shunt resistor. The bus node is characterized in that a bus shunt bridge switch is open in the allocation time period before the bus address is assigned to the bus node, and is closed in the allocation time period after the bus address is assigned to the bus node, and is closed in the operating time period.

[0013] DE 10 2018 104 489 A1 relates to a data bus system with bus nodes for a serial data bus, the bus nodes each having a bus shunt resistor, which is respectively inserted into the data bus. In addition, they should also have an addressing current source for determining the bus position of the bus node in the data bus, which can additionally feed the addressing current into the data bus in a controlled manner so that the total current through the bus shunt resistor of the bus node corresponds to a predetermined or calculated or otherwise determined total current. Here, the regulation is carried out via a control loop. Here, the addressing current flows through the bus shunt resistor of the relevant automatic addressing bus node. Here, a variant of the proposed bus node has a device for detecting the current through the bus shunt resistor, which can include the detection of the measured value. This detection current through the bus shunt resistor can be used for self-testing, so that the above-mentioned faults (for example, bus shunt resistor loss) can be detected. In a particularly preferred variant of the automatic addressing bus node, the addressing power supply increases the addressing current with a first time constant and reduces the addressing current with a second time constant that is less than the first time constant.

[0014] US2017 / 0359195 A1 relates to an integrated circuit device for controlling a LIN slave node based on a control signal transmitted from a LIN master. The IC device includes a slave node circuit for processing the control signal when the control signal is received in the form of a LIN message frame via a first data line terminal. The IC device also includes a master node circuit for processing another control signal, which is transmitted to the LIN slave node via a second data line port in the form of a LIN message frame. The IC device also includes a processing unit for controlling the LIN slave node based on the control signal by synthesizing the other control signal.

[0015] Here, EP 1490772 B1 relates to the so-called BSM (English: Bus Shunt Method), automatic addressing procedure or automatic addressing process. At the beginning of this method, no SNPD device is assigned an address. The automatic addressing routine is performed during the continuous field of the LIN communication protocol. The breakdown field is divided into three phases, including offset current measurement, followed by pull-up operation (Pull-up-Betrieb), and then followed by current source mode. For offset current measurement or offset phase, all outputs, pull-ups and current sources are disconnected, and the bus current (Ioffset) is measured. During the second phase, the pull-up (Pull-up) is turned on and the current source remains turned off. The bus current (IPU) is measured and a node with ΔI=IPU-Ioffset<1mA is "selected". In the third phase, which is referred to as the current source mode in this article, the selected node turns on the current source and all other nodes turn off the pull-up. The bus current (ICS) is measured. The node with ΔI=ICS-Ioffset<1 mA is detected as the last node. The current source is switched off and the pull-up is switched on. The last node accepts the address contained in the LIN configuration message. This technique is described in the above-mentioned patent EP 1490772 B1 but also in US 7091876 B2.

[0016] In order to enable an SNPD instrument to implement the above-described address assignment method, the voltage amplifiers of the SNPD instrument (so-called auto-addressing amplifiers) are offset-calibrated during the manufacture and / or development of the instrument. The calibration values ​​obtained in this way are then stored in the instrument and permanently set at the auto-addressing input amplifiers. Subsequent changes in the deviation due to various effects (e.g. packaging, aging, drift, etc.) can only be taken into account with difficulty as systematic errors.

[0017] The above description also applies to the CAN bus system. The CAN (Controller Area Network) bus is a serial bus system and belongs to the fieldbus. CAN is internationally standardized in ISO 11898-1 and defines layer 2 (data security layer) in the ISO / OSI reference model. The two most common implementations of the physical layer are defined according to ISO 11898-2 (high-speed physical layer) and ISO 11898-3 (fault-tolerant physical layer). Summary of the invention

[0018] Against the background of the prior art, an object of the present invention is to provide a device and a method, which are respectively suitable for improving the prior art.

[0019] This object is achieved by the features of the independent claims. The contents of the independent and dependent claims are optional developments.

[0020] The object is therefore achieved by a data processing device for connection to a communication bus (optionally of a motor vehicle).

[0021] The data processing device includes an analysis logic unit, an offset circuit, and a voltage amplifier, wherein the offset circuit is configured to generate an offset voltage and output the offset voltage to the analysis logic unit, and the voltage amplifier is configured to amplify the voltage dropped through a measurement resistor that can be connected to a communication bus and output the amplified voltage obtained thereby to the analysis logic unit.

[0022] The analysis logic is configured to adjust the height of the offset voltage output by the offset circuit based on the amplified voltage and the offset voltage received (at the analysis logic) during (further) operation of the data processing device.

[0023] Depending on where the offset circuit is fed with the offset voltage, the offset voltage can be output to the analysis logic directly or via a voltage amplifier (indirectly, so to speak). In detail, this means that the offset circuit can be configured to generate an offset voltage and output the generated offset voltage to the voltage amplifier. The voltage amplifier can then be connected to the offset circuit on the input side and to the analysis logic on the output side, and the voltage amplifier is configured to amplify the voltage formed by the sum of the voltage dropped through the measuring resistor that can be connected to the communication bus and the offset voltage, and output the amplified voltage obtained in this way, which already includes the offset voltage, to the analysis logic. The analysis logic then uses the amplified voltage received from the voltage amplifier to adjust the offset voltage. However, additionally or alternatively, the offset circuit can also be configured to generate an offset voltage and output the generated offset voltage directly to the analysis logic, so that the voltage amplifier (which is only connected to the measuring resistor but not to the offset circuit on the input side) can be connected to the analysis logic on the output side, and the voltage amplifier can be configured to amplify the voltage dropped through the measuring resistor that can be connected to the communication bus, and output the amplified voltage obtained thereby to the analysis logic. The analysis logic then uses the amplified voltage received from the voltage amplifier and adds the offset voltage received directly from the offset circuit (or unamplified) in order to adjust the height of the offset voltage.

[0024] The communication bus may be an optionally serial data bus, for example a LIN bus, a CAN bus and / or a CAN-FD bus (Controller Area Network Flexible Data-rate). The data processing device may be a SNPD instrument.

[0025] The analysis logic may be a finite state automaton (EA, also called a state machine, state automaton; English: finite state machine). This may be understood as a model of behavior including states, state transitions, and actions. When the number of states (the number that the automaton can accept) is finite, the automaton is called finite. A finite automaton is a special case formed by the number of automata. In digital circuits, EA is constructed with the aid of a memory programmable controller, logic gates, flip-flops, and / or relays. The hardware implementation may include registers for storing state variables, a logic unit for determining state transitions, a second logic unit for output, and a clock and / or delay element for switching / distinguishing between previous, current, and subsequent states.

[0026] Additionally or alternatively, the analysis logic may be a processor, optionally a CPU (English: abbreviation for Central Processing Unit). In informatics, a processor or processing unit is an electronic component (digital circuit) that performs operations on an external data source (usually on a memory or other data stream), and optionally has the form of a microprocessor, which may optionally be implemented as a single metal oxide semiconductor integrated chip.

[0027] The evaluation logic can have an algorithm which directly or indirectly receives the amplified voltage output by the voltage amplifier as an input variable and, on this basis, regulates or adjusts the offset voltage according to the algorithm's rules.

[0028] The offset voltage can be understood as a characteristic parameter of the (accumulated) systematic deviation of the characteristic curve of the electrical instrument from the ideally expected curve. In this article, it can be optionally understood as the input offset voltage of the voltage amplifier, wherein the voltage amplifier can have an operational amplifier or can be implemented as an operational amplifier. It can be considered that the offset voltage is the voltage to be input at the voltage amplifier on the input side, so that in the case of a predetermined input voltage (in addition to the offset voltage, it is additionally input into the voltage amplifier), the output voltage of the voltage amplifier corresponds to a specific (reference) (voltage) value. In one case, the offset voltage can be the differential input voltage of the voltage amplifier, which is necessary to make the voltage amplifier produce a zero output voltage when no other or additional input voltage is applied to the voltage amplifier except the offset voltage. However, the present invention is not limited to this. More specifically, if it is necessary to measure a negative current, a non-zero voltage value can also be achieved as a target value by adjusting the offset voltage, such as a voltage value greater than zero.

[0029] The invention provides a number of advantages, in particular because the offset can be automatically adjusted or adjusted during operation of the data processing device. Thus, changes in the offset of the voltage amplifier, optionally the self-addressing amplifier described above (e.g. packaging, aging, drift, etc.) can be compensated by various effects in the operation of the data processing device. In addition, the expenditure for calibration and adjustment of the offset during development and / or manufacture of the data processing device can be minimized or eliminated.

[0030] Possible embodiments of the above-described data processing device are explained in detail below. All of these embodiments enhance the above-described advantages of the data processing device according to the invention individually or in combination.

[0031] The evaluation logic can be configured to adjust the level of the offset voltage during operation of the data processing device based on the amplified voltage and the offset voltage and a predetermined reference value. The reference value can be predetermined by design and / or can be programmed or determined via a data bus via a digital-to-analog converter.

[0032] The data processing device may include an analog-to-digital converter, via which the analysis logic is connected to the voltage amplifier. The analog-to-digital converter may be configured to convert the voltage amplified by the voltage amplifier and the offset voltage from analog values ​​into digital values ​​and output them to the analysis logic. The analysis logic may be configured to adjust the level of the offset voltage output from the offset circuit based on the digital value of the amplified voltage and the digital value of the offset voltage received from the analog-to-digital converter during operation of the data processing device. As described above, depending on the position or connection of the offset circuit, the offset voltage may also be part of the amplified voltage here.

[0033] The analysis logic may be configured to determine a current value based on the digital value of the amplified voltage and the digital value of the offset voltage and the height of the measuring resistor, and to adjust the height of the offset voltage output from the offset circuit based on the determined current value during operation of the data processing device.

[0034] The evaluation logic may be configured to compare the determined current value with a reference value and to adjust the offset voltage such that the difference between the current value and the reference value is reduced.

[0035] The evaluation logic may be configured to adjust the offset voltage stepwise in such a way that the difference between the current value and the reference value decreases.

[0036] In other words, the above description relates to a more specific design of the present invention, as described below only in an optional and non-limiting manner: the input voltage of an amplifier called AA-AMP (short for automatic address amplifier) ​​can be the differential voltage between the potential of the positive input terminal of the amplifier (also serving as the bus master) and the negative input terminal of the amplifier (also serving as the bus slave). The amplifier can include an offset circuit, which can be controlled by means of a control signal of an analysis circuit called an analysis logic unit. The offset circuit can selectively generate an offset voltage corresponding to the offset value. The sum of the offset voltage and the input voltage can be the input signal of the amplifier. The amplifier can optionally amplify the input signal into an amplified input signal. The analog-to-digital converter can convert the amplified input signal into a digital signal.

[0037] The logic unit can control the addressing power supply and the slave resistor and the slave switch. During the offset phase of the bus cycle, the logic unit can detect the current value. It is conceivable that the device for determining the offset value implements one or more determination processes in time during the offset phase. The offset value can have an (optionally predefined) starting value or correspond to the starting value at the beginning of the determination process. It is conceivable that the logic unit compares the detected current value with the reference value and forms a difference between the detected current value and the reference value. The following can be considered: if the difference is large, the logic unit prompts the offset circuit to reduce the generated offset voltage by a predetermined or calculated value by correspondingly increasing the offset value. If the difference is small, the logic unit prompts the offset circuit to increase the generated offset voltage by a predetermined or calculated value by correspondingly reducing the offset value. For these two cases, for example, successive approximation can be used. These steps can be repeatedly performed in the determination process. When the difference is numerically less than a predetermined value and / or when the offset phase ends, the determination process can be terminated. Thus, the adjusted offset value can be the offset value determined by such a determination process. It is conceivable that the logic unit averages a plurality of determined offset values ​​from a plurality of determination processes and generates a final offset value from this. From this, the offset circuit can generate an offset voltage corresponding to the final offset value.

[0038] Furthermore, the present invention relates to a method for operating the above-mentioned data processing device. The method comprises generating an offset voltage by means of an offset circuit and outputting the generated offset voltage to an analysis logic section, amplifying a voltage dropped through a measuring resistor connectable to a communication bus by means of a voltage amplifier, and outputting the thus obtained amplified voltage from the voltage amplifier to the analysis logic section. The method also comprises adjusting the height of the offset voltage output from the offset circuit during operation of the data processing device based on the amplified voltage and the offset voltage.

[0039] The method may be a computer-implemented method, ie one, several or all steps of the method may be at least partially implemented by a computer or an apparatus for data processing or a data processing device.

[0040] The method can be part of an automatic addressing method, in which a clear identifier is assigned to a data processing device. The automatic addressing method can be, for example, the BSM automatic addressing procedure described at the beginning. The method can optionally be performed or implemented completely in a first phase, namely the so-called offset phase of the automatic addressing method. In detail, this can mean that during the offset phase of the so-called LIN-Breakfield in the automatic addressing cycle, in addition to the normal or traditional measurement of the current in the LIN bus, an algorithm is additionally and / or alternatively executed at least sometimes, which runs the offset fine-tuning circuit of the voltage amplifier. Here, the goal can be to adapt the current measurement value to a known target value. In other words, the offset calibration can be always or automatically started in the automatic addressing cycle from each slave at any data processing device or at the LIN bus (so-called SNPD instrument). For this purpose, the offset phase of the LIN SNPD can be used. Then, for example, a successive approximation or similar algorithm can be used, which uses the fine-tuning circuit of the automatic addressing amplifier to adjust its offset. As a result, in particular, effects caused by drift (such as packaging, aging, load, etc.) can be reduced or even eliminated.

[0041] What has been described above with respect to the data processing device also applies analogously to the method, and vice versa.

[0042] In addition, the present invention relates to a system for data processing, wherein the system comprises the above data processing device and a control device connected to the data processing device via a communication bus. The control device is configured to control the data processing device via the communication bus so that the data processing device implements the above method.

[0043] The control device may be an electronic control unit (ECU in English). The electronic control device or electronic control unit may be an intelligent processor-controlled unit which can communicate with other modules, for example, via a central gateway (CGW) and which may form a vehicle on-board network via a fieldbus (such as a CAN bus, a LIN bus, a MOST bus, a FlexRay) and / or via automotive Ethernet (for example together with a telematics control unit and / or an environmental sensor system) as necessary. It is conceivable that the control device controls functions that are important for the driving characteristics of the motor vehicle, such as engine control, power transmission, brake system and / or tire pressure control system. In addition, driver assistance systems, such as parking assistance, adaptive speed regulation (ACC, Adaptive Cruise Control in English), lane keeping assistance, lane change assistance, traffic sign recognition, light recognition, start-up assistance, night vision assistance and / or intersection assistance, may be controlled by the control device.

[0044] In particular in the case where the communication bus is a LIN bus via which the data processing device is connected to the control device, but also in other or additional cases, the data processing device may be regarded as a slave and the control device as a master.

[0045] Here, the system for data processing is not limited to a single master or slave. Rather, it is conceivable to set a plurality of masters and / or slaves, which are connected to each other or to each other via a single or multiple communication buses.

[0046] What is described above with respect to the data processing apparatus and method is similarly applicable to the system, and vice versa.

[0047] Furthermore, the invention relates to a motor vehicle comprising the above-mentioned data processing device or the above-mentioned system for data processing.

[0048] The motor vehicle may be a passenger vehicle, such as a car, a motorized two-wheeled or three-wheeled vehicle and / or a vehicle, such as a truck.

[0049] The motor vehicle may be autonomous. The motor vehicle may be designed to at least partially and / or at least temporarily take over the longitudinal control and / or the lateral control during autonomous driving of the motor vehicle.

[0050] Automatic driving can be implemented in such a way that the movement of the motor vehicle takes place (largely) autonomously. Automatic driving can be controlled at least partially and / or temporarily by a data processing device or a system for data processing.

[0051] The motor vehicle may be an autonomy level 1 motor vehicle, ie, have certain driver assistance systems which assist the driver in maneuvering the vehicle, such as, for example, adaptive cruise control (ACC).

[0052] The motor vehicle may be an autonomy level 2 motor vehicle, ie may be partially autonomous, so that functions such as automatic parking, lane keeping or lateral maneuvering, general longitudinal maneuvering (in particular starting), acceleration and / or braking may be taken over by a driver assistance system.

[0053] The motor vehicle may be a motor vehicle of autonomy level 3, that is, conditionally automated so that the driver does not have to constantly monitor the system vehicle. The motor vehicle performs autonomous functions, such as triggering flashers, changing lanes and / or keeping lanes. The driver may move on to other tasks, but if necessary, the system requests the driver to take over control within the warning time.

[0054] The motor vehicle may be a motor vehicle of autonomy level 4, that is, highly automated, such that the system vehicle continuously takes over control of the vehicle. If the system no longer manages the driving task, the driver may be requested to take over control.

[0055] The vehicle may be a Level 5 autonomy vehicle, that is, fully automated such that a driver is not required to perform the driving task. No human intervention is required other than specifying a destination and activating the system. The vehicle may not have a steering wheel and pedals.

[0056] Furthermore, the invention relates to a computer program for an evaluation logic of a data processing device, the data processing device being intended for connection to a communication bus.

[0057] The data processing device includes: an offset circuit configured to generate an offset voltage and output it to an analysis logic section; and a voltage amplifier configured to amplify a voltage dropped through a measurement resistor connectable to a communication bus and output the amplified voltage obtained thereby to the analysis logic section.

[0058] The computer program includes instructions that, when executed by the analysis logic, cause the analysis logic to adjust the height of an offset voltage output by the offset circuit based on the amplified voltage and the offset voltage when the data processing device is running.

[0059] The program code of the computer program may be present as any desired code, in particular as a code suitable for controlling a motor vehicle.

[0060] The data processing device may be the data processing device described above.

[0061] The computer program may comprise instructions which, when executed by a computer, optionally the data processing apparatus described above and / or the system for data processing described above, cause them to at least partially perform or implement the method described above.

[0062] The above descriptions of the data processing device, the motor vehicle and the method also apply analogously to the computer program and vice versa.

[0063] Furthermore, a computer-readable medium, in particular a computer-readable storage medium, is provided, which at least partially comprises the above-mentioned computer program.

[0064] That is, there may be provided a computer readable medium comprising the computer program defined above.The computer readable medium may be any digital data storage device, such as a USB stick, hard drive, CD-ROM, SD card or SSD card.

[0065] The computer program does not necessarily have to be stored on such a computer-readable storage medium in order to be made available to the motor vehicle, but can also be imported from outside via the Internet or in some other way.

[0066] The computer-readable medium may include instructions, which, when executed by a computer, optionally the data processing apparatus described above, and / or the system for data processing described above, cause them to at least partially implement the method described above.

[0067] The above descriptions of the method, the data processing device, the computer program and the motor vehicle also apply analogously to the computer-readable medium and vice versa. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Below, reference Figures 1 to 3 An implementation method will be described.

[0069] Figure 1 A data processing device according to the invention for connection to a communication bus of a motor vehicle is schematically shown, and

[0070] Figure 2 Schematically shows a method for operating in Figure 1 A flow chart of a method of a data processing apparatus is shown in

[0071] Figure 3 A data processing device according to the invention is shown schematically for connection to a further communication bus of a motor vehicle. DETAILED DESCRIPTION

[0072] exist Figure 1 The motor vehicle 1 shown in FIG. 1 has a system 2 for data processing, which has a plurality of serially connected (see FIG. Figure 1 The dashed arrow in the figure) is referred to below as the data processing device 3 of the slave (wherein Figure 1 These data processing devices are connected to a control device 5, which is implemented as an ECU and is referred to as a master in the following, via a communication bus 4, which is implemented as a LIN bus (LIN-Bus) in this case. The line called VS provides the supply voltage for the slaves 3 and the master 5, wherein the line called GND (ground in English) is connected to ground.

[0073] Next, we will Figure 1 The slave 3 shown in FIG. 1 is described as a representative of further slaves, not shown, which may have the same configuration.

[0074] The slave 3 includes an internal measuring resistor 31, wherein the measuring resistor 31 is connected in parallel with an external measuring resistor 41 of the communication bus 4 (only one of the measuring resistors 31, 41 is sufficient), a voltage amplifier 32 connected in parallel with the two measuring resistors 31, 41 and implemented as an operational amplifier, an analog-to-digital converter 33 connected in series with the voltage amplifier 32, an analysis logic unit 34 connected in series with the analog-to-digital converter 33, and an offset circuit 35, which is configured to generate an offset voltage.

[0075] The voltage amplifier 32 is connected on the input side to an offset circuit 35 and to the two measuring resistors 31 , 41 and on the output side via an analog-to-digital converter 33 to an evaluation logic 34 .

[0076] The system 2 for data processing is configured with the above components to implement the following reference Figure 2 A detailed description of the method.

[0077] In the first step S1 of the method, the master 5 grounds the communication bus 4 in order to switch from the normal operating mode to the automatic addressing mode, which includes the last three phases, namely the offset phase, followed by the pull-up operation and then the current source mode (see above for details). The steps of the method described below are implemented by the slave 3 in the first phase, namely the offset phase.

[0078] In the second step S2 of the method, a bias voltage having a first height or a first voltage value (also referred to as a default value) is output by the bias circuit 35, so that in addition to the voltage dropped through the measuring resistors 31, 41 being applied to the voltage amplifier 32 on the input side, the bias voltage is applied to the voltage amplifier 32 on the input side.

[0079] In the third step S3 of the method, the voltage amplifier 32 amplifies the voltage applied on the input side, ie, a voltage formed by the sum of the voltage dropped across the measuring resistors 31 , 41 and the offset voltage generated by the offset circuit 35 .

[0080] In the fourth step S4 of the method, the voltage amplifier 32 outputs the amplified voltage obtained in the third step S3 to the analog-to-digital converter 33 .

[0081] In a fifth step S5 of the method, the analog-to-digital converter 33 converts the obtained amplified voltage from an analog value into a digital value and outputs the digital value to the evaluation logic 34 .

[0082] In the sixth step S6 of the method, the analysis logic unit 34 determines a current value based on the obtained digital (voltage) value and the height or size of a total measuring resistance, for example, having an external measuring resistor 41 and an internal measuring resistor 31 or consisting of these in this context, which current value can also be referred to as a bus current (i.e., the current flowing in the communication bus 4).

[0083] In a seventh step S7 of the method, the analysis logic 34 compares the determined current value with a reference value and determines based on the result of the comparison whether the offset voltage should be increased or decreased so that the determined current value approaches the reference value.

[0084] Accordingly, an offset value is determined by the evaluation logic 34 , which corresponds to the value or the level of the offset voltage which the offset circuit is to set.

[0085] In the eighth step S8 of the method, the analysis logic unit outputs a control signal to the offset circuit 35 so that during the operation of the data processing device 3, more precisely during the offset phase, the height of the offset voltage output by the offset circuit 35 is adjusted to the determined offset value, or the offset voltage is adjusted so that the offset voltage corresponds to the offset value in order to reduce the difference between the current value and the reference value.

[0086] The second step to the eighth step S8 can be repeatedly performed, so that the rated-actual comparison of the current value with the reference value by the evaluation logic 34 in the seventh step S7 is repeatedly performed, and the output of the control signal for adjusting the offset voltage in the eighth step S8 is repeatedly performed. The offset voltage is adjusted step by step in this case so that after each repetition of steps S2-S8, the (measured) current value is closer to the reference value.

[0087] The method is carried out until the end of the drift phase. This can correspond to a predetermined time period or a specified time interval, which can optionally be standardized in the communication standard used (for example, the LIN specification). Additionally or alternatively, it is also conceivable to carry out the method until the difference between the reference value and the current value is less than a predetermined limit value.

[0088] After the method has ended, the slave 3 can use the determined offset value for a further or subsequent addressing method. It is conceivable that the evaluation logic 34 determines an average value from a plurality or all of the offset values ​​determined (during the offset phase) in the last round before the method ends, and that the slave 3 uses this average value for a further addressing method. However, the slave can also use the last determined offset value and thus no longer make changes to the offset circuit 35.

[0089] It is conceivable to use the bus current determined (finally) in the sixth step S6 for a different addressing method of the slave 3 .

[0090] The above-described method and the above-described device make it possible to achieve relatively short test times and reduced complexity for testing the slaves during development and / or production, as well as to reduce external influences during addressing.

[0091] Furthermore, the above method can be applied, additionally or alternatively, to a motor vehicle 1 which is implemented as a CAN bus system. Figure 3 A communication system 2' is schematically shown in FIG.

[0092] exist Figure 3 The motor vehicle 1 shown in FIG. 1 has a system 2′ for data processing, which has a plurality of serially connected data processing devices 3′, each of which is referred to as a slave in the following text. Figure 3 Only three slaves 3' are shown in the figure, and the data processing device 3' is connected to a control device 5, which is hereinafter referred to as a master, via a communication bus 4', which is implemented as a Can-Bus in this case. Figure 3 For a detailed description of the structure of the communication system 2 ′ shown in and the sequence of an addressing method that can be performed by the communication system 2 ′, reference is made to DE 10 2020 109 717 A1, the content of which is incorporated by reference.

[0093] Next, we will Figure 3 The slave 3 ′ shown in FIG. 1 is described as a representative of other slaves 3 ′ which may have the same configuration.

[0094] The slave 3' comprises a voltage amplifier 32' which is connected in parallel with an external measuring resistor 41' of the communication bus 4 and is implemented as an operational amplifier, an analog-to-digital converter 33' which is connected in series with the voltage amplifier 32', an evaluation logic unit 34' which is connected in series with the analog-to-digital converter 33', and an offset circuit 35' which is configured to generate an offset voltage.

[0095] The voltage amplifier 32 ′ is connected on the input side to a measuring resistor 41 ′ and on the output side to an offset circuit 35 ′ and via an analog-to-digital converter 33 ′ to an evaluation logic 34 ′.

[0096] The data processing system 2' is configured with the above components to implement the above reference Figure 2 A detailed description of the method.

[0097] Reference numerals list

[0098] 1Motor Vehicle

[0099] 2.2'Systems for data processing or communication systems

[0100] 3.3' Data processing device or slave

[0101] 31 Internal measuring resistor or shunt

[0102] 32, 32' voltage amplifier

[0103] 33. 33'Analog-to-digital converter

[0104] 34. 34'Analysis Logic Department

[0105] 35, 35' offset circuit

[0106] 4.4' Communication Bus

[0107] 41, 41' External measuring resistor or shunt

[0108] 5. 5' control device or host

[0109] S1-S8 Method Steps

Claims

1. A data processing device (3) for connection to a communication bus (4), wherein: The data processing device (3) comprises: -Analysis logic unit (34), - an offset circuit (35) configured to generate an offset voltage and output it to the analysis logic (34), and a voltage amplifier (32) configured to amplify the voltage dropped across a measuring resistor (31, 41) connectable to the communication bus (4) and to output the amplified voltage thus obtained to the analysis logic (34), It is characterized in that The analysis logic (34) is configured to adjust the level of the offset voltage output by the offset circuit (35) based on the amplified voltage and the received offset voltage when the data processing device (3) is running.

2. The data processing device (3) according to claim 1, characterized in that The analysis logic (34) is configured to adjust the level of the offset voltage based on the amplified voltage and the offset voltage and a predetermined reference value when the data processing device (3) is running.

3. The data processing device (3) according to claim 2, characterized in that: the data processing device (3) comprises an analog-to-digital converter (33), the analysis logic (34) being connected to the voltage amplifier (32) via the analog-to-digital converter, - wherein the analog-to-digital converter (33) is configured to convert the voltage amplified by the voltage amplifier (32) and the offset voltage from analog values ​​into digital values ​​and output them to the analysis logic section (34), and - the analysis logic (34) is configured to adjust the level of the offset voltage output by the offset circuit (35) when the data processing device (3) is running, based on the digital value of the amplified voltage and the digital value of the offset voltage received from the analog-to-digital converter (33).

4. The data processing device (3) according to claim 3, characterized in that The analysis logic unit (34) is configured to: - determining a current value based on the digital value of the amplified voltage and the digital value of the offset voltage and the size of the measuring resistor, and - based on the determined current value, adjusting the level of the offset voltage output by the offset circuit (35) when the data processing device (3) is in operation.

5. The data processing device (3) according to claim 4, characterized in that The analysis logic (34) is configured to compare the determined current value with a reference value and to adjust the offset voltage such that a difference between the current value and the reference value is reduced.

6. The data processing device (3) according to claim 5, characterized in that The analysis logic (34) is configured to adjust the offset voltage stepwise so that the difference between the current value and the reference value decreases.

7. A method for operating a data processing device (3) according to any one of claims 1 to 6, wherein: The method comprises: - generating an offset voltage by means of an offset circuit (35) and outputting it to an evaluation logic (34), - amplifying by means of a voltage amplifier (32) the voltage dropped across a measuring resistor (31, 41) which can be connected to a communication bus (4), and - outputting the amplified voltage thus obtained from the voltage amplifier (32) to the analysis logic (34), Characterized in that the method comprises: - Based on the amplified voltage and the received offset voltage, adjusting the level of the offset voltage output by the offset circuit (35) when the data processing device (3) is running.

8. A system (2) for data processing, characterized in that The system comprises: - a data processing device (3) according to any one of claims 1 to 6, and - a control device (5) connected to the data processing device (3) via a communication bus (4), - wherein the control device (5) is configured to control the data processing device (3) via the communication bus (4) so ​​that the data processing device (3) implements the method according to claim 7.

9. A motor vehicle (1), characterized in that The motor vehicle (1) comprises a data processing device (3) according to any one of claims 1 to 6 or a system (2) according to claim 8.

10. A computer program product for an analysis logic unit (34) of a data processing device (3) connected to a communication bus (4), wherein: The data processing device (3) comprises: - an offset circuit (35) configured to generate an offset voltage and output it to the analysis logic (34), and a voltage amplifier (32) configured to amplify the voltage dropped across a measuring resistor (31, 41) connectable to the communication bus (4) and to output the amplified voltage thus obtained to the analysis logic (34), It is characterized in that - the computer program product comprises instructions which, when executed by the analysis logic, cause the analysis logic (34) to adjust the level of the offset voltage output by the offset circuit (35) based on the amplified voltage and the offset voltage when the data processing device (3) is running.

11. A computer readable medium having a computer program stored thereon, characterized in that: When the computer program is executed, the method according to claim 7 is implemented.

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