An input current average sampling circuit

Abstract

The present application belongs to the technical field of analog integrated circuits, and particularly relates to an input current mean value sampling circuit. The present application is directed to an application scene with a blocking power tube, and a problem that a traditional current detection circuit needs an external resistor and an additional pin, and proposes a low-power integrated input current mean value sampling circuit without a resistor connected in series in a power stage, which can be applied to current limitation or overcurrent protection of a circuit and the like.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to an input current average sampling circuit. Background Technology

[0002] In power management chips, such as buck circuits, two power transistors (transistors) are typically used to control the flow of power current. Recently, some new charger chips have introduced a new blocking power transistor between the input and upper power transistors. Its source is connected to the input power supply, and its drain is connected to the upper power transistor. This power transistor is normally open during operation. One function of this transistor is to block reverse current from the battery to the input power supply using its own diode. Another function is that the intermediate node between it and the upper power transistor can be used to supply power to external circuits. Current monitoring is essential for power management chips. Excessive current can damage the chip, so circuits sample current information for current limiting or overcurrent protection functions. Traditional current sampling involves connecting a small resistor in series in the power supply path and then sending the voltage across the resistor to the internal circuitry for processing to obtain the current information. This method not only introduces an extra pin to transmit the voltage information from the external resistor back to the chip but also introduces unnecessary power stage losses, leading to reduced conversion efficiency. Therefore, the traditional method of detecting current using a series resistor requires more external components and introduces additional high power losses, which is detrimental to low-power and miniaturized applications. Summary of the Invention

[0003] Power transistors can be of various types. The present invention is based on rectifier circuits using NMOS as the power transistor. This invention addresses the application scenarios that require blocking power transistors and the problems of traditional current detection circuits requiring external resistors and additional pins. It proposes a low-power on-chip fully integrated input current averaging sampling circuit that does not require series resistors in the power stage. It can be used for applications such as current limiting or overcurrent protection in circuits.

[0004] The technical solution of this invention is as follows:

[0005] The input current sampling circuit includes a first sampling high-voltage NMOS transistor, a second sampling high-voltage NMOS transistor, a third high-voltage NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a sampling resistor RS, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first PNP transistor, a second PNP transistor, a third PNP transistor, a fourth PNP transistor, a first high-voltage PMOS transistor, a second high-voltage PMOS transistor, a third high-voltage PMOS transistor, a bias current IB, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

[0006] Define the source, drain, and gate voltages of the blocking power transistors as VIN, PMID, and VG, respectively. The drain of the first sampling high-voltage NMOS transistor is connected to VIN, the gate to VG, and the source to one end of the first resistor. The emitters of the first and second PNP transistors are shorted to the other end of the first resistor and connected to ground through the first capacitor. The collector of the first PNP transistor is connected to the source of the first high-voltage PMOS transistor. The collector of the second PNP transistor is connected to the bias current IB through the second high-voltage PMOS transistor. The base of the first PNP transistor is connected to the base and collector of the second PNP transistor, and the third P... The base and collector of the NP transistor, and the base of the fourth PNP transistor; the drain of the first high-voltage PMOS transistor is connected to the drain of the first NMOS transistor through a third resistor, the drain of the second NMOS transistor is connected to the source of the first NMOS transistor and the source of the second NMOS transistor is grounded; the gate of the first high-voltage PMOS transistor is connected to the gate and drain of the second high-voltage PMOS transistor, and the gate of the third high-voltage PMOS transistor; the drain of the second sampling high-voltage NMOS transistor is connected to PMID and the source is connected to the emitter of the third PNP transistor, the emitter of the fourth PNP transistor, and one end of the second capacitor, the first The other end of the two capacitors is grounded; the collector of the third PNP transistor is connected to the bias current IB through the second high-voltage PMOS transistor; the collector of the fourth PNP transistor is connected to the drain of the third NMOS transistor through the third high-voltage PMOS transistor; the gate of the third NMOS transistor is connected to the gate of the first NMOS transistor and the drain of the first high-voltage PMOS transistor; the connection point between the third high-voltage PMOS transistor and the third NMOS transistor is connected to one end of the third capacitor and the gate of the first PMOS transistor; the other end of the third capacitor is grounded; the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor and the source of the fourth NMOS transistor is grounded; the gate of the fourth NMOS transistor is connected to the gate of the second NMOS transistor and the drain of the first NMOS transistor; the drain of the third high-voltage NMOS transistor is connected to the source of the first sampling high-voltage NMOS transistor; the source of the third high-voltage NMOS transistor is connected to the source of the first PMOS transistor; the gate of the third high-voltage NMOS transistor is connected to an external enable signal; the drain of the first PMOS transistor is connected to ground through the sampling resistor RS; and the drain of the first PMOS transistor outputs the sampling voltage VS through the fourth resistor; one end of the fourth capacitor is connected to the drain of the first PMOS transistor through the fourth resistor, and the other end is grounded.

[0007] The beneficial effects of this invention are as follows: This invention adopts an on-chip sampling method and does not require a sampling resistor in series on the power path, effectively avoiding the additional high power consumption and additional pins introduced by traditional sampling circuits, thereby realizing input current sampling suitable for low power consumption and miniaturized applications. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a buck circuit with a blocking power transistor.

[0009] Figure 2 This is a schematic diagram of the input current average sampling structure proposed in this invention. Detailed Implementation

[0010] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings:

[0011] like Figure 1 As shown, the source of the blocking power transistor Q1 is connected to the input voltage VIN, the gate voltage is labeled VG, and the drain voltage PMID is connected to the upper power transistor Q2. The upper power transistor Q2 is connected to ground through the lower power transistor Q3, and is connected to the output voltage VOUT through the inductor L and its equivalent series resistance RDCR. The output voltage is connected to ground through the load resistor RLOAD and also through the load capacitor COUT and its equivalent series resistance RESR. The invention proposed in this paper is a circuit structure that processes the relevant voltage information of the blocking power transistor to obtain the average input current information.

[0012] like Figure 2 As shown, the bias current IB is connected to the second and third PNP transistors (which are diode-connected) through the second high-voltage PMOS transistor, thus providing bias current for the circuit. The first to fourth PNP transistors are all the same size. A current mirror formed by the first and second PNP transistors shows that the current flowing through the emitters of the first and second PNP transistors is the same. Similarly, the current flowing through the emitters of the third and fourth PNP transistors is the same. The third resistor, the first NMOS transistor, and the second NMOS transistor form a low-voltage common-source common-gate current mirror, so the current flowing through the first and fourth PNP transistors is the same. Therefore, the current flowing through the first resistor, which is the sum of the currents of the first and second PNP transistors, is equal to the current flowing through the second resistor, which is the sum of the currents of the third and fourth PNP transistors. Therefore, the source voltages of the first and second sampling high-voltage NMOS transistors are the same. Since the blocking power transistor operates in the deep linear region, the current relationship can be obtained from its gate, source, and drain voltages:

[0013]

[0014] The first and second sampling high-voltage NMOS transistors are identical in size and operate in the same deep linear region as the blocking power transistors. Therefore, their on-resistances are equal, and similarly, the current difference flowing through them, i.e., the sampling current, can be obtained.

[0015]

[0016] Since the first and second sampling high-voltage NMOS transistors and the blocking power transistor are the same type of NMOS transistor, different input current sampling ratios can be achieved simply by adjusting the width-to-length ratio of the sampling transistor and the power transistor. The sampling current flows through the sampling resistor RS to generate a sampling voltage, thus the equivalent current sampling resistor can be obtained as:

[0017]

[0018] Because the upper and lower power transistors continuously switch during actual circuit operation, the input current also contains current ripple with switching frequency components. To obtain the average value of the input current, this invention employs multi-stage filtering to significantly suppress AC signals. The RC filter network composed of the first resistor and the first capacitor can filter out certain high-frequency signals, and its pole locations can be represented as:

[0019]

[0020] The third high-voltage NMOS is used for high-voltage applications in the circuit. Ignoring its impact on the loop, the loop gain and GBW of the circuit design in this invention can be obtained as follows:

[0021]

[0022]

[0023] By setting the bias current IB and the value of the third capacitor, the loop bandwidth of the simultaneous circuit is designed to be lower than the switching frequency. Therefore, a pole below the switching frequency is formed when the circuit is closed, thus suppressing switching ripple. Because the op-amp bandwidth is designed to be relatively small, IB is relatively small, which allows the sampling circuit proposed in this invention to achieve low power consumption. In actual design, a trade-off can be made between circuit response speed and bandwidth filtering effect. The voltage across the sampling resistor RS passes through a filter network generated by the fourth resistor and the fourth capacitor to obtain the sampling voltage VS. The pole frequency of this filter network can be obtained as:

[0024]

[0025] By filtering the circuit three times, a sampling voltage VS containing input current information can be obtained that is close to DC. Compared with traditional current sampling circuits, this invention greatly reduces power consumption.

[0026] Based on the above analysis of the invention's principles, it can be seen that this invention not only reduces additional sampling pins but also greatly reduces the power consumption required for current sampling, making it more suitable for miniaturized and low-power applications.

[0027] Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the essence of this invention, and these modifications and combinations are still within the protection scope of this invention.

Claims

1. An input current averaging sampling circuit for a buck circuit with a blocking power transistor, wherein the source of the blocking power transistor Q1 is connected to the input voltage VIN, the gate voltage is labeled VG, and the drain voltage PMID is connected to the upper power transistor Q2; the upper power transistor Q2 is connected to ground through the lower power transistor Q3, and is connected to the output voltage Vout through an inductor L and its equivalent series resistance Rdcr, the output voltage being connected to ground through a load resistor Rload and simultaneously through a load capacitor Cout and its equivalent series resistance Resr, characterized in that... The sampling circuit includes a first high-voltage NMOS transistor, a second high-voltage NMOS transistor, a third high-voltage NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a sampling resistor Rs, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first PNP transistor, a second PNP transistor, a third PNP transistor, a fourth PNP transistor, a first high-voltage PMOS transistor, a second high-voltage PMOS transistor, a third high-voltage PMOS transistor, a bias current IB, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; Define the source, drain, and gate voltages of the blocking power transistors as VIN, PMID, and VG, respectively. The drain of the first sampling high-voltage NMOS transistor is connected to VIN, the gate to VG, and the source to one end of the first resistor. The emitters of the first and second PNP transistors are shorted to the other end of the first resistor and connected to ground through the first capacitor. The collector of the first PNP transistor is connected to the source of the first high-voltage PMOS transistor. The collector of the second PNP transistor is connected to the bias current IB through the second high-voltage PMOS transistor. The base of the first PNP transistor is connected to the base and collector of the second PNP transistor, and the third P... The base and collector of the NP transistor, and the base of the fourth PNP transistor; the drain of the first high-voltage PMOS transistor is connected to the drain of the first NMOS transistor through a third resistor, the drain of the second NMOS transistor is connected to the source of the first NMOS transistor and the source of the second NMOS transistor is grounded; the gate of the first high-voltage PMOS transistor is connected to the gate and drain of the second high-voltage PMOS transistor, and the gate of the third high-voltage PMOS transistor; the drain of the second sampling high-voltage NMOS transistor is connected to PMID and the source is connected to the emitter of the third PNP transistor, the emitter of the fourth PNP transistor, and one end of the second capacitor, the first The other end of the two capacitors is grounded; the collector of the third PNP transistor is connected to the bias current IB through the second high-voltage PMOS transistor; the collector of the fourth PNP transistor is connected to the drain of the third NMOS transistor through the third high-voltage PMOS transistor; the gate of the third NMOS transistor is connected to the gate of the first NMOS transistor and the drain of the first high-voltage PMOS transistor; the connection point between the third high-voltage PMOS transistor and the third NMOS transistor is connected to one end of the third capacitor and the gate of the first PMOS transistor; the other end of the third capacitor is grounded; the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor and the source of the fourth NMOS transistor is grounded; the gate of the fourth NMOS transistor is connected to the gate of the second NMOS transistor and the drain of the first NMOS transistor; the drain of the third high-voltage NMOS transistor is connected to the source of the first sampling high-voltage NMOS transistor; the source of the third high-voltage NMOS transistor is connected to the source of the first PMOS transistor; the gate of the third high-voltage NMOS transistor is connected to an external enable signal; the drain of the first PMOS transistor is connected to ground through the sampling resistor Rs; and the drain of the first PMOS transistor outputs the sampling voltage Vs through the fourth resistor; one end of the fourth capacitor is connected to the drain of the first PMOS transistor through the fourth resistor, and the other end is grounded.

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