A semiconductor device testing tool and system
By testing probe arrays and programmable device modules to detect short-circuit connections in semiconductor devices, the problem of high procurement costs caused by different packaging forms is solved, and compatible testing of multiple packaging forms and efficient Kelvin four-wire testing are achieved.
Patent Information
- Application Number
- CN202410042263.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-11
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2044-01-11
AI Technical Summary
Different package forms of discrete semiconductor devices require different test fixtures, resulting in high procurement costs for manufacturers and users. Furthermore, differences in device size between different manufacturers can lead to test defects, requiring users to equip themselves with a variety of fixtures to accommodate different package forms.
Employing a test probe array and programmable device modules, this system detects short-circuit connections between probe contacts, adapting to various package types of semiconductor devices, including programmable chips and memory cells, to store and process short-circuit connection data, supporting compatible testing of multiple package forms.
It enables flexible testing of semiconductor devices in various package types, reducing procurement costs for manufacturers and users, and supports Kelvin four-wire testing, improving testing efficiency and adaptability.
Smart Images
Figure CN117907784B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device testing, and in particular to a semiconductor device testing tool and system. Background Technology
[0002] Semiconductor discrete device test fixtures can test the functionality of semiconductor discrete devices and are widely used in R&D testing by device manufacturers and material selection testing by end users. During testing, test fixtures are used to connect the pins of the semiconductor discrete device to the corresponding interface of the test fixture. The test fixtures accurately and stably hold the pins of the semiconductor discrete device. Semiconductor discrete devices come in various package forms, such as Dual Flat No-Lead (DFN) and Quad Flat No-Lead (QFN), with each package form corresponding to a specific test fixture. Therefore, semiconductor discrete device manufacturers need to equip themselves with test fixtures for different packages to adapt to their product form factors, resulting in higher procurement costs for manufacturers. Furthermore, users have the opportunity to select components from various manufacturers. However, due to differences in molds between manufacturers, the dimensions of components with the same package produced by different manufacturers also vary. Users often encounter situations where the test fixture can test components from manufacturer A normally, but cannot test components from manufacturer B with the same package due to slight size differences. A set of test fixtures suitable for manufacturer B must be prepared for normal testing, resulting in high procurement costs for users.
[0003] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention
[0004] The purpose of this application is to provide a semiconductor device testing tool and system, so that the testing tool is applicable to semiconductor devices under test of various package types, thereby reducing the procurement costs for semiconductor device manufacturers and users.
[0005] To address the aforementioned technical problems, this application provides a semiconductor device testing tool, comprising: a test probe array, a programmable device module, and an output connection interface;
[0006] The test probe array includes multiple probe contacts, each of which is connected to the programmable device module.
[0007] One end of the output connection interface is connected to the programmable device module, and the other end is used to connect to semiconductor device testing equipment;
[0008] The programmable device module is used to detect the short-circuit connection between adjacent probe contacts so that probe contacts with the same short-circuit connection can be connected to a test terminal of the semiconductor device under test.
[0009] In one possible implementation, the programmable device module includes a first storage unit and a programmable chip;
[0010] The first storage unit is used to store a program for detecting short-circuit connections between probe contacts;
[0011] The probe contacts are connected to the input / output interface of the programmable chip, which is used to run a program to detect the short-circuit connection between the probe contacts in order to determine the short-circuit connection between the probe contacts.
[0012] As one possible implementation, the programmable device module further includes: a first communication interface;
[0013] One end of the first communication interface is connected to the programmable chip, and the other end of the first communication interface is connected to the second communication interface of the semiconductor device testing tool; the second communication interface is connected to the client.
[0014] The first communication interface and the second communication interface are used to transmit the short-circuit connection relationship between the probe contacts to the client and to transmit the client partitioning instruction to the programmable chip, so that the programmable chip can divide the target probe contact array with the same short-circuit connection relationship into multiple different probe contact sub-arrays, or merge the target probe contact arrays with different short-circuit connection relationships.
[0015] As one possible implementation, the programmable device module further includes: a display control unit connected to the programmable chip;
[0016] The display control unit is used to display the short-circuit connection relationship between the probe contacts; receive and transmit customer partitioning instructions to the programmable chip, so that the programmable chip can divide the target probe contact array with the same short-circuit connection relationship into multiple different probe contact sub-arrays, or merge the target probe contact arrays with different short-circuit connection relationships.
[0017] As one possible implementation, the programmable device module further includes: a second storage unit;
[0018] The second storage unit is used to store the short-circuit connection relationship between the probe contacts.
[0019] As one possible implementation, it further includes: a test carrier board; the probe test array, the programmable device module, and the output connection interface are disposed on the test carrier board.
[0020] As one possible implementation, it also includes: a fixing component;
[0021] The fixing component is fixed to the test carrier plate and is used to fix the semiconductor device under test.
[0022] As one possible implementation, the fixing component is an elastic fixing component.
[0023] In one possible implementation, one end of the elastic fixing member is fixed to the test carrier plate, and the elastic fixing member rotates about the fixed end as an axis.
[0024] This application also provides a semiconductor device testing system, including semiconductor device testing equipment and any of the semiconductor device testing tools described above.
[0025] This application provides a semiconductor device testing tool, comprising: a test probe array, a programmable device module, and an output connection interface; the test probe array includes multiple probe contacts, each of which is connected to the programmable device module; one end of the output connection interface is connected to the programmable device module, and the other end is used to connect to a semiconductor device testing equipment; the programmable device module is used to detect short-circuit connections between adjacent probe contacts, so that probe contacts with the same short-circuit connection are connected to a test terminal of the semiconductor device under test.
[0026] As can be seen, the test probe array in the semiconductor device testing tool of this application includes multiple probe contacts. The programmable device module can detect the short-circuit connection between the probe contacts. Probe contacts with the same short-circuit connection can be connected to a test terminal of the semiconductor device under test (DUT), and then the semiconductor device testing equipment can test the DUT. Connecting to the test terminal of the DUT via a probe contact array is applicable to various package types of DUTs, offering high flexibility and reducing procurement costs for semiconductor device manufacturers and users.
[0027] In addition, this application also provides a semiconductor device testing system with the above advantages. Attached Figure Description
[0028] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1This is a schematic diagram showing the distribution of probe contacts inside a test fixture in a related technology;
[0030] Figure 2 A top view of a discrete semiconductor device;
[0031] Figure 3 for Figure 2 The bottom view of the semiconductor discrete device shown;
[0032] Figure 4 for Figure 2 A schematic diagram showing the distribution of each pin in a discrete semiconductor device.
[0033] Figure 5 for Figure 2 The schematic diagram of the semiconductor discrete device is shown.
[0034] Figure 6 The structural framework of a semiconductor device testing tool provided in the embodiments of this application. Figure 1 ;
[0035] Figure 7 The structural framework of a semiconductor device testing tool provided in the embodiments of this application. Figure 2 ;
[0036] Figure 8 The structural framework of a semiconductor device testing tool provided in the embodiments of this application. Figure 3 ;
[0037] Figure 9 This is a graphical schematic diagram of the detection result of probe contact short circuit connection relationship provided in an embodiment of this application;
[0038] Figure 10 To Figure 9 A schematic diagram showing the probe contacts after being divided and merged;
[0039] Figure 11 The structural framework of a semiconductor device testing tool provided in the embodiments of this application. Figure 4 ;
[0040] Figure 12 The structural framework of a semiconductor device testing tool provided in the embodiments of this application. Figure 5 ;
[0041] Figure 13 A front view of a test carrier provided in an embodiment of this application. Figure 1 ;
[0042] Figure 14 A schematic diagram of the back side of a test carrier provided in an embodiment of this application. Figure 1 ;
[0043] Figure 15 A front view of a test carrier provided in an embodiment of this application. Figure 2 ;
[0044] Figure 16 A schematic diagram of the back side of a test carrier provided in an embodiment of this application. Figure 2 ;
[0045] Figure 17 This is a structural block diagram of a semiconductor device testing system provided in an embodiment of this application;
[0046] Figure 18 This is a flowchart illustrating the semiconductor device testing system in this application testing the semiconductor device under test. Detailed Implementation
[0047] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0048] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.
[0049] As described in the background section, discrete semiconductor devices come in various package forms, and each package requires a specific test fixture for functional testing. Therefore, semiconductor discrete device manufacturers need to equip themselves with test fixtures for different packages to fit their product shapes, leading to higher procurement costs. Furthermore, while users have the opportunity to choose from devices from various manufacturers, differences in molds between manufacturers result in variations in the dimensions of devices in the same package. Even for devices with the same package form, these slight dimensional differences between manufacturers necessitate the purchase of multiple test fixtures for proper testing, further increasing procurement costs for users.
[0050] For discrete semiconductor devices currently packaged in a double-sided flat, leadless 3x3 package, the schematic diagram of the probe contact distribution inside the test fixture is as follows: Figure 1 As shown. Figure 1The test setup includes 10 probe contacts, each hidden within its own recess. When a discrete semiconductor device is placed on the test socket, it is pressed down by the upper pressure block, causing the corresponding pins of the device to contact the probe contacts. These probe contacts then connect to the various test ports of the semiconductor power device analyzer.
[0051] Figure 1 The 10 probe contacts are arranged in three rows. In order from top to bottom, the first row has four probe contacts, named 1#, 2#, 3# and 4# from left to right. The second row has two probe contacts, named 5# and 6# from left to right. The third row has four probe contacts, named 7#, 8#, 9# and 10# from left to right.
[0052] The datasheet for a semiconductor discrete device in a double-sided flat, leadless 3x3 package is as follows: Figures 2 to 5 As shown, a discrete semiconductor device has three pin terminals: G (gate), D (drain), and S (source). The discrete semiconductor device has a total of eight pins: Pin1, Pin2, and Pin3 correspond to the S terminal; Pin4 corresponds to the G terminal; and Pin5, Pin6, Pin7, and Pin8 correspond to the D terminal. The correspondence between each pin terminal and the probe contact is shown in Table 1.
[0053] Table 1
[0054] G pole, Pin4 Probe contact #10 S pole, Pin1, Pin2, Pin3 Probe contacts 7#, 8#, 9# D terminal, Pin5, Pin6, Pin7, Pin8 Probe contacts 1#, 2#, 3#, 4#
[0055] In view of this, this application provides a semiconductor device testing tool, please refer to... Figure 6 It includes: test probe array 1, programmable device module 2, and output connection interface 3;
[0056] The test probe array 1 includes multiple probe contacts 11, each probe contact 11 being connected to the programmable device module 2;
[0057] One end of the output connection interface 3 is connected to the programmable device module 2, and the other end is used to connect to the semiconductor device testing equipment;
[0058] The programmable device module 2 is used to detect the short-circuit connection relationship between adjacent probe contacts 11 so that probe contacts 11 with the same short-circuit connection relationship can be connected to a test terminal of the semiconductor device under test.
[0059] In this embodiment, the number of probe contacts 11 in the test probe array 1 is not limited and can be set by the user. The probe contacts 11 can be distributed in a regular array, for example, the probe contacts 11 can be distributed in an M×N array, where M is the number of probe contacts 11 in each row and N is the number of probe contacts 11 in each column. M and N can be equal or unequal.
[0060] In the test probe array 1, each probe contact 11 is independent and not connected to each other.
[0061] The semiconductor device under test can be a discrete semiconductor device such as a diode, a transistor, or a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and this application does not impose any specific limitations.
[0062] The output connection interface 3 can be a cable interface, one end of which is connected to the programmable device module 2 and the other end is connected to the semiconductor device testing equipment. Since the programmable device module 2 is connected to the probe contact 11 with the same short-circuit connection relationship, and the probe contact 11 with the same short-circuit connection relationship is connected to the test terminal of the semiconductor device under test, the semiconductor device testing equipment can test the function of the semiconductor device under test.
[0063] The programmable device module 2 detects whether there is a short circuit between adjacent probe contacts 11 due to contact with the same device pin.
[0064] Furthermore, the programmable device module 2 can also be used to mark probe contacts 11 that are in the same short-circuit connection relationship. The marking method can be to add the same identifier to probe contacts 11 that are in the same short-circuit connection relationship. For example, when a graphic symbol (such as a circle, square, etc.) represents a probe contact 11, the graphic symbols corresponding to probe contacts 11 that are in the same short-circuit connection relationship are filled with the same color or the same pattern, and so on.
[0065] As one possible implementation, the semiconductor device test tool may also include a power supply port, which connects to a power source to supply power to the various components within the semiconductor device test tool.
[0066] In this embodiment, the test probe array 1 of the semiconductor device testing tool includes multiple probe contacts 11. The programmable device module 2 can detect the short-circuit connection between the probe contacts 11. Probe contacts 11 with the same short-circuit connection can be connected to a test terminal of the semiconductor device under test (DUT), and then the semiconductor device testing equipment can test the DUT. Connecting to the test terminal of the DUT via the probe contact array 11 is applicable to various package types of DUTs, offering high flexibility and reducing procurement costs for semiconductor device manufacturers and users.
[0067] Please refer to Figure 7 Based on the above embodiments, in one embodiment of this application, the semiconductor device testing tool includes: a test probe array 1, a programmable device module 2, and an output connection interface 3;
[0068] The test probe array 1 includes multiple probe contacts 11, each probe contact 11 being connected to the programmable device module 2;
[0069] One end of the output connection interface 3 is connected to the programmable device module 2, and the other end is used to connect to the semiconductor device testing equipment;
[0070] The programmable device module 2 is used to detect the short-circuit connection relationship between adjacent probe contacts 11 so that the probe contacts 11 with the same short-circuit connection relationship can be connected to a test terminal of the semiconductor device under test.
[0071] The programmable device module 2 includes a first storage unit 22 and a programmable chip 21.
[0072] The first storage unit 22 is used to store the program for detecting the short-circuit connection relationship between the probe contacts 11;
[0073] The probe contacts 11 are connected to the input / output interface of the programmable chip 21. The programmable chip 21 is used to run a program to detect the short-circuit connection relationship between the probe contacts 11 in order to determine the short-circuit connection relationship between the probe contacts 11.
[0074] Programmable chips 21 include, but are not limited to, field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs).
[0075] For discrete semiconductor devices, with advancements in device manufacturing processes, the Rdson (on-resistance of MOSFETs) has become as small as a few mohms (mΩ, milliohms, a unit of resistance). Accurately testing mohm-level resistances can no longer be done using the conventional two-wire method; the Kelvin four-wire method is required. When testing discrete semiconductor devices using the Kelvin four-wire method (two wires from each end of the resistor, for a total of four wires), the test fixture must be designed so that certain pins have two branch lines, and the branching point of these two lines is located on a pin of the device.
[0076] In related technologies, test fixtures are all custom-made by third-party manufacturers. The pin connections on these manufacturer-made fixtures cannot be modified. If a single wire is connected (including cases where multiple wires are shorted together), the device cannot be used for semiconductor devices requiring Kelvin four-wire testing. To resolve this technical issue, please refer to... Figure 8 Based on any of the above embodiments, in one embodiment of this application, the semiconductor device testing tool includes: a test probe array 1, a programmable device module 2, and an output connection interface 3;
[0077] The test probe array 1 includes multiple probe contacts 11, each probe contact 11 being connected to the programmable device module 2;
[0078] One end of the output connection interface 3 is connected to the programmable device module 2, and the other end is used to connect to the semiconductor device testing equipment;
[0079] The programmable device module 2 is used to detect the short-circuit connection relationship between adjacent probe contacts 11 so that the probe contacts 11 with the same short-circuit connection relationship can be connected to a test terminal of the semiconductor device under test.
[0080] The programmable device module 2 includes a first storage unit 22, a programmable chip 21, and a first communication interface 23.
[0081] The first storage unit 22 is used to store the program for detecting the short-circuit connection relationship between the probe contacts 11;
[0082] The probe contacts 11 are connected to the input / output interface of the programmable chip 21. The programmable chip 21 is used to run a program to detect the short-circuit connection relationship between the probe contacts 11 in order to determine the short-circuit connection relationship between the probe contacts 11.
[0083] One end of the first communication interface 23 is connected to the programmable chip 21, and the other end of the first communication interface 23 is connected to the second communication interface 4 of the semiconductor device testing tool; the second communication interface 4 is connected to the client.
[0084] The first communication interface 23 and the second communication interface 4 are used to transmit the short-circuit connection relationship between probe contacts 11 to the client and transmit the client partitioning instruction to the programmable chip 21 so that the programmable chip 21 can divide the array of target probe contacts 11 with the same short-circuit connection relationship into multiple different probe contact 11 sub-arrays, or merge the arrays of target probe contacts 11 with different short-circuit connection relationships.
[0085] The second communication interface 4 of the semiconductor device testing tool can serve as a data communication interface between the client and the semiconductor device testing tool. The client connected to the second communication interface 4 can be a laptop, tablet, smartphone, etc.
[0086] After determining the short-circuit connection relationship between the probe contacts 11, the programmable chip 21 sends the short-circuit connection relationship between the probe contacts 11 to the client through the first communication interface 23 and the second communication interface 4. The client can then display the test probe array 1 and the probe contacts 11 marked by the programmable chip 21 that are in the same short-circuit connection relationship, such as... Figure 9 As shown. Figure 9 The example illustrates five groups of probe contacts 11 with the same short-circuit connection. These probe contacts 11 with the same short-circuit connection are grouped together by dashed boxes and labeled as region A, region B, region C, region D, and region E, respectively. The black-filled circles within each dashed box represent probe contacts 11 with the same short-circuit connection.
[0087] According to the Kelvin four-wire test requirements, two lines need to be drawn from both the source (S) and drain (D) terminals of the semiconductor device under test. Therefore, the user can divide region A into two regions in the software and draw two lines from each region. Similarly, the user can merge regions B and C in the software, treating the merged region B and C, along with region D, as two separate regions, and draw two lines from each. Region E requires no processing and can be directly drawn. For example... Figure 10 As shown.
[0088] It should be noted that the method of dividing and merging regions can be set arbitrarily and is not limited in this application, as long as it meets the requirements of the Kelvin four-line method test. For example, region A can be divided into two regions, region C and region D can be merged, and the merged region D, region C, and region B can be considered as two regions, with region E directly extracted without processing. Alternatively, region A can be divided into two regions, region E and region D can be merged, and the merged region D, region E, and region C can be considered as two regions, with region B directly extracted without processing.
[0089] The semiconductor device testing tool in this embodiment is not only compatible with testing semiconductor devices under test with various different packages, but also enables Kelvin four-wire testing, making the test preparation process highly efficient.
[0090] For discrete semiconductor devices, with advancements in device manufacturing processes, the Rdson resistance can now be as small as a few mohms. Accurate testing of mohm-level resistances can no longer be achieved using the conventional two-wire method; the Kelvin four-wire method is required. When testing discrete semiconductor devices using the Kelvin four-wire method, the test fixture must have two wires branching off from certain pins, with the branching point of these two wires located on a pin of the device.
[0091] In related technologies, test fixtures are all custom-made by third-party manufacturers. The pin connections on these manufacturer-made fixtures cannot be modified. If a single wire is connected (including cases where multiple wires are shorted together), the device cannot be used for semiconductor devices requiring Kelvin four-wire testing. To resolve this technical issue, please refer to... Figure 11 Based on any of the above embodiments, in one embodiment of this application, the semiconductor device testing tool includes: a test probe array 1, a programmable device module 2, and an output connection interface 3;
[0092] The test probe array 1 includes multiple probe contacts 11, each probe contact 11 being connected to the programmable device module 2;
[0093] One end of the output connection interface 3 is connected to the programmable device module 2, and the other end is used to connect to the semiconductor device testing equipment;
[0094] The programmable device module 2 is used to detect the short-circuit connection relationship between adjacent probe contacts 11 so that the probe contacts 11 with the same short-circuit connection relationship can be connected to a test terminal of the semiconductor device under test.
[0095] The programmable device module 2 includes a first storage unit 22, a programmable chip 21, and a display control unit 24 connected to the programmable chip 21.
[0096] The first storage unit 22 is used to store the program for detecting the short-circuit connection relationship between the probe contacts 11;
[0097] The probe contacts 11 are connected to the input / output interface of the programmable chip 21. The programmable chip 21 is used to run a program to detect the short-circuit connection relationship between the probe contacts 11 in order to determine the short-circuit connection relationship between the probe contacts 11.
[0098] The display control unit 24 is used to display the short-circuit connection relationship between probe contacts 11; receive and transmit customer partitioning instructions to the programmable chip 21 so that the programmable chip 21 can divide the array of target probe contacts 11 with the same short-circuit connection relationship into multiple different probe contact 11 sub-arrays, or merge the arrays of target probe contacts 11 with different short-circuit connection relationships.
[0099] The display control unit 24 has a UI (User Interface) design, which can display the test probe array 1 and the probe contacts 11 marked by the programmable chip 21 that are in the same short-circuit connection relationship. Users can also perform touch operations on the display control unit 24.
[0100] like Figure 9 As shown, five groups of probe contacts 11 with the same short-circuit connection are illustrated as an example. These probe contacts 11 are grouped together by dashed lines and labeled as region A, region B, region C, region D, and region E. According to the Kelvin four-wire method testing requirements, two lines need to be drawn from both the S-terminal and D-terminal of the semiconductor device under test. Therefore, the user can operate on the display control unit 24 to divide region A into two regions, drawing two lines from each. Similarly, the user can merge regions B and C, treating the merged region B, region C, and region D as two separate regions, drawing two lines from each. Region E requires no processing and is directly drawn out. Figure 10 As shown.
[0101] It should be noted that the method of dividing and merging regions can be set arbitrarily, and this embodiment does not impose any limitations, as long as it meets the requirements of the Kelvin four-line method test. For example, region A can be divided into two regions, region C and region D can be merged, and the merged region D, region C, and region B can be considered as two regions, with region E directly extracted without processing. Alternatively, region A can be divided into two regions, region E and region D can be merged, and the merged region D, region E, and region C can be considered as two regions, with region B directly extracted without processing.
[0102] The semiconductor device testing tool in this embodiment is not only compatible with testing semiconductor devices under test with various different packages, but also enables Kelvin four-wire testing, making the test preparation process highly efficient.
[0103] Please refer to Figure 12 Based on any of the above embodiments, in one embodiment of this application, the semiconductor device testing tool includes: a test probe array 1, a programmable device module 2, and an output connection interface 3;
[0104] The test probe array 1 includes multiple probe contacts 11, each probe contact 11 being connected to the programmable device module 2;
[0105] One end of the output connection interface 3 is connected to the programmable device module 2, and the other end is used to connect to the semiconductor device testing equipment;
[0106] The programmable device module 2 is used to detect the short-circuit connection relationship between adjacent probe contacts 11 so that the probe contacts 11 with the same short-circuit connection relationship can be connected to a test terminal of the semiconductor device under test.
[0107] The programmable device module 2 includes a first storage unit 22, a programmable chip 21, a display control unit 24 connected to the programmable chip 21, and a second storage unit 25.
[0108] The first storage unit 22 is used to store the program for detecting the short-circuit connection relationship between the probe contacts 11;
[0109] The probe contacts 11 are connected to the input / output interface of the programmable chip 21. The programmable chip 21 is used to run a program to detect the short-circuit connection relationship between the probe contacts 11 in order to determine the short-circuit connection relationship between the probe contacts 11.
[0110] The second storage unit 25 is used to store the short-circuit connection relationship between the probe contacts 11.
[0111] The detected short-circuit connection relationship between adjacent probe contacts 11 is stored in the second storage unit 25 for easy querying of the short-circuit connection relationship of probe contacts 11 later.
[0112] In this embodiment, the user can recall the short-circuit connection relationship between the probe contacts 11 stored in the second storage unit 25 through the display control unit 24.
[0113] Please refer to Figure 13 and 14 Based on any of the above embodiments, in one embodiment of this application, the semiconductor device testing tool includes: a test probe array 1, a programmable device module 2, an output connection interface 3, and a test carrier board 5;
[0114] The test probe array 1 includes multiple probe contacts 11, each probe contact 11 being connected to the programmable device module 2;
[0115] One end of the output connection interface 3 is connected to the programmable device module 2, and the other end is used to connect to the semiconductor device testing equipment;
[0116] The programmable device module 2 is used to detect the short-circuit connection relationship between adjacent probe contacts 11 so that the probe contacts 11 with the same short-circuit connection relationship can be connected to a test terminal of the semiconductor device under test.
[0117] The probe test array, programmable device module 2, and output connection interface 3 are set on the test carrier board 5.
[0118] The test carrier 5 can be a PCB (Printed Circuit Board) or its circuit board.
[0119] like Figure 13 As shown, a test probe array 1, consisting of multiple independent and unconnected probe contacts 11, is disposed on the front side of the test carrier board 5, as follows: Figure 14 As shown, the programmable device module 2 and the output connection interface 3 are located on the back of the test carrier board 5, which can reduce the area occupied by the semiconductor device test tool.
[0120] Based on the above embodiments, in one embodiment of this application, the semiconductor device testing tool includes: a test probe array 1, a programmable device module 2, an output connection interface 3, a test carrier board 5, and a fixing component 6;
[0121] The test probe array 1 includes multiple probe contacts 11, each probe contact 11 being connected to the programmable device module 2;
[0122] One end of the output connection interface 3 is connected to the programmable device module 2, and the other end is used to connect to the semiconductor device testing equipment;
[0123] The programmable device module 2 is used to detect the short-circuit connection relationship between adjacent probe contacts 11 so that the probe contacts 11 with the same short-circuit connection relationship can be connected to a test terminal of the semiconductor device under test.
[0124] The probe test array, programmable device module 2, and output connection interface 3 are mounted on the test carrier board 5.
[0125] The fixing component 6 is fixed on the test carrier plate 5 and is used to fix the semiconductor device under test.
[0126] During testing, the semiconductor device under test is fixed by the fixing component 6 to ensure good contact between the pin of the semiconductor device under test and the probe contact 11, and the test proceeds smoothly.
[0127] It should be noted that the type of fixing component 6 is not limited in this embodiment and can be set by the user. For example, the fixing component 6 can be a pressure block, an elastic component, etc.
[0128] Please refer to Figure 15 Based on the above embodiments, in one embodiment of this application, the semiconductor device testing tool includes: a test probe array 1, a programmable device module 2, an output connection interface 3, a test carrier board 5, and a fixing component 6;
[0129] The test probe array 1 includes multiple probe contacts 11, each probe contact 11 being connected to the programmable device module 2;
[0130] One end of the output connection interface 3 is connected to the programmable device module 2, and the other end is used to connect to the semiconductor device testing equipment;
[0131] The programmable device module 2 is used to detect the short-circuit connection relationship between adjacent probe contacts 11 so that the probe contacts 11 with the same short-circuit connection relationship can be connected to a test terminal of the semiconductor device under test.
[0132] The probe test array, programmable device module 2, and output connection interface 3 are mounted on the test carrier board 5.
[0133] The fixing component 6 is fixed on the test carrier plate 5 to fix the semiconductor device under test, and the fixing component 6 is an elastic fixing component.
[0134] At least one end of the elastic fixing component is fixed to the test carrier plate 5. The elastic fixing component can be a spring plate, elastic belt, etc., all of which are within the scope of protection of this application.
[0135] In this embodiment, the fixing component 6 is set as an elastic fixing component, which can be applied to semiconductor devices under test of different sizes, and can further enhance the contact between the semiconductor device under test and the probe contact 11.
[0136] As one possible implementation, one end of the elastic fixing member is fixed to the test carrier plate 5, and the elastic fixing member rotates about the fixed end as an axis.
[0137] The fixing component 6 can be set on either side of the test probe array 1. Figure 15 The example shown is located on the left side of the test probe array 1.
[0138] One end of the elastic fixing component can be fixed to the test carrier plate 5 by screw 7, such as Figure 16 As shown, the elastic fixing component rotates at its fixed end, covering a larger area of the test probe array 1, and can be fixed even if the semiconductor device under test is in any position.
[0139] Based on any of the above embodiments, in one embodiment of this application, the test substrate 5 is provided with holes, and elastic telescopic components are provided in the holes. The number of holes is equal to the number of probe contacts 11, and each probe contact 11 is disposed in one hole. The probe contact 11 is disposed on the elastic telescopic component and extends out of the surface of the test substrate 5. The probe contact 11 is telescopic, which provides better ohmic connection when the probe contact 11 contacts the pin of the semiconductor device under test during the test, while avoiding damage to the pin of the semiconductor device under test. The elastic telescopic component can be a spring.
[0140] The following is a description of a semiconductor device testing tool described in this application.
[0141] The semiconductor device testing tool includes: a test probe array 1, a programmable device module 2, an output connection interface 3, a test carrier board 5, an elastic fixing component, and a second communication interface 4; wherein, the programmable device module 2 includes a first storage unit 22, a programmable chip 21, a first communication interface 23, a display control unit 24, and a second storage unit 25.
[0142] The first storage unit 22 is used to store the program for detecting the short-circuit connection relationship between the probe contacts 11; the programmable chip 21 is used to run the program for detecting the short-circuit connection relationship between the probe contacts 11 to determine the short-circuit connection relationship between the probe contacts 11.
[0143] One end of the first communication interface 23 is connected to the programmable chip 21, and the other end of the first communication interface 23 is connected to the second communication interface 4; the second communication interface 4 is connected to the client.
[0144] The first communication interface 23 and the second communication interface 4 are used to transmit the short-circuit connection relationship between probe contacts 11 to the client and transmit the client partitioning instruction to the programmable chip 21 so that the programmable chip 21 can divide the target probe contact 11 array with the same short-circuit connection relationship into multiple different probe contact 11 sub-arrays, or merge the target probe contact 11 arrays with different short-circuit connection relationships.
[0145] The display control unit 24 is used to display the short-circuit connection relationship between probe contacts 11; receive and transmit customer partitioning instructions to the programmable chip 21 so that the programmable chip 21 can divide the target probe contact 11 array with the same short-circuit connection relationship into multiple different probe contact 11 sub-arrays, or merge the target probe contact 11 arrays with different short-circuit connection relationships.
[0146] The second storage unit 25 is used to store the short-circuit connection relationship between the probe contacts 11;
[0147] The test probe array 1 includes multiple probe contacts 11, each probe contact 11 is connected to the input / output interface of the programmable chip 21; each probe contact 11 is located in a hole on the test carrier board 5, and an elastic telescopic component is provided below the probe contact 11, with the probe contact 11 extending out of the surface of the test carrier board 5.
[0148] One end of the output connection interface 3 is connected to the input / output interface of the programmable chip 21, and the other end is connected to the semiconductor device testing equipment;
[0149] The probe test array and the elastic fixing component are located on the front side of the test carrier board 5, while the programmable device module 2, the output connection interface 3, and the second communication interface 4 are located on the back side of the test carrier board 5.
[0150] The fixing component 6 is used to fix the semiconductor device under test; one end of the elastic fixing component is fixed on the test carrier plate 5, and the elastic fixing component rotates about the fixing end as an axis.
[0151] This invention also provides a semiconductor device testing system, please refer to [reference needed]. Figure 17 It includes a semiconductor device testing equipment 200 and a semiconductor device testing tool 100 of any of the above embodiments.
[0152] The following describes the testing process of the semiconductor device testing system in this application for the semiconductor device under test. The testing process is as follows: Figure 18 As shown.
[0153] Multiple probe contacts on the front of the test substrate are connected to the input ports of the programmable chip. When the semiconductor device under test (DUT) is placed in and secured using a flexible fixing component, the self-test program inside the programmable device module is activated. It begins detecting the short-circuit connections between the probe contacts and records the results to the second storage unit within the programmable device module. After the self-test of the short-circuit connections between the probe contacts is complete, the user can retrieve the test results via the display control unit. The results are then presented graphically, such as... Figure 9 The black probe contacts indicate probes that are short-circuited to each other. The user can then manually divide and merge short-circuited areas via the display control unit, such as... Figure 10 As shown, the programmable chip executes probe contact short-circuiting according to the user-defined area, the Kelvin four-wire method test line segmentation ends, and the test equipment begins detection.
[0154] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0155] The semiconductor device testing tools and systems provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the methods and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A semiconductor device testing tool, characterized in that, include: Test probe array, programmable device module, output connection interface; The test probe array includes multiple probe contacts, each of which is connected to the programmable device module. One end of the output connection interface is connected to the programmable device module, and the other end is used to connect to semiconductor device testing equipment; The programmable device module is used to detect the short-circuit connection relationship between adjacent probe contacts, so that the probe contacts with the same short-circuit connection relationship can be connected to a test terminal of the semiconductor device under test. The programmable device module includes a first storage unit, a programmable chip, a first communication interface, a display control unit connected to the programmable chip, and a second storage unit; the first storage unit is used to store a program for detecting the short-circuit connection relationship between the probe contacts; The probe contacts are connected to the input / output interface of the programmable chip. The programmable chip is used to run a program that detects the short-circuit connection relationship between the probe contacts to determine the short-circuit connection relationship between the probe contacts. One end of the first communication interface is connected to the programmable chip, and the other end of the first communication interface is connected to the second communication interface of the semiconductor device testing tool. The second communication interface is connected to the client. The first communication interface and the second communication interface are used to transmit the short-circuit connection relationship between the probe contacts to the client and transmit the client partitioning instruction to the programmable chip, so that the programmable chip can divide the target probe contact array with the same short-circuit connection relationship into multiple different probe contact subarrays, or merge target probe contact arrays with different short-circuit connection relationships. The display control unit is used to display the short-circuit connection relationship between the probe contacts; receive and transmit customer partitioning instructions to the programmable chip, so that the programmable chip can divide the target probe contact array with the same short-circuit connection relationship into multiple different probe contact sub-arrays, or merge target probe contact arrays with different short-circuit connection relationships; The second storage unit is used to store the short-circuit connection relationship between the probe contacts.
2. The semiconductor device testing tool as described in claim 1, characterized in that, Also includes: Test carrier board; The test probe array, the programmable device module, and the output connection interface are mounted on the test carrier board.
3. The semiconductor device testing tool as described in claim 2, characterized in that, Also includes: Fixed components; The fixing component is fixed to the test carrier plate and is used to fix the semiconductor device under test.
4. The semiconductor device testing tool as described in claim 3, characterized in that, The fixing component is an elastic fixing component.
5. The semiconductor device testing tool as described in claim 4, characterized in that, One end of the elastic fixing component is fixed to the test plate, and the elastic fixing component rotates about the fixed end as an axis.
6. A semiconductor device testing system, characterized in that, It includes semiconductor device testing equipment and semiconductor device testing tools as described in any one of claims 1 to 5.
Citation Information
Patent Citations
Integrated circuit component testing socket and platform
CN107247163A
Probe card, chip testing method, testing machine and storage medium
CN115754388A