A data comparison and verification method, system, device and medium

Abstract

The present invention provides a data comparison and verification method, system, equipment and medium, including: adding a visualization component to a UVM verification environment, writing a test case, and simulating and running the UVM verification environment based on the test case and the visualization component; and, writing the target data to be compared and verified with the corresponding expected data to the UVM verification environment, and calling a curve generation component through an image drawing function in the UVM verification environment; respectively drawing and generating corresponding target data curves and expected data curves through the curve generation component, and adjusting the visualization parameters of the target data curves and the expected data curves to compare and display the target data curves and the expected data curves. The present invention can increase the contrast and readability of the curve by adjusting the visualization parameters of the curve, such as the color of the curve, the width of the curve, etc., greatly improving the visualization and readability of the data to be verified, making the verification simple, efficient and intuitive, and being able to support large-volume and multi-dimensional data processing.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data comparison and verification method, system, device and medium. Background Art

[0002] In the field of chip verification, existing data comparison and verification solutions often use manual calculations or use simulation tools to manually load corresponding waveforms to observe data errors. However, when verifying chips, it is difficult or impossible to observe trends for large amounts of data with multiple dimensions, especially changes in the relationship between output data and expected data, just by looking at the original data or waveforms. Therefore, how to intuitively implement chip data comparison and verification is a problem that needs to be solved urgently. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a data comparison and verification method, system, device and medium for solving the technical problems existing in the prior art.

[0004] To achieve the above purpose and other related purposes, the present invention provides a data comparison and verification method, comprising the following steps:

[0005] Adding a visualization component to a pre-established or real-time data verification environment, wherein the data verification environment includes a UVM (Universal Verification Methodology) verification environment;

[0006] Using the test components in the UVM verification environment to write test cases, and simulating and running the UVM verification environment based on the test cases and the visualization components; and,

[0007] Writing the target data to be compared and verified with the corresponding expected data into the UVM verification environment, and calling the curve generation component through the image drawing function in the UVM verification environment; wherein the target data includes the output data of the design to be tested;

[0008] The target data curve corresponding to the target data and the expected data curve corresponding to the expected data are respectively drawn and generated by the curve generating component, and the visualization parameters of the target data curve and the expected data curve are adjusted to compare and display the target data curve and the expected data curve; wherein the visualization parameters of the target data curve and the expected data curve are different.

[0009] In one embodiment of the present invention, if the curve generating component is a matlab module component, the process of generating a target data curve corresponding to the target data and an expected data curve corresponding to the expected data by drawing the matlab module component, and adjusting visualization parameters of the target data curve and the expected data curve includes:

[0010] The text document containing the target data and the expected data is transmitted to the matlab module component;

[0011] Draw a curve of the first expected data in the text document by using the first function in the matlab module component, which is recorded as the first expected data curve; and adjust the visualization parameters of the first expected data curve by modifying the internal parameters of the first function; wherein the first function includes a plot function;

[0012] Maintaining the state of the first expected data curve at the current moment by using the second function in the matlab module component, and using the first function to draw a curve of the first target data in the text document, recorded as the first target data curve; and adjusting the visualization parameters of the first target data curve by modifying the internal parameters of the first function; wherein the second function includes a hold on function, and the first target data and the first expected data are the same group of comparison display data;

[0013] The curve of the target data and the curve of the expected data are compared and displayed according to different visualization parameters.

[0014] In one embodiment of the present invention, the establishment process of the UVM verification environment includes:

[0015] Obtaining components for establishing the UVM verification environment, including: a test component, an environment component, a scoreboard component, an agent component, a monitor component, a virtual sequencer component, and a driver component; wherein the visualization component is connected to the scoreboard component;

[0016] combining the agent component, the monitor component, the virtual sequencer component and the driver component to obtain a first hierarchical component; and,

[0017] combining the visualization component, the scoreboard component and the first hierarchical component to obtain a second hierarchical component; and,

[0018] combining the test component and the second hierarchical component to obtain a third hierarchical component; and,

[0019] The design to be tested and the third hierarchical component are combined to obtain a top-level component.

[0020] In one embodiment of the present invention, the establishment process of the UVM verification environment also includes:

[0021] Performing data modeling and generating a reference model from a sequence according to sequence entries, and transmitting the reference model to the virtual sequencer component;

[0022] Connecting the virtual sequencer component to the driver component via a sequence entry port, and driving the information of the sequence entry port to the port of the design to be tested;

[0023] The output data of the design under test is received by the monitor component and transmitted to the scoreboard component through the analysis port of the proxy component, and the data sent by the reference model and the monitor component are compared respectively, and whether the design under test works correctly is determined according to the comparison result.

[0024] In one embodiment of the present invention, the process of simulating and running the UVM verification environment based on the test case and the visualization component includes:

[0025] Performing simulation operation hierarchicalization on the UVM verification environment according to a stage mechanism, and adding the visualization component to the scoreboard stage;

[0026] Entering the construction phase, creating a UVM tree, and instantiating each component in the UVM verification environment based on the test case;

[0027] Entering the connection phase, following the bottom-up execution, each component in the UVM verification environment is instantiated through built-in port connections;

[0028] Entering the elaboration phase, displaying the test bench topology, and testing the test bench;

[0029] Entering the simulation start phase, printing the test bench topology structure;

[0030] Enter the simulation operation phase and conduct simulation operation test on the design to be tested;

[0031] Entering the extraction phase, respectively extracting the final states of the design to be tested and the test bench;

[0032] Entering the inspection phase, analyzing the simulation results;

[0033] Entering the reporting phase in the scoreboard phase, the visualization component is added, and a report is formed based on the analyzed simulation results.

[0034] In an embodiment of the present invention, the visualization parameter includes at least one of the following: curve color, curve width.

[0035] In one embodiment of the present invention, before transmitting the text document containing the target data and the expected data to the matlab module component, the method further comprises: writing the target data and the expected data to be graphically processed into the text document through a third function;

[0036] The data parameters written into the text document by the third function include: memory address, data length, data type and file pointer.

[0037] The present invention also provides a data comparison and verification system, the system comprising:

[0038] A verification environment module, used to add a visualization component to a data verification environment established in advance or in real time, wherein the data verification environment includes a UVM verification environment;

[0039] A test case module, used for writing test cases using the test components in the UVM verification environment, and simulating and running the UVM verification environment based on the test cases and the visualization components;

[0040] The simulation operation module writes the target data to be compared and verified with the corresponding expected data into the UVM verification environment, and calls the curve generation component through the image drawing function in the UVM verification environment; wherein the target data includes the output data of the design to be tested;

[0041] A comparison and verification module is used to draw and generate a target data curve corresponding to the target data and an expected data curve corresponding to the expected data through the curve generation component, and adjust the visualization parameters of the target data curve and the expected data curve to compare and display the target data curve and the expected data curve; wherein the visualization parameters of the target data curve and the expected data curve are different.

[0042] The present invention also provides a data comparison and verification device, comprising:

[0043] processor; and,

[0044] A computer-readable medium storing instructions, when the processor executes the instructions, causes the device to perform any of the data comparison and verification methods described above.

[0045] The present invention also provides a computer-readable medium having instructions stored thereon, wherein the instructions are loaded by a processor and executed by any of the data comparison and verification methods described above.

[0046] As described above, the present invention provides a data comparison and verification method, system, device and medium, which have the following beneficial effects: first, a visualization component is added to a data verification environment established in advance or in real time, and the data verification environment includes a UVM verification environment; secondly, a test case is written using the test component in the UVM verification environment, and the UVM verification environment is simulated and run based on the test case and the visualization component; and, the target data to be compared and verified and the corresponding expected data are written into the UVM verification environment, and a curve generation component is called through an image drawing function in the UVM verification environment; wherein the target data includes output data of the design to be tested; finally, a target data curve corresponding to the target data and an expected data curve corresponding to the expected data are respectively drawn and generated through the curve generation component, and the visualization parameters of the target data curve and the expected data curve are adjusted to compare and display the target data curve and the expected data curve; wherein the visualization parameters of the target data curve and the expected data curve are different. It can be seen from this that the present invention proposes a scheme for fully automated data processing and curve drawing in a UVM verification environment, by adjusting the visualization parameters of the curve, such as curve color, curve width, etc., the curve contrast and readability can be increased, so that the trend and relationship changes between the output data of the design to be tested and the expected data can be visualized, and the function call curve generation component provided by the simulation language is used to realize the fully automated process, which greatly improves the visualization and readability of the data to be verified, makes the verification simple, efficient and intuitive, and can support large-scale and multi-dimensional data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of an exemplary system architecture for applying the technical solutions in one or more embodiments of the present invention;

[0048] Figure 2 A schematic diagram of a flow chart of a data comparison and verification method provided in an embodiment of the present invention;

[0049] Figure 3 A schematic diagram of the framework structure of a UVM verification environment provided by an embodiment of the present invention;

[0050] Figure 4 A schematic diagram of a phase mechanism during the UVM simulation runtime provided by an embodiment of the present invention;

[0051] Figure 5 A schematic diagram of a specific processing flow of a visualization component provided in an embodiment of the present invention;

[0052] Figure 6 A schematic diagram of a specific processing flow of a matlab component provided by an embodiment of the present invention;

[0053] Figure 7A schematic diagram of the hardware structure of a data comparison and verification system provided by an embodiment of the present invention;

[0054] Figure 8 The present invention is a schematic diagram of the hardware structure of a data comparison and verification device suitable for implementing one or more embodiments of the present invention. DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0056] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0057] Matlab is a mathematical software used in data analysis, wireless communications, deep learning, image processing and computer vision, signal processing, quantitative finance and risk management, robotics, control systems and other fields.

[0058] Figure 1 FIG. 1 is a schematic diagram showing an exemplary system architecture to which the technical solution in one or more embodiments of the present invention can be applied. Figure 1 As shown, the system architecture 100 may include a terminal device 110, a network 120, and a server 130. The terminal device 110 may include various electronic devices such as a smart phone, a tablet computer, a laptop computer, and a desktop computer. The server 130 may be an independent physical server, or a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. The network 120 may be a communication medium of various connection types that can provide a communication link between the terminal device 110 and the server 130, such as a wired communication link or a wireless communication link.

[0059] According to the implementation requirements, the system architecture in the embodiment of the present invention may have any number of terminal devices, networks and servers. For example, the server 130 may be a server group composed of multiple server devices. In addition, the technical solution provided in the embodiment of the present invention may be applied to the terminal device 110, or to the server 130, or may be implemented by the terminal device 110 and the server 130 together, and the present invention does not make any special limitation on this.

[0060] In one embodiment of the present invention, the terminal device 110 or the server 130 of the present invention can add a visualization component to a data verification environment established in advance or in real time, and the data verification environment includes a UVM verification environment; secondly, a test case is written using the test component in the UVM verification environment, and the UVM verification environment is simulated and run based on the test case and the visualization component; and, the target data to be compared and verified and the corresponding expected data are written into the UVM verification environment, and a curve generation component is called through an image drawing function in the UVM verification environment; wherein the target data includes output data of the design to be tested; finally, a target data curve corresponding to the target data and an expected data curve corresponding to the expected data are respectively drawn through the curve generation component, and the visualization parameters of the target data curve and the expected data curve are adjusted to compare and display the target data curve and the expected data curve; wherein the visualization parameters of the target data curve and the expected data curve are different. By using the terminal device 110 or the server 130 to execute the data comparison verification method, a scheme for fully automatically processing data and drawing curves can be implemented in the UVM verification environment. By adjusting the visualization parameters of the curve, such as the curve color, the curve width, etc., the curve contrast and readability can be increased, so that the trend and relationship changes between the output data of the design to be tested and the expected data can be visualized, and the function call curve generation component provided by the simulation language is used to implement a fully automated process, which greatly improves the visualization and readability of the data to be verified, making the verification simple, efficient, and intuitive, thereby being able to support large-scale and multi-dimensional data processing.

[0061] The above section introduces the contents of an exemplary system architecture that applies the technical solution of the present invention. Next, the data comparison and verification method of the present invention will be introduced.

[0062] Figure 2 FIG. 1 is a flow chart of a data comparison and verification method provided by an embodiment of the present invention. Specifically, in an exemplary embodiment, Figure 2 As shown, this embodiment provides a data comparison and verification method, which includes the following steps:

[0063] S210, adding a visualization component to a data verification environment established in advance or in real time, the data verification environment including a UVM verification environment;

[0064] S220, writing test cases using test components in the UVM verification environment, and running the UVM verification environment based on the test cases and the visualization component simulation;

[0065] S230, writing the target data to be compared and verified with the corresponding expected data into the UVM verification environment, and calling the curve generation component through the image drawing function in the UVM verification environment; wherein the target data includes the output data of the design to be tested;

[0066] S240, respectively draw a target data curve corresponding to the target data and an expected data curve corresponding to the expected data through a curve generation component, and adjust visualization parameters of the target data curve and the expected data curve to compare and display the target data curve and the expected data curve; wherein the visualization parameters of the target data curve and the expected data curve are different. As an example, the visualization parameters in this embodiment include but are not limited to: curve color and curve width.

[0067] It can be seen that the present embodiment proposes a scheme for fully automated data processing and curve drawing in a UVM verification environment, by adjusting the visualization parameters of the curve, such as curve color, curve width, etc., the curve contrast and readability can be increased, so that the trend and relationship changes between the output data of the design to be tested and the expected data can be visualized, and the function call curve generation component of the simulation language is used to realize the fully automated process, which greatly improves the visualization and readability of the data to be verified, making the verification simple, efficient and intuitive, so as to support large-scale and multi-dimensional data processing.

[0068] According to the above records, in an exemplary embodiment, if the curve generating component is a matlab module component, the process of drawing and generating a target data curve corresponding to the target data and an expected data curve corresponding to the expected data by the matlab module component, and adjusting the visualization parameters of the target data curve and the expected data curve includes:

[0069] Transfer the text document containing the target data and expected data to the matlab module component;

[0070] A curve of the first expected data in the text document is drawn by the first function in the matlab module component, which is recorded as the first expected data curve; and the visualization parameters of the first expected data curve are adjusted by modifying the internal parameters of the first function; wherein the first function includes a plot function. In this embodiment, the plot function is a two-dimensional line drawing function in matlab, and this embodiment uses the basic calling format plot(y, linewidth, MarkerEdgeColor). The curve width can be set by configuring linewidth, and the curve color can be set by configuring MarkerEdgeColor.

[0071] The state of the first expected data curve at the current moment is maintained by the second function in the matlab module component, and the curve of the first target data in the text document is drawn using the first function, which is recorded as the first target data curve; and the visualization parameters of the first target data curve are adjusted by modifying the internal parameters of the first function; wherein the second function includes a holdon function, and the first target data and the first expected data are the same set of comparative display data. In this embodiment, the basic syntax of the hold on function in matlab is "hold on". When drawing a graph, the hold on function can be used first to keep the current graph from being cleared, and then in the subsequent drawing process, other drawing functions can be used to draw curves or graphs, so that multiple curves or graphs can be drawn on the same graph.

[0072] The curve of the target data and the curve of the expected data are compared and displayed according to different visualization parameters. In this embodiment, after the curve is drawn, it can be saved in batches in png format to facilitate viewing, monitoring and analyzing data, and automatically close matlab.

[0073] According to the above records, in an exemplary embodiment, the process of establishing the UVM verification environment includes: obtaining components for establishing the UVM verification environment, including: a test component, an environment component, a scoreboard component, an agent component, a monitor component, a virtual sequencer component, and a driver component; wherein the visualization component is connected to the scoreboard component; combining the agent component, the monitor component, the virtual sequencer component, and the driver component to obtain a first hierarchical component; and, combining the visualization component, the scoreboard component, and the first hierarchical component to obtain a second hierarchical component; and, combining the test component and the second hierarchical component to obtain a third hierarchical component; and, combining the design to be tested and the third hierarchical component to obtain a top-level component. In this embodiment, the bottom-up components in the UVM verification environment are the first hierarchical component, the second hierarchical component, the third hierarchical component, and the top-level component. In addition, the process of establishing the UVM verification environment also includes: performing data modeling, generating a reference model from a sequence according to sequence entries, and transmitting the reference model to a virtual sequencer component; connecting the virtual sequencer component to a driver component through a sequence entry port, and driving the information of the sequence entry port to a port of a design to be tested; receiving output data of the design to be tested through a monitor component, and transmitting the output data to a scoreboard component through an analysis port of an agent component, comparing the data sent by the reference model and the monitor component respectively, and determining whether the design to be tested works correctly based on the comparison result.

[0074] According to the above records, in an exemplary embodiment, the process of simulating and running the UVM verification environment based on the test case and the visualization component includes: simulating and running the UVM verification environment hierarchically according to the stage mechanism, and adding the visualization component to the scoreboard stage; entering the construction stage, creating a UVM tree, and instantiating each component in the UVM verification environment based on the test case; entering the connection stage, executing from the bottom up, connecting each component in the UVM verification environment after instantiation through the built-in port; entering the elaboration stage, displaying the test bench topology, and detecting the test bench; entering the simulation start stage, printing the test bench topology; entering the simulation run stage, performing simulation run test on the DUT; entering the extraction stage, respectively extracting the final states of the DUT and the test bench; entering the inspection stage, analyzing the simulation results; entering the report stage in the scoreboard stage, adding the visualization component, and forming a report based on the analyzed simulation results.

[0075] According to the above records, in an exemplary embodiment, before the text document containing the target data and the expected data is transferred to the matlab module component, the method also includes: writing the target data and the expected data that need to be graphically processed into the text document through the third function; wherein the data parameters written into the text document by the third function include: memory address, data length, data type and file pointer. In this embodiment, the third function can be a $fwrite function, wherein the $fwrite function is a SystemVerilog function for writing data into a file. It can write the data in the memory into the disk file, and it can also write the data in the disk file into the memory. Its syntax is: $fwrite(), wherein the parameters are: memory address, data length to be written, data type to be written, file pointer. Data transmission from memory to file can be realized, and text files, binary files, etc. can also be read, so that the required data can be obtained from the file.

[0076] In another exemplary embodiment of the present invention, Figures 3 to 6 As shown, this embodiment also provides a data comparison verification method based on a UVM verification environment, comprising the following steps:

[0077] Step 1: UVM verification environment basic framework is built. Specifically, the UVM verification environment basic framework in the present invention is built as follows Figure 3 As shown, including:

[0078] ①First, perform data modeling sequence_item(transaction);

[0079] ②After it is built, it is generated by the sequence and transmitted to the corresponding virtual sequencer;

[0080] ③ Then the virtual sequencer Sequencer is connected to the driver Driver through the sequence item port seq_item_port, and the information in the sequence item sequence_item is driven to the port interface of the DUT (Design Under Test, DUT for short);

[0081] ④ The monitor receives the output of the DUT and sends it to the scoreboard through the analysis port analysis_port. It compares the data sent by the reference model and the monitor respectively, and determines whether the DUT is working correctly based on the comparison result.

[0082] Among them, Test is the top-level Component of UVM, which mainly instantiates and configures the top-level Env, and generates stimulus to DUT by calling Sequence through Env.

[0083] Env (Environment): Mainly used to layer UVM components. Generally, Agent and Scoreboard are instantiated in Env, and other Envs are set. The top-level Env is used to encapsulate the environment used to test the DUT.

[0084] Scoreboard: used to compare the output of the design under test with the expected output and generate test results. Receive the input and output transactions of the DUT through the analysis port of the agent. Pour the input transaction into the reference model to produce the expected results, and then compare with the actual output results of the DUT. Unlike general operations, the function of writing output data and expected data into a text document (.txt) is added here. It is used to prepare for subsequent data processing.

[0085] Agent: Responsible for communicating with the DUT and generating and receiving DUT signals. Agent usually includes one or more drivers and one or more monitors.

[0086] Monitor: Used to monitor the data transmission status of the modules or interfaces in the design under test.

[0087] Sequencer (virtual sequencer): used to generate test sequences. A virtual sequencer usually includes one or more virtual sequence generators and one or more virtual sequence distributors.

[0088] Driver: Used to send data to the module or interface in the design under test.

[0089] Step 2: Write test cases. Write corresponding test cases according to the verification plan.

[0090] Step 3, UVM simulation operation. In this embodiment, there are different phases when UVM simulation is running. The significance of the Phase mechanism is to make the operation of UVM hierarchical so that the order of various instantiations is correct. The visualization component in the present invention is added to report_phase to achieve the purpose of automation. Specifically, the Phase mechanism is based on Figure 4 The execution is carried out in the corresponding order. First, the objects of each component are created, and the build_phase is executed first; then, the connect_phase is executed to connect the components, and the execution order is from bottom to top; then, the test stimulus is sent to the DUT in the run_phase, and the run_phase and other run time phases are parallel; in the run_phase, some waiting, stimulus, and sampling tasks are completed; such as power-on and reset, register configuration, sending test content, and waiting for the DUT to complete the test.

[0091] Among them: build_phase (build phase): execute from top to bottom, create the UVM tree, and instantiate all components.

[0092] connet: Executes from the bottom up, connecting components through built-in ports.

[0093] end_of_elaboration: execute from bottom to top, display the test bench topology; check the correctness of the test bench.

[0094] start_of_simulation (start of simulation): execute from bottom to top, and print the test bench topology.

[0095] Run: Execute from bottom to top, the only task phase. Most tasks are executed in this phase. The four phases of reset, configure, main, and shutdown are the core. These four phases usually simulate the normal working mode of DUT: ① In reset_phase, the DUT is reset, initialized, and other operations are performed. ② In configure_phase, the DUT is configured. ③ In main_phase, the DUT is mainly operated. ④ In shutdown_phase, some operations related to powering off the DUT are mainly performed.

[0096] Through this subdivision, the present embodiment can achieve more precise control of the DUT, and can also achieve jumps between phases, making it easier to build some scenarios.

[0097] Extract (Extraction phase): Execute from the bottom up to extract the final state of the testbench; extract the final state of the DUT (backdoor).

[0098] Check (checking phase): execute from bottom to top and analyze the simulation results.

[0099] Report (report phase): execute from bottom to top and report the simulation results. The visualization component in the present invention is added here to achieve the purpose of automation.

[0100] Final: Executed from top to bottom, the last stage.

[0101] According to the above records, the specific processing flow of the visualization component in this embodiment is as follows: Figure 5 As shown. Includes:

[0102] ① Data preprocessing unit: Run the verification environment based on the UVM framework, and record the output data and expected data to be compared into the array inside UVM in the Scoreboard. The recording action can be triggered by different conditions, such as time triggering to select data recording within a given time (for example, data within 1 to 3 seconds can be selected to record), and event triggering can select data recording under a certain condition (such as receiving given data);

[0103] ② Use the $fwrite function to write the output data and expected data that need to be processed graphically into a text document (.txt);

[0104] $fwrite function: $fwrite function is a SystemVerilog function used to write data to a file. It can write data in memory to a disk file, or write data in a disk file to memory. Its syntax is: $fwrite(), where the parameters are: memory address, length of data to be written, data type to be written, and file pointer. It can realize data transfer from memory to file, and can also read text files, binary files, etc., so that the required data can be obtained from the file.

[0105] ③ In the report_phase of UVM, use the $system function to call the matlab module, and control matlab to automatically open the graphical interface;

[0106] $system function: In SystemVerilog, $system() is a system task used to execute external system commands. It accepts a string parameter, which represents the system command to be executed, and can return an integer value, which represents the result of the command execution. The $system() task sends the command to the system and then waits for the command to be executed. It can be used to execute external tools, call script files, or perform any operation that requires calling system commands.

[0107] ④UVM control unit: By setting the number of data comparison groups through the internal parameters of the control unit, it is possible to compare a set of output data with the expected data, or to draw multiple sets of output data and multiple sets of corresponding expected data in one graph for comparison.

[0108] ⑤ Comparison data drawing generation unit: pass the text document (.txt) to the matlab module, and use the plot function to complete the drawing of the first set of expected data and adjust the color of the curve to red and the width to 3 by modifying the internal parameters of the plot function; then use the hold on function to keep the first set of curves unchanged, and on this basis continue to use the plot function to draw the second set of actual output data and adjust the color of the curve to blue and the width to 5 by modifying the internal parameters of the plot function. If the UVM control unit sets multiple sets of data comparison, continue drawing. In this embodiment, the plot function is a two-dimensional line drawing function in matlab, and the basic call format plot (y, linewidth, MarkerEdgeColor) is used here. The curve width can be set by configuring linewidth, and the curve color can be set by configuring MarkerEdgeColor. Hold on function: In matlab, the basic syntax of the hold on function is "hold on". When drawing a graph, you can first use the hold on function to keep the current graph from being cleared, and then use other drawing functions to draw curves or graphs in the subsequent drawing process, so that multiple curves or graphs can be drawn on the same graph. In this embodiment, the color, width, etc. of the curve can be adjusted by modifying the internal parameters of the plot function as required to increase the contrast and readability.

[0109] ⑥ Drawing result storage unit: After drawing is completed, batches are saved in .png format for easy viewing, monitoring and analysis of data. And matlab is automatically closed.

[0110] According to the above records, the specific processing flow of the matlab module in this embodiment is as follows: Figure 6 shown. Specifically,

[0111] ① Pass the text document (.txt) to the matlab module;

[0112] ② Use the plot function to plot the first set of expected data and adjust the color of the curve to red and the width to 3 by modifying the internal parameters of the plot function;

[0113] ③Then use the hold on function to keep the first set of curves unchanged. On this basis, continue to use the plot function to draw the second set of actual output data and adjust the color of the curve to blue and the width to 5 by modifying the internal parameters of the plot function; if the UVM control unit sets multiple sets of data comparison, continue drawing.

[0114] ④After drawing, save it in .png format for easy viewing;

[0115] ⑤Automatically shut down matlab.

[0116] Step 4: UVM result analysis. Display the error size and change trend between the output data and the expected data.

[0117] It can be seen from this that the present embodiment proposes a method for using matlab to fully automate data processing and curve drawing in a UVM verification environment, which can support large-scale, multi-dimensional data processing, and visualize the trend and relationship changes between output data and expected data. Matlab can be used to fully automate data processing and curve drawing in a UVM verification environment. The color, width, etc. of the curve can be adjusted to increase contrast and readability. And the $system function carried by the simulation language is used to call matlab to realize the fully automated process, which greatly improves the visualization and readability of the data to be verified, making verification simple, efficient and intuitive.

[0118] In summary, the present invention provides a data comparison and verification method, firstly, a visualization component is added to a data verification environment established in advance or in real time, and the data verification environment includes a UVM verification environment; secondly, a test case is written by using the test component in the UVM verification environment, and the UVM verification environment is simulated and run based on the test case and the visualization component; and, target data to be compared and verified and corresponding expected data are written into the UVM verification environment, and a curve generation component is called through an image drawing function in the UVM verification environment; wherein the target data includes output data of a design to be tested; finally, a target data curve corresponding to the target data and an expected data curve corresponding to the expected data are respectively drawn and generated through the curve generation component, and visualization parameters of the target data curve and the expected data curve are adjusted to compare and display the target data curve and the expected data curve; wherein the visualization parameters of the target data curve and the expected data curve are different. It can be seen that this method proposes a solution for fully automated data processing and curve drawing in the UVM verification environment. By adjusting the visualization parameters of the curve, such as curve color, curve width, etc., the curve contrast and readability can be increased, so that the trend and relationship changes between the output data of the design to be tested and the expected data can be visualized, and the function call curve generation component provided by the simulation language is used to realize the fully automated process, which greatly improves the visualization and readability of the data to be verified, making the verification simple, efficient and intuitive, so as to support large-scale and multi-dimensional data processing.

[0119] In another exemplary embodiment of the present invention, Figure 7 As shown, this embodiment also provides a data comparison and verification system, including:

[0120] A verification environment module 710, for adding a visualization component to a pre-established or real-time data verification environment, wherein the data verification environment includes a UVM verification environment;

[0121] The test case module 720 is used to write test cases using test components in the UVM verification environment, and simulate and run the UVM verification environment based on the test cases and the visualization components;

[0122] The simulation operation module 730 writes the target data to be compared and verified with the corresponding expected data into the UVM verification environment, and calls the curve generation component through the image drawing function in the UVM verification environment; wherein the target data includes the output data of the design to be tested;

[0123] The comparison and verification module 740 is used to draw a target data curve corresponding to the target data and an expected data curve corresponding to the expected data through a curve generation component, and adjust the visualization parameters of the target data curve and the expected data curve to compare and display the target data curve and the expected data curve; wherein the visualization parameters of the target data curve and the expected data curve are different. As an example, the visualization parameters in this embodiment include but are not limited to: curve color and curve width.

[0124] It can be seen that the present embodiment proposes a scheme for fully automated data processing and curve drawing in a UVM verification environment, by adjusting the visualization parameters of the curve, such as curve color, curve width, etc., the curve contrast and readability can be increased, so that the trend and relationship changes between the output data of the design to be tested and the expected data can be visualized, and the function call curve generation component of the simulation language is used to realize the fully automated process, which greatly improves the visualization and readability of the data to be verified, making the verification simple, efficient and intuitive, so as to support large-scale and multi-dimensional data processing.

[0125] According to the above records, in an exemplary embodiment, if the curve generating component is a matlab module component, the process of drawing and generating a target data curve corresponding to the target data and an expected data curve corresponding to the expected data by the matlab module component, and adjusting the visualization parameters of the target data curve and the expected data curve includes:

[0126] Transfer the text document containing the target data and expected data to the matlab module component;

[0127] A curve of the first expected data in the text document is drawn by the first function in the matlab module component, which is recorded as the first expected data curve; and the visualization parameters of the first expected data curve are adjusted by modifying the internal parameters of the first function; wherein the first function includes a plot function. In this embodiment, the plot function is a two-dimensional line drawing function in matlab, and this embodiment uses the basic calling format plot(y, linewidth, MarkerEdgeColor). The curve width can be set by configuring linewidth, and the curve color can be set by configuring MarkerEdgeColor.

[0128] The state of the first expected data curve at the current moment is maintained by the second function in the matlab module component, and the curve of the first target data in the text document is drawn using the first function, which is recorded as the first target data curve; and the visualization parameters of the first target data curve are adjusted by modifying the internal parameters of the first function; wherein the second function includes a holdon function, and the first target data and the first expected data are the same set of comparative display data. In this embodiment, the basic syntax of the hold on function in matlab is "hold on". When drawing a graph, the hold on function can be used first to keep the current graph from being cleared, and then in the subsequent drawing process, other drawing functions can be used to draw curves or graphs, so that multiple curves or graphs can be drawn on the same graph.

[0129] The curve of the target data and the curve of the expected data are compared and displayed according to different visualization parameters. In this embodiment, after the curve is drawn, it can be saved in batches in png format to facilitate viewing, monitoring and analyzing data, and automatically close matlab.

[0130] According to the above records, in an exemplary embodiment, the process of establishing the UVM verification environment includes: obtaining components for establishing the UVM verification environment, including: a test component, an environment component, a scoreboard component, an agent component, a monitor component, a virtual sequencer component, and a driver component; wherein the visualization component is connected to the scoreboard component; combining the agent component, the monitor component, the virtual sequencer component, and the driver component to obtain a first hierarchical component; and, combining the visualization component, the scoreboard component, and the first hierarchical component to obtain a second hierarchical component; and, combining the test component and the second hierarchical component to obtain a third hierarchical component; and, combining the design to be tested and the third hierarchical component to obtain a top-level component. In this embodiment, the bottom-up components in the UVM verification environment are the first hierarchical component, the second hierarchical component, the third hierarchical component, and the top-level component. In addition, the process of establishing the UVM verification environment also includes: performing data modeling, generating a reference model from a sequence according to sequence entries, and transmitting the reference model to a virtual sequencer component; connecting the virtual sequencer component to a driver component through a sequence entry port, and driving the information of the sequence entry port to a port of a design to be tested; receiving output data of the design to be tested through a monitor component, and transmitting the output data to a scoreboard component through an analysis port of an agent component, comparing the data sent by the reference model and the monitor component respectively, and determining whether the design to be tested works correctly based on the comparison result.

[0131] According to the above records, in an exemplary embodiment, the process of simulating and running the UVM verification environment based on the test case and the visualization component includes: simulating and running the UVM verification environment hierarchically according to the stage mechanism, and adding the visualization component to the scoreboard stage; entering the construction stage, creating a UVM tree, and instantiating each component in the UVM verification environment based on the test case; entering the connection stage, executing from the bottom up, connecting each component in the UVM verification environment after instantiation through the built-in port; entering the elaboration stage, displaying the test bench topology, and detecting the test bench; entering the simulation start stage, printing the test bench topology; entering the simulation run stage, performing simulation run test on the DUT; entering the extraction stage, respectively extracting the final states of the DUT and the test bench; entering the inspection stage, analyzing the simulation results; entering the report stage in the scoreboard stage, adding the visualization component, and forming a report based on the analyzed simulation results.

[0132] According to the above records, in an exemplary embodiment, before the text document containing the target data and the expected data is transferred to the matlab module component, the method also includes: writing the target data and the expected data that need to be graphically processed into the text document through the third function; wherein the data parameters written into the text document by the third function include: memory address, data length, data type and file pointer. In this embodiment, the third function can be a $fwrite function, wherein the $fwrite function is a SystemVerilog function for writing data into a file. It can write the data in the memory into the disk file, and it can also write the data in the disk file into the memory. Its syntax is: $fwrite(), wherein the parameters are: memory address, data length to be written, data type to be written, file pointer. Data transmission from memory to file can be realized, and text files, binary files, etc. can also be read, so that the required data can be obtained from the file.

[0133] In summary, the present invention provides a data comparison and verification system. First, a visualization component is added to a data verification environment established in advance or in real time, and the data verification environment includes a UVM verification environment; secondly, a test case is written by using the test component in the UVM verification environment, and the UVM verification environment is simulated and run based on the test case and the visualization component; and, target data to be compared and verified and corresponding expected data are written into the UVM verification environment, and a curve generation component is called through an image drawing function in the UVM verification environment; wherein the target data includes output data of a design to be tested; finally, a target data curve corresponding to the target data and an expected data curve corresponding to the expected data are respectively drawn and generated through the curve generation component, and visualization parameters of the target data curve and the expected data curve are adjusted to compare and display the target data curve and the expected data curve; wherein the visualization parameters of the target data curve and the expected data curve are different. It can be seen that this system proposes a solution for fully automated data processing and curve drawing in the UVM verification environment. By adjusting the visualization parameters of the curve, such as curve color, curve width, etc., the curve contrast and readability can be increased, so that the trend and relationship changes between the output data of the design to be tested and the expected data can be visualized, and the function call curve generation component provided by the simulation language is used to realize the fully automated process, which greatly improves the visualization and readability of the data to be verified, making the verification simple, efficient and intuitive, so as to support large-scale and multi-dimensional data processing.

[0134] It should be noted that the data comparison and verification system provided in the above embodiment and the data comparison and verification method provided in the above embodiment belong to the same concept, wherein the specific manner in which the data comparison and verification method performs operations has been described in detail in the above method embodiment, and will not be repeated here. In actual applications, the data comparison and verification system provided in the above embodiment can distribute the above functions to different functional modules as needed, that is, divide the internal structure of the system into different functional modules, so as to realize all or part of the functions of the data comparison and verification system through the above method embodiment, and this is not limited here.

[0135] The embodiment of the present invention also provides a data comparison and verification device, which may include: one or more processors; and one or more machine-readable media having instructions stored thereon, which, when executed by the one or more processors, enable the device to perform Figure 2 The data comparison and verification method described. Figure 8 FIG. 1 shows a schematic diagram of the structure of a data comparison and verification device 1000. Figure 8 As shown, the data comparison and verification device 1000 includes: a processor 1010 , a memory 1020 , a power supply 1030 , a display unit 1040 , and an input unit 1060 .

[0136] The processor 1010 is the control center of the data comparison and verification device 1000. It uses various interfaces and lines to connect various components, and executes various functions of the data comparison and verification device 1000 by running or executing software programs and / or data stored in the memory 1020, thereby monitoring the data comparison and verification device 1000 as a whole. In the embodiment of the present invention, when the processor 1010 calls the computer program stored in the memory 1020, the following is executed: Figure 2 The data comparison and verification method described. Optionally, the processor 1010 may include one or more processing units; preferably, the processor 1010 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface and application, etc., and the modem processor mainly processes wireless communication. In some embodiments, the processor and the memory may be implemented on a single chip, and in some embodiments, they may also be implemented separately on separate chips.

[0137] The memory 1020 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, various applications, etc.; the data storage area may store data created according to the use of the data comparison and verification device 1000, etc. In addition, the memory 1020 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices, etc.

[0138] The data comparison and verification device 1000 also includes a power supply 1030 (such as a battery) for supplying power to each component. The power supply can be logically connected to the processor 1010 through a power management system, thereby managing functions such as charging, discharging, and power consumption through the power management system.

[0139] The display unit 1040 can be used to display information input by the user or information provided to the user and various menus of the data comparison and verification device 1000. In the embodiment of the present invention, it is mainly used to display the display interface of each application in the data comparison and verification device 1000 and the text, pictures and other objects displayed in the display interface. The display unit 1040 may include a display panel 1050. The display panel 1050 may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), etc.

[0140] The input unit 1060 may be used to receive information such as numbers or characters input by the user. The input unit 1060 may include a touch panel 1070 and other input devices 1080. The touch panel 1070, also known as a touch screen, may collect touch operations of the user on or near it (such as operations of the user using a finger, a stylus, or any other suitable object or accessory on or near the touch panel 1070).

[0141] Specifically, the touch panel 1070 can detect the user's touch operation, detect the signal brought by the touch operation, convert these signals into touch point coordinates, send them to the processor 1010, and receive and execute the command sent by the processor 1010. In addition, the touch panel 1070 can be implemented in various types such as resistive, capacitive, infrared and surface acoustic wave. Other input devices 1080 can include but are not limited to one or more of a physical keyboard, function keys (such as volume control keys, power on / off keys, etc.), a trackball, a mouse, a joystick, etc.

[0142] Of course, the touch panel 1070 can cover the display panel 1050. When the touch panel 1070 detects a touch operation on or near it, it is transmitted to the processor 1010 to determine the type of touch event, and then the processor 1010 provides a corresponding visual output on the display panel 1050 according to the type of touch event. Figure 8 In the figure, the touch panel 1070 and the display panel 1050 are two independent components to realize the input and output functions of the data comparison and verification device 1000, but in some embodiments, the touch panel 1070 and the display panel 1050 can be integrated to realize the input and output functions of the data comparison and verification device 1000.

[0143] The data comparison and verification device 1000 may further include one or more sensors, such as a pressure sensor, a gravity acceleration sensor, a proximity light sensor, etc. Of course, according to the needs of specific applications, the data comparison and verification device 1000 may also include other components such as a camera.

[0144] The embodiment of the present invention further provides a computer-readable storage medium, in which instructions are stored. When one or more processors execute the instructions, the above device can perform the present invention as follows: Figure 2 The data comparison and verification method described.

[0145] It can be understood by those skilled in the art that Figure 8 This is only an example of a data comparison and verification device and does not constitute a limitation on the device. The device may include more or fewer components than shown in the figure, or combine certain components, or different components. For the convenience of description, the above parts are divided into modules (or units) according to their functions and described separately. Of course, when implementing the present invention, the functions of each module (or unit) can be implemented in the same or multiple software or hardware.

[0146] Those skilled in the art should understand that the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be applied to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0147] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A data comparison and verification method, characterized in that: The method comprises the following steps: Adding a visualization component to a pre-established or real-time data verification environment, the data verification environment including a UVM verification environment; Using the test components in the UVM verification environment to write test cases, and simulating and running the UVM verification environment based on the test cases and the visualization components; and, Writing the target data to be compared and verified with the corresponding expected data into the UVM verification environment, and calling the curve generation component through the image drawing function in the UVM verification environment; wherein the target data includes the output data of the design to be tested; The target data curve corresponding to the target data and the expected data curve corresponding to the expected data are respectively drawn and generated by the curve generating component, and the visualization parameters of the target data curve and the expected data curve are adjusted to compare and display the target data curve and the expected data curve; wherein the visualization parameters of the target data curve and the expected data curve are different; Wherein, the process of simulating and running the UVM verification environment based on the test case and the visual component includes: hierarchically simulating and running the UVM verification environment according to the stage mechanism, and adding the visual component to the scoreboard stage; entering the construction stage, creating a UVM tree, and instantiating each component in the UVM verification environment based on the test case; entering the connection stage, executing from the bottom up, connecting each component in the UVM verification environment after instantiation through the built-in port; entering the elaboration stage, displaying the test bench topology, and detecting the test bench; entering the simulation start stage, printing the test bench topology; entering the simulation run stage, performing simulation run test on the design to be tested; entering the extraction stage, respectively extracting the final states of the design to be tested and the test bench; entering the inspection stage, analyzing the simulation results; entering the report stage in the scoreboard stage, adding the visual component, and forming a report based on the analyzed simulation results; The curve generation component includes a matlab module component, and the process of drawing and generating a target data curve corresponding to the target data and an expected data curve corresponding to the expected data through the matlab module component, and adjusting visualization parameters of the target data curve and the expected data curve includes: The text document containing the target data and the expected data is transmitted to the matlab module component; Draw a curve of the first expected data in the text document by using the first function in the matlab module component, which is recorded as the first expected data curve; and adjust the visualization parameters of the first expected data curve by modifying the internal parameters of the first function; wherein the first function includes a plot function; Maintaining the state of the first expected data curve at the current moment by using the second function in the matlab module component, and using the first function to draw a curve of the first target data in the text document, recorded as the first target data curve; and adjusting the visualization parameters of the first target data curve by modifying the internal parameters of the first function; wherein the second function includes a hold on function, and the first target data and the first expected data are the same group of comparison display data; The curve of the target data and the curve of the expected data are compared and displayed according to different visualization parameters.

2. The data comparison and verification method according to claim 1, characterized in that: The establishment process of the UVM verification environment includes: Obtaining components for establishing the UVM verification environment, including: a test component, an environment component, a scoreboard component, an agent component, a monitor component, a virtual sequencer component, and a driver component; wherein the visualization component is connected to the scoreboard component; combining the agent component, the monitor component, the virtual sequencer component and the driver component to obtain a first hierarchical component; and, combining the visualization component, the scoreboard component and the first hierarchical component to obtain a second hierarchical component; and, combining the test component and the second hierarchical component to obtain a third hierarchical component; and, The design to be tested and the third hierarchical component are combined to obtain a top-level component.

3. The data comparison and verification method according to claim 2, characterized in that: The establishment process of the UVM verification environment also includes: Performing data modeling and generating a reference model from a sequence according to sequence entries, and transmitting the reference model to the virtual sequencer component; Connecting the virtual sequencer component to the driver component via a sequence entry port, and driving the information of the sequence entry port to the port of the design to be tested; The output data of the design under test is received by the monitor component and transmitted to the scoreboard component through the analysis port of the proxy component, and the data sent by the reference model and the monitor component are compared respectively, and whether the design under test works correctly is determined according to the comparison result.

4. The data comparison and verification method according to claim 1, characterized in that: The visualization parameter includes at least one of the following: curve color and curve width.

5. The data comparison and verification method according to claim 1, characterized in that: Before transmitting the text document containing the target data and the expected data to the matlab module component, the method further comprises: writing the target data and the expected data to be graphically processed into the text document through a third function; The data parameters written into the text document by the third function include: memory address, data length, data type and file pointer.

6. A data comparison and verification system, characterized in that: The system comprises: A verification environment module, used to add a visualization component to a data verification environment established in advance or in real time, wherein the data verification environment includes a UVM verification environment; A test case module is used to write test cases using test components in the UVM verification environment, and simulate and run the UVM verification environment based on the test cases and the visual components; wherein the process of simulating and running the UVM verification environment based on the test cases and the visual components comprises: hierarchically simulating and running the UVM verification environment according to a stage mechanism, and adding the visual components to a scoreboard stage; entering a construction stage, creating a UVM tree, and instantiating each component in the UVM verification environment based on the test cases; entering a connection stage, executing from the bottom up, and connecting each component in the UVM verification environment after instantiation through built-in ports; entering an elaboration stage, displaying a test bench topology, and detecting the test bench; entering a simulation start stage, printing the test bench topology; entering a simulation run stage, and performing a simulation run test on a design to be tested; entering an extraction stage, respectively extracting the final states of the design to be tested and the test bench; entering an inspection stage, analyzing the simulation results; entering a report stage in the scoreboard stage, adding the visual components, and forming a report based on the analyzed simulation results; The simulation operation module writes the target data to be compared and verified with the corresponding expected data into the UVM verification environment, and calls the curve generation component through the image drawing function in the UVM verification environment; wherein the target data includes the output data of the design to be tested; The comparison and verification module is used to draw and generate a target data curve corresponding to the target data and an expected data curve corresponding to the expected data respectively through the curve generation component, and adjust the visualization parameters of the target data curve and the expected data curve to compare and display the target data curve and the expected data curve; wherein the visualization parameters of the target data curve and the expected data curve are different; if the curve generation component includes a matlab module component, the process of drawing and generating a target data curve corresponding to the target data and an expected data curve corresponding to the expected data through the matlab module component, and adjusting the visualization parameters of the target data curve and the expected data curve includes: comparing the target data and the expected data A text document is transmitted to the matlab module component; a curve of the first expected data in the text document is drawn through the first function in the matlab module component, which is recorded as the first expected data curve; and the visualization parameters of the first expected data curve are adjusted by modifying the internal parameters of the first function; wherein the first function includes the plot function; the state of the first expected data curve at the current moment is maintained through the second function in the matlab module component, and the curve of the first target data in the text document is drawn using the first function, which is recorded as the first target data curve; and the visualization parameters of the first target data curve are adjusted by modifying the internal parameters of the first function; wherein the second function includes the hold on function, the first target data and the first expected data are the same group of comparison display data; the curve of the target data and the curve of the expected data are compared and displayed according to different visualization parameters.

7. A data comparison and verification device, characterized in that: include: processor; and, A computer-readable medium storing instructions, when the processor executes the instructions, causes the device to perform the data comparison and verification method as described in any one of claims 1 to 5.

8. A computer-readable medium, characterized in that Instructions are stored thereon, and the instructions are loaded by a processor to execute the data comparison and verification method as described in any one of claims 1 to 5.

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