Optical Clock Recovery System and Method

Abstract

The present invention relates to the field of optical communication technologies, and discloses an optical clock recovery system and method. The present invention converts an optical signal of a clock to be recovered into an electrical signal, and outputs the electrical signal to a digital signal processing module; outputs a configuration instruction to the digital signal processing module, and when the digital signal configuration rate in the configuration instruction matches the electrical signal, performs signal locking, controls an indication module to perform corresponding locking indication, and configures the digital signal processing module to enable a clock output module to output the recovered clock in the optical signal of the clock to be recovered. The present invention has the technical effects of supporting single-mode and multi-mode optical signal input, fast signal locking, stability, and small output clock jitter.

Description

Technical Field

[0001] The present invention relates to the field of optical communication technologies, and particularly to an optical clock recovery system and method. Background Art

[0002] With the rapid development of data centers, base stations, etc., the rates of various interfaces are continuously increasing; the eye diagram test of optical modules requires the clock recovered by CDR for testing. Currently, the devices on the market do not support single-mode and multi-mode, resulting in the inability to meet the needs of production testing. For single-channel rates such as 4*100G / 8*100G optical modules reaching 100 Gpcs, to test the optical eye diagram, the clock must be recovered from the optical signal to accurately test the optical eye diagram.

[0003] Single-wave 100G clock recovery is a difficult problem in domestic design. Most clock recovery devices on the market use analog CDR chips. Since an external precise phase matching circuit is required, it is easy to have frequency deviation, resulting in unstable clock signals, etc. Meeting the rate requirement of 100 Gbps poses higher requirements for clock recovery technology because it is necessary to quickly and accurately recover the clock signal to ensure the correct transmission and demodulation of data. Currently, many clock recovery devices on the market use analog CDR chips. Although these chips can achieve clock recovery to a certain extent, they may require additional precise phase matching circuits and more complex circuit designs to cope with the challenges at high speeds. The signals at high speeds may be affected by frequency deviation, which may lead to the instability of the clock signal, thereby affecting the accurate transmission of data.

[0004] The above content is only used to assist in understanding the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of the present invention is to provide an optical clock recovery system and method, aiming to solve the technical problem of unstable output clock signals in the prior art.

[0006] To achieve the above purpose, the present invention provides an optical clock recovery system. The optical clock recovery system includes an optical signal output module, an optical signal conversion module, a digital signal processing module, a programmable clock module, a control module, a clock output module, and an indication module. The control module is respectively connected to the optical signal conversion module, the digital signal processing module, the programmable clock module, and the indication module. The digital signal processing module is respectively connected to the optical signal output module, the optical signal conversion module, the programmable clock module, and the clock output module;

[0007] The optical signal output module is used to transmit the optical signal of the clock to be recovered to the optical signal conversion module;

[0008] The optical signal conversion module is configured to convert the optical signal into an electrical signal and output the electrical signal to the digital signal processing module;

[0009] The control module is configured to output a configuration instruction to the digital signal processing module. When the digital signal configuration rate in the configuration instruction matches the electrical signal, signal locking is performed, the indication module is controlled to perform corresponding locking indication, and the digital signal processing module is configured so that the clock output module outputs the recovered clock from the optical signal of the clock to be recovered.

[0010] Optionally, the digital signal processing module includes a high-speed differential receiving unit, an internal clock unit, an LTX channel, and an MCLK channel. The high-speed differential receiving unit is respectively connected to the optical signal conversion module and the internal clock unit, and the internal clock unit is respectively connected to the LTX channel and the MCLK channel;

[0011] The high-speed differential receiving unit is configured to receive the electrical signal converted by the optical signal conversion module and extract a synchronous clock signal from the electrical signal;

[0012] The internal clock unit is configured to adjust the bandwidth of the synchronous clock signal and perform filtering processing to obtain a clock signal with low jitter;

[0013] The internal clock unit is further configured to control all clock links inside the digital signal processing module;

[0014] The LTX channel and the MCLK channel are configured to output the clock signal with low jitter to the clock output module.

[0015] Optionally, the control module is connected to an external intelligent terminal through a network interface;

[0016] The network interface is configured to receive the configuration instruction of the intelligent terminal so that the control module controls the digital signal processing module to output the required clock.

[0017] Optionally, the optical signal conversion module uses silicon optical materials.

[0018] In addition, to achieve the above object, the present invention further provides an optical clock recovery method. The optical clock recovery method is applied to the optical clock recovery system as described above. The optical clock recovery system includes an optical signal output module, an optical signal conversion module, a digital signal processing module, a programmable clock module, a control module, a clock output module, and an indication module. The optical clock recovery method includes the following steps:

[0019] Configure the digital signal processing module;

[0020] When the configuration rate of the digital signal processing module matches the electrical signal transmitted by the optical signal conversion module, control the digital signal processing module to lock the electrical signal;

[0021] Control the digital signal processing module to process the electrical signal to obtain a clock signal with low jitter;

[0022] Output the clock signal with low jitter through the clock output module.

[0023] Optionally, the configuration of the digital signal processing module includes:

[0024] Control the programmable clock module to provide a working clock to the digital signal processing module, and download a digital signal control program to control the digital signal processing module to achieve the configuration of the digital signal processing module.

[0025] Optionally, the step of when the configuration rate of the digital signal processing module matches the electrical signal transmitted by the optical signal conversion module, controlling the digital signal processing module to lock the electrical signal includes:

[0026] Receive a control instruction input externally through a USB interface, and control the configuration rate of the digital signal processing module to match the electrical signal;

[0027] When the configuration rate of the digital signal processing module does not match or the electrical signal received by the digital signal processing module is too weak, control the indication module to turn on a red light;

[0028] When the configuration rate of the digital signal processing module matches, control the digital signal processing module to lock the electrical signal, and control the indication module to turn on a green light.

[0029] Optionally, the step of controlling the digital signal processing module to process the electrical signal to obtain a clock signal with low jitter includes:

[0030] Extract a synchronous clock signal from the locked electrical signal through the digital signal processing module, and transmit the synchronous clock signal to the internal clock unit;

[0031] Adjust the bandwidth of the synchronous clock signal through a filter of the internal clock unit, and perform filtering processing to obtain a clock signal with low jitter.

[0032] Optionally, after obtaining the clock signal with low jitter, it further includes:

[0033] When it is required to output a clock signal within a preset frequency range, output the clock signal with low jitter through the MCLK channel;

[0034] When a clock signal with a demand output exceeding the preset frequency range is required, the low-jitter clock signal is output through the LTX channel.

[0035] Optionally, it further includes:

[0036] Set the frequency division ratio of the low-jitter clock signal output from the MCLK channel or the LTX channel to obtain a frequency-divided clock signal;

[0037] Transmit the frequency-divided clock signal to the clock output module;

[0038] Output the clock through the clock output module.

[0039] An optical clock recovery system and method proposed by the present invention convert an optical signal of a clock to be recovered into an electrical signal and output the electrical signal to a digital signal processing module; output a configuration instruction to the digital signal processing module. When the digital signal configuration rate in the configuration instruction matches the electrical signal, signal locking is performed, the control indication module performs corresponding locking indication, and the digital signal processing module is configured to enable the clock output module to output the recovered clock in the optical signal of the clock to be recovered. The present invention has the technical effects of supporting single-mode and multi-mode optical signal input, fast signal locking, stability, and small output clock jitter. The system and method use silicon photonics materials and have good responsiveness to both single-mode and multi-mode signals, thus realizing a clock recovery device that supports single and multi-modes. Description of the Drawings

[0040] Figure 1 It is a structural block diagram of the first embodiment of the optical clock recovery system of the present invention;

[0041] Figure 2 It is a structural block diagram of the digital signal processing module in the first embodiment of the optical clock recovery system of the present invention;

[0042] Figure 3 It is an internal implementation flow block diagram of clock extraction by DSP in the first embodiment of the optical clock recovery system of the present invention;

[0043] Figure 4 It is a schematic flow diagram of the first embodiment of the optical clock recovery method of the present invention;

[0044] Figure 5 It is a schematic flow diagram of the second embodiment of the optical clock recovery method of the present invention.

[0045] The realization, functional characteristics, and advantages of the object of the present invention will be further described with reference to the embodiments and the drawings. Detailed Embodiments

[0046] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0047] An embodiment of the present invention provides an optical clock recovery system. Refer to Figure 1 , Figure 1 which is a structural block diagram of the first embodiment of the optical clock recovery system of the present invention.

[0048] In this embodiment, the optical clock recovery system includes an optical signal output module 10, an optical signal conversion module 20, a digital signal processing module 30, a programmable clock module 40, a control module 50, a clock output module 60, and an indication module 70. The control module 50 is respectively connected to the optical signal conversion module 20, the digital signal processing module 30, the programmable clock module 40, and the indication module 70. The digital signal processing module 30 is respectively connected to the optical signal output module 10, the optical signal conversion module 20, the programmable clock module 40, and the clock output module 60;

[0049] In this embodiment, the optical signal output module 10 is configured to transmit an optical signal of the clock to be recovered to the optical signal conversion module 20;

[0050] In this embodiment, the optical signal conversion module 20 is configured to convert the optical signal into an electrical signal and output the electrical signal to the digital signal processing module 30;

[0051] In a specific implementation, the optical signal conversion module converts the optical signal transmitted by the optical signal output module into an electrical signal, and then transmits the electrical signal to the DSP module.

[0052] In this embodiment, the control module 50 is configured to output a configuration instruction to the digital signal processing module 30. When the digital signal configuration rate in the configuration instruction matches the electrical signal, signal locking is performed, the indication module 70 is controlled to perform a corresponding locking indication, and the digital signal processing module 30 is configured to enable the clock output module 60 to output the recovered clock in the optical signal of the clock to be recovered.

[0053] It should be noted that the optical signal output module 10 can be an FC / PC interface. The FC / PC (Fiber Connector / Physical Contact) interface is a standardized interface for fiber optic connections. The optical signal conversion module 20 can be a photodetector, which is an optoelectronic sensor including photodiodes, photodetector arrays, photomultiplier tubes, photoconductors, etc., and is used to convert optical signals into electrical signals. The digital signal processing module 30 is mainly a DSP module, and the control module 50 can be an MCU control unit. The MCU (Microcontroller Unit), also known as a microcontroller unit in Chinese, is a microcomputer system integrating core functions such as a central processing unit (CPU), memory (RAM and / or ROM), input / output ports, timers, counters, etc.

[0054] It should be understood that the programmable clock module only provides the working clock for the DSP.

[0055] As Figure 2 shown, Figure 2 As shown in the block diagram of the digital signal processing module in the first embodiment of the optical clock recovery system of the present invention, the digital signal processing module 30 includes a high-speed differential receiving unit, an internal clock unit, an LTX channel, and an MCLK channel. The high-speed differential receiving unit is respectively connected to the optical signal conversion module and the internal clock unit, and the internal clock unit is respectively connected to the LTX channel and the MCLK channel;

[0056] The high-speed differential receiving unit is used to receive the electrical signal converted by the optical signal conversion module and extract the synchronous clock signal from the electrical signal;

[0057] It should be noted that the data signal converted by the photodetector is received by the high-speed differential receiving unit.

[0058] The internal clock unit is used to adjust the bandwidth of the synchronous clock signal and perform filtering processing to obtain a low-jitter clock signal;

[0059] It should be noted that since the bandwidth of the clock channel is usually not too high, it is necessary to adjust the bandwidth and perform filtering processing.

[0060] The internal clock unit is also used to control all the clock links inside the digital signal processing module;

[0061] The LTX channel and the MCLK channel are used to output the low-jitter clock signal to the clock output module.

[0062] It should be noted that the internal clock unit can be the PLL clock inside the DSP module.

[0063] Further, the control module is connected to an external intelligent terminal through a network interface;

[0064] The network interface is used to receive a configuration instruction from the intelligent terminal, so that the control module controls the digital signal processing module to output a required clock.

[0065] Further, the optical signal conversion module uses silicon photonics materials.

[0066] It should be noted that the PD uses a PD made of silicon photonics materials. The PD made of silicon photonics materials has good responsivity to both single-mode and multi-mode signals, thereby realizing a clock recovery device that supports single and multi-mode.

[0067] As Figure 3 shown, Figure 3 This is a block diagram of the internal implementation process of clock extraction by DSP in the first embodiment of the optical clock recovery system of the present invention. The date (electrical signal) is obtained through RX (the high-speed differential receiving unit of DSP), the electrical signal is subjected to RECOVERYCLOCK (signal locking), a synchronous clock signal is extracted from the locked electrical signal, and transmitted to the PLL (internal clock unit). The bandwidth is adjusted and filtered through the filter in the PLL to obtain a clock signal. At this time, the clock signal can be output from two channels, one is the MCLK channel, and the other is the LTX channel. After setting the frequency division ratio of the clock signals transmitted through the MCLK channel and the LTX channel, the clock is output.

[0068] In this embodiment, an optical clock recovery system converts an optical signal of a clock to be recovered into an electrical signal, and outputs the electrical signal to a digital signal processing module; an output configuration instruction is sent to the digital signal processing module. When the digital signal configuration rate in the configuration instruction matches the electrical signal, signal locking is performed, the control indication module performs corresponding locking indication, and the digital signal processing module is configured to enable the clock output module to output the clock recovered from the optical signal of the clock to be recovered, having the technical effects of supporting single-mode and multi-mode optical signal input, fast signal locking, stability, and small output clock jitter.

[0069] The embodiment of the present invention also provides an optical clock recovery method. Referring to Figure 4 , Figure 4 This is a schematic flowchart of the first embodiment of the optical clock recovery method of the present invention.

[0070] In this embodiment, the method is applied to the optical clock recovery system as described above, and includes the following steps:

[0071] Step S10: Configure the digital signal processing module.

[0072] It should be noted that the digital signal processing module is an electronic module or integrated circuit specifically designed to process digital signals. Digital Signal Processing (DSP) is a technology that processes digital signals through algorithms and mathematical operations. It usually includes hardware and / or software components for performing various signal processing tasks.

[0073] It should be understood that the digital signal processing module also has a clock and timing unit: a clock unit for synchronization and timing processing to ensure that the digital signal processing module operates according to a predetermined timing sequence.

[0074] Furthermore, the control programmable clock module provides a working clock to the digital signal processing module and downloads a digital signal control program to control the digital signal processing module, thereby realizing the configuration of the digital signal processing module.

[0075] It should be noted that the programmable clock module is an electronic module or integrated circuit with programmability, which allows users to adjust and configure parameters such as the frequency, phase, and other related parameters of the clock signal, and provides a working clock for the DSP.

[0076] It can be understood that the digital signal control program can be written in C language, MATLAB / Simulink, VHDL / Verilog, or Python.

[0077] In a specific implementation, the MCU controls the programmable clock to provide a clock for the DSP and simultaneously downloads initialization software to the DSP.

[0078] Step S20: When the configuration rate of the digital signal processing module matches the electrical signal transmitted by the optical signal conversion module, control the digital signal processing module to lock the electrical signal.

[0079] It should be noted that the setting of the clock ensures that the clock frequency of the digital signal processing module matches the rate of the electrical signal transmitted by the optical signal conversion module. If multiple modules or devices need to synchronize the clock, ensure that they use the same clock source or are synchronized through a dedicated synchronization signal.

[0080] It can be understood that during the configuration process, it is necessary to ensure that the digital signal processing module can receive and process signal standards that match the electrical signal output by the optical signal conversion module. This may include different level, protocol, baud rate, etc. settings to ensure that the input interface or port of the digital signal processing module can adapt to the signal type output by the optical signal conversion module. Sometimes, an adapter or converter may be required to handle different types of interfaces.

[0081] It should be understood that the digital signal processing module locks the electrical signal to capture and stabilize the input signal.

[0082] In a specific implementation, when it is detected that the configuration rate of the digital signal processing module matches the electrical signal transmitted by the optical signal conversion module, the electrical signal is locked.

[0083] Furthermore, by receiving a control instruction input externally, the configuration rate of the digital signal processing module is controlled to match the electrical signal; when the configuration rate of the digital signal processing module does not match or the electrical signal received by the digital signal processing module is too weak, the control indication module lights up a red light; when the configuration rate of the digital signal processing module matches, the digital signal processing module is controlled to lock the electrical signal, and the control indication module lights up a green light.

[0084] It should be noted that the externally input control instruction is connected to a computer through a USB interface, and the user inputs the control instruction through the computer.

[0085] It should be understood that the control indication module can be an indicator light, and the color of the lit light can also be adjusted according to actual needs.

[0086] It can be understood that when the configuration rate of the digital signal processing module does not match or the electrical signal received by the digital signal processing module is too weak, clock recovery cannot be performed normally at this time, and it is necessary to further input a control instruction or perform an adaptive adjustment by the digital signal processing module to make the configuration rate match the input signal.

[0087] In a specific implementation, a control instruction is received through a USB connection to a computer to control the configuration rate of the digital signal processing module to match the electrical signal; when the configuration rate of the digital signal processing module does not match or the electrical signal received by the digital signal processing module is too weak, the indicator light is controlled to light up a red light; when the configuration rate of the digital signal processing module matches, the digital signal processing module is controlled to lock the electrical signal, and the indicator light is controlled to light up a green light.

[0088] Step S30: Control the digital signal processing module to process the electrical signal to obtain a low-jitter clock signal.

[0089] It should be noted that a low-jitter clock signal refers to a clock signal with very stable and consistent characteristics, with very small phase and frequency variations. Jitter refers to the random or periodic fluctuations of the clock signal in the time domain. In fields that require high precision, high reliability, or high requirements for signal stability, a low-jitter clock signal is crucial.

[0090] In a specific implementation, through internal PLL clock switching in the digital signal processing module and adjusting the recovery clock link bandwidth, a high-quality low-jitter output clock is obtained.

[0091] Step S40: Output the low-jitter clock signal through the clock output module.

[0092] It should be noted that the clock output module includes a preset number of SMA interfaces. The SMA connector is a threaded connector that provides a reliable way to connect and disconnect. This is very useful for the frequent connection and disconnection between the optical clock recovery module and other devices, such as during debugging or maintenance.

[0093] The SMA interface is usually used to transmit high-frequency clock signals. This can be a clock signal recovered from the optical signal received by the optical fiber. The SMA interface provides a channel for high-frequency transmission, ensuring that the clock signal can be efficiently transmitted between components.

[0094] In a specific implementation, the low-jitter output clock is output through the SMA interface of the clock output module.

[0095] In this embodiment, the optical signal of the clock to be recovered is converted into an electrical signal and output to the digital signal processing module; a configuration instruction is output to the digital signal processing module. When the digital signal configuration rate in the configuration instruction matches the electrical signal, signal locking is performed, the indication module is controlled to perform corresponding locking indication, and the digital signal processing module is configured so that the clock output module outputs the clock recovered from the optical signal of the clock to be recovered. It has the technical effects of fast signal locking, stability, and small output clock jitter, and through the indication module, the user can intuitively observe the progress of the target optical clock recovery process.

[0096] Reference Figure 5 , Figure 5 is a schematic flowchart of the second embodiment of the optical clock recovery method of the present invention.

[0097] Based on the above first embodiment, in this embodiment, in order to process the electrical signal, the step S30 may include:

[0098] Step S301: Extract the synchronous clock signal from the locked electrical signal through the digital signal processing module and transmit the synchronous clock signal to the internal clock unit.

[0099] It should be noted that the synchronous clock signal is mainly used to keep the clocks of different arithmetic units in the system within a certain deviation range, so that the states of each unit are the same during the operation. Time synchronization mainly sets a clock as the standard time. During the operation of the system, other computing units obtain the standard clock through the network or other communication methods, and then remove the communication delay and set their own clocks to the standard clock.

[0100] Step S302: Adjust the bandwidth of the synchronous clock signal through the filter of the internal clock unit and perform filtering processing to obtain a low-jitter clock signal.

[0101] Note that in digital communication, bandwidth refers to the frequency range that a system can transmit. The wider the bandwidth, the higher-frequency signals the system can transmit, and thus theoretically higher transmission rates can be achieved. However, increasing the bandwidth may introduce more noise and distortion, so a trade-off is needed in actual design.

[0102] Filtering is used to adjust the spectral characteristics of a signal. Filtering can be used to limit the bandwidth of a signal, remove unwanted frequency components, and improve the quality of the signal. The design of the filtering process directly affects the frequency response of the system and the shape of the signal.

[0103] Since the bandwidth of the clock channel is usually not very high, it is necessary to adjust the bandwidth and perform filtering.

[0104] In a specific implementation, the bandwidth of the recovered clock link is adjusted to obtain a high-quality low-jitter output clock.

[0105] Furthermore, in this embodiment, step S302 may include:

[0106] When a clock signal within a preset frequency range needs to be output, the low-jitter clock signal is output through the MCLK channel; when a clock signal outside the preset frequency range needs to be output, the low-jitter clock signal is output through the LTX channel.

[0107] Note that the clock signal can be output from two channels. One is the MCLK channel, and the other is the LTX channel. Both can be achieved through DSP information configuration. The MCLK channel usually involves the transmission of the main clock. The advantage of the LTX channel is that the amplitude can be adjusted and the channel bandwidth is more sufficient.

[0108] Still further, a division ratio is set for the low-jitter clock signal output from the MCLK channel or the LTX channel to obtain a divided clock signal; the divided clock signal is transmitted to the clock output module; and clock output is performed through the clock output module.

[0109] Note that setting the division ratio usually involves setting a clock or frequency divider in an electronic system to reduce the frequency of the input signal to the required output frequency. The division ratio is the ratio of the input frequency to the output frequency and is used to determine the division ratio. When the data signal received by RX is 53.125 GBaud, if a 4-division is set, a clock signal of 53.125 GBaud / 4 = 13.28125 G is output.

[0110] In this embodiment, the digital signal processing module extracts the synchronous clock signal from the locked electrical signal, transmits the synchronous clock signal to the internal clock unit, and then adjusts the bandwidth of the synchronous clock signal through the filter of the internal clock unit and performs filtering to obtain a low-jitter clock signal.

[0111] It should be noted that in this article, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or system comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or system. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or system comprising such element.

[0112] The serial numbers of the embodiments of the present invention above are only for description and do not represent the superiority or inferiority of the embodiments.

[0113] Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such understanding, the technical solution of the present invention, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as a read-only memory / random access memory, magnetic disk, optical disk), and includes several instructions to enable a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0114] The above are only the preferred embodiments of the present invention and do not limit the patent scope of the present invention accordingly. Any equivalent structural or equivalent process transformation made by using the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. An optical clock recovery system, characterized in that, The optical clock recovery system includes an optical signal output module, an optical signal conversion module, a digital signal processing module, a programmable clock module, a control module, a clock output module, and an indication module. The control module is respectively connected to the optical signal conversion module, the digital signal processing module, the programmable clock module, and the indication module. The digital signal processing module is respectively connected to the optical signal output module, the optical signal conversion module, the programmable clock module, and the clock output module; The optical signal output module is configured to transmit the optical signal of the clock to be recovered to the optical signal conversion module; The optical signal conversion module is configured to convert the optical signal into an electrical signal and output the electrical signal to the digital signal processing module; The control module is configured to output a configuration instruction to the digital signal processing module. When the digital signal configuration rate in the configuration instruction matches the electrical signal, signal locking is performed, the indication module is controlled to perform corresponding locking indication, and the digital signal processing module is configured to enable the clock output module to output the recovered clock in the optical signal of the clock to be recovered; The digital signal processing module includes a high-speed differential receiving unit, an internal clock unit, an LTX channel, and an MCLK channel. The high-speed differential receiving unit is respectively connected to the optical signal conversion module and the internal clock unit. The internal clock unit is respectively connected to the LTX channel and the MCLK channel; The high-speed differential receiving unit is configured to receive the electrical signal converted by the optical signal conversion module and extract a synchronous clock signal from the electrical signal; The internal clock unit is configured to adjust the bandwidth of the synchronous clock signal and perform filtering processing to obtain a clock signal with low jitter; The internal clock unit is further configured to control all clock links inside the digital signal processing module; The LTX channel and the MCLK channel are configured to output the clock signal with low jitter to the clock output module.

2. The optical clock recovery system according to claim 1, characterized in that, The control module is connected to an external intelligent terminal through a network interface; The network interface is configured to receive the configuration instruction of the intelligent terminal, so that the control module controls the digital signal processing module to output the required clock.

3. The optical clock recovery system according to claim 1, wherein The optical signal conversion module uses silicon photonics materials.

4. A method for optical clock recovery, characterized in that, The optical clock recovery method is applied to the optical clock recovery system according to any one of claims 1 to 3. The optical clock recovery system includes an optical signal output module, an optical signal conversion module, a digital signal processing module, a programmable clock module, a control module, a clock output module, and an indication module. The optical clock recovery method includes the following steps: Configure the digital signal processing module; When the configuration rate of the digital signal processing module matches the electrical signal transmitted by the optical signal conversion module, control the digital signal processing module to lock the electrical signal; Control the digital signal processing module to process the electrical signal to obtain a clock signal with low jitter; Output the clock signal with low jitter through the clock output module.

5. The optical clock recovery method according to claim 4, wherein The configuring the digital signal processing module includes: The control programmable clock module provides an operating clock to the digital signal processing module and downloads a digital signal control program to control the digital signal processing module, thereby achieving the configuration of the digital signal processing module.

6. The optical clock recovery method according to claim 4, wherein When the configuration rate of the digital signal processing module matches the electrical signal transmitted by the optical signal conversion module, controlling the digital signal processing module to lock the electrical signal includes: Receiving an externally input control instruction through a USB interface to control the configuration rate of the digital signal processing module to match the electrical signal; When the configuration rate of the digital signal processing module does not match or the electrical signal received by the digital signal processing module is too weak, controlling the indicator module to turn on a red light; When the configuration rate of the digital signal processing module matches, controlling the digital signal processing module to lock the electrical signal and controlling the indicator module to turn on a green light.

7. The optical clock recovery method according to claim 4, wherein Controlling the digital signal processing module to process the electrical signal to obtain a low-jitter clock signal includes: Extracting a synchronous clock signal from the locked electrical signal through the digital signal processing module and transmitting the synchronous clock signal to the internal clock unit; Adjusting the bandwidth of the synchronous clock signal through a filter of the internal clock unit and performing filtering processing to obtain a low-jitter clock signal.

8. The optical clock recovery method according to claim 4, wherein After obtaining the low-jitter clock signal, it further includes: When a clock signal within a preset frequency range is required to be output, outputting the low-jitter clock signal through an MCLK channel; When a clock signal outside the preset frequency range is required to be output, outputting the low-jitter clock signal through an LTX channel.

9. The optical clock recovery method according to claim 8, wherein It further includes: Setting a division ratio for the low-jitter clock signal output through the MCLK channel or the LTX channel to obtain a divided clock signal; Transmitting the divided clock signal to a clock output module; Performing clock output through the clock output module.

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