A high-voltage pre-modulation circuit applied to wide LDO input

Abstract

The application relates to the technical field of power modulation circuits, in particular to a high-voltage pre-modulation circuit applied to a wide LDO input, which comprises a main switch tube, a first transient response circuit and a second transient response circuit; when the modulation power voltage jumps from low to high, the first transient response circuit is turned on to reduce the modulation power voltage; when the modulation power voltage jumps from high to low, the second transient response circuit outputs a bias current to a main switch tube control module of the main switch tube to increase the current flowing through the main switch tube of the power supply circuit. The beneficial effect is that the first transient response circuit and the second transient response circuit are configured, and different trigger conditions are set. When the voltage of the power supply circuit in the front stage jumps to high voltage or low voltage, the current flowing through the main switch tube and the output node can be discharged or increased in time through the first transient response circuit or the second transient response circuit, so that the output voltage approaches the target value, and a faster response speed is realized.

Description

Technical Field

[0001] This invention relates to the field of power modulation circuit technology, and more specifically to a high-voltage pre-modulation circuit applied to wide LDO input. Background Technology

[0002] In recent years, with the increasing demand for automobiles and the growing proportion of electronic systems in vehicles, the automotive electronics market has been developing at a rapid pace. In the field of automotive electronics applications, high-voltage power management chips, as a core component of high-voltage electronic systems, have received increasing attention and research. Compared to other power management chips, LDOs offer faster transient response, lower noise, a simpler circuit structure, and lower cost, making them more widely used as high-voltage power management chips. The application environment of automotive electronic systems, such as "load dump" scenarios, demands a wide input range from LDO chips, while also requiring stable operation when external high voltage transients are generated.

[0003] In existing technologies, there are solutions that incorporate pre-modulation of the power supply voltage and loop control into LDO chips to achieve better output stability. For example, Chinese patent CN201510473212.6 describes a high-voltage LDO using a charge pump, which includes an internal LDO module, a charge pump, a voltage-controlled oscillator (VCO), a modulator, a high-voltage LDNMOS transistor, and a feedback voltage sampling circuit. The drain of the high-voltage LDNMOS transistor is connected to the input voltage, and the source of the high-voltage LDNMOS transistor is the output terminal of the high-voltage LDO. The input terminal of the feedback voltage sampling circuit is connected to the output terminal of the high-voltage LDO, and the output terminal of the feedback voltage sampling circuit is sequentially connected to the modulator, the VCO, and the charge pump. The output terminal of the charge pump is connected to the gate of the high-voltage LDNMOS transistor. This invention uses the feedback voltage output from the feedback voltage sampling circuit to generate a feedback signal through the modulator, which controls the VCO to generate variable frequencies with different duty cycles. This allows the charge pump output to adapt to different gate voltages, thereby achieving the purpose of adjusting the output voltage and output current.

[0004] However, in actual implementation, the inventors found that the feedback loop, which controls the voltage-controlled oscillator to change the control frequency by sampling and modulating the circuit to stabilize the voltage, has a slow adjustment speed and is difficult to achieve a good response speed. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, a high-voltage pre-modulation circuit for wide LDO input is provided.

[0006] The specific technical solution is as follows:

[0007] A high-voltage pre-modulation circuit for wide LDO input includes:

[0008] The main switch transistor has its gate and input terminals connected to an external power supply circuit.

[0009] A first transient response circuit, wherein the input terminal of the first transient response circuit is connected to the output terminal of the main switching transistor, and the output terminal of the first transient response circuit is connected to the output node;

[0010] The output node is connected to the subsequent functional circuit.

[0011] A second transient response circuit, wherein the input terminal of the second transient response circuit is connected to the power supply circuit, and the feedback terminal of the second transient response circuit is connected to the output node;

[0012] When the modulation power supply voltage output by the output node to the functional circuit stabilizes at the target value, the first transient response circuit and the second transient response circuit do not work.

[0013] When the modulation power supply voltage jumps from low to high, the first transient response circuit is turned on to ground to reduce the modulation power supply voltage.

[0014] When the modulation power supply voltage jumps from high to low, the second transient response circuit outputs a bias current to the main switch control module of the main switch to increase the current flowing through the main switch in the power supply circuit.

[0015] On the other hand, the first transient response circuit includes:

[0016] The first transient control switch is connected to the input and output terminals of the first transient response circuit, respectively.

[0017] The first voltage divider module has its input terminal connected to the input terminal of the first transient switch transistor, and its output terminal connected to the gate of the first transient control switch transistor.

[0018] A first capacitor, the first terminal of which is connected to the gate of the first transient control switch, and the second terminal of which is grounded;

[0019] The first discharge switch transistor has its drain connected to the input and output terminals of the first transient response circuit, respectively, and its gate connected to the drain of the first transient control switch transistor.

[0020] On the other hand, the first voltage divider module includes:

[0021] The first loop resistor has its first end connected to the input terminal of the first voltage divider module.

[0022] The second loop resistor has its first end connected to the second end of the first loop resistor, and its second end connected to the output terminal of the first voltage divider module.

[0023] The first transient response circuit further includes:

[0024] The second discharge switch transistor has its drain connected to the second terminal of the first loop resistor and its gate connected to the drain of the first transient control switch transistor.

[0025] The first loop bias current source has its input terminal connected to the source of the second discharge switch transistor, and its output terminal grounded.

[0026] The third loop resistor has its first end connected to the drain of the first transient control switch transistor, and its second end grounded.

[0027] On the other hand, the main switch control module includes:

[0028] The first control switch has its drain connected to the power supply circuit, its source connected to the input terminal of the main switch, and its gate connected to the gate of the main switch.

[0029] The second control switch has its source connected to the power supply circuit, its drain connected to the input terminal of the main switch, and its gate connected to the bias current output terminal of the second transient response circuit.

[0030] The second voltage divider module has its input terminal connected to the power supply circuit and its output terminal connected to the gate of the main switching transistor.

[0031] On the other hand, the main switch control module also includes:

[0032] The main switch resistor, the first end of which is connected to the gate of the main switch transistor;

[0033] A main switch bias current source is provided, with its input terminal connected to the second terminal of the main switch resistor and its output terminal grounded.

[0034] On the other hand, the second transient response circuit includes:

[0035] The second capacitor has its first terminal connected to the feedback terminal of the second transient response circuit.

[0036] The first current mirror switch is connected to the first input terminal of the second transient response circuit, and the gate of the first current mirror switch is connected to the second terminal of the second capacitor.

[0037] The second current mirror switch has its source connected to the second input terminal of the second transient response circuit, its gate connected to the second terminal of the second capacitor, and its gate connected to the drain of the second current mirror switch.

[0038] The gate of the first current mirror switch is connected to the gate of the second current mirror switch;

[0039] The second loop bias current source has its input terminal connected to the drain of the second current mirror switch, and its output terminal grounded.

[0040] The third current mirror switch has its drain connected to the drain of the first current mirror switch, its gate connected to the drain of the third current mirror switch, and its source grounded.

[0041] The fourth current mirror switch has its gate connected to the gate of the third current mirror switch, its drain connected to the bias output terminal of the second transient response circuit, and its source grounded.

[0042] On the other hand, the second transient response circuit includes:

[0043] The third capacitor, the first end of which is connected to the feedback terminal of the second transient response circuit;

[0044] The third loop bias current source, the first end of the third loop bias current source is connected to the second end of the third capacitor and the bias output end of the second transient response circuit respectively;

[0045] A current mirror blocking MOSFET is provided, the source of which is connected to the first input terminal of the second transient response circuit, the gate of which is connected to the drain of which is connected to the drain of which is connected to the source of the first current mirror switching transistor.

[0046] On the other hand, it also includes a startup circuit, which includes:

[0047] A startup bias current source is established, the input terminal of which is connected to the power supply circuit, and the input terminal of which is connected to the bias input terminal of the main switch control module.

[0048] A first start-up resistor, the first end of which is connected to the output terminal of the start-up bias current source;

[0049] The first start-up switch transistor has its drain connected to the second terminal of the first start-up resistor, and its source connected to the bias output terminal of the second transient response circuit.

[0050] The first startup MOSFET has its source connected to the power supply circuit and its gate connected to its drain.

[0051] The second startup MOSFET has its source connected to the drain of the first startup MOSFET, its gate connected to the drain of the second startup MOSFET, and its drain connected to the bias input terminal of the main switch control module.

[0052] On the other hand, the startup circuit also includes:

[0053] A startup current mirror switch is configured, wherein the source of the startup current mirror switch is connected to the power supply circuit, the gate of the startup current mirror switch is connected to the gate of the first startup switch, and the gate of the startup current mirror switch is connected to the drain of the startup current mirror switch.

[0054] The high-voltage modulation circuit also includes:

[0055] An output MOS transistor, wherein the source of the output MOS transistor is connected to the output node, and the gate of the output MOS transistor is connected to the drain of the output MOS transistor;

[0056] The first transistor has its collector connected to the drain of the output MOSFET, and its base connected to the drain of the output MOSFET.

[0057] An output resistor, the first end of which is connected to the emitter of the first transistor;

[0058] The second transistor has its collector connected to the second terminal of the output resistor, its base connected to its collector, and its emitter grounded.

[0059] A load resistor, the first end of which is connected to the drain of the start-up current mirror switch transistor;

[0060] An output control switch is provided, the drain of which is connected to the second terminal of the load resistor, and the gate of which is connected to an external start signal terminal.

[0061] The third transistor has its collector connected to the source of the output control switch, its base connected to the base of the second transistor, and its emitter grounded.

[0062] The above technical solution has the following advantages or beneficial effects:

[0063] To address the slow response speed of existing modulation circuits, this embodiment incorporates a first transient response circuit and a second transient response circuit with different triggering conditions. When the voltage of the preceding power supply circuit transitions to a higher or lower voltage, the first or second transient response circuit can promptly discharge or increase the current flowing through the main switch and output node, thereby bringing the output voltage closer to the target value and achieving a faster response speed. Attached Figure Description

[0064] Embodiments of the invention will be described more fully with reference to the accompanying drawings. However, the drawings are for illustration and explanation only and do not constitute a limitation on the scope of the invention.

[0065] Figure 1 This is an overall schematic diagram of an embodiment of the present invention;

[0066] Figure 2 This is a simplified diagram of the second transient response circuit in an embodiment of the present invention;

[0067] Figure 3 This is a simplified diagram of the negative feedback loop in an embodiment of the present invention. Detailed Implementation

[0068] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0069] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0070] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0071] This invention includes:

[0072] A high-voltage pre-modulation circuit for wide LDO input includes:

[0073] The main switch HVP1 has its gate and input terminals connected to the external power supply circuit VIN.

[0074] The main switch HVP1 is a high-voltage P-type MOSFET with its input terminal being the source and its output terminal being the drain. The output terminal is connected to the first transient response circuit 1.

[0075] The first transient response circuit 1 has its input terminal connected to the output terminal of the main switch transistor and its output terminal connected to the output node VDD.

[0076] The output node VDD is connected to the subsequent functional circuit.

[0077] The second transient response circuit 2 has its input terminal connected to the power supply circuit VIN and its feedback terminal connected to the output node VDD.

[0078] When the modulated power supply voltage output from the output node VDD to the functional circuit stabilizes at the target value, the first transient response circuit 1 and the second transient response circuit 2 do not work.

[0079] When the modulation power supply voltage jumps from low to high, the first transient response circuit 1 is turned on to ground to reduce the modulation power supply voltage.

[0080] When the modulated power supply voltage jumps from high to low, the second transient response circuit 2 outputs a bias current to the main switch control module 3 of the main switch HVP1 to increase the current flowing through the main switch HVP1 in the power supply circuit.

[0081] Specifically, addressing the issue of slow response speed in existing modulation circuits, this embodiment introduces a first transient response circuit 1 and a second transient response circuit 2 into the modulation circuit for adjustment. The power supply circuit VIN is the power supply circuit located before the modulation circuit in the LDO chip, and it has already used appropriate circuitry to generate the supply voltage, intended to supply power to the subsequent functional circuits.

[0082] Under normal operating conditions, the gate-source voltage of the main switch HVP1 is controlled by the main switch control module 3 so that the main switch HVP1 is in the conducting state. The current output by the power supply circuit VIN flows through the main switch HVP1 and the first transient response circuit 1 into the output node VDD. During this process, the first transient response circuit 1 senses the voltage flowing through and determines whether a transition from low to high occurs.

[0083] If it does not exist, the first transient response circuit 1 will not work; if it exists, the first transient response circuit 1 will be connected to ground to reduce the modulation power supply voltage.

[0084] At the same time, when the current input is at the output node VDD, the second transient response circuit 2 also obtains the modulated power supply voltage on the output node VDD through the feedback terminal and determines whether there is a jump from high to low.

[0085] If it does not exist, the second transient response circuit 2 will not operate; if it does exist, the second transient response circuit 2 will output a bias current to the main switch control module 3 of the main switch HVP1 to increase the current flowing through the main switch HVP1 in the power supply circuit, thereby raising the modulated power supply voltage. Through the above settings, a faster response speed can be achieved.

[0086] In one embodiment, the first transient response circuit 1 includes:

[0087] The first transient control switch PM5 has its source connected to the input and output terminals of the first transient response circuit 1, respectively. The first transient control switch PM5 is a P-type MOS transistor.

[0088] The first voltage divider module 11 has its input terminal connected to the input terminal of the first transient switch 11, and its output terminal connected to the gate of the first transient control switch PM5.

[0089] The first capacitor C1 has its first terminal connected to the gate of the first transient control switch PM5, and its second terminal grounded.

[0090] The first discharge switch NM3 has its drain connected to the input and output terminals of the first transient response circuit, and its gate connected to the drain of the first transient control switch. The first discharge switch NM3 is an N-type MOS transistor.

[0091] Specifically, to achieve a better response speed, this embodiment introduces a control circuit consisting of a first transient control switch PM5 and a first capacitor C1. The source of the first transient control switch PM5 is connected to both the input and output terminals of the first transient response circuit 1, making its source voltage equal to the modulation power supply voltage on the output line.

[0092] Under normal operating conditions, the gate-source voltage difference of the first transient control switch PM5 is small under the control of the first voltage divider module 11, and the first transient control switch PM5 is in the off state.

[0093] When the modulation power supply voltage on the output node VDD jumps from low to high, the source voltage of the first transient control switch PM5 rises, while the gate voltage rises more slowly due to the hysteresis effect of the first capacitor C1. This causes the gate-source voltage difference of the first transient control switch PM5 to meet the conduction condition, and the first transient control switch PM5 turns on. This causes the gate voltage of the first discharge switch NM3 to rise, and the first discharge switch NM3 turns on, forming a path from the output node VDD to ground. This constitutes a negative feedback regulation loop to reduce the modulation power supply voltage. After the modulation power supply voltage stabilizes again to the target value, the first transient control switch PM5 and the first discharge switch NM3 turn off.

[0094] The above-mentioned adjustment process relies on the hysteresis effect of the first capacitor C1 on the gate voltage of the first transient control switch PM5 to control the conduction and turn-off of the first transient control switch PM5. Therefore, its adjustment speed is significantly faster than the traditional modulator adjustment of duty cycle scheme, and a faster response speed is achieved.

[0095] In one embodiment, the first voltage divider module 11 includes:

[0096] The first loop resistor R2 has its first end connected to the input terminal of the first voltage divider module 11.

[0097] The second loop resistor R3 has its first end connected to the second end of the first loop resistor R2, and its second end connected to the output terminal of the first voltage divider module 11.

[0098] The first transient response circuit 1 also includes:

[0099] The second discharge switch NM2 has its drain connected to the second end of the first loop resistor R2 and its gate connected to the drain of the first transient control switch. The second discharge switch NM2 is an N-type MOS transistor.

[0100] First loop bias current source I BIAS1 First loop bias current source I BIAS1 The input terminal is connected to the source of the second discharge switch transistor NM2, and the first loop bias current source I... BIAS1 The output terminal is grounded;

[0101] The third loop resistor R4 has its first end connected to the drain of the first transient control switch transistor, and its second end grounded.

[0102] Specifically, to achieve better voltage modulation, in this embodiment, the first voltage divider module 11 is configured as a voltage divider circuit consisting of a first loop resistor R2 and a second loop resistor R3. A second discharge switch NM2 is positioned after the voltage divider node of the first loop resistor R2 and the second loop resistor R3, which controls whether the first loop bias current source I is switched on. BIAS1 Connect to the output line.

[0103] In one embodiment, the main switch control module 3 includes:

[0104] The first control switch NM1 has its drain connected to the power supply circuit VIN, its source connected to the input terminal of the main switch HVP1, and its gate connected to the gate of the main switch HVP1. The first control switch NM1 is an N-type MOS transistor.

[0105] The second control switch PM4 has its source connected to the power supply circuit VIN, its drain connected to the input terminal of the main switch HVP1, and its gate connected to the bias current output terminal of the second transient response circuit 2. The second control switch PM4 is a P-type MOS transistor.

[0106] The second voltage divider module 31 has its input terminal connected to the power supply circuit VIN and its output terminal connected to the gate of the main switch HVP1.

[0107] Specifically, in order to achieve better control of the current flowing through the main switch HVP1, in this embodiment, a second voltage divider module 31 is set in the main switch control module 3 to form a current path from the self-powered circuit VIN to the main switch HVP1, and the power supply voltage is stepped down.

[0108] Subsequently, the gate of the first control switch NM1 is at the same voltage as the gate of the main switch HVP1, the first control switch NM1 is turned on, and a path is formed for the self-powered circuit VIN to flow through the first control switch NM1 to the source of the main switch HVP1, and the main switch HVP1 is turned on to output current.

[0109] When the voltage is stable or a low-to-high transition occurs, the gate voltage of the second control switch PM4 is fixed by the bias current output terminal of the second transient response circuit 2 and the start-up circuit.

[0110] When the modulation power supply voltage transitions from high to low, the bias current of the second transient response circuit 2 decreases, thereby reducing the gate voltage V of the second control switch PM4. PThe reduction in voltage increases the current flowing through the second control switch PM4 and the main switch HVP1, thereby raising the modulation power supply voltage.

[0111] In one embodiment, the main switch control module 3 further includes:

[0112] The main switch resistor R1 is connected to the gate of the main switch HVP1.

[0113] Main switch bias current source I BIAS0 Main switch bias current source I BIAS0 The input terminal is connected to the second terminal of the main switch resistor R1, and the main switch bias current source I... BIAS0 The output terminal is grounded.

[0114] Specifically, to control the gate of the main switch HVP1, in this embodiment, the main switch resistor R1 is set as a load at the connection node between the second voltage divider module 31 and the gate of the main switch HVP1, and a main switch bias current source I is set. BIAS0 The output pull-down bias current enables effective control of the gate voltage of the main switch HVP1.

[0115] The second voltage divider module 31 includes a first voltage divider switch PM1, a second voltage divider switch PM2, and a third voltage divider switch PM3 arranged sequentially along the current transmission direction. The first voltage divider switch PM1, the second voltage divider switch PM2, and the third voltage divider switch PM3 are all P-type MOSFETs and are connected in a diode configuration, that is, the source is used as the input terminal, the drain is used as the output terminal, and the gate is connected to the drain.

[0116] In one embodiment, the second transient response circuit 2 includes:

[0117] The second capacitor C2, the first end of the second capacitor C2 is connected to the feedback terminal of the second transient response circuit 2;

[0118] The source of the first current mirror switch PM12 is connected to the first input terminal of the second transient response circuit 2, and the gate of the first current mirror switch PM12 is connected to the second terminal of the second capacitor C2.

[0119] The second current mirror switch PM13 has its source connected to the second input terminal of the second transient response circuit 2, its gate connected to the second terminal of the second capacitor, and its gate connected to the drain of the second current mirror switch PM13.

[0120] The gate of the first current mirror switch PM12 is connected to the gate of the second current mirror switch PM13.

[0121] The first current mirror switch PM12 and the second current mirror switch PM13 form a current mirror. Both the first current mirror switch PM12 and the second current mirror switch PM13 are P-type MOSFETs.

[0122] Second loop bias current source I BIAS2 Second loop bias current source I BIAS2 The input terminal is connected to the drain of the second current mirror switch PM13, and the second loop bias current source I... BIAS2 The output terminal is grounded;

[0123] The third current mirror switch NM5 has its drain connected to the drain of the first current mirror switch PM12, its gate connected to its drain, and its source grounded.

[0124] The fourth current mirror switch NM4 has its gate connected to the gate of the third current mirror switch NM5, its drain connected to the bias output terminal of the second transient response circuit 2, and its source grounded.

[0125] Both the third current mirror switch NM5 and the fourth current mirror switch NM4 are N-type MOSFETs.

[0126] Specifically, to effectively reduce the gate voltage of the second control switch PM4 when the modulation power supply voltage transitions from high to low, this embodiment includes a second loop bias current source I for pull-down. BIAS2 It is configured with a current mirror consisting of a first current mirror switch PM12 and a second current mirror switch PM13, which is in the off state under normal operating conditions. Since this current mirror is in the off state, the second loop bias current source I... BIAS2 It is not connected to the bias output terminal of the second transient response circuit 2. When the modulation power supply voltage jumps from high to low, since the third capacitor C3 acts as a load, the gate voltages of the first current mirror switch PM12 and the second current mirror switch PM13 decrease as the modulation power supply voltage decreases, thus satisfying the conduction conditions of the first current mirror switch PM12 and the second current mirror switch PM13. The current mirrors are turned on, and the subsequent third current mirror switch NM5 and fourth current mirror switch NM4 also meet the conduction conditions, forming another set of current mirrors. The combination of the above two sets of current mirrors enables the second loop bias current source I. BIAS2 The bias output terminal of the second transient response circuit 2 is connected to effectively reduce the gate voltage of the second control switch PM4, thereby increasing the current flowing through the main switch HVP1.

[0127] In one embodiment, the second transient response circuit 2 includes:

[0128] The third capacitor C3, the first end of the third capacitor C3 is connected to the feedback terminal of the second transient response circuit 2;

[0129] Third loop bias current source I BIAS3 Third loop bias current source I BIAS3 The first end is connected to the second end of the third capacitor C3 and the bias output end of the second transient response circuit 2, respectively;

[0130] The current mirror blocks the MOSFET PM11. The source of the current mirror blocks the MOSFET PM11 is connected to the first input terminal of the second transient response circuit 2. The gate of the current mirror blocks the MOSFET PM11 is connected to the drain of the current mirror blocks the MOSFET PM11. The drain of the current mirror blocks the MOSFET PM11 is connected to the source of the first current mirror switch MOSFET PM12.

[0131] Specifically, to achieve better control of the modulated power supply voltage during the transition from high to low, in this embodiment, a third capacitor C3 is configured in the second transient response circuit 2 to connect the feedback terminal and the bias output terminal of the second transient response circuit 2, and a third loop bias current source I, which is connected to ground, is further configured at the second terminal of the third capacitor C3. BIAS3 When the modulation power supply voltage jumps from high to low, due to the presence of the third capacitor C3, the jump will be coupled to the gate of the second control switch PM4 through the bias output terminal of the second transient response circuit 2, so that its gate voltage is further reduced, forming a negative feedback loop for increasing the modulation power supply voltage, thus achieving a better control effect on the modulation power supply voltage;

[0132] In addition, to ensure that the first current mirror switch PM12 meets the corresponding conduction conditions, a diode-connected current mirror blocking MOSFET PM11 is configured to be reverse-connected between the source of the first current mirror switch PM12 and the first input terminal of the second transient response circuit 2, thereby blocking the source input voltage of the first current mirror switch PM12 and avoiding the problem of false triggering of the first current mirror switch PM12.

[0133] In one embodiment, a startup circuit 4 is further included, the startup circuit 4 comprising:

[0134] Start-up bias current source I BIAS4 Start bias current source I BIAS4 The input terminal is connected to the power supply circuit VIN, and the bias current source I is started. BIAS4 The input terminal is connected to the bias input terminal of the main switch control module 3;

[0135] The first starting resistor R7 is connected to the output terminal of the starting bias current source.

[0136] The first start-up switch HVN2 has its drain connected to the second terminal of the first start-up resistor R7, and its source connected to the bias output terminal of the second transient response circuit 2.

[0137] The first startup switch transistor, HVN2, is a voltage-rated N-type MOSFET.

[0138] The first startup MOSFET PM9 has its source connected to the power supply circuit and its gate connected to the drain.

[0139] The first startup MOSFET PM9 is a P-type MOSFET;

[0140] The second startup MOSFET HVP2 has its source connected to the drain of the first startup MOSFET PM9, its gate connected to the drain of the second startup MOSFET HVP2, and its drain connected to the bias input terminal of the main switch control module 3.

[0141] The second startup MOSFET, HVP2, is a voltage-rated P-type MOSFET.

[0142] Specifically, to achieve the effect that the gate voltage of the second control switch PM4 is initially high during operation, and then pulled low as the second transient response circuit 2 operates, a specific startup circuit 4 is configured at the node between the bias output terminal of the second transient response circuit 2 and the bias input terminal of the main switch control module 3 in this embodiment. Among them, the startup bias current source I... BIAS4 A bias current is input to the bias input terminal of the main switch control module 3. Furthermore, the first startup MOSFET PM9 and the second startup MOSFET HVP2 are connected in a diode configuration, providing a clamping voltage to stabilize the bias input terminal of the main switch control module 3. This configuration raises the gate voltage of the second control switch PM4. During circuit startup, the gate of the first startup switch HVN2 receives an external startup signal and turns on, thereby connecting the bias output terminal of the second transient response circuit 2 with the bias input terminal of the main switch control module 3. This allows the second transient response circuit 2 to subsequently pull down the gate voltage of the second control switch PM4 by applying a bias current.

[0143] In one embodiment, it also includes:

[0144] The source and drain of the capacitor MOSFET PM10 are connected to the power supply circuit VIN.

[0145] The first end of the stabilizing resistor R8 is connected to the gate of the capacitor MOSFET PM10, and the second end of the stabilizing resistor R8 is connected to the bias input terminal of the main switch control module 3.

[0146] Specifically, to achieve better loop stability, this embodiment also includes a capacitor-connected MOSFET PM10 and a stabilizing resistor R8. A zero-point rise phase is introduced at the bias input of the main switch control module 3 to ensure that the loop has sufficient phase margin, thus achieving better loop stability.

[0147] In one embodiment, the startup circuit 2 further includes:

[0148] The starting current mirror switch PM7 is activated. The source of the starting current mirror switch PM7 is connected to the power supply circuit VIN. The gate of the starting current mirror switch PM7 is connected to the gate of the first starting switch PM8. The gate of the starting current mirror switch PM7 is connected to the drain of the starting current mirror switch.

[0149] The output modulation module 5 also includes:

[0150] Output MOSFET PM6, the source of output MOSFET PM6 is connected to the output node, and the gate of output MOSFET PM6 is connected to the drain of output MOSFET PM6.

[0151] The collector of the first transistor Q1 is connected to the drain of the output MOSFET PM6, and the base of the first transistor Q1 is connected to the drain of the output MOSFET PM6.

[0152] Output resistor R5, the first end of output resistor R5 is connected to the emitter of the first transistor Q1;

[0153] The collector of the second transistor Q2 is connected to the second terminal of the output resistor R5, the base of the second transistor Q2 is connected to the collector of the second transistor Q2, and the emitter of the second transistor Q2 is grounded.

[0154] Load resistor R6, the first end of load resistor R6 is connected to the drain of the starting current mirror switching transistor;

[0155] The output control switch HVN1 is connected to the second terminal of the load resistor R6, and the gate of the output control switch HVN1 is connected to the external start signal terminal.

[0156] The output control switch HVN1 is a voltage-rated N-type MOSFET;

[0157] During startup, the output control switch HVN1 receives an externally input control signal to turn on;

[0158] The collector of the third transistor Q3 is connected to the source of the output control switch HVN1, the base of the third transistor Q3 is connected to the base of the second transistor Q2, and the emitter of the third transistor Q3 is grounded.

[0159] The second transient response circuit 2 also includes the following at its first and second input terminals:

[0160] The ninth resistor R9 has its first terminal connected to the power supply circuit VIN.

[0161] The third withstand voltage switch HVN3 has its drain connected to the second terminal of the ninth resistor R9, and its source connected to the first input terminal of the second transient response circuit 2. The gate of the third withstand voltage switch HVN3 is controlled by an external second start signal.

[0162] The third withstand voltage switching transistor, HVN3, is a withstand voltage N-type switching transistor;

[0163] The fourth withstand voltage switch HVN4 has its drain connected to the second terminal of the ninth resistor R9, its source connected to the second input terminal of the second transient response circuit 2, and its gate controlled by the modulation power supply voltage.

[0164] Based on the above configuration, the circuit establishes the modulation power supply voltage during startup in the following manner:

[0165] After the zero point, the front-end power supply circuit starts up, and the power supply voltage is input through the power supply circuit VIN. At the same time, the external bias module is powered on and bias current and voltage are established. As the power supply voltage rises, the bias current and bias voltage are established, the startup circuit 4 starts to work, and the power supply voltage input through the power supply circuit VIN is also raised to the target amplitude.

[0166] On the main switch HVP1 side, since the first voltage divider switch PM1, the second voltage divider switch PM2, and the third voltage divider switch PM3 in the second voltage divider module 31 are connected in a diode configuration, a certain voltage drop occurs in the input voltage VIN of the power supply circuit, establishing the gate voltage of the main switch HVP1, which is approximately V. IN -3V GS ;

[0167] With the first bias voltage V B1 and bias current I BIAS3 I BIAS4With the establishment of the first start-up switch HVN2, the corresponding conduction condition is met, forming a self-starting bias current source I. BIAS4 First starting resistor R7, first starting switch HVN2, third loop bias current source I BIAS3 When the circuit is open, the bias input terminal of the main switch control module 3 generates a voltage V. P This allows the gate voltage of the second control switch PM4 to be established and turned on, introducing the supply voltage to the source of the main switch HVP1.

[0168] At this time, since the output MOS transistor PM6, the first transistor Q1, and the second transistor Q2 in the output modulation module 5 are connected in the form of diodes that are connected to ground, the main switch HVP1 is turned on, forming a path of the fourth PMOS transistor PM4, the main switch HVP1, the output MOS transistor PM6, the first transistor Q1, the output resistor R5, and the second transistor Q2, and outputting the modulation power supply voltage through the output node VDD.

[0169] To achieve better stability, a Zener diode D1 is also included. The cathode of Zener diode D1 is connected to the output node VDD, and the anode is grounded. This is used to reverse conduct and discharge when the modulation power supply voltage rises too high, thus preventing the voltage from becoming excessively high. In one embodiment, this voltage is approximately 7V.

[0170] Furthermore, to prevent excessive source-drain voltage difference in the second control switch PM4 during the power supply voltage rise, a first control switch NM1 is also provided. The drain voltage required for NM1 to turn on is higher than the source voltage of the second control switch PM4. When the power supply voltage rises and meets the turn-on condition of the first control switch NM1, NM1 turns on, pulling up its source voltage and reducing the source-drain voltage difference of the second control switch PM4, thus protecting the second control switch PM4.

[0171] With the output of the modulated power supply voltage and the bias voltage V B2 With the establishment of the second transient response circuit 2, the third withstand voltage switch HVN3 and the fourth withstand voltage switch HVN4 are turned on, forming a connection between the ninth resistor R9, the fourth withstand voltage switch HVN4, the second current mirror switch PM13, and the second loop bias current source I. BIAS2 The current mirror circuit establishes a gate voltage for the first current mirror switch PM12. However, because the current mirror blocks the MOSFET PM11 from acting as a reverse diode, the first current mirror switch PM12 and the third current mirror switch NM5 are not turned on, thus preventing the second loop bias current source I from conducting. BIAS2 It will not participate in the establishment of the modulated power supply voltage. Therefore, only the bias current I... BIAS4 and I BIAS3It participates in establishing the modulated power supply voltage.

[0172] Once the modulation power supply voltage is established, the first startup MOSFET PM9 and the second startup MOSFET HVP2 act as clamping diodes to stabilize the gate voltage of the second control switch PM4, thus stabilizing the voltage V. P Maintain at VIN-2V GS Then I BIAS4 No longer participating in the loop, by I BIAS3 This provides current to the circuit. Finally, the modulated power supply voltage on the output node VDD is established, which can be described as follows:

[0173] VDD_A = 2V BE +V GS +R×(I BIAS3 -I BIAS4 )

[0174] Based on the circuit setup described above, since both the first and second transient response circuits involve adjusting the voltage V through a negative feedback loop... P . Figure 2 For the simplified negative feedback loop of the second transient response circuit 2, Figure 3 A simplified diagram of the negative feedback loop of the second transient response circuit 2, which is disconnected from the feedback terminal.

[0175] Small-signal analysis of the negative feedback loop shows the signal propagation path from VIN to Vo as follows:

[0176]

[0177] In the above formula:

[0178]

[0179]

[0180]

[0181] Here, the second capacitor C2 is subjected to Miller equivalent conversion in the analysis, Av PM4 This is the gain of the common-source amplifier for the second control switch PM4.

[0182] The final transfer function of the loop can be obtained as follows:

[0183]

[0184] Two poles can be obtained:

[0185]

[0186]

[0187] As can be seen, the second transient response circuit 2 has two poles and no zeros. However, considering the first capacitor C1 in the first transient response circuit 1, the overall negative feedback loop should have three poles. To ensure loop stability, a MOS capacitor (made of MOSFET PM10) and a stabilizing resistor R8 are added to the feedback terminal, introducing a zero-point phase rise to ensure sufficient phase margin for the loop. Ultimately, this high-voltage pre-modulation circuit can generate a stable modulation power supply voltage.

[0188] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A high voltage pre-modulation circuit applied to wide LDO input, characterized in that, The application relates to a power supply circuit, which comprises: a main switch tube, the gate and input end of which are respectively connected with an external power supply circuit; a first transient response circuit, the input end of which is connected with the output end of the main switch tube, and the output end of which is connected with an output node; the output node is connected with a functional circuit in a later stage; a second transient response circuit, the input end of which is connected with the power supply circuit, and the feedback end of which is connected with the output node; when the modulated power supply voltage output from the output node to the functional circuit is stabilized at a target value, the first transient response circuit and the second transient response circuit do not work; when the modulated power supply voltage jumps from low to high, the first transient response circuit is connected with the ground to reduce the modulated power supply voltage; when the modulated power supply voltage jumps from high to low, the second transient response circuit outputs a bias current to a main switch tube control module of the main switch tube to increase the current flowing through the main switch tube of the power supply circuit.

2. The high-voltage premodulation circuit of claim 1, wherein, The first transient response circuit comprises: a first transient control switch tube, the source of which is connected with the input end and the output end of the first transient response circuit; a first voltage division module, the input end of which is connected with the input end of the first transient switch tube, and the output end of which is connected with the gate of the first transient control switch tube; a first capacitor, the first end of which is connected with the gate of the first transient control switch tube, and the second end of which is connected with the ground; a first discharge switch tube, the drain of which is connected with the input end and the output end of the first transient response circuit, the gate of which is connected with the drain of the first transient control switch tube, and the source of which is connected with the ground.

3. The high-voltage premodulation circuit of claim 2, wherein, The first voltage division module comprises: a first loop resistance, the first end of which is connected with the input end of the first voltage division module; a second loop resistance, the first end of which is connected with the second end of the first loop resistance, and the second end of which is connected with the output end of the first voltage division module; The first transient response circuit further comprises: a second discharge switch tube, the drain of which is connected with the second end of the first loop resistance, and the gate of which is connected with the drain of the first transient control switch tube; a first loop bias current source, the input end of which is connected with the source of the second discharge switch tube, and the output end of which is connected with the ground; a third loop resistance, the first end of which is connected with the drain of the first transient control switch tube, and the second end of which is connected with the ground.

4. The high-voltage premodulation circuit of claim 1, wherein, The main switch tube control module comprises: a first control switch tube, the drain of which is connected with the power supply circuit, the source of which is connected with the input end of the main switch tube, and the gate of which is connected with the gate of the main switch tube. A second control switch tube, a source of the second control switch tube is connected with the power supply circuit, a drain of the second control switch tube is connected with an input end of the main switch tube, and a gate of the second control switch tube is connected with a bias current output end of the second transient response circuit; A second voltage division module, an input end of the second voltage division module is connected with the power supply circuit, and an output end of the second voltage division module is connected with a gate of the main switch tube.

5. The high-voltage premodulation circuit of claim 4, wherein, The main switch tube control module further comprises: A main switch tube resistor, a first end of the main switch tube resistor is connected with a gate of the main switch tube; A main switch tube bias current source, an input end of the main switch tube bias current source is connected with a second end of the main switch tube resistor, and an output end of the main switch tube bias current source is grounded.

6. The high-voltage premodulation circuit of claim 4, wherein, The second transient response circuit comprises: A second capacitor, a first end of the second capacitor is connected with a feedback end of the second transient response circuit; A first current mirror switch tube, a source of the first current mirror switch tube is connected with a first input end of the second transient response circuit, and a gate of the first current mirror switch tube is connected with a second end of the second capacitor; A second current mirror switch tube, a source of the second current mirror switch tube is connected with a second input end of the second transient response circuit, a gate of the second current mirror switch tube is connected with the second end of the second capacitor, and the gate of the second current mirror switch tube is connected with a drain of the second current mirror switch tube; The gate of the first current mirror switch tube is connected with the gate of the second current mirror switch tube; A second loop bias current source, an input end of the second loop bias current source is connected with the drain of the second current mirror switch tube, and an output end of the second loop bias current source is grounded; A third current mirror switch tube, a drain of the third current mirror switch tube is connected with a drain of the first current mirror switch tube, a gate of the third current mirror switch tube is connected with the drain of the third current mirror switch tube, and a source of the third current mirror switch tube is grounded; A fourth current mirror switch tube, a gate of the fourth current mirror switch tube is connected with the gate of the third current mirror switch tube, a drain of the fourth current mirror switch tube is connected with a bias output end of the second transient response circuit, and a source of the fourth current mirror switch tube is grounded.

7. The high-voltage premodulator circuit of claim 6, wherein, The second transient response circuit comprises: A third capacitor, a first end of the third capacitor is connected with a feedback end of the second transient response circuit; A third loop bias current source, a first end of the third loop bias current source is connected with a second end of the third capacitor and a bias output end of the second transient response circuit respectively; A current mirror blocking MOS tube, a source of the current mirror blocking MOS tube is connected with a first input end of the second transient response circuit, a gate of the current mirror blocking MOS tube is connected with a drain of the current mirror blocking MOS tube, and the drain of the current mirror blocking MOS tube is connected with a source of the first current mirror switch tube.

8. The high-voltage premodulation circuit of claim 7, wherein, Further comprising a starting circuit, the starting circuit comprises: A starting bias current source, an input end of the starting bias current source is connected with the power supply circuit, and an output end of the starting bias current source is connected with a bias input end of the main switch tube control module; A first start-up resistor, a first end of the first start-up resistor is connected to an output end of the start-up bias current source; A first start-up switch tube, a drain of the first start-up switch tube is connected to a second end of the first start-up resistor, a source of the first start-up switch tube is connected to a bias output end of the second transient response circuit; A first start-up MOS tube, a source of the first start-up MOS tube is connected to the power supply circuit, a gate of the first start-up MOS tube is connected to a drain of the first start-up MOS tube; A second start-up MOS tube, a source of the second start-up MOS tube is connected to a drain of the first start-up MOS tube, a gate of the second start-up MOS tube is connected to a drain of the second start-up MOS tube, a drain of the second start-up MOS tube is connected to a bias input end of the main switch tube control module.

9. The high-voltage premodulator circuit of claim 8, wherein, The start-up circuit further comprises: A start-up current mirror switch tube, a source of the start-up current mirror switch tube is connected to the power supply circuit, a gate of the start-up current mirror switch tube is connected to a gate of the first start-up switch tube, a gate of the start-up current mirror switch tube is connected to a drain of the start-up current mirror switch tube; The high-voltage pre-modulation circuit further comprises: An output MOS tube, a source of the output MOS tube is connected to the output node, a gate of the output MOS tube is connected to a drain of the output MOS tube; A first triode, a collector of the first triode is connected to a drain of the output MOS tube, a base of the first triode is connected to a drain of the output MOS tube; An output resistor, a first end of the output resistor is connected to an emitter of the first triode; A second triode, a collector of the second triode is connected to a second end of the output resistor, a base of the second triode is connected to a collector of the second triode, an emitter of the second triode is grounded; A load resistor, a first end of the load resistor is connected to a drain of the start-up current mirror switch tube; An output control switch tube, a drain of the output control switch tube is connected to a second end of the load resistor, a gate of the output control switch tube is connected to an external start-up signal end; A third triode, a collector of the third triode is connected to a source of the output control switch tube, a base of the third triode is connected to a base of the second triode, an emitter of the third triode is grounded.

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