A server, a baseboard management controller, and a management method of a server

Abstract

The embodiment of the application provides a kind of server, substrate management controller and the management method of server.It is provided that the server includes substrate management controller and multiple server nodes, substrate management controller includes multiple input-output IO interface groups, each IO interface group includes multiple communication interfaces, server node is connected with the communication interface of corresponding IO interface group, and substrate management controller is used to monitor the server node connected with IO interface group.Thereby, the multiple IO interface groups of the embodiment of the application are integrated by substrate management controller, and multiple communication interfaces in each IO interface group are connected with corresponding server node, so that the purpose that one BMC monitors multiple server nodes is realized on the basis that BMC and IO interface group corresponding server node are normally connected and communicated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a server, a baseboard management controller and a management method of a server. BACKGROUND

[0002] Current server architecture is generally composed of multiple processors of the same model and capable of supporting storage (also known as Cache) consistency interconnection, such as 2-way processors, 4-way processors, etc. The multiple processors run the same operating system and share the memory and input / output (IO) resources of the server. With the development of process technology, the performance of a single processor is becoming stronger and stronger, and most applications can be completed in a single processor. Therefore, single-path servers based on single processors have become an important trend in future development.

[0003] The server includes a baseboard management controller (BMC), which is used to monitor the operation of the processor of the server, such as monitoring the temperature, fan speed, power supply condition, operating system state, etc. of the processor. SUMMARY

[0004] The embodiments of the present application provide a server, a baseboard management controller and a management method of a server, which are used to realize that one BMC manages multiple server nodes.

[0005] In a first aspect, the embodiments of the present application provide a server, which includes a baseboard management controller and multiple server nodes, and the baseboard management controller includes multiple input / output (IO) interface groups, each IO interface group includes multiple communication interfaces, the server nodes are connected with the communication interfaces of the corresponding IO interface groups, and the baseboard management controller is used to monitor the server nodes connected with the IO interface groups. Thus, the embodiments of the present application integrate multiple IO interface groups in the baseboard management controller, each IO interface group includes multiple communication interfaces connected with and communicating with the server nodes, and the multiple communication interfaces in each IO interface group are connected with the corresponding server nodes. On the basis that the BMC and the server nodes corresponding to the IO interface groups are normally connected and communicated, one BMC monitors multiple server nodes. Moreover, since the multiple server nodes share one BMC, the cost of the server is reduced.

[0006] In a possible implementation, the plurality of communication interfaces includes a first multiplexed high-speed interface, the baseboard management controller further includes a first processing unit and a plurality of controllers, the first processing unit is connected between the first multiplexed high-speed interface and the plurality of controllers, the server node includes a second multiplexed high-speed interface and a second processing unit, the second multiplexed high-speed interface is connected to the first multiplexed high-speed interface and the second processing unit; the first processing unit is configured to encapsulate low-speed information from the plurality of controllers into high-speed information, and send the high-speed information to the second processing unit through the first multiplexed high-speed interface and the second multiplexed high-speed interface; and the second processing unit is configured to parse the high-speed information into a plurality of low-speed information. In this way, on the basis of implementing that one BMC manages a plurality of server nodes, the number of pins provided by the BMC is reduced, and the low-speed interface is replaced by a high-speed interface to improve transmission efficiency.

[0007] In another possible implementation, a plurality of IO interface groups share the first multiplexed high-speed interface and the first processing unit, the plurality of controllers corresponding to each IO interface group are connected to the first processing unit, and a plurality of server nodes share the second multiplexed high-speed interface and the second processing unit, each server node being connected to the second processing unit. In this way, the number of pins provided by the BMC is further reduced.

[0008] In yet another possible implementation, the first processing unit is configured to encapsulate a plurality of low-speed information sent to a target server node and an identifier of the target server node into high-speed information; and the second processing unit is configured to parse the high-speed information to obtain the plurality of low-speed information and the identifier of the target server node, and send the plurality of low-speed information to information channels corresponding to the target server node according to the identifier of the target server node. In this way, by carrying the identifier of the target server node in the transmitted information, the BMC can accurately control the corresponding server node.

[0009] Optionally, the plurality of communication interfaces includes a high-speed serial computer expansion bus standard (PCIe) interface, an enhanced peripheral management interface (eSPI), a low frame number (LPC) interface, an integrated circuit bus (I2C), an enhanced two-wire serial bus (I3C) interface, a serial peripheral interface (SPI), a universal asynchronous receiver-transmitter (UART) interface, a general-purpose input / output (GPIO) interface, and a platform environment control interface (PECI).

[0010] In a second aspect, the embodiments of the present application provide a baseboard management controller, comprising a plurality of input / output (IO) interface groups, each of the IO interface groups comprising a plurality of communication interfaces, a server node being connected to a communication interface of a corresponding IO interface group, and the baseboard management controller being configured to monitor the server node connected to the IO interface group. The baseboard management controller integrates a plurality of IO interface groups, each of the IO interface groups comprising a plurality of communication interfaces connected to and communicating with a server node, and the plurality of communication interfaces in each of the IO interface groups being connected to a corresponding server node, so that the baseboard management controller can monitor a plurality of server nodes on the basis of normal connection and communication between the baseboard management controller and the server nodes corresponding to the IO interface groups. In addition, since the plurality of server nodes share one baseboard management controller, the cost of the server can be reduced.

[0011] In a possible implementation, the plurality of communication interfaces comprises a first multiplexed high-speed interface for connecting to the corresponding server node, and the baseboard management controller further comprises a first processing unit and a plurality of controllers, the first processing unit being connected between the first multiplexed high-speed interface and the plurality of controllers, and the first processing unit being configured to encapsulate low-speed information from the plurality of controllers into high-speed information and send the high-speed information to the server node via the first multiplexed high-speed interface, the transmission speed of the low-speed information being lower than the transmission speed of the high-speed information.

[0012] Optionally, the baseboard management controller further comprises a plurality of graphic processing units (GPUs), each of the IO interface groups comprises a PCIe interface, the PCIe interface of each of the IO interface groups being connected to a corresponding GPU, and each of the GPUs being configured to acquire image information from the server node connected to the corresponding IO interface group, or each of the GPUs being configured to send image information to the server node connected to the corresponding IO interface group. In this way, the GPU processing of the image information of the plurality of server nodes by the baseboard management controller can be implemented.

[0013] In another possible implementation, the baseboard management controller further comprises a video graphics compression module, an Ethernet interface, a display interface, and a switch circuit; one end of the video graphics compression module is connected to a first end of the switch circuit, the other end of the video graphics compression module is connected to a remote display via the Ethernet interface; a second end of the switch circuit is connected to a local display via the display interface; a third end of the switch circuit is connected to N GPUs; and the switch circuit is configured to acquire processed image information from one of the N GPUs, and send the acquired image information to the video graphics compression module to display on the remote display via the Ethernet interface, or send the acquired image information to the local display via the display interface to display.

[0014] Optionally, one GPU can be connected to the PCIe interface of each of the IO interface groups, so as to implement the image display of the plurality of server nodes by the one GPU.

[0015] In another possible implementation manner, the plurality of communication interfaces include: a Peripheral Component Interconnect Express (PCIe) interface, an enhanced peripheral management interface (eSPI), a low pin count (LPC) interface, an integrated circuit bus (I2C), an enhanced two-wire serial bus (I3C) interface, a serial peripheral interface (SPI), a universal asynchronous receiver-transmitter (UART) interface, a general purpose input / output (GPIO) interface, and a platform environment control interface (PECI).

[0016] In a third aspect, the embodiments of the present application provide a management method of a server, applied to a baseboard management controller. The baseboard management controller includes a plurality of input / output (IO) interface groups, each IO interface group being configured to be connected with a corresponding server node, and each IO interface group including a plurality of communication interfaces connected with the corresponding server node. The target server node is managed through a target IO interface group, where the target IO interface group is any one of the plurality of IO interface groups, and the target server node is the target server node connected with the target IO interface.

[0017] In a possible implementation manner, the plurality of communication interfaces include a first multiplexing high-speed interface, the baseboard management controller further includes a first processing unit and a plurality of controllers, the first processing unit being connected between the first multiplexing high-speed interface and the plurality of controllers, and the server node includes a second multiplexing high-speed interface and a second processing unit, the second multiplexing high-speed interface being connected with the first multiplexing high-speed interface and the second processing unit. The first processing unit encapsulates low-speed information from the plurality of controllers into high-speed information, and sends the high-speed information to the second processing unit through the first multiplexing high-speed interface and the second multiplexing high-speed interface. The second processing unit is configured to parse the high-speed information into a plurality of low-speed information.

[0018] In another possible implementation manner, the baseboard management controller further includes a plurality of image processors, each IO interface group includes a PCIe interface, and the PCIe interface of each IO interface group is connected with a corresponding image processor. Each GPU is configured to acquire image information from the server node connected through the corresponding IO interface group, or each GPU is configured to send image information to the server node connected through the corresponding IO interface group.

[0019] In yet another possible implementation manner, the first processing unit is configured to encapsulate a plurality of low-speed information sent to the target server node and an identifier of the target server node into high-speed information. The second processing unit parses the high-speed information to obtain the plurality of low-speed information and the identifier of the target server node, and sends the plurality of low-speed information to information channels corresponding to the target server node according to the identifier of the target server node.

[0020] In a possible implementation, the baseboard management controller further comprises a video graphics compression module, an Ethernet interface, a display interface, and a switch circuit. One end of the video graphics compression module is connected to a first end of the switch circuit, and the other end of the video graphics compression module is connected to a remote display through the Ethernet interface; a second end of the switch circuit is connected to a local display through the display interface; a third end of the switch circuit is connected to the N GPUs; and the switch circuit is configured to: acquire processed image information from one of the N GPUs; and send the acquired image information to the video graphics compression module, so as to display the image information on the remote display through the Ethernet interface, or send the acquired image information to the local display through the display interface for display. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A schematic diagram of connection between a BMC and a server in a conventional solution;

[0022] Figure 2 A structural schematic diagram of a server provided in an embodiment of the present application;

[0023] Figure 3 A structural schematic diagram of another server provided in an embodiment of the present application;

[0024] Figure 4 A structural schematic diagram of still another server provided in an embodiment of the present application;

[0025] Figure 5 A schematic diagram of TDM multiplexing;

[0026] Figure 6 A schematic diagram of a method for managing multiple server nodes by one BMC provided in an embodiment of the present application;

[0027] Figure 7 A structural schematic diagram of a GPU comprising multiple GPU virtual modules provided in an embodiment of the present application;

[0028] Figure 8 A structural schematic diagram of a BMC integrated with multiple GPUs;

[0029] Figure 9 A schematic diagram after adding a switch circuit. DETAILED DESCRIPTION

[0030] A server is a type of computing device, and a server runs faster and has higher load than an ordinary computer. The server provides computing or application services for other clients (such as PC, smart phone, and other devices) in a network. The server has high processor operation ability, long-time reliable operation, strong external data throughput capacity, and better scalability. The server is divided into rack type, blade type, tower type, and cabinet type according to the appearance.

[0031] Current server architecture is generally composed of multiple same model processors capable of supporting cache coherent interconnect. The multiple processors run the same operating system and share the server's memory and input / output (IO) resources.

[0032] Currently, the server includes a BMC, which is used to monitor the processor operating conditions of the server, such as temperature, fan speed, power supply condition, operating system state, etc. The BMC can also perform operations such as firmware upgrade on the processor of the server in an unpowered state, and can record critical logs when the processor of the server crashes.

[0033] Referring to Figure 1 The figure is a schematic diagram of the structure of a server in a related scheme.

[0034] Figure 1 (a) in the figure shows a BMC connected to the main processor of the server through various communication interfaces. The BMC can manage other slave CPUs in the server through the main central processing unit (CPU).

[0035] Figure 1 (b) in the figure shows a BMC connected to the south bridge of the server through various communication interfaces. The BMC manages components such as the main CPU and other slave CPUs of the server through the south bridge.

[0036] Figure 1The various types of communication interfaces shown in the middle include at least one of the following communication interfaces: a Peripheral Component Interconnect Express (PCIe) interface, an Enhanced Serial Peripheral Interface (eSPI) and a Low Pin Count (LPC) interface, an Inter-Integrated Circuit (I2C) interface / Improved Inter-Integrated Circuit (I3C) interface, a serial peripheral interface (SPI), a Universal Asynchronous Receiver-Transmitter (UART) interface, a General-Purpose Input, Output (GPIO) interface, a System Management Bus (SMBus) interface, or a Platform Environment Control Interface (PECI).

[0037] Among the above communication interfaces, the PCIe interface can connect a graphics processing unit (GPU) and a processor. The eSPI / LPC interface is used for communication between the BMC and the BIOS. The PECI is used as a communication channel for obtaining processor temperature, internal management information, debugging and diagnostic information, etc. The I3C / I2C interface is used as a communication channel for obtaining processor temperature, internal management information, debugging and diagnostic information, etc. The SPI is used to trigger a processor BIOS loading upgrade channel. The UART interface is used as a channel for obtaining log information of various components. The GPIO interface is used to obtain exception information of the processor and respond in a timely manner. The SMBus interface is used for system management and power management control bus.

[0038] Currently, a BMC can only monitor the operation of a processor in a server. However, with the development of process technology, the number of cores supported by a single processor is increasing, and the performance is becoming stronger. Most applications can be completed in a single processor, and single-path servers have become a future development trend. Therefore, using a BMC to monitor the processors of multiple single-path servers can reduce the number of BMCs and save costs when multiple single-path servers are integrated.

[0039] In view of the above problems, the embodiment of the present application provides a server, the server comprising a baseboard management controller and a plurality of server nodes, the baseboard management controller comprising a plurality of IO interface groups, each IO interface group comprising a plurality of communication interfaces connected and communicating with the server nodes, and the plurality of communication interfaces in each IO interface group being connected to the plurality of communication interfaces of the corresponding server nodes, so that the baseboard management controller (BMC) can monitor a plurality of server nodes on the basis of normal connection and communication between the baseboard management controller and the server nodes corresponding to the IO interface groups. The server provided by the embodiment of the present application is described in detail below in combination with the drawings.

[0040] In order to better illustrate the server provided by the embodiment of the present application, the following describes an example in which one BMC is connected to two server nodes through two IO interface groups. However, the BMC can have three, four, five or more IO interface groups, and each IO interface group can be connected to one server node.

[0041] Referring to Figure 2 The figure is a structural schematic diagram of a server provided by the embodiment of the present application. The server comprises one BMC and a plurality of server nodes.

[0042] Among them, one server node refers to a device comprising a processor, for example, a single-path server. In addition, the server node comprises, in addition to the processor, a south bridge, a complex programmable logic device (CPLD) or a power supply module (PSU) in the same device as the processor.

[0043] In the embodiment of the present application, the BMC comprises two IO interface groups, and the two IO interface groups are connected to two server nodes. Specifically, the IO interface group 1 is connected to the server node 1, and the IO interface group 2 is connected to the server node 2.

[0044] The embodiment of the present application does not specifically limit the object of the IO interface group connected to the server node. For example, the IO interface group can be connected to the CPU of the server node, the south bridge of the server node, the CPLD of the server node, or the PSU of the server node. In addition, the IO interface group can also be connected to at least two of the CPU, the south bridge, the CPLD and the PSU of the server node.

[0045] The number of interfaces in each IO interface group is not specifically limited in the embodiments of the present application. Each IO interface group includes multiple communication interfaces, for example, the multiple communication interfaces can include at least one of a PCIe interface, an eSPI, an LPC interface, a PECI, an I3C / I2C interface, an SPI, an SMBus interface, a UART interface, and a GPIO interface. The number of each communication interface can be one or multiple. If each IO interface group includes the above content, it can be ensured that the BMC can communicate and connect with the corresponding server node through each IO interface group. Figure 2 The content shows that each IO interface group includes all communication interfaces of a PCIe interface, an eSPI, an LPC interface, a PECI, an I3C / I2C interface, an SPI, an SMBus interface, a UART interface, and a GPIO interface. Each communication interface is connected to the corresponding communication interface on the server node, for example, the GPIO interface of the IO interface group is connected to the GPIO interface of the server node, the PCIe interface of the IO interface group is connected to the PCIe interface of the server node, and so on.

[0046] Among them, the GPIO interface and the UART interface in the server node are connected to the CPLD of the server node, the SMBUS interface is connected to the PSU, and the other interfaces (such as the PCIe interface, the I3C / I2C interface, the PECI, and the eSPI) are connected to the processor or the south bridge.

[0047] In the BMC, the interface corresponding to each IO interface group is connected to the corresponding controller, for example, the GPIO interface of the IO interface group 1 is connected to the corresponding GPIO controller, the I2C / I3C interface of the IO interface group 1 is connected to the corresponding I2C / I3C controller, and so on. The specific connection mode is shown in Figure 2 The controller corresponding to all communication interfaces is connected to the processor of the BMC, and the PCIe controller is connected to the GPU of the BMC in addition to the processor. The processor of the BMC is used to interact with the corresponding server node through the controller of the corresponding communication interface. The GPU also interacts with the corresponding server node through the PCIe controller.

[0048] In the embodiments of the present application, the BMC monitors the server node connected with the IO interface group. Specifically, the BMC monitors the server node connected with the IO interface group, including monitoring the state of the server node, including temperature, voltage, fan, and power supply, resetting the server node through reset and power-on reset, recording abnormal running data or abnormal logs, and the like.

[0049] The embodiments of the present application do not specifically limit the way in which the BMC monitors the server node connected with the IO interface group.

[0050] In an example, the plurality of server nodes can be monitored in a polling manner.

[0051] For example, the BMC monitors the server node 1 through the IO interface group 1 at T1. The BMC monitors the server node 2 through the IO interface group 2 at T2. The BMC monitors the server node 1 at T3 and monitors the server node 2 at T4, and so on.

[0052] The T1, T2, T3, T4 and the like are used to represent a plurality of adjacent time points. The time interval between adjacent time points in T1, T2, T3, T4 can be the same or different, which is not limited in the present application.

[0053] In another example, the BMC can monitor the plurality of server nodes by manually controlling the switching interface. Compared with the polling manner, this manner has better user experience.

[0054] For example, the web interface corresponding to the BMC includes a switching interface. The switching interface is provided with a switching button. The user can trigger the switching button to monitor the plurality of server nodes. The triggering manner can be single click, double click, voice control and the like, which is not limited in the present application.

[0055] Alternatively, the switching interface includes a server node list corresponding to the plurality of server nodes. The user directly triggers the server node in the server node list to monitor the triggered server node.

[0056] In addition, the switching interface can also display input information. The user can input the address of the specified server node on the switching interface, and the BMC controls the specified server node. For example, the user inputs the MAC address corresponding to the server node 1 on the switching interface. The BMC can manage the server node 1 according to the MAC address corresponding to the server node 1.

[0057] In this way, the embodiments of the present application integrate a plurality of IO interface groups through the BMC. Each IO interface group includes a plurality of communication interfaces connected and communicated with the server node. The plurality of communication interfaces in each IO interface group are connected to the plurality of communication interfaces of the corresponding server node, which realizes the purpose that one BMC can manage a plurality of server nodes on the basis of normal connection and communication between the BMC and the server node corresponding to the IO interface group.

[0058] In addition, considering that the plurality of IO interface groups are integrated through the BMC, the plurality of IO interface groups can be integrated through the BMC in the following manners. Figure 2The communication interface of the IO interface group of the illustrated BMC is directly connected with the server node, and the BMC needs to provide a large number of pins to support various types and quantities of interfaces. Too many pins will cause the corresponding device of the BMC, such as the BMC chip, to increase in size, thereby affecting the cost of the BMC chip. Moreover, if the BMC is an independent plug-in card or a card, each server node requires a group of IO interfaces to be connected with the BMC, which will cause too many signals between the BMC and the N server nodes, and it is difficult to implement in engineering.

[0059] Based on this, the embodiment of the present application also provides a scheme, which multiplexes a plurality of low-speed interfaces into one high-speed serial interface on the basis of the above scheme, in other words, replaces a plurality of low-speed interfaces with one high-speed serial interface, thereby reducing the number of pins provided by the BMC.

[0060] The communication interface of the IO interface group connected with the server node includes a low-speed interface and a high-speed interface. The information transmission speed of the low-speed interface is lower than a preset speed threshold, and the information transmission speed of the high-speed interface is greater than the preset speed threshold. For example, among the various communication interfaces connected with the server node in the above IO interface group, the low-speed interface is an I2C / I3C interface, a UART interface, a GPIO interface, and an SMBUS interface. The high-speed interface is a PCIe, eSPI, LPC interface, PECI, etc. The embodiment of the present application replaces a plurality of low-speed interfaces with one high-speed interface.

[0061] The embodiment of the present application does not specifically limit the size of the preset speed threshold. For example, the preset speed threshold can be 50 Mbps, 200 Kbps, 100 Kbps, etc.

[0062] The embodiment of the present application does not specifically limit the use specification of the high-speed interface. For example, the use specification can be a Low Voltage Differential Signaling (LVDS) channel protocol, or an LTPI protocol, etc.

[0063] The following will take an example of multiplexing the low-speed interfaces including I2C, I3C, UART, GPIO, and SMBUS into one high-speed interface to illustrate the multiplexing mode. Other embodiments can also involve other custom low-speed interfaces, which can be multiplexed into one high-speed interface together with existing low-speed interfaces. Here, no longer discussed.

[0064] Referring to Figure 3 , the figure is another structural schematic diagram of a server provided by the embodiment of the present application.

[0065] In the embodiment of the present application, the plurality of communication interfaces of each IO interface group in the BMC includes a first multiplexed high-speed interface, and the first multiplexed high-speed interface is used to multiplex Figure 2The plurality of low-speed interfaces are, for example, I2C / I3C interfaces, UART interfaces, GPIO interfaces, and SMBUS interfaces. Specifically, the BMC further comprises a plurality of controllers, for example, I2C / I3C controllers, UART controllers, GPIO controllers, and SMBUS controllers, and a first processing unit connected between the first multiplexed high-speed interface and the plurality of controllers, the plurality of controllers interacting with the first processing unit, and the first processing unit being connected with the server node through the first multiplexed high-speed interface.

[0066] In the embodiments of the present application, each IO interface group corresponds to a first processing unit, and the IO interface group is connected with the corresponding first processing unit, for example, the IO interface group 1 is connected with one first processing unit, and the IO interface group 2 is connected with another first processing unit.

[0067] In an example, the I2C / I3C controller, the UART controller, the GPIO controller, and the SMBUS controller respectively send the sent I2C / I3C information, UART information, GPIO information, and SMBUS information to the first processing unit. The first processing unit encapsulates the I2C / I3C information, UART information, GPIO information, and SMBUS information into first high-speed serial information (high-speed information) according to a preset rule, and sends the first high-speed serial information to the corresponding server node through the first multiplexed high-speed interface of the IO interface group and the first multiplexed high-speed interface of the corresponding server node. Wherein, the first high-speed serial information is used to represent the high-speed serial information sent by the first processing unit of the BMC.

[0068] For example, the first processing unit corresponding to the IO interface group 1 acquires the low-speed information sent by the corresponding plurality of controllers, for example, I2C / I3C information sent by the I2C / I3C controller, UART information sent by the UART controller, GPIO information sent by the GPIO controller, and SMBUS information sent by the SMBUS controller. Then, the first processing unit encapsulates the plurality of low-speed information into first high-speed serial information according to a preset rule, and sends the first high-speed serial information to the server node 1 through the first multiplexed high-speed interface of the IO interface group 1.

[0069] In another example, the first multiplexed high-speed interface of the IO interface group receives second high-speed serial information from the corresponding server node. The first processing unit corresponding to the IO interface group parses the second high-speed serial information to obtain multiple low-speed information according to a preset rule, for example, I2C / I3C information, UART information, GPIO information and SMBUS information. Then, the first processing unit sends the multiple low-speed information to the corresponding controller, and sends the multiple low-speed information to the processor or GPU through the controller. Wherein, the second high-speed serial information is used to represent the high-speed serial information received by the first processing unit of the BMC.

[0070] For example, the first multiplexed high-speed interface corresponding to the IO interface group 1 receives second high-speed serial information from the server node 1 and sends the second high-speed serial information to the corresponding first processing unit. The first processing unit parses the second high-speed serial information based on a preset rule to obtain I2C / I3C information, UART information, GPIO information and SMBUS information. Then the first processing unit sends the parsed I2C / I3C information to the corresponding I2C / I3C controller, sends the UART information to the corresponding UART controller, sends the GPIO information to the corresponding GPIO controller, and sends the SMBUS information to the corresponding SMBUS controller.

[0071] The preset rule is not specifically limited in the embodiments of the present application. For example, the preset rule can be a time division multiplexing rule, or the preset rule can be to encapsulate the I2C / I3C information, UART information, GPIO information and SMBUS information in a fixed order, for example, the encapsulated high-speed serial information is {I2C / I3C information, UART information, GPIO information, SMBUS information}.

[0072] It should be noted that the server node corresponding to the IO interface group includes a second multiplexed high-speed interface, a second processing unit and a plurality of information transmission channels, and the second processing unit is connected between the second multiplexed high-speed interface and the plurality of information transmission channels. The second multiplexed high-speed interface is used for communication with the first multiplexed high-speed interface of the IO interface group. The second multiplexed high-speed interface is used to multiplex Figure 2 the low-speed information sent by the plurality of low-speed interfaces of the server node. The plurality of low-speed interfaces are, for example, I2C / I3C interface, UART interface, GPIO interface and SMBUS interface. The plurality of information transmission channels include I2C / I3C information transmission channel, UART information transmission channel, GPIO information transmission channel and SMBUS information transmission channel.

[0073] For example, the IO interface group 1 communicates with the second multiplexed high-speed interface of the server node 1 through the first multiplexed high-speed interface.

[0074] The server node also includes a second processing unit connected to the second multiplexed high-speed interface. To accurately realize information transmission between the BMC and the server node, avoid transmission errors and omissions, etc. The second processing unit adopts the same preset rules as the first processing unit, but performs operations opposite to the first processing unit.

[0075] Example 1: The I2C / I3C controller, UART controller, GPIO controller, and SMBUS controller in IO interface group 2 transmit I2C / I3C information, UART information, GPIO information, and SMBUS information to the first processing unit. The first processing unit corresponding to IO interface group 2 encapsulates the I2C / I3C information, UART information, GPIO information, and SMBUS information into first high-speed serial information, such as {I2C / I3C information, UART information, GPIO information, SMBUS information}, according to the time division multiplexing mode. The BMC sends the first high-speed serial information to the second processing unit corresponding to the server node 2 through the first multiplexed high-speed interface in IO interface group 2.

[0076] The second processing unit analyzes the first high-speed serial information {I2C / I3C information, UART information, GPIO information, SMBUS information} according to the same time division multiplexing mode as the first processing unit, and obtains I2C / I3C information, UART information, GPIO information, and SMBUS information. The second processing unit sends the I2C / I3C information, UART information, GPIO information, and SMBUS information to the information transmission channels of I2C / I3C, UART, GPIO, and SMBUS in the server node 2, respectively.

[0077] Among them, the I2C / I3C information transmission channel, also known as the I2C / I3C channel, is an I2C / I3C channel connected between the second processing unit and the CPU / south bridge of the server node 2. The UART information transmission channel, also known as the URAT channel, is a URAT channel connected between the second processing unit and the CPLD of the server node 2. The GPIO information transmission channel, also known as the GPIO channel, is a GPIO channel connected between the second processing unit and the CPLD of the server node 2. The SMBUS information transmission channel, also known as the SMBUS channel, is an SMBUS channel connected between the second processing unit and the PSU of the server node 2.

[0078] Exemplary 2: the corresponding devices in the server node 2 respectively transmit I2C / I3C information, UART information, GPIO information, and SMBUS information to the second processing unit through I2C / I3C channels, UART channels, GPIO channels, and SMBUS channels. The second processing unit in the server node 2 encapsulates the I2C / I3C information, the UART information, the GPIO information, and the SMBUS information into second high-speed serial information {I2C / I3C information, UART information, GPIO information, SMBUS information} according to time division multiplexing. The second processing unit sends the second high-speed serial information to the first multiplexing high-speed interface of the IO interface group 2 in the server node 2 through the second multiplexing high-speed interface, and sends the second high-speed serial information to the first processing unit corresponding to the IO interface group 2 through the first multiplexing high-speed interface.

[0079] The first processing unit analyzes the second high-speed serial information {I2C / I3C information, UART information, GPIO information, SMBUS information} according to the same multiplexing and demultiplexing manner as the second processing unit, and obtains the I2C / I3C information, the UART information, the GPIO information, and the SMBUS information. The I2C / I3C information, the UART information, the GPIO information, and the SMBUS information are sent to the I2C / I3C controller, the UART controller, the GPIO controller, and the SMBUS controller corresponding to the IO interface group 2.

[0080] Figure 3 It is also shown that a plurality of non-multiplexing high-speed serial interfaces are connected to a plurality of non-multiplexing high-speed serial interfaces of the server node. The non-multiplexing high-speed serial interface refers to a communication interface that is not multiplexed with other low-speed interfaces, but the information transmission speed is greater than a preset transmission threshold, for example, a PCIe interface, an eSPI interface, and a PECI.

[0081] Therefore, compared with the BMC pin number shown in Figure 2 , Figure 3 , the number of BMC pins is reduced, that is, multiplexing a plurality of low-speed interfaces into one high-speed serial interface can reduce the number of pins provided by the BMC.

[0082] The embodiments of the present application do not specifically limit the form of the first processing unit. For example, the first processing unit can be a CPLD or an FPGA. The embodiments of the present application do not specifically limit the form of the second processing unit. For example, the second processing unit can be a CPLD or an FPGA.

[0083] The embodiments of the present application multiplex a plurality of low-speed interfaces through one high-speed serial interface, which can reduce the number of pins required by the BMC connector, thereby helping to reduce the cost of the BMC chip. Moreover, it helps to reduce the number of signals provided by the connector of the independent BMC plug-in card or BMC draw-in card, and reduces the engineering implementation difficulty.

[0084] In addition, the first multiplexed high-speed interface and the first processing unit can be shared by a plurality of IO interface groups in the BMC, a plurality of controllers corresponding to each of the IO interface groups are connected with the first processing unit, and the second multiplexed high-speed interface and the second processing unit are shared by a plurality of server nodes, and each server node is connected with the second processing unit, so as to further reduce the number of pins required to be provided by the BMC chip.

[0085] Referring to Figure 4 The figure is a structural schematic diagram of another server provided by the embodiment of the application. The BMC can only monitor one server node at each moment.

[0086] In the embodiment of the application, a plurality of IO interface groups in the BMC use the same first multiplexed high-speed interface. For example, the IO interface group 1 and the IO interface group 2 share the same first multiplexed high-speed interface, the IO interface group 1 is connected with the server node 1 through the first multiplexed high-speed interface, and the IO interface group 2 is connected with the server node 2 through the first multiplexed high-speed interface.

[0087] In the embodiment of the application, the BMC includes a first processing unit for being connected with the first multiplexed high-speed interface. The first processing unit is connected with a low-speed interface controller corresponding to each IO interface group. For example, the I2C / I3C controller, the UART controller, the GPIO controller and the SMBUS controller corresponding to the IO interface group 1 are connected with the first processing unit, and the I2C / I3C controller, the UART controller, the GPIO controller and the SMBUS controller corresponding to the IO interface group 2 are connected with the first processing unit.

[0088] In an example, the first processing unit obtains high-speed serial receiving information from the first multiplexed high-speed interface of the IO interface group, parses the high-speed serial receiving information, obtains a plurality of low-speed information, and sends the low-speed information to the processor through the low-speed interface controller.

[0089] In another example, the first processing unit obtains low-speed information from the low-speed interface controller corresponding to the IO interface group, encapsulates the low-speed information based on a preset rule to obtain high-speed serial sending information, and sends the high-speed serial sending information through the first multiplexed high-speed interface.

[0090] For example, the first processing unit obtains I2C / I3C information, UART information, GPIO information and SMBUS information from the I2C / I3C controller, the UART controller, the GPIO controller and the SMBUS controller corresponding to the IO interface group 1. The first processing unit encapsulates the I2C / I3C information, the UART information, the GPIO information and the SMBUS information based on a preset rule to obtain first high-speed serial information, and sends the first high-speed serial information through the first multiplexed high-speed interface.

[0091] In the embodiment of the present application, all server nodes connected with the BMC share a second processing unit and a second multiplexed high-speed interface. For example, server node 1 shares a second processing unit and a second multiplexed high-speed interface with server node 2. On the server node side, the second processing unit is connected with the second multiplexed high-speed interface. The second processing unit is used to obtain first high-speed serial information from the second multiplexed high-speed interface, and parse the first high-speed serial information based on a preset rule to obtain a plurality of low-speed information, and send the plurality of low-speed information to the server node.

[0092] The second multiplexed high-speed interface on the server node side is connected with the first high-speed serial interface of the IO interface group set, so as to realize that one BMC monitors the operation of a plurality of server nodes. For example, one BMC monitors server node 1 and server node 2.

[0093] Since the plurality of IO interface groups on the BMC side share a first multiplexed high-speed interface, and the plurality of server nodes on the server node side share a second multiplexed high-speed interface, when the first multiplexed high-speed interface on the BMC side communicates with the second multiplexed high-speed interface on the server node side, the BMC needs to know which IO interface group the received information belongs to, and on the server node side, it needs to know which server node the received information belongs to.

[0094] In an example, the high-speed serial information exchanged between the BMC and the server node carries an identifier of the corresponding server node. The first processing unit or the second processing unit processes according to the carried server node identifier. For example, the first processing unit is used to encapsulate a plurality of low-speed information sent to a target server node and an identifier of the target server node into high-speed information; the second processing unit parses the high-speed information to obtain the plurality of low-speed information and the identifier of the target server node, and sends the plurality of low-speed information to the information channel corresponding to the target server node according to the identifier of the target server node.

[0095] Exemplary illustration: If the second processing unit obtains I2C / I3C information, UART information, GPIO information and SMBUS information from the I2C / I3C, UART, GPIO and SMBUS low-speed channels corresponding to server node 1. Among them, the I2C / I3C information, UART information, GPIO information and SMBUS information carry the identifier of server node 1, for example, carry the identifier "Service 1", indicating that the information comes from server node 1. It can also be other identifiers indicating server node 1, and the embodiment of the present application is not specifically limited.

[0096] The second processing unit encapsulates the low-speed information according to a preset rule to obtain second high-speed serial information carrying a server node identifier. The second processing unit sends the second high-speed serial information to the first multiplexing high-speed interface on the BMC side through the second multiplexing high-speed interface, and then sends the second high-speed serial information to the first processing unit. The first processing unit parses the second high-speed serial information carrying the server node identifier to obtain low-speed information carrying the server node identifier, and sends the low-speed information to the low-speed interface controller connected to the IO interface group corresponding to the server node. For example, the first processing unit sends the parsed low-speed information carrying the identifier of server node 1 to the low-speed interface controller corresponding to the IO interface group 1.

[0097] For example, the first processing unit obtains various low-speed information from the low-speed interface controller corresponding to the IO interface group 1 in the BMC, such as I2C / I3C information from the I2C / I3C controller and UART information from the UART controller. The low-speed information carries the identifier of server node 1 corresponding to the IO interface group 1. The first processing unit encapsulates the information carrying the identifier of server node 1 based on a preset rule to obtain first high-speed serial information carrying the identifier of server node 1, and sends the first high-speed serial information carrying the identifier of server node 1 to the second multiplexing high-speed interface of server node 1 through the first multiplexing high-speed interface and the second processing unit. The second processing unit sends the parsed low-speed information to server node 1 according to the identifier of server node 1.

[0098] In another example, the BMC can specify the server node that is working in a polling manner or a specified manner. In this case, the BMC needs to store the correspondence between the server node and the IO interface group in advance, and needs to store the correspondence between the IO interface group and the low-speed interface controller. For example, the specified server node is server node 1, server node 1 corresponds to IO interface group 1, and IO interface group 1 corresponds to a group of low-speed interface controllers. The first processing unit or the second processing unit sends the received information to the low-speed interface controller corresponding to the IO interface group corresponding to the specified server node, or to the specified server node.

[0099] In summary, the plurality of IO interface groups share the same high-speed serial interface and processing unit, which helps to further reduce the number of pins of the BMC connector.

[0100] The following takes a preset rule as an example of time division multiplexing rule (TDM) for illustration. TDM takes channel transmission time as the division object, and realizes multiplexing by allocating non-overlapping time segments to multiple channels.

[0101] Referring to Figure 5Fig. 2 is a schematic diagram of a TDM multiplexing. Figure 5 The information frames transmitted in adjacent time periods are illustrated by taking Frame T0 and Frame T-1 as examples. Frame T0 is high-speed serial information in the T0 period, and Frame T-1 is high-speed serial information in the T-1 period. -1 period. T -1 , T0 is adjacent time periods, and in each time period, one low-speed information transmission is completed to the first processing unit or to the second processing unit.

[0102] First, the implementation of information transmission from the BMC to the server node is introduced.

[0103] The BMC sends M low-speed information to the first processing unit through the corresponding low-speed interface controller, the first processing unit converts the M low-speed information into first high-speed serial information, and sends the first high-speed serial information to the second processing unit through the high-speed serial bus. The second processing unit parses the first high-speed serial information to obtain M low-speed information, and sends the M low-speed information to the corresponding low-speed interface channel. The low-speed interface channel is used to transmit low-speed information, such as a GPIO channel, an I2C / I3C channel, a UART channel, and an SMBUS channel.

[0104] Figure 5 Frame T0 and Frame T-1 are first high-speed serial information {GPIO information, I2C / I3C information, UART information, and SMBUS information}. That is, the BMC sends the GPIO information, the I2C / I3C information, the UART information, and the SMBUS information to the first processing unit through the GPIO channel controlled by the GPIO controller, the I2C / I3C channel controlled by the I2C / I3C controller, the UART channel controlled by the UART controller, and the SMBUS channel controlled by the SMBUS controller, respectively. The first processing unit encapsulates the GPIO information, the I2C / I3C information, the UART information, and the SMBUS information into high-speed serial transmission information {GPIO information, I2C / I3C information, UART information, and SMBUS information}, and the first processing unit communicates with the first multiplexing high-speed interface of the server node through the first multiplexing high-speed interface.

[0105] The second processing unit of the server node receives the high-speed serial transmission information {GPIO information, I2C / I3C information, UART information, SMBUS information} through the second multiplex high-speed interface of the server node, parses based on a preset rule, obtains low-speed information GPIO information, I2C / I3C information, UART information, and SMBUS information, and sends the GPIO information, I2C / I3C information, UART information, and SMBUS information to the GPIO channel, I2C / I3C channel, UART channel, and SMBUS channel respectively.

[0106] Figure 5 It is also shown that Frame T-1 is first sent to the server node, and then Frame T0 is sent to the server node.

[0107] (see Figure 5 the upper half of the figure).

[0108] The implementation of transmitting information from the server node to the BMC is introduced below.

[0109] The server node sends M low-speed information to the second processing unit through the corresponding communication interface channel, the second processing unit encapsulates the M low-speed information into second high-speed serial information based on a preset rule, and sends the high-speed serial reception information to the first processing unit of the BMC through the high-speed serial bus. The first processing unit of the BMC parses the high-speed serial information based on a preset rule, obtains M low-speed information, and transmits the M low-speed information according to the corresponding communication interface channel.

[0110] Figure 5 It is shown that Frame T0 and Frame T-1 are second high-speed serial information {GPIO information, I2C / I3C information, UART information, SMBUS information}. That is, the server node sends the GPIO information, I2C / I3C information, UART information, and SMBUS information to the second processing unit through the GPIO channel, I2C / I3C channel, UART channel, and SMBUS channel respectively, the second processing unit encapsulates the GPIO information, I2C / I3C information, UART information, and SMBUS information into second high-speed serial information {GPIO information, I2C / I3C information, UART information, SMBUS information}, and the second processing unit communicates the second high-speed serial information {GPIO information, I2C / I3C information, UART information, SMBUS information} with the first multiplex high-speed interface of the IO interface group through the second multiplex high-speed interface.

[0111] The first processing unit corresponding to the IO interface group receives the second high-speed serial information {GPIO information, I2C / I3C information, UART information, and SMBUS information}, and analyzes based on a preset rule to obtain low-speed information GPIO information, I2C / I3C information, UART information, and SMBUS information. The GPIO information, I2C / I3C information, UART information, and SMBUS information are respectively sent to the GPIO channel controlled by the GPIO controller, the I2C / I3C channel controlled by the I2C / I3C controller, the UART channel controlled by the UART controller, and the SMBUS channel controlled by the SMBUS controller.

[0112] Figure 5 It is also shown that Frame T-1 is first sent to the IO interface group, and then Frame T-1 is sent to the IO interface group.

[0113] (see Figure 5 the lower half of the figure).

[0114] The following will take an image display as an example to introduce in detail the implementation manner of 1 BMC monitoring multiple server nodes.

[0115] Referring to Figure 6 , the figure is a schematic diagram of a method for BMC managing multiple server nodes provided by an embodiment of the present application.

[0116] The IO interface group 1, the IO interface group 2, …, and the IO interface group N in the BMC are connected to a GPU. Specifically, the PCIe interface of the IO interface group 1 is connected to the GPU through a PCIe controller, the PCIe interface of the IO interface group 2 is connected to the GPU through a PCIe controller, …, and the PCIe interface of the IO interface group N is connected to the GPU through a PCIe controller. In addition, the PCIe interface of the IO interface group is also connected to a processor through a PCIe controller. Wherein N is an integer greater than or equal to 2.

[0117] The CPU on the server node side sends configuration information to the CPU through the PCIe interface of the IO interface group, the CPU sends the configuration information to the GPU, and the GPU is configured according to the configuration information. GPU configuration includes loading a kernel mode driver and initializing the GPU, etc., so that the GPU works normally.

[0118] After the GPU is configured, the CPU on the server node side sends the image display information to the GPU first, the GPU processes the image information after obtaining the image display information, and sends the obtained display data to the local display for local display through a display interface after the processing is completed, or the GPU completes the preprocessing and encoding process of the video encoding process through a video coding engine (VCE), encodes the data, and sends the encoded data to the remote display for remote display through an Ethernet interface.

[0119] In the embodiments of the present application, the VCE can be a chip responsible for encoding operation or a special hardware circuit integrated in the BMC. Compared with software encoding or GPU encoding, the VCE can improve the processing speed and greatly reduce the power consumption caused by the GPU processing process.

[0120] It should be understood that the configuration process of the GPU needs a certain time, and if the configuration time of the GPU is greater than the switching time of the server node and the time for sending the image display information to the GPU, the GPU will not be configured when receiving the image information sent by other server nodes. For example, when the server node 1 is switched to the server node 2, the server node 2 sends the image display information 2 to the GPU, and at this time, the GPU has not been configured. At this time, the image display information 2 is processed using the parameters of the GPU which has not been configured, which will cause the image display information 2 to be processed incorrectly or the display data to be lost.

[0121] In view of the above problems, the embodiments of the present application provide two processing methods to avoid the problem of data loss caused by one GPU managing the graphic information sent by multiple servers.

[0122] Referring to Figure 7 , the figure is a structural schematic diagram of a GPU including multiple GPU virtual modules.

[0123] Among them, one GPU includes multiple GPU virtual modules, and each GPU virtual module corresponds to a PCIe interface of an IO interface group. That is, the GPU virtual machine module 1 is connected to the PCIe interface of the IO interface group 1, the GPU virtual machine module 2 is connected to the PCIe interface of the IO interface group 2, …, and the GPU virtual module N is connected to the PCIe interface of the IO interface group N.

[0124] The CPU of the server node 1 can configure the GPU virtual module 1 through the IO interface group 1, the GPU virtual module 1 can obtain image display information from the CPU in the server node 1 through the PCIe interface in the IO interface group 1 for processing, obtain display data and send to the local display for local display, or send to the remote display through the video coding engine (VCE) and the Ethernet interface for remote display.

[0125] The CPU of the server node 2 can configure the GPU virtual module 2 through the IO interface group 2, the GPU virtual module 2 can obtain image display information from the CPU in the server node 2 through the PCIe interface in the IO interface group 2 for processing, obtain display data and send to the local display for local display, or send to the remote display through the video coding engine (VCE) and the Ethernet interface for remote display.

[0126] By analogy, one BMC manages N server nodes for image display.

[0127] The embodiment of the application can avoid data loss and other problems by virtually outputting multiple GPU virtual modules from the GPU, each of which controls a server node.

[0128] Referring to Figure 8 , the figure is a structural schematic diagram of a BMC integrated with multiple GPUs.

[0129] When the server node is N, the BMC includes N GPUs. Specifically, GPU1 is connected to server node 1 through the PCIe interface of IO interface group 1, GPU2 is connected to server node 2 through the PCIe interface of IO interface group 2, …, GPUN is connected to server node N through the PCIe interface of IO interface group N. One VCE is connected to N GPUs respectively.

[0130] The CPU of the server node 1 can configure the GPU1 through the IO interface group 1, the GPU1 can obtain image display information from the CPU in the server node 1 through the PCIe interface in the IO interface group 1 for processing, obtain display data and send to the local display for local display, or send to the remote display through the video coding engine (VCE) and the Ethernet interface for remote display.

[0131] The CPU of the server node 2 can configure the GPU 2 through the IO interface group 2, the GPU 2 can obtain image display information from the CPU in the server node 2 through the PCIe interface in the IO interface group 2 for processing, obtain display data and send to the local display for local display, or send to the remote display through the video coding engine (VCE) and the Ethernet interface for remote display.

[0132] By analogy, one BMC manages the image display of N server nodes.

[0133] In addition, considering that one BMC manages multiple server nodes, the following problems exist: the implementation of VCE and the like is relatively complex, and if multiple GPU graphics information processing is simultaneously supported, a large space will be occupied. Moreover, the BMC card or BMC card currently only supports single. The present embodiment increases a switch switching circuit between multiple GPUs and VCE or a display interface module. The switch switching circuit is used to realize that only one server node corresponding CPU and VCE of the BMC exchange information at one time.

[0134] Referring to Figure 9 , this diagram is a schematic diagram after adding a switch switching circuit. Figure 8

[0135] The first end of the switch switching circuit is connected with the VCE, the third end is connected with the N GPUs, and the second end is connected with the display interface.

[0136] The switch switching circuit realizes the communication between two ends, for example, the communication between the GPUi and the VCE, or the communication between the GPUi and the display interface. Wherein, 1 < i < N, and i is an integer.

[0137] In one example, the third end of the switch switching circuit is connected with the GPU1, GPU2, …, GPUN, GPU1, … in turn based on a polling mode. In this way, only one GPU is connected with the VCE at one time, so that the CPU corresponding to one server node and the VCE of the BMC exchange information at one time.

[0138] In another example, the switch switching circuit is always connected with a certain fixed GPU.

[0139] ​The switching mode of the third end of the switch switching circuit is not specifically limited in the application. For example, the switch switching circuit can switch the connected server nodes in turn through a preset polling mode. The switch switching circuit can also be switched to a specified server node and then no longer be switched through a specified server mode. In addition, a switching interface can be designed on the BMC Web interface, a switching button can be designed on the BMC card, and the like, which are used to switch the server nodes interacting with the BMC.

[0140] The above is only a preferred embodiment of the application, and does not limit the application in any form. Although the application has been disclosed as above with a preferred embodiment, it is not intended to limit the application. Any person skilled in the art can make many possible changes and modifications to the application or modify equivalent embodiments without departing from the scope of the application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the application, without departing from the content of the application, are still within the scope of protection of the application.

Claims

1. A server, characterized in that, The system includes a baseboard management controller and multiple server nodes. The baseboard management controller includes multiple input / output (I / O) interface groups, and each I / O interface group includes multiple communication interfaces, including a first multiplexed high-speed interface. The server nodes include a second multiplexed high-speed interface. Each server node is connected to the communication interface of its corresponding I / O interface group. The second multiplexed high-speed interface is connected to the first multiplexed high-speed interface in its corresponding I / O interface group. The baseboard management controller is used to monitor the server nodes connected to the I / O interface groups.

2. The server according to claim 1, characterized in that, The baseboard management controller further includes a first processing unit and multiple controllers. The first processing unit is connected between the first multiplexed high-speed interface and the multiple controllers. The server node includes a second multiplexed high-speed interface and a second processing unit. The second multiplexed high-speed interface is connected to both the first multiplexed high-speed interface and the second processing unit. The first processing unit is used to encapsulate low-speed information from the multiple controllers into high-speed information and send it to the second processing unit through the first multiplexed high-speed interface and the second multiplexed high-speed interface. The second processing unit is used to parse the high-speed information into multiple low-speed information, and the transmission speed of the low-speed information is lower than that of the high-speed information.

3. The server according to claim 2, characterized in that, The multiple I / O interface groups share the first multiplexed high-speed interface and the first processing unit. The various controllers corresponding to each I / O interface group are all connected to the first processing unit. The multiple server nodes share the second multiplexed high-speed interface and the second processing unit. Each server node is connected to the second processing unit.

4. The server according to claim 3, characterized in that, The first processing unit is used to encapsulate multiple low-speed information and the identifier of the target server node into high-speed information; the second processing unit parses the high-speed information to obtain multiple low-speed information and the identifier of the target server node, and sends the multiple low-speed information to the information channel corresponding to the target server node according to the identifier of the target server node.

5. A baseboard management controller, characterized in that, The system includes multiple input / output (I / O) interface groups, each I / O interface group including multiple communication interfaces, the multiple communication interfaces including a first multiplexed high-speed interface; server nodes are connected to the communication interfaces of the corresponding I / O interface groups; wherein, the server node is connected to the first multiplexed high-speed interface in the corresponding I / O interface group through its own second multiplexed high-speed interface; the management controller is used to monitor the server nodes connected to the I / O interface groups.

6. The baseboard management controller according to claim 5, characterized in that, The management controller further includes a first processing unit and multiple controllers. The first processing unit is connected between the first multiplexed high-speed interface and the multiple controllers. The first processing unit is used to encapsulate low-speed information from the multiple controllers into high-speed information and send it to the server node through the first multiplexed high-speed interface. The transmission speed of the low-speed information is lower than the transmission speed of the high-speed information.

7. The baseboard management controller according to claim 5, characterized in that, The baseboard management controller also includes multiple image processors (GPUs). Each I / O interface group includes a PCIe interface. The PCIe interface of each I / O interface group is connected to the corresponding GPU. Each GPU is used to obtain image information from the server node connected to the corresponding I / O interface group, or to send image information to the connected server node through the corresponding I / O interface group.

8. The baseboard management controller according to claim 7, characterized in that, The baseboard management controller also includes a video graphics compression module, an Ethernet interface, a display interface, and a switch switching circuit; One end of the video graphics compression module is connected to the first end of the switch circuit, and the other end of the video graphics compression module is connected to a remote display via the Ethernet interface; the second end of the switch circuit is connected to a local display via the display interface; the third end of the switch circuit is connected to the N GPUs. The switching circuit is used to: acquire processed image information from one of the N GPUs; and send the acquired image information to the video graphics compression module for display on the remote display via the Ethernet interface, or send the acquired image information to the local display via the display interface.

9. The baseboard management controller according to any one of claims 5-8, characterized in that, The various communication interfaces include: the high-speed serial computer expansion bus standard PCIe interface, the enhanced peripheral management interface eSPI, the low frame rate LPC interface, the integrated circuit bus I2C, the enhanced two-wire serial bus I3C interface, the serial peripheral interface SPI, the universal asynchronous transceiver interface UART interface, the general-purpose I / O GPIO interface, and the platform environment control interface PECI.

10. A method for managing a server, characterized in that, The application is applied to a baseboard management controller, which includes multiple input / output (IO) interface groups. Each IO interface group is used to connect to a corresponding server node, and each IO interface group includes multiple communication interfaces connected to the corresponding server node. The multiple communication interfaces include a first multiplexed high-speed interface. The server node connects to the first multiplexed high-speed interface in the corresponding IO interface group through its own second multiplexed high-speed interface. The method includes: The target server node is managed through a target IO interface group, wherein the target IO interface group is any one of multiple IO interface groups, and the target server node is the target server node connected to the target IO interface.

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