Standby control signal generating circuit, display driving device and method, display apparatus

Abstract

The present disclosure provides a standby control signal generation circuit, comprising: an amplification sub-circuit connected with an input end of the standby control signal generation circuit, configured to receive a video signal and amplify the video signal; an XOR sub-circuit connected with the amplification sub-circuit, configured to perform XOR processing on the amplified video signal and a ground signal; and an adjustment sub-circuit connected with the XOR sub-circuit, configured to proportionally adjust the amplitude of an output signal of the XOR sub-circuit to generate a standby control signal. The present disclosure also provides a display driving device and driving method, and a display device.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to standby control signal generation circuits, display driving devices and methods, and display equipment. Background Technology

[0002] Display devices include a display panel and a display driver. The display driver is used to drive the display panel to display information according to the display information. To prevent residual charge on the display panel after the power is turned off, the display panel needs to be discharged after the display device is powered off. Summary of the Invention

[0003] This disclosure presents a standby control signal generation circuit, a display driver and method, and a display device.

[0004] This disclosure provides a standby control signal generation circuit, including:

[0005] An amplification sub-circuit is connected to the input terminal of the standby control signal generation circuit and is configured to receive video signals and amplify the video signals.

[0006] An XOR sub-circuit, connected to the amplification sub-circuit, is configured to perform XOR processing on the amplified video signal and the ground signal;

[0007] An adjustment sub-circuit, connected to the XOR sub-circuit, is configured to proportionally adjust the amplitude of the output signal of the XOR sub-circuit to generate a standby control signal.

[0008] In some embodiments, the amplification sub-circuit includes: an operational amplifier, a first resistor, and a second resistor;

[0009] The positive input terminal of the operational amplifier is connected to the input terminal of the standby control generation circuit, the negative input terminal of the operational amplifier is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the ground terminal, and the output terminal of the operational amplifier is connected to the XOR sub-circuit.

[0010] The two ends of the second resistor are connected to the inverting input and output terminals of the operational amplifier, respectively.

[0011] In some embodiments, the ratio of the second resistor to the first resistor is greater than or equal to the ratio of the first threshold to the minimum voltage of the video signal, wherein the first threshold is the threshold at which the XOR sub-circuit identifies a high-level voltage.

[0012] In some embodiments, the XOR sub-circuit includes: an XOR gate chip, the first input terminal of the XOR gate chip being connected to the amplification sub-circuit, the second input terminal of the XOR gate chip being connected to a ground terminal, and the output terminal of the XOR gate chip being connected to the adjustment sub-circuit.

[0013] In some embodiments, the XOR sub-circuit includes:

[0014] The first NOT gate unit is connected to the amplifier sub-circuit and is used to invert the amplifier sub-circuit.

[0015] The second NOT gate unit is connected to the ground terminal and is used to invert the ground signal of the ground terminal;

[0016] The first AND gate unit is connected to the output terminals of the first NOT gate unit and the second NOT gate unit, and is used to perform AND operations on the output signals of the first NOT gate unit and the second NOT gate unit.

[0017] The second AND gate unit is connected to the amplifier sub-circuit and the ground terminal, and is used to perform an AND operation between the output signal of the amplifier sub-circuit and the signal of the ground terminal.

[0018] An OR gate unit is connected to the output terminals of the first AND gate unit and the second AND gate unit, and is used to perform AND operations on the output signals of the first AND gate unit and the second AND gate unit;

[0019] The third NOT gate is connected to the output terminal of the OR gate unit and is used to invert the output signal of the OR gate unit.

[0020] In some embodiments, the first NOT gate unit includes: a fourth resistor, a fifth resistor, and a first transistor, wherein,

[0021] The fifth resistor is connected between the output terminal of the amplifier sub-circuit and the base of the first transistor;

[0022] The emitter of the first transistor is connected to the ground terminal, and the fourth resistor is connected between the power supply terminal and the collector of the first transistor; the connection node between the fourth resistor and the collector of the first transistor serves as the output terminal of the first NOT gate unit.

[0023] In some embodiments, the second NOT gate unit includes: a sixth resistor, a seventh resistor, and a second transistor.

[0024] The seventh resistor is connected between the output terminal of the amplifier sub-circuit and the base of the second transistor.

[0025] The emitter of the second transistor is connected to the ground terminal, and the sixth resistor is connected between the collector of the second transistor and the power supply terminal; the connection node between the sixth resistor and the collector of the second transistor serves as the output terminal of the second NOT gate unit.

[0026] In some embodiments, the first AND gate unit includes: an eighth resistor, a ninth resistor, a first diode, and a second diode;

[0027] The eighth resistor and the ninth resistor are connected in series between the power supply terminal and the ground terminal, and the connection node between the eighth resistor and the ninth resistor serves as the output terminal of the first AND gate unit.

[0028] The anode of the first diode is connected to the output terminal of the first AND gate, and the cathode of the first diode is connected to the output terminal of the first NOT gate; the anode of the second diode is connected to the output terminal of the first AND gate, and the cathode of the first diode is connected to the output terminal of the second NOT gate.

[0029] In some embodiments, the second AND gate unit includes: a third diode, a fourth diode, a tenth resistor, and an eleventh resistor;

[0030] The tenth resistor and the eleventh resistor are connected in series between the power supply terminal and the ground terminal, and the connection node between the tenth resistor and the eleventh resistor serves as the output terminal of the second AND gate unit.

[0031] The negative terminal of the third diode is connected to the output terminal of the amplifier sub-circuit, the positive terminal of the third diode is connected to the output terminal of the second AND gate unit, the negative terminal of the fourth diode is connected to the ground terminal, and the positive terminal of the fourth diode is connected to the output terminal of the second AND gate unit.

[0032] In some embodiments, the OR gate unit includes: a fifth diode and a sixth diode;

[0033] The positive terminal of the fifth diode is connected to the output terminal of the first AND gate unit, and the negative terminal of the fifth diode is connected to the output terminal of the OR gate unit.

[0034] The positive terminal of the sixth diode is connected to the output terminal of the second AND gate unit, and the negative terminal of the sixth diode is connected to the output terminal of the OR gate unit.

[0035] In some embodiments, the third NOT gate unit includes: a third transistor, a twelfth resistor, and a thirteenth resistor;

[0036] The two ends of the thirteenth resistor are respectively connected to the output terminal of the OR gate unit and the base of the third transistor;

[0037] The two ends of the twelfth resistor are connected to the power supply terminal and the collector of the third transistor, respectively. The emitter of the third transistor is connected to the ground terminal. The connection node between the twelfth resistor and the collector of the third transistor serves as the output terminal of the third NOT gate unit.

[0038] In some embodiments, the regulating sub-circuit includes: a first voltage divider resistor and a second voltage divider resistor connected in series between the output terminal and the ground terminal of the XOR sub-circuit, wherein the connection node between the first voltage divider resistor and the second voltage divider resistor is connected to the output terminal of the standby control signal generation circuit.

[0039] In some embodiments, the standby control signal generation circuit is used to output the standby control signal to the display control chip, and the voltage range of the high-level voltage identified by the display control chip is denoted as: Vm~Vn;

[0040] Wherein, the resistance value r3 of the first voltage divider resistor and the resistance value r3' of the second voltage divider resistor satisfy:

[0041] Vm≤[r3' / (r3+r3')]*Vd≤Vn

[0042] Wherein, Vd is the voltage output by the XOR sub-circuit when the video signal is in a high-level state.

[0043] In some embodiments, the system further includes: a backup delay sub-circuit, the backup delay sub-circuit including a fourteenth resistor and a capacitor, one end of the fourteenth resistor being floating, the other end of the fourteenth resistor being connected to one end of the capacitor, and the other end of the capacitor being connected to a ground terminal.

[0044] This disclosure also provides a display driving device, including a display driving chip and the aforementioned standby control signal generation circuit. The display driving chip is configured to drive a display panel to display a corresponding video according to the video signal; and to control the display panel to enter a standby stage when the power signal is in an active state and the standby control signal is in an inactive state.

[0045] In some embodiments, controlling the display panel to enter a standby phase includes:

[0046] When the power signal is active and the standby control signal is inactive, the control display device displays multiple preset discharge frames.

[0047] This disclosure also provides a driving method for a display driving device as described above, comprising:

[0048] The standby control signal generation circuit amplifies the received video signal, performs XOR processing on the amplified video signal to generate a signal to be adjusted, and proportionally adjusts the amplitude of the signal to be adjusted to generate a standby control signal.

[0049] The display driver chip drives the display panel to display the corresponding video when the video signal is valid; and controls the display panel to enter the standby stage when the power signal is valid and the standby control signal is invalid.

[0050] This disclosure also provides a display device, including the above-described display driver, system board, and display panel;

[0051] The system board is configured to output a power signal in response to a power-on command and to output a video signal according to the content to be displayed on the display panel. Attached Figure Description

[0052] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0053] Figure 1 This is a timing diagram showing the required sequence of standby control signals and power signals when the display device is powered off.

[0054] Figure 2 This is a standby control signal generation circuit provided in some embodiments of the present disclosure.

[0055] Figure 3 This is a schematic diagram of a standby control signal generation circuit provided in some other embodiments of this disclosure.

[0056] Figure 4 This is a schematic diagram of a standby control signal generation circuit provided in some other embodiments of this disclosure.

[0057] Figure 5 This is a schematic diagram of a standby control signal generation circuit provided in some other embodiments of this disclosure.

[0058] Figure 6 This is a schematic diagram of a display driving device provided in some embodiments of the present disclosure.

[0059] Figure 7 This is a schematic diagram of a display device provided in some embodiments of the present disclosure.

[0060] Figure 8 This is a timing diagram of the operation of a display device provided in some embodiments of this disclosure. Detailed Implementation

[0061] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0063] The terminology used herein to describe embodiments of this disclosure is not intended to limit and / or restrict the scope of this disclosure. For example, unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense as would be understood by one of ordinary skill in the art to which this disclosure pertains. It should be understood that the terms “first,” “second,” and similar terms used herein do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Unless the context clearly indicates otherwise, the singular forms “a,” “one,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as “comprising” or “including” mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0064] The display device includes a display panel, a display driver chip (DDIC), and a system board. The system board provides a power signal to the display driver chip upon receiving a power-on command, and provides a video input signal (LVDS, or Low-Voltage Differential Signaling) to the display driver chip based on the content to be displayed on the display panel. The display driver chip then provides display control signals to the display panel based on the video input signal, thereby driving the display panel to perform its display function.

[0065] In some products, the display driver chip may include a timing control circuit and a data driving circuit. A gate driving circuit is provided on the display panel. The timing control circuit provides timing signals to the gate driving circuit and the data driving circuit based on the video input signal. This causes the gate driving circuit to provide scan signals to the pixels on the display panel row by row. For each row of pixels, the data driving circuit provides a data voltage signal to the corresponding row of pixels, causing that row of pixels to display the corresponding grayscale. By adjusting the magnitude of the data voltage signal, the grayscale of the pixel can be adjusted.

[0066] To prevent residual charge from remaining on the display panel after power-off, it is necessary to discharge the display panel after the display device is powered off to prevent residual charge from affecting the display screen upon the next power-on. Specifically, the display driver chip controls the display panel to display a discharge screen based on the STBYB signal (standby control signal). For example, the data voltage signal provided by the data driver circuit reaches its maximum value when the display panel displays a white screen, and reaches its minimum value when the display panel displays a black screen. In this case, the aforementioned discharge screen is a black screen.

[0067] It should be noted that controlling the display panel to display the discharge screen means providing the display panel with the data signal corresponding to the discharge screen.

[0068] Figure 1 This is a timing diagram showing the required sequence of standby control signals and power signals when the display device is powered off, such as... Figure 1 As shown, when the display device is turned off (e.g., Figure 1 At time T1, the standby control signal STBYB switches from an active level (e.g., high level) to an inactive level (e.g., low level). After time t, the power signal VDDI switches from a high level to a low level. The display driver chip controls the display panel to display the discharge image based on the switching of the standby control signal STBYB from an active level to an inactive level.

[0069] Most system boards lack an output pin for the standby control signal STBYB, thus failing to provide the STBYB signal to the display driver chip. Consequently, the display driver chip cannot control the display panel to discharge according to the required timing. Some display devices use a delay in the power signal VDDI to generate the STBYB signal, but this generated STBYB signal often fails to meet the aforementioned requirements, leading to abnormal discharge of the display panel.

[0070] Figure 2This disclosure provides a standby control signal generation circuit in some embodiments, which is applied in the display driver of a display device to generate a standby control signal. For example... Figure 2 As shown, the input terminal IN of the standby control signal generation circuit is connected to the video signal terminal of the system board, which provides the video signal. The output terminal OUT of the standby control signal generation circuit outputs the standby control signal. Specifically, when the system board receives a power-on signal, the video signal transitions from a low level to a high level, and when the display device receives a power-off signal, it transitions from a high level to a low level. It should be understood that the video signal is generated by the system board based on the content to be displayed on the display panel. Therefore, when the video signal is in a high-level state, it is not at a fixed potential, but fluctuates around a preset bias voltage. The bias voltage is, for example, 1.2V.

[0071] The standby control signal generation circuit includes: an amplifier sub-circuit 10, an XOR sub-circuit 20, and an adjustment sub-circuit 30.

[0072] The amplification sub-circuit 10 is connected to the input terminal IN of the standby control signal generation circuit and is configured to receive and amplify the video signal. The XOR sub-circuit 20 is connected to the amplification sub-circuit 10 and is configured to perform XOR processing between the amplified video signal and the ground signal.

[0073] Since the voltage of the video signal is low when it is in a high-level state, it fluctuates around the bias voltage. The input voltage of the XOR sub-circuit 20 needs to reach a certain threshold before it can identify the input voltage as a high-level voltage. Therefore, amplifying the video signal first and then providing the amplified video signal to the XOR sub-circuit 20 helps the XOR sub-circuit 20 to identify the high-level state in the video signal.

[0074] The amplification factor of the amplification sub-circuit 10 can be determined based on the voltage of the video signal when it is in a high-level state and the threshold for the XOR sub-circuit 20 to identify a high-level voltage. For example, if the XOR sub-circuit 20 identifies the input voltage as a high-level voltage when its input voltage is greater than 5V, and the voltage of the video signal when it is in a high-level state fluctuates around a bias voltage of 1.2V, and the minimum voltage of the video signal is 1.1V, then the amplification factor of the amplification sub-circuit can be configured to be greater than or equal to 4.6.

[0075] The processing rule of the XOR sub-circuit 20 is as follows: when the voltage output by the amplifier sub-circuit 10 is detected to be a high-level voltage, it is XORed with the ground signal to output a fixed high-level voltage; when the voltage output by the amplifier sub-circuit 10 is detected to be a low-level voltage, it is XORed with the ground signal to output a fixed low-level voltage.

[0076] The adjustment sub-circuit 30 is connected to the XOR sub-circuit 20 and is configured to proportionally adjust the amplitude of the output signal of the XOR sub-circuit 20 to generate a standby control signal. This standby control signal can be output to the display driver chip, so that the display driver chip can control the display panel to display a preset discharge screen according to the standby control signal.

[0077] For the display control chip, only signals with voltages within a specific range will be recognized as high-level signals. By adjusting the settings of the adjustment sub-circuit 30, the output voltage of the adjustment sub-circuit 30 can be adjusted, so that the display control signal can recognize the high-level and low-level states in the output voltage.

[0078] The standby control circuit provided in this embodiment can XOR the amplified video signal with a ground signal, and then proportionally adjust the XOR signal to generate a standby control signal. Since the ground signal remains at a low level, when the video signal is at a high level, the XOR sub-circuit 20 outputs a high-level signal, thus causing the standby control signal output by the adjustment sub-circuit 30 to be at a high level; when the video signal is at a low level, the XOR sub-circuit 20 outputs a low-level signal, thus causing the standby control signal output by the adjustment sub-circuit 30 to be at a low level. When the system board receives a power-off command, it first switches the video signal from a high level to a low level, and after a period of time, switches the power supply voltage from a high level to a low level. Therefore, when the display device is powered off, the standby control signal generated by the standby control signal generation circuit switches to a low level earlier than the power supply voltage. This allows the display driver chip to control the display panel to display a preset discharge screen based on the level switching of the standby control signal before the power supply voltage drops, thereby ensuring the normal discharge of the display panel.

[0079] Figure 3 This is a schematic diagram of a standby control signal generation circuit provided in some other embodiments of this disclosure. Figure 3 for Figure 2 A specific implementation scheme, such as Figure 3 As shown, the amplifier sub-circuit 10 includes: an operational amplifier OP, a first resistor R1, and a second resistor R2.

[0080] In this circuit, the positive input terminal of operational amplifier OP is connected to the input terminal of the standby control generation circuit, the negative input terminal of operational amplifier OP is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the ground terminal GND, and the output terminal of operational amplifier OP is connected to the XOR sub-circuit 20. The two ends of the second resistor R2 are connected to the negative input terminal and the output terminal of operational amplifier OP, respectively.

[0081] The operational amplifier OP has a gain of r2 / r1, where r2 is the resistance of the second resistor R2 and r1 is the resistance of the first resistor R1. The gain of the operational amplifier OP can be determined based on the bias voltage of the video signal and the threshold voltage at which the XOR sub-circuit 20 identifies the high-level signal. The resistance values ​​of the first resistor R1 and the second resistor R2 are then set according to this gain.

[0082] In one example, the minimum voltage of the video signal is 1.1V, and the XOR sub-circuit 20 identifies the threshold voltage of the high-level signal as 5V. In this case, the ratio of r2 / r1 is set to 4.7. The specific resistance values ​​of the first resistor R1 and the second resistor R2 can be determined according to the current required by the device itself. For example, the first resistor R1 is set to 1KΩ, and the resistance value of the second resistor R2 is set to 4.7KΩ.

[0083] In some embodiments, the XOR sub-circuit 20 may employ an XOR gate chip, with its first input terminal connected to the amplification sub-circuit 10, its second input terminal grounded, and its output terminal connected to the adjustment sub-circuit 30. For example, the XOR gate chip may be a 74LS86 chip.

[0084] In some embodiments, such as Figure 3 As shown, the adjustment sub-circuit 30 includes: a first voltage divider resistor R3 and a second voltage divider resistor R3' connected in series between the output terminal of the XOR sub-circuit 20 and the ground terminal GND. The connection node between the first voltage divider resistor R3 and the second voltage divider resistor R3' serves as the output terminal of the adjustment sub-circuit 30 and is connected to the output terminal OUT of the standby control signal generation circuit, thereby outputting the voltage of the connection node to the display control chip.

[0085] In some embodiments, when the video signal is at a high level, the voltage output by the XOR sub-circuit 20 is denoted as Vd. Then, the voltage Vb output by the adjustment sub-circuit 30 is Vb = [r3' / (r3+r3')]*Vd, where r3 is the resistance value of the first voltage divider resistor R3 and r3' is the resistance value of the second voltage divider resistor R3'. The adjustment ratio of the adjustment sub-circuit 30 can be determined based on Vd and the range of the high-level signal identified by the display control chip, thereby setting the resistance values ​​of the first voltage divider resistor R3 and the second voltage divider resistor R3' according to the adjustment ratio. That is, assuming the display control chip identifies a high-level voltage range of Vm to Vn, then r3 and r3' satisfy: Vm ≤ [r3' / (r3+r3')]*Vd ≤ Vn.

[0086] Figure 4 This is a schematic diagram of a standby control signal generation circuit provided in some other embodiments of the present disclosure. In some embodiments, such as... Figure 4As shown, the standby control signal generation circuit may further include: a backup delay sub-circuit 40, which is an RC delay circuit, including a fourteenth resistor R14 and a capacitor C. One end of the fourteenth resistor R14 is floating, and the other end is connected to one end of the capacitor C. The other end of the capacitor C is connected to the ground terminal GND.

[0087] The standby control signal generation circuit can be integrated on the driver circuit board. The fourteenth resistor R14 and capacitor C are reserved on the driver circuit board. In actual production, after the amplification sub-circuit 10, XOR sub-circuit 20 and adjustment sub-circuit 30 are made, signal testing can be performed. If a fault occurs in the amplification sub-circuit 10, XOR sub-circuit 20 and adjustment sub-circuit 30, resulting in the inability to generate the required standby control signal, the fourteenth circuit can be connected to the power supply terminal VDD. The connection node between the fourteenth resistor R14 and capacitor C is used as the output terminal OUT of the standby control signal generation circuit to connect to the display driver chip. The signal of the power supply terminal VDD is then delayed by the RC delay circuit to generate the standby control signal.

[0088] Figure 5 This is a schematic diagram of a standby control signal generation circuit provided in some other embodiments of this disclosure. Figure 5 In the middle, the structures of the amplification sub-circuit 10 and the adjustment sub-circuit 30 are both similar to... Figure 3 The same applies here, so I won't repeat it again.

[0089] exist Figure 5 In this circuit, the XOR sub-circuit 20 specifically includes: a first NOT gate unit 21, a second NOT gate unit 22, a first AND gate unit 23, a second AND gate unit 24, an OR gate unit 25, and a third NOT gate unit 26.

[0090] The first NOT gate unit 21 is connected to the amplifier sub-circuit 10 and is used to invert the amplifier sub-circuit 10.

[0091] The second NOT gate unit 22 is connected to the ground terminal GND and is used to invert the signal at the ground terminal GND.

[0092] The first AND gate unit 23 is connected to the output terminal of the first NOT gate unit 21 and the output terminal of the second NOT gate unit 22, and is used to perform AND operation on the output signal of the first NOT gate unit 21 and the output signal of the second NOT gate unit 22.

[0093] The second AND gate unit 24 is connected to the amplifier sub-circuit 10 and the ground terminal GND, and is used to perform an AND operation between the output signal of the amplifier sub-circuit 10 and the signal of the ground terminal GND.

[0094] OR gate unit 25 is connected to the output terminal of the first AND gate unit 23 and the output terminal of the second AND gate unit 24, and is used to perform AND operation on the output signal of the first AND gate unit 23 and the output signal of the second AND gate unit 24.

[0095] The third NOT gate unit 26 is connected to the output terminal of the OR gate unit 25 and is used to invert the output signal of the OR gate unit 25.

[0096] Specifically, when the amplifier sub-circuit 10 outputs a high-level signal, the first NOT gate unit 21 outputs a low-level signal; the second NOT gate unit 22 outputs a high-level signal; the first AND gate unit 23 performs an AND operation on the low-level signal output by the first NOT gate unit 21 and the high-level signal output by the second NOT gate unit 22, and outputs a low-level signal; the second AND gate unit 24 performs an AND operation on the high-level signal output by the amplifier sub-circuit 10 and the low-level signal at the ground terminal GND, and outputs a low-level signal; the OR gate unit 25 performs an OR operation on the low-level signal output by the first AND gate unit 23 and the low-level signal output by the second AND gate unit 24, and outputs a low-level signal; and the third NOT gate unit 26 inverts the low-level signal output by the OR gate unit 25, and outputs a high-level signal.

[0097] When the amplifier sub-circuit 10 outputs a low-level signal, the first NOT gate unit 21 outputs a high-level signal, and the second NOT gate unit 22 outputs a high-level signal; the first AND gate unit 23 performs an AND operation on the high-level signals output by the first NOT gate unit 21 and the second NOT gate unit 22, and outputs a high-level signal; the second AND gate unit 24 performs an AND operation on the low-level signal output by the amplifier sub-circuit 10 and the low-level signal at the ground terminal GND, and outputs a high-level signal; the OR gate unit 25 performs an OR operation on the high-level signals output by the first AND gate unit 23 and the second AND gate unit 24, and outputs a high-level signal; the third NOT gate unit 26 inverts the high-level signal output by the OR gate unit 25, and outputs a low-level signal.

[0098] In some embodiments, such as Figure 5 As shown, the first NOT gate unit 21 includes: a fourth resistor R4, a fifth resistor R5, and a first transistor Q1. The fourth resistor R4 is connected between the power supply terminal VDD and the collector of the first transistor Q1. The fifth resistor R5 is connected between the output terminal of the amplifier sub-circuit 10 and the base of the first transistor Q1. The emitter of the first transistor Q1 is connected to the ground terminal GND. The connection node between the fourth resistor R4 and the collector of the first transistor Q1 serves as the output terminal of the first NOT gate unit 21.

[0099] The fourth resistor R4 serves as the gate resistor for the first transistor Q1, providing voltage to the output of the first NOT gate unit 21. When the first transistor is saturated and conducting, a large voltage drop occurs across the fourth resistor R4, making the collector potential almost equal to the emitter potential. When the first transistor Q1 is off, the voltage at the first power supply terminal VDD is applied to the collector through the fourth resistor R4, making the collector voltage equal to the voltage at the power supply terminal VDD. The fifth resistor R5 is the input resistance of the first transistor, allowing a forward bias current to be applied to it.

[0100] When the input terminal of the first NOT gate unit 21 (i.e. the output terminal of the amplifier sub-circuit 10) receives a low-level signal, the base of the first transistor Q1 is cut off because it does not receive a forward bias current. At this time, no collector current flows through it, and no voltage drop is generated across the fourth resistor R4. The output terminal of the first NOT gate unit 21 outputs the voltage signal of the power supply terminal VDD, i.e., a high-level signal.

[0101] When the input terminal of the first NOT gate unit 21 (i.e. the output terminal of the amplifier sub-circuit 10) receives a high-level signal, the high-level signal is applied to the base of the first transistor Q1 through the fifth resistor R5, providing a forward bias current to the base and causing the first transistor Q1 to saturate and conduct. At this time, a large voltage drop is generated across the fourth resistor R4, causing the voltage at the output terminal of the first NOT gate unit 21 to reach a low level.

[0102] like Figure 5 As shown, the second NOT gate unit 22 includes a sixth resistor R6, a seventh resistor R7, and a second transistor Q2. The sixth resistor R6 is connected between the collector of the second transistor Q2 and the power supply terminal VDD. The seventh resistor R7 is connected between the output terminal of the amplifier sub-circuit 10 and the base of the second transistor Q2. The emitter of the second transistor Q2 is connected to the ground terminal GND. The connection node between the sixth resistor R6 and the collector of the second transistor Q2 serves as the output terminal of the second NOT gate unit 22.

[0103] The working principle of the second NOT gate unit 22 is the same as that of the first NOT gate unit 21, and will not be repeated here.

[0104] like Figure 5 As shown, the first AND gate unit 23 includes: a first diode D1, a second diode D2, an eighth resistor R8, and a ninth resistor R9.

[0105] In this configuration, the eighth resistor R8 and the ninth resistor R9 are connected in series between the power supply terminal VDD and the ground terminal GND. Specifically, one end of the eighth resistor R8 is connected to the power supply terminal VDD, and the other end of the eighth resistor R8 is connected to the ninth resistor R9. The other end of the ninth resistor R9 is connected to the ground terminal GND. The connection node between the eighth resistor R8 and the ninth resistor R9 serves as the output terminal of the first AND gate unit 23. The anode of the first diode D1 is connected to the output terminal of the first AND gate unit 23, and the cathode of the first diode D1 is connected to the output terminal of the first NOT gate 21. The anode of the second diode D2 is connected to the output terminal of the first AND gate unit 23, and the cathode of the first diode D1 is connected to the output terminal of the second NOT gate 22.

[0106] Taking a 5V voltage at the first power supply terminal VDD and 1KΩ resistors R8 and R9 as an example, after the 5V voltage is divided by resistors R8 and R9, the voltage at the connection node E of resistors R8 and R9 is 2.5V. When a low-level signal (e.g., 0V) is simultaneously input to the cathodes of the first diode D1 and the second diode D2, both diodes D1 and D2 conduct, and the voltage at connection node E drops to a low level. That is, when a low-level signal is simultaneously input to the cathodes of both diodes D1 and D2, the first AND gate unit 23 outputs a low-level signal. When a low-level signal (e.g., 0V) is input to the cathode of the first diode D1 and a high-level signal (e.g., 5V) is input to the cathode of the second diode D2, the first diode D1 conducts, and the voltage at connection node E drops to a low level, thus turning off the second diode D2. That is, when a low-level signal is input to the cathode of the first diode D1 and a high-level signal is input to the cathode of the second diode D2, the first AND gate unit 23 outputs a low-level signal. When a high-level signal is input to the cathode of the first diode D1 and a low-level signal is input to the cathode of the second diode D2, the first diode D1 is cut off, the second diode D2 is turned on, and the output terminal of the first AND gate unit 23 (i.e., at connection node E) outputs a low-level signal. When both the cathodes of the first diode D1 and the cathodes of the second diode D2 are input with high-level signals (e.g., 5V), both the first diode D1 and the second diode D2 are cut off, and the output terminal of the first AND gate unit 23 (i.e., at connection node E) outputs a high-level signal (i.e., the aforementioned 2.5V signal).

[0107] like Figure 5 As shown, the second AND gate unit 24 includes: a third diode D3, a fourth diode D4, a tenth resistor R10, and an eleventh resistor R11.

[0108] In this circuit, the tenth resistor R10 and the eleventh resistor R11 are connected in series between the power supply terminal VDD and the ground terminal GND. Specifically, one end of the tenth resistor R10 is connected to the power supply terminal VDD, and the other end of the tenth resistor R10 is connected to one end of the eleventh resistor R11. The other end of the eleventh resistor R11 is connected to the ground terminal GND. The connection node between the tenth resistor R10 and the eleventh resistor R11 serves as the output terminal of the second AND gate unit 24. The cathode of the third diode D3 is connected to the output terminal of the amplifier sub-circuit 10, and the anode of the third diode D3 is connected to the output terminal of the second AND gate unit 24. The cathode of the fourth diode D4 is connected to the ground terminal GND, and the anode of the fourth diode D4 is connected to the output terminal of the second AND gate unit 24.

[0109] The working principle of the second AND gate unit 24 is the same as that of the first AND gate unit 23, and will not be repeated here.

[0110] like Figure 5 As shown, the OR gate unit 25 includes a fifth diode D5 and a sixth diode D6, wherein the anode of the fifth diode D5 is connected to the output terminal of the first AND gate unit 23, the cathode of the fifth diode D5 is connected to the output terminal of the OR gate unit 25, the anode of the sixth diode D6 is connected to the output terminal of the second AND gate unit 24, and the cathode of the sixth diode D6 is connected to the output terminal of the OR gate unit 25.

[0111] Specifically, when the anode of at least one of the fifth diode D5 and the sixth diode D6 receives a high-level signal, at least one of the fifth diode D5 and the sixth diode D6 conducts, thereby causing the output terminal of OR gate unit 25 to output a high-level signal. When the anodes of both the fifth diode D5 and the sixth diode D6 receive low-level signals, both the fifth diode D5 and the sixth diode D6 are turned off, and the output terminal of OR gate unit 25 outputs a low-level signal.

[0112] like Figure 5 As shown, the third NOT gate unit 26 includes: a third transistor Q3, a twelfth resistor R12, and a thirteenth resistor R13.

[0113] In this configuration, the two ends of the thirteenth resistor R13 are connected to the output terminal of the OR gate unit 25 and the base of the third transistor Q3, respectively. The two ends of the twelfth resistor R12 are connected to the power supply terminal VDD and the collector of the third transistor Q3, respectively. The emitter of the third transistor Q3 is connected to the ground terminal GND. The connection node between the twelfth resistor R12 and the collector of the third transistor Q3 serves as the output terminal of the third NOT gate unit 26.

[0114] The working principle of the third NOT gate unit 26 is the same as that of the first NOT gate unit 21 and the second NOT gate unit 22, and will not be described again here.

[0115] Figure 6This is a schematic diagram of a display driving device provided in some embodiments of the present disclosure, such as... Figure 6 As shown, the display driving device includes a display driving chip 200 and a standby control signal generation circuit 100 in the above embodiment.

[0116] The display driver chip 200 is configured to drive the display panel to display the corresponding video according to the video signal; and to control the display panel to enter the standby stage when the power signal is valid and the standby control signal is invalid.

[0117] In this embodiment, the terms "valid state" and "invalid state" are relative. The valid state of the video signal refers to the state in which the video signal carries image information, thereby driving the display panel to display an image. The power signal can be considered as the power supply for the display panel and display driver device during operation. The valid state of the power signal refers to the state in which it has a certain voltage, thereby controlling the display panel and display driver device to operate. In this embodiment, both the valid state of the video signal and the valid state of the power signal are high-level states; correspondingly, both the invalid state of the video signal and the invalid state of the power signal are low-level states. Since the standby control signal is generated by amplifying, XORing, and proportionally adjusting the video signal, its valid state is also high-level, and its invalid state is low-level.

[0118] In some embodiments, controlling the display panel to enter a standby phase may specifically include: controlling the display panel to display multiple preset discharge frames. That is, providing the display panel with data signals corresponding to the preset discharge frames.

[0119] For example, if the preset discharge screen is a black screen, and the data voltage required to display the black screen is Vd1 when the display panel is displaying an image normally before being turned off, then when the display panel is controlled to enter standby mode, a data signal of size Vd1 is provided to the display panel.

[0120] This disclosure also provides a driving method for the above-described display driving device, including:

[0121] The standby control signal generation circuit amplifies the received video signal, performs XOR processing on the amplified video signal to generate the signal to be adjusted, and performs proportional adjustment on the signal to be adjusted to generate the standby control signal.

[0122] When the video signal is valid, the display driver chip drives the display panel to display the corresponding video; and when the power signal is valid and the standby control signal is invalid, it controls the display panel to enter the standby stage.

[0123] Specifically, controlling the display panel to enter the standby phase may include: controlling the display panel to display a preset discharge screen, such as displaying a black screen.

[0124] Figure 7 This is a schematic diagram of a display device provided in some embodiments of the present disclosure, such as... Figure 7 As shown, the display device includes: system board 1, display panel 3 and the aforementioned display driver 2.

[0125] System board 1 is configured to output a power signal in response to a power-on command and to output a video signal according to the content to be displayed on the display panel.

[0126] The display driver 2 generates a standby control signal based on the video signal output from the system board; drives the display panel to display the corresponding video based on the voltage of the video signal when it is in an active state; and controls the display panel to enter the standby stage when the power signal is in an active state and the standby control signal is in an inactive state.

[0127] The display panel 3 is a liquid crystal display panel, and the display device also includes a backlight for providing backlighting to the display panel. The system board 1 can also control the turning the backlight on and off.

[0128] Figure 8 This is a timing diagram of the operation of a display device provided in some embodiments of this disclosure, such as... Figure 8 As shown, at time t0, the system board receives the power-on signal and begins to output a high-level power signal.

[0129] During the t1 phase (initialization phase) following time t0, system board 1 outputs a high-level video signal with a magnitude equal to the preset initialization voltage.

[0130] In stage t2 (i.e., the normal display stage), system board 1 continues to output a high-level video signal according to the content to be displayed on display panel 3, and display driver chip 2 drives display panel to perform display based on the video signal. Simultaneously, system board 1 outputs a valid backlight control signal to control the backlight source to emit light. Specifically, display driver chip 2 driving display panel according to video signal means that display driver chip 2 writes corresponding data voltages to each pixel of display panel 3 according to the video signal, thereby deflecting the liquid crystal of each pixel to adjust the brightness of the light transmitted through the pixel.

[0131] At time t3, system board 1 responds to the power-off command by outputting an invalid backlight control signal, thereby controlling the backlight to stop emitting light.

[0132] At time t4, system board 1 stops outputting video signals.

[0133] In addition, the standby control signal generation circuit generates a standby control signal based on the video signal. Due to the inherent signal delay of electronic components, there is a certain time difference between the rising edge of the standby control signal and the rising edge of the video signal, and between the falling edge of the standby control signal and the falling edge of the video signal. For example... Figure 8 As shown in t11 and t12.

[0134] After time t5 (the falling edge of the standby control signal) and before time t6 (the falling edge of the power signal), the display driver chip drives the display panel to display multiple frames (e.g., 5 or 6 frames or other numbers) of preset discharge images.

[0135] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A standby control signal generation circuit, comprising: An amplification sub-circuit is connected to the input terminal of the standby control signal generation circuit and is configured to receive video signals and amplify the video signals. An XOR sub-circuit, connected to the amplification sub-circuit, is configured to perform XOR processing on the amplified video signal and the ground signal; An adjustment sub-circuit, connected to the XOR sub-circuit, is configured to proportionally adjust the amplitude of the output signal of the XOR sub-circuit to generate a standby control signal.

2. The standby control signal generation circuit according to claim 1, wherein, The amplifier sub-circuit includes: an operational amplifier, a first resistor, and a second resistor; The positive input terminal of the operational amplifier is connected to the input terminal of the standby control signal generation circuit, the negative input terminal of the operational amplifier is connected to the first end of the first resistor, the second end of the first resistor is connected to the ground terminal, and the output terminal of the operational amplifier is connected to the XOR sub-circuit. The two ends of the second resistor are connected to the inverting input and output terminals of the operational amplifier, respectively.

3. The standby control signal generation circuit according to claim 2, wherein, The ratio of the second resistor to the first resistor is greater than or equal to the ratio of the first threshold to the minimum voltage of the video signal, wherein the first threshold is the threshold at which the XOR sub-circuit identifies a high-level voltage.

4. The standby control signal generation circuit according to claim 1, wherein, The XOR sub-circuit includes an XOR gate chip, the first input terminal of which is connected to the amplification sub-circuit, the second input terminal of which is connected to ground, and the output terminal of which is connected to the adjustment sub-circuit.

5. The standby control signal generation circuit according to any one of claims 1 to 4, wherein, The XOR sub-circuit includes: The first NOT gate unit is connected to the amplifier sub-circuit and is used to invert the amplifier sub-circuit. The second NOT gate unit is connected to the ground terminal and is used to invert the ground signal of the ground terminal; The first AND gate unit is connected to the output terminals of the first NOT gate unit and the second NOT gate unit, and is used to perform AND operation on the output signals of the first NOT gate unit and the second NOT gate unit. The second AND gate unit is connected to the amplifier sub-circuit and the ground terminal, and is used to perform an AND operation between the output signal of the amplifier sub-circuit and the signal of the ground terminal. An OR gate unit is connected to the output terminals of the first AND gate unit and the second AND gate unit, and is used to perform AND operations on the output signals of the first AND gate unit and the second AND gate unit; The third NOT gate unit is connected to the output terminal of the OR gate unit and is used to invert the output signal of the OR gate unit.

6. The standby control signal generation circuit according to claim 5, wherein, The first NOT gate unit includes: a fourth resistor, a fifth resistor, and a first transistor, wherein, The fifth resistor is connected between the output terminal of the amplifier sub-circuit and the base of the first transistor; The emitter of the first transistor is connected to the ground terminal, and the fourth resistor is connected between the power supply terminal and the collector of the first transistor; the connection node between the fourth resistor and the collector of the first transistor serves as the output terminal of the first NOT gate unit.

7. The standby control signal generation circuit according to claim 5, wherein, The second NOT gate unit includes: a sixth resistor, a seventh resistor, and a second transistor. The seventh resistor is connected between the output terminal of the amplifier sub-circuit and the base of the second transistor. The emitter of the second transistor is connected to the ground terminal, and the sixth resistor is connected between the collector of the second transistor and the power supply terminal; the connection node between the sixth resistor and the collector of the second transistor serves as the output terminal of the second NOT gate unit.

8. The standby control signal generation circuit according to claim 5, wherein, The first AND gate unit includes: an eighth resistor, a ninth resistor, a first diode, and a second diode; The eighth resistor and the ninth resistor are connected in series between the power supply terminal and the ground terminal, and the connection node between the eighth resistor and the ninth resistor serves as the output terminal of the first AND gate unit. The anode of the first diode is connected to the output terminal of the first AND gate, and the cathode of the first diode is connected to the output terminal of the first NOT gate; the anode of the second diode is connected to the output terminal of the first AND gate, and the cathode of the first diode is connected to the output terminal of the second NOT gate.

9. The standby control signal generation circuit according to claim 5, wherein, The second AND gate unit includes: a third diode, a fourth diode, a tenth resistor, and an eleventh resistor; The tenth resistor and the eleventh resistor are connected in series between the power supply terminal and the ground terminal, and the connection node between the tenth resistor and the eleventh resistor serves as the output terminal of the second AND gate unit. The negative terminal of the third diode is connected to the output terminal of the amplifier sub-circuit, the positive terminal of the third diode is connected to the output terminal of the second AND gate unit, the negative terminal of the fourth diode is connected to the ground terminal, and the positive terminal of the fourth diode is connected to the output terminal of the second AND gate unit.

10. The standby control signal generation circuit according to claim 5, wherein, The OR gate unit includes: a fifth diode and a sixth diode; The positive terminal of the fifth diode is connected to the output terminal of the first AND gate unit, and the negative terminal of the fifth diode is connected to the output terminal of the OR gate unit. The positive terminal of the sixth diode is connected to the output terminal of the second AND gate unit, and the negative terminal of the sixth diode is connected to the output terminal of the OR gate unit.

11. The standby control signal generation circuit according to claim 5, wherein, The third NOT gate unit includes: a third transistor, a twelfth resistor, and a thirteenth resistor; The two ends of the thirteenth resistor are respectively connected to the output terminal of the OR gate unit and the base of the third transistor; The two ends of the twelfth resistor are connected to the power supply terminal and the collector of the third transistor, respectively. The emitter of the third transistor is connected to the ground terminal. The connection node between the twelfth resistor and the collector of the third transistor serves as the output terminal of the third NOT gate unit.

12. The standby control signal generation circuit according to any one of claims 1 to 4, wherein, The regulating sub-circuit includes: a first voltage divider resistor and a second voltage divider resistor connected in series between the output terminal and the ground terminal of the XOR sub-circuit, and the connection node between the first voltage divider resistor and the second voltage divider resistor is connected to the output terminal of the standby control signal generation circuit.

13. The standby control signal generation circuit according to claim 12, wherein, The standby control signal generation circuit is used to output the standby control signal to the display control chip. The voltage range of the high-level voltage identified by the display control chip is denoted as: Vm~Vn. Wherein, the resistance value r3 of the first voltage divider resistor and the resistance value of the second voltage divider resistor are... satisfy: Wherein, Vd is the voltage output by the XOR sub-circuit when the video signal is in a high-level state.

14. The standby control signal generation circuit according to any one of claims 1 to 4, wherein, Also includes: A backup delay sub-circuit is provided, comprising a fourteenth resistor and a capacitor. One end of the fourteenth resistor is floating, and the other end of the fourteenth resistor is connected to one end of the capacitor, which is then connected to ground.

15. A display driving device, comprising a display driving chip and a standby control signal generation circuit according to any one of claims 1 to 14, wherein the display driving chip is configured to drive a display panel to display a corresponding video according to the video signal; and to control the display panel to enter a standby phase when a power signal is active and the standby control signal is inactive.

16. The display driving device according to claim 15, wherein, The step of controlling the display panel to enter the standby phase includes: The display panel is controlled to display multiple preset discharge frames.

17. A driving method for a display driving device as described in claim 15 or 16, comprising: The standby control signal generation circuit amplifies the received video signal and performs XOR processing on the amplified video signal to generate the signal to be adjusted. And proportionally adjust the amplitude of the signal to be adjusted to generate a standby control signal; When the video signal is valid, the display driver chip drives the display panel to display the corresponding video. And when the power signal is valid and the standby control signal is invalid, the display panel is controlled to enter the standby stage.

18. A display device, comprising the display driving device, system board, and display panel as described in claim 15 or 16; The system board is configured to output a power signal in response to a power-on command and to output a video signal according to the content to be displayed on the display panel.

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