Display panel and display device

Abstract

The present invention discloses a display panel and a display device; wherein, the counter substrate is disposed opposite to the array substrate; the support pillars are disposed between the array substrate and the counter substrate; wherein, the array substrate includes a first substrate, a thin-film transistor layer disposed on one side of the first substrate close to the counter substrate, a first spacer structure disposed on one side of the thin-film transistor layer close to the counter substrate, a spacer layer disposed on one side of the first spacer structure close to the counter substrate, a first opening formed in the spacer layer and located on one side of the first spacer structure close to the counter substrate, and a second spacer structure, the second spacer structure fills the first opening and protrudes from the surface of the spacer layer close to the counter substrate, the support pillars are disposed between the counter substrate and the second spacer structure, and the depth of the first opening is less than the thickness of the spacer layer; the present invention can avoid the support pillars from scratching the film layer, and can avoid the generation of etching residues in the second spacer structure, further improving the yield of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] A liquid crystal display panel is composed of a color filter substrate, a thin film transistor substrate, liquid crystal sandwiched between the color filter substrate and the thin film transistor substrate, and a sealant frame. Among them, the liquid crystal display panel further includes spacers for maintaining the cell thickness.

[0003] However, due to movement of the spacers caused by support or use during the process, the spacers are likely to scratch the film layers inside the liquid crystal display panel, thereby affecting the display effect. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device, which can avoid the support pillars from scratching the film layers and improve the yield rate of the second spacer structure.

[0005] Embodiments of the present invention provide a display panel, which includes:

[0006] An array substrate;

[0007] A counter substrate, which is disposed opposite to the array substrate;

[0008] Support pillars, which are disposed between the array substrate and the counter substrate;

[0009] Wherein, the array substrate includes a first substrate, a thin film transistor layer disposed on a side of the first substrate close to the counter substrate, a first spacer structure disposed on a side of the thin film transistor layer close to the counter substrate, a spacer layer disposed on a side of the first spacer structure close to the counter substrate, a first opening formed in the spacer layer and located on a side of the first spacer structure close to the counter substrate, and a second spacer structure. The second spacer structure fills the first opening and protrudes from a surface of the spacer layer close to the counter substrate. The support pillars are disposed between the counter substrate and the second spacer structure, and a depth of the first opening is less than a thickness of the spacer layer.

[0010] In an embodiment of the present invention, the spacer layer includes a color resist layer disposed on a side of the thin film transistor layer away from the first substrate and a planarization layer covering the color resist layer. The color resist layer includes a plurality of color resist blocks. The first spacer structure and the second spacer structure are disposed between adjacent color resist blocks, and the first opening is formed in the planarization layer.

[0011] In an embodiment of the present invention, the opposing substrate includes a second substrate and a black matrix layer disposed on a side of the second substrate close to the array substrate, and the first spacer structure and the second spacer structure are orthogonally projected on the second substrate within the orthographic projection of the black matrix layer on the second substrate.

[0012] In an embodiment of the present invention, the support pillar is disposed on a side of the black matrix layer away from the second substrate and is located between the black matrix layer and the second spacer structure.

[0013] In an embodiment of the present invention, the array substrate further includes a light-shielding layer disposed on a side of the color-resist layer away from the thin-film transistor layer. The light-shielding layer includes a plurality of first light-shielding portions arranged along a first direction and extending along a second direction, the first direction intersects with the second direction, the black matrix layer includes a plurality of second light-shielding portions arranged along the second direction and extending along the first direction, and the plurality of first light-shielding portions and the plurality of second light-shielding portions intersect to define a plurality of sub-pixel regions, and the plurality of color-resist blocks are disposed in the plurality of sub-pixel regions.

[0014] In an embodiment of the present invention, the material of the light-shielding layer is a conductive material, or the material of the light-shielding layer is the same as the material of the black matrix layer.

[0015] In an embodiment of the present invention, the thin-film transistor layer includes a plurality of data lines arranged along the first direction and extending along the second direction, and a plurality of scan lines arranged along the second direction and extending along the first direction. The orthographic projection of the data lines on the first substrate is located within the orthographic projection of the first light-shielding portions on the first substrate, and the orthographic projection of the scan lines on the first substrate is located within the orthographic projection of the second light-shielding portions on the first substrate.

[0016] In an embodiment of the present invention, the array substrate further includes a third spacer structure disposed between the thin-film transistor layer and the spacer layer, a second opening formed in the spacer layer and located on a side of the third spacer structure close to the opposing substrate, and a fourth spacer structure. The fourth spacer structure is filled in the second opening, and the surface of the fourth spacer structure close to the opposing substrate does not extend beyond the surface of the spacer layer close to the opposing substrate.

[0017] In an embodiment of the present invention, the thin-film transistor layer further includes a plurality of thin-film transistors disposed on the first substrate and corresponding to the plurality of sub-pixel regions. The plurality of thin-film transistors include a first thin-film transistor, and the first thin-film transistor includes a first active layer, a first gate, and a first source and a first drain respectively connected to both sides of the first active layer. One end of the first drain is connected to the first active layer, and the other end extends to the surface of the first spacer structure away from the first substrate side.

[0018] In an embodiment of the present invention, the plurality of thin-film transistors further include a second thin-film transistor. The second thin-film transistor includes a second active layer, a third gate, and a second source and a second drain respectively connected to both sides of the second active layer. One end of the second drain is connected to the second active layer, and the other end extends to the surface of the third spacer structure away from the first substrate side.

[0019] In an embodiment of the present invention, the array substrate further includes a first electrode layer disposed on the side of the spacer layer away from the thin-film transistor layer. The first electrode layer includes a first electrode connected to the first thin-film transistor and a second electrode connected to the second thin-film transistor. The plurality of sub-pixel regions include a first sub-pixel region corresponding to the first thin-film transistor and a second sub-pixel region corresponding to the second thin-film transistor;

[0020] Wherein, one end of the first electrode extends into the first opening and is connected to the first drain, and the other end extends into the first sub-pixel region, and the second spacer structure is located on the side of the first electrode away from the first substrate;

[0021] One end of the second electrode extends into the second opening and is connected to the second drain, and the other end extends into the second sub-pixel region, and the fourth spacer structure is located on the side of the second electrode away from the first substrate.

[0022] In an embodiment of the present invention, the color of the color-resist block in the first sub-pixel region is blue, and the color of the color-resist block in the second sub-pixel region is red or green.

[0023] In an embodiment of the present invention, the array substrate further includes:

[0024] A second electrode layer disposed on the side of the first electrode layer away from the spacer layer;

[0025] An insulating layer disposed on the side of the second electrode layer away from the spacer layer;

[0026] A third electrode layer, disposed on a side of the insulating layer away from the second electrode layer;

[0027] Wherein, the first electrode layer is connected to the second electrode layer and forms a storage capacitor structure with the third electrode layer.

[0028] In an embodiment of the present invention, the spacer layer covers a part of the first spacer structure, a pore diameter of the first opening near a side of the first spacer structure is smaller than a width of the first spacer structure in a direction parallel to the first substrate, and the first opening and the color resist block are arranged at intervals.

[0029] In an embodiment of the present invention, materials of the first spacer structure and the second spacer structure both include organic materials.

[0030] According to the above object of the present invention, an embodiment of the present invention provides a display device, the display device includes the display panel and a backlight module, and the display panel is disposed on a light-emitting side of the backlight module.

[0031] Advantages of the present invention: After forming the first opening of the spacer layer, the present invention forms a second spacer structure protruding from a surface of the spacer layer, and the second spacer structure is correspondingly arranged with the support column. Further, a film layer around the second spacer structure is farther away from the support column in a thickness direction of the display panel, which can prevent the film layer around the second spacer structure from being scratched due to movement of the support column, and ensures a yield rate and a display effect of the display panel; further, by disposing the first spacer structure below the first opening, a depth of the first opening can be made smaller than a thickness of the spacer layer, a thickness of the second spacer structure during film deposition is reduced, and an etching residue phenomenon caused by too thick a thickness of the second spacer structure is avoided, further improving the yield rate of the display panel. Description of the Drawings

[0032] The following combines the drawings and details the specific embodiments of the present invention, and the technical solutions and other beneficial effects of the present invention will be obvious.

[0033] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0034] Figure 2 Corresponding to an embodiment of the present invention Figure 1 A size identification diagram;

[0035] Figure 3 It is another schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0036] Figure 4Schematic diagram of a planar distribution of multiple sub-pixel regions in a display panel provided by an embodiment of the present invention;

[0037] Figure 5 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0038] Figure 6 Corresponding to an embodiment of the present invention Figure 5 A size marking diagram;

[0039] Figure 7 Another structural schematic diagram of a display panel provided by an embodiment of the present invention. Detailed implementation manners

[0040] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0041] The following disclosure provides many different implementation manners or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various implementation manners and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0042] Please refer to Figure 1 and Figure 2 , an embodiment of the present invention provides a display panel, which includes an array substrate 10, a counter substrate 20, and support columns 30.

[0043] Among them, the counter substrate 20 is disposed opposite to the array substrate 10; the support columns 30 are disposed between the array substrate 10 and the counter substrate 20.

[0044] Further, the array substrate 10 includes a first substrate 11, a thin film transistor layer 12 disposed on one side of the first substrate 11 close to the counter substrate 20, a first spacer structure 141 disposed on one side of the thin film transistor layer 12 close to the counter substrate 20, a spacer layer 13 disposed on one side of the first spacer structure 141 close to the counter substrate 20, a first opening 1301 formed in the spacer layer 13 and located on one side of the first spacer structure 141 close to the counter substrate 20, and a second spacer structure 142. The second spacer structure 142 fills the first opening 1301 and protrudes from the surface of the spacer layer 13 on the side close to the counter substrate 20. The support pillar 30 is disposed between the counter substrate 20 and the second spacer structure 142, and the depth L1 of the first opening 1301 is less than the thickness L2 of the spacer layer 13.

[0045] During the implementation and application process, in the embodiment of the present invention, after forming the first opening 1301 of the spacer layer 13, the second spacer structure 142 protruding from the surface of the spacer layer 13 is formed at the same time, and the second spacer structure 142 is correspondingly disposed with the support pillar 30. Furthermore, the film layer around the second spacer structure 142 is farther away from the support pillar 30 in the thickness direction of the display panel, which can prevent the film layer around the second spacer structure 142 from being scratched due to the movement of the support pillar 30, ensuring the yield and display effect of the display panel; further, in the embodiment of the present invention, by disposing the first spacer structure 141 below the first opening 1301, the depth L1 of the first opening 1301 can be made less than the thickness L2 of the spacer layer 13, reducing the thickness of the second spacer structure 142 during film deposition, and avoiding the phenomenon of etching residue due to the too thick thickness of the second spacer structure 142 during film deposition, further improving the yield of the display panel.

[0046] Specifically, in an embodiment of the present invention, please refer to Figure 1 , Figure 2 and Figure 3 , the display panel provided by the embodiment of the present invention includes an array substrate 10 and a counter substrate 20 disposed opposite to each other, a liquid crystal layer (not shown in the figure) disposed between the array substrate 10 and the counter substrate 20, and support pillars 30 disposed between the array substrate 10 and the counter substrate 20, and the support pillars 30 are used to maintain the cell thickness of the liquid crystal layer.

[0047] Among them, the array substrate 10 includes a first substrate 11, a thin film transistor layer 12 disposed on the first substrate 11, a spacer layer 13 disposed on the thin film transistor layer 12, a first electrode layer 16 disposed on the spacer layer 13, a second electrode layer 171 disposed on the first electrode layer 16, an insulating layer 173 disposed on the second electrode layer 171, and a third electrode layer 172 disposed on the insulating layer 173, and the counter substrate 20 is located on the side of the third electrode layer 172 away from the first substrate 11.

[0048] Furthermore, the thin film transistor layer 12 includes a plurality of thin film transistors disposed on the first substrate 11 and a plurality of interlayer insulating layers covering the thin film transistors. Among them, the display panel includes a display area 101 and a non-display area 102 adjacent to the display area 101, and the plurality of thin film transistors include a first thin film transistor 121 and a second thin film transistor 122 disposed in the display area 101, and a third thin film transistor 129 disposed in the non-display area 102; the plurality of interlayer insulating layers include a first interlayer insulating layer 123, a second interlayer insulating layer 124, a third interlayer insulating layer 125, a fourth interlayer insulating layer 126, a fifth interlayer insulating layer 127, and a sixth interlayer insulating layer 128 sequentially disposed on the first substrate 11.

[0049] It should be noted that the display panel provided by the embodiment of the present invention is applicable to a low temperature poly-oxide (LTPO) display panel. Among them, the first thin film transistor 121 and the second thin film transistor 122 can be oxide thin film transistors, while the third thin film transistor 129 can be a low temperature polysilicon thin film transistor.

[0050] In one embodiment, the first thin film transistor 121 includes a first gate 1213 disposed on the second interlayer insulating layer 124 and covered by the third interlayer insulating layer 125, a first active layer 1211 disposed on the third interlayer insulating layer 125 and covered by the fourth interlayer insulating layer 126, a second gate 1214 disposed on the fourth interlayer insulating layer 126 and covered by the fifth interlayer insulating layer 127, a first source 1212 disposed on the fifth interlayer insulating layer 127 and covered by the sixth interlayer insulating layer 128, and a first drain 1215. Among them, the first gate 1213 and the second gate 1214 are respectively located on the upper and lower sides of the first active layer 1211 and are disposed corresponding to the channel region of the first active layer 1211. The first source 1212 and the first drain 1215 are respectively connected to both sides of the first active layer 1211, and the connection positions are respectively located on the opposite sides of the channel region.

[0051] The second thin film transistor 122 includes a third gate 1223 disposed on the second interlayer insulating layer 124 and covered by the third interlayer insulating layer 125, a second active layer 1221 disposed on the third interlayer insulating layer 125 and covered by the fourth interlayer insulating layer 126, a fourth gate 1224 disposed on the fourth interlayer insulating layer 126 and covered by the fifth interlayer insulating layer 127, a second source 1222 disposed on the fifth interlayer insulating layer 127 and covered by the sixth interlayer insulating layer 128, and a second drain 1225. The third gate 1223 and the fourth gate 1224 are respectively located on the upper and lower sides of the second active layer 1221 and are disposed corresponding to the channel region of the second active layer 1221. The second source 1222 and the second drain 1225 are respectively connected to both sides of the second active layer 1221, and the connection positions are respectively located on the opposite sides of the channel region.

[0052] The spacer layer 13 includes a color resist layer 131 disposed on the side of the thin film transistor layer 12 away from the first substrate 11, a planarization layer 132 covering the color resist layer 131, a first interlayer dielectric layer 133 disposed on the side of the planarization layer 132 away from the color resist layer 131, and a second interlayer dielectric layer 134 disposed on the side of the first interlayer dielectric layer 133 away from the planarization layer 132.

[0053] Among them, please refer to Figure 1 , Figure 3 and Figure 4 . The display panel includes a plurality of sub-pixel regions distributed in the display area 101, and the color resist layer 131 includes a plurality of color resist blocks 1311 respectively located in the plurality of sub-pixel regions. In an embodiment of the present invention, the array substrate 10 further includes a light-shielding layer 19 disposed on the side of the color resist layer 131 away from the thin film transistor layer 12, and the counter substrate 20 further includes a second substrate 21 and a black matrix layer 22 disposed on the side of the second substrate 21 close to the array substrate 10. The light-shielding layer 19 includes a plurality of first light-shielding portions 191 arranged along the first direction X and extending along the second direction Y, and the first direction X intersects the second direction Y. The black matrix layer 22 includes a plurality of second light-shielding portions 221 arranged along the second direction Y and extending along the first direction X, and the plurality of first light-shielding portions 191 and the plurality of second light-shielding portions 221 intersect to define a plurality of sub-pixel regions. Among them, the plurality of sub-pixel regions may include a first sub-pixel region 1011 corresponding to the first thin film transistor 121 and a second sub-pixel region 1012 corresponding to the second thin film transistor 122.

[0054] In one embodiment, the first direction X is perpendicular to the second direction Y.

[0055] In one embodiment, the array substrate 10 further includes a plurality of data lines (not shown in the figure) arranged along the first direction X and extending along the second direction Y, and a plurality of scan lines (not shown in the figure) arranged along the second direction Y and extending along the first direction X. The orthographic projection of the data lines on the first substrate 11 is located within the orthographic projection of the first light-shielding portion 191 on the first substrate 11, and the orthographic projection of the scan lines on the first substrate 11 is located within the orthographic projection of the second light-shielding portion 221 on the first substrate 11. In the embodiment of the present invention, by respectively disposing the light-shielding components between adjacent sub-pixel regions on the array substrate 10 and the counter substrate 20, it is possible to avoid the concentrated setting of the light-shielding components on the same film layer of the same substrate, thereby reducing the spatial conflict between the film layer processes.

[0056] Specifically, in a corresponding first thin-film transistor 121 and a first sub-pixel region 1011, as Figure 1 shown, the array substrate 10 further includes a first spacer structure 141 and a third interlayer dielectric layer 15 disposed between the thin-film transistor layer 12 and the spacer layer 13, and the first spacer structure 141 protrudes from the surface of the third interlayer dielectric layer 15 on the side away from the first substrate 11. The first spacer structure 141 is correspondingly located on the side of the first thin-film transistor 121 away from the first substrate 11, and the spacer layer 13 is disposed on the side of the first spacer structure 141 away from the first substrate 11.

[0057] A first opening 1301 is provided in the spacer layer 13, and the first opening 1301 is located on the side of the first spacer structure 141 away from the first substrate 11. The bottom of the first opening 1301 exposes a part of the upper surface of the first spacer structure 141. Since the first spacer structure 141 is disposed below the first opening 1301, the depth L1 of the first opening 1301 is less than the thickness L2 of the spacer layer 13; and the array substrate 10 further includes a second spacer structure 142 disposed on the side of the first spacer structure 141 away from the first substrate 11, and the second spacer structure 142 fills the first opening 1301 and protrudes from the surface of the spacer layer 13 on the side away from the thin-film transistor layer 12, that is, the second spacer structure 142 forms a boss at the surface of the second interlayer dielectric layer 134 on the side away from the thin-film transistor layer 12, and the support pillar 30 is disposed between the second spacer structure 142 and the counter substrate 20. Therefore, the film layers around the second spacer structure 142 are farther away from the support pillar 30 in the thickness direction of the display panel, which can prevent the film layers around the second spacer structure 142 from being scratched due to the movement of the support pillar 30, ensuring the yield and display effect of the display panel.

[0058] In one embodiment, the materials of the first spacer structure 141 and the second spacer structure 142 both include organic materials and may be the same as the material of the planarization layer 132. In the embodiment of the present invention, by disposing the first spacer structure 141 below the first opening 1301, the depth L1 of the first opening 1301 can be made smaller than the thickness L2 of the spacer layer 13, reducing the depth L1 of the first opening 1301. Furthermore, the thickness of the second spacer structure 142 during film deposition can be reduced, avoiding the phenomenon of etching residue caused by the too thick thickness of the second spacer structure 142 during film deposition, so as to ensure that the second spacer structure 142 can smoothly form a boss on the surface of the spacer layer 13 away from the thin film transistor layer 12, further improving the yield rate of the display panel.

[0059] Furthermore, one end of the first drain 1215 of the first thin film transistor 121 passes through the sixth interlayer insulating layer 128, the fifth interlayer insulating layer 127, and the fourth interlayer insulating layer 126 to be connected to the first active layer 1211, and the other end extends to the surface of the first spacer structure 141 away from the first substrate 11. The first electrode layer 16 includes a first electrode 161. One end of the first electrode 161 extends into the first opening 1301 to be connected to the first drain 1215, and the other end extends into the first sub-pixel region 1011 corresponding to the first thin film transistor 121 and can be reused as a pixel electrode. Moreover, the portion of the second spacer structure 142 filled in the first opening 1301 covers the first electrode 161 in the first opening 1301, that is, the second spacer structure 142 is located on the side of the first electrode 161 away from the first substrate 11.

[0060] It should be noted that the color resist block 1311 located in the first sub-pixel region 1011 also fills the contact hole between the first drain 1215 and the first active layer 1211 to avoid a concave film morphology at the contact hole.

[0061] Continuing from the above, in the embodiment of the present invention, on the basis of filling the first opening 1301 with the second spacer structure 142 to improve the film layer morphology, the second spacer structure 142 is used to simultaneously form a boss protruding from the surface of the spacer layer 13, and the support column 30 is disposed at the corresponding position of the boss, so as to prevent the support column 30 from scratching the film layer of the array substrate 10 other than the boss due to movement. That is, in the embodiment of the present invention, while improving the yield of the display panel, the process of filling the first opening 1301 and forming the boss is combined. At the same time, the first opening 1301 is a contact hole between the first electrode 161 and the first drain 1215. Since there is a planarization layer 132 and a color resist layer 131 between the first electrode 161 and the first drain 1215, the distance that the contact hole needs to pass through is relatively large. However, a first spacer structure 141 is disposed under the first opening 1301 to reduce the depth L1 of the first opening 1301 and avoid the phenomenon of residue of the second spacer structure 142 during the etching process due to the large thickness to be deposited. Therefore, in the embodiment of the present invention, by combining the setting of the first spacer structure 141 under the first opening 1301, the filling of the first opening 1301 with the second spacer structure 142 and the protrusion of the second spacer structure 142 from the surface of the spacer layer 13, and the setting of the support column 30 between the second spacer structure 142 and the counter substrate 20, the yield of the display panel and the display effect can be effectively improved on the basis of forming the boss.

[0062] With the improvement of the resolution of the display panel, the available space in the display panel is getting smaller and smaller, and the aperture of the contact hole between the drain and the pixel electrode is also small, which increases the etching difficulty. Therefore, in the related art, there will be a phenomenon that the contact hole is not completely etched, or the contact hole exposes the adjacent color resist block 1311 due to over-etching. However, in the embodiment of the present invention, by setting the first spacer structure 141 to reduce the depth of the first opening 1301, the depth to be etched in the planarization layer 132 is reduced, and it can be avoided that the first opening 1301 is not completely etched or over-etched, resulting in the exposure of the color resist block 1311 adjacent to the first opening 1301. That is, the first opening 1301 in the embodiment of the present invention is disposed in the planarization layer 132, the first interlayer dielectric layer 133 and the second interlayer dielectric layer 134 and is spaced apart from the color resist block 1311. The yield of the display panel is improved, and the display panel provided by the embodiment of the present invention can achieve a higher resolution.

[0063] In one embodiment, the support pillar 30 is disposed between the black matrix layer 22 and the second spacer structure 142. The orthographic projection of the support pillar 30 on the first substrate 11 is located within the orthographic projection of the black matrix layer 22 on the first substrate 11. The orthographic projections of the first opening 1301, the first spacer structure 141, and the second spacer structure 142 on the first substrate 11 are all located within the orthographic projection of the black matrix layer 22 on the first substrate 11. The aperture of the first opening 1301 on the side close to the first spacer structure 141 is smaller than the width of the first spacer structure 141 in the direction parallel to the first substrate 11.

[0064] In one embodiment, the second electrode layer 171 is connected to the first electrode layer 16 and is disposed opposite to the third electrode layer 172 to form a storage capacitor structure. Specifically, the second electrode layer 171 includes a third electrode connected to the first electrode 161. The first electrode 161 is connected to the third electrode, and together with the third electrode layer 172, they form a storage capacitor structure. In the embodiment of the present invention, by adding the second electrode layer 171 connected to the first electrode layer 16, and the second electrode layer 171 is closer to the third electrode layer 172 than the first electrode layer 16, the capacitance of the storage capacitor structure can be enhanced.

[0065] In addition, the first electrode 161 and the third electrode layer 172 are stacked to serve as a pixel electrode, and the third electrode layer 172 is a common electrode. After voltages are applied to the first electrode 161, the third electrode, and the third electrode layer 172, an electric field can be generated to control the deflection of liquid crystal molecules in the liquid crystal layer.

[0066] In one embodiment, the material of the light-shielding layer 19 is a conductive material. The light-shielding layer 19 further includes a connection portion 192 disposed in the non-display area 102. By changing the wiring in the non-display area 102 to input an electrical signal to the connection portion 192, and then applying the electrical signal to the first light-shielding portion 191, the static electricity generated in the array substrate 10 can be released, and a stable electrical signal can be applied to the first light-shielding portion 191 to prevent large fluctuations in the electrical signal in the first light-shielding portion 191 from interfering with the signal transmission in the array substrate 10.

[0067] Optionally, the voltage signal applied to the first light-shielding portion 191 is greater than or equal to -500 mA and less than or equal to 500 mA.

[0068] In addition, in a corresponding second thin-film transistor 122 and a second sub-pixel region 1012, such as Figure 3As shown, the array substrate 10 further includes a third spacer structure 143 disposed on a side of the second thin film transistor 122 away from the first substrate 11, a second opening 1302 disposed in the spacer layer 13 and on a side of the third spacer structure 143 away from the first substrate 11, and a fourth spacer structure 144.

[0069] The second opening 1302 is disposed in the planarization layer 132 and is spaced apart from the color resist block 1311, and the depth L1 of the second opening 1302 is less than the thickness L2 of the spacer layer 13. The fourth spacer structure 144 is filled in the second opening 1302, and a side of the fourth spacer structure 144 away from the thin film transistor layer 12 does not extend beyond the surface of the spacer layer 13 away from the thin film transistor layer 12; and the support pillar 30 is not disposed in the area corresponding to the fourth spacer structure 144.

[0070] It should be noted that the orthographic projection of the second opening 1302 on the first substrate 11, the orthographic projection of the third spacer structure 143 on the first substrate 11, and the orthographic projection of the fourth spacer structure 144 on the first substrate 11 are all located within the orthographic projection of the black matrix layer 22 on the first substrate 11. Among them, the aperture of the second opening 1302 on a side close to the third spacer structure 143 is smaller than the width of the third spacer structure 143 in a direction parallel to the first substrate 11.

[0071] Among them, the first electrode layer 16 includes a second electrode 162, and the second electrode layer 171 includes a fourth electrode. One end of the second drain 1225 passes through the sixth interlayer insulating layer 128, the fifth interlayer insulating layer 127, and the fourth interlayer insulating layer 126 to be connected to the second active layer 1221, and the other end extends to the surface of the third spacer structure 143 away from the thin film transistor layer 12. One end of the second electrode 162 extends into the second opening 1302 to be connected to the second drain 1225, and the other end extends into the second sub-pixel region 1012 corresponding to the second thin film transistor 122 and can be reused as a pixel electrode; and a part of the fourth spacer structure 144 filled in the first opening 1301 covers the second electrode 162 in the second opening 1302, that is, the fourth spacer structure 144 is located on a side of the second electrode 162 away from the first substrate 11.

[0072] It should be noted that the color resist block 1311 located in the second sub-pixel region 1012 also fills the contact hole between the second drain 1225 and the second active layer 1221 to avoid a concave film morphology at the contact hole.

[0073] It can be understood that in the embodiment of the present invention, due to the arrangement of the first spacer structure 141 and the third spacer structure 143, the depths of the first opening 1301 and the second opening 1302 can be reduced, and further, the probability of breakage of the first electrode 161 and the second electrode 162 due to a long overlapping distance can be reduced.

[0074] In one embodiment, the color of the color resist block 1311 in the first sub-pixel region 1011 is blue, and the color of the color resist block 1311 in the second sub-pixel region 1012 is red or green; and the material of the blue color resist is less likely to be exposed and developed compared to the materials of the red color resist and the green color resist. Therefore, compared with the red color resist block and the green color resist block, a larger space is usually reserved around the corresponding region of the blue color resist block to etch and form the blue color resist block. Since the support pillar 30 also needs to occupy a certain space, setting the blue color resist block in the first sub-pixel region 1011 is more conducive to reserving space for setting the support pillar 30.

[0075] Continuing from the above, in the embodiment of the present invention, after forming the first opening 1301 of the spacer layer 13, a second spacer structure 142 protruding from the surface of the spacer layer 13 is formed at the same time, and the second spacer structure 142 is correspondingly arranged with the support pillar 30. Furthermore, the film layer around the second spacer structure 142 is farther away from the support pillar 30 in the thickness direction of the display panel, which can prevent the film layer around the second spacer structure 142 from being scratched due to the movement of the support pillar 30, ensuring the yield and display effect of the display panel; further, in the embodiment of the present invention, a first spacer structure 141 is arranged below the first opening 1301, so that the depth L1 of the first opening 1301 is less than the thickness L2 of the spacer layer 13, reducing the thickness of the second spacer structure 142 during film deposition, and avoiding the phenomenon of etching residue due to the too thick thickness of the second spacer structure 142 during film deposition, further improving the yield of the display panel.

[0076] In another embodiment of the present invention, please refer to Figure 5 、 Figure 6 and Figure 7 . The difference between this embodiment and the embodiments shown in Figure 1 、 Figure 2 and Figure 3 is that the material of the light-shielding layer 19 is the same as that of the black matrix layer 22, and the light-shielding layer 19 includes a plurality of first light-shielding portions 191 arranged along the first direction X and extending along the second direction Y, and the first light-shielding portions 191 are arranged in the color resist layer 131 and located between adjacent color resist blocks 1311, and the planarization layer 132 covers the plurality of color resist blocks 1311 and the first light-shielding portions 191.

[0077] In this embodiment, the spacer layer 13 includes a color resist layer 131 and a planarization layer 132. The first opening 1301 is formed in the planarization layer 132. The second spacer structure 142 is filled in the first opening 1301 and protrudes from the surface of the planarization layer 132 on the side away from the thin film transistor layer 12. The second opening 1302 is formed in the planarization layer 132. The fourth spacer structure 144 is filled in the second opening 1302 and does not exceed the surface of the planarization layer 132 on the side away from the thin film transistor layer 12. The first electrode layer 16 is disposed on the surface of the planarization layer 132 and extends into the first opening 1301 or the second opening 1302.

[0078] It should be noted that in this embodiment, the light-shielding layer 19 is disposed between adjacent color resist blocks 1311. Thus, compared with the Figure 1 , Figure 2 and Figure 3 embodiments shown, the setting of the first interlayer dielectric layer 133 and the second interlayer dielectric layer 134 can be reduced, the thickness of the array substrate 10 can be decreased, and the thickness of the display panel can be decreased.

[0079] Continuing from the above, in the embodiment of the present invention, after forming the first opening 1301 of the spacer layer 13, the second spacer structure 142 protruding from the surface of the spacer layer 13 is formed at the same time, and the second spacer structure 142 is correspondingly disposed with the support column 30. Thus, the film layers around the second spacer structure 142 are farther away from the support column 30 in the thickness direction of the display panel, which can prevent the film layers around the second spacer structure 142 from being scratched due to the movement of the support column 30, ensuring the yield and display effect of the display panel. Further, in the embodiment of the present invention, by disposing the first spacer structure 141 below the first opening 1301, the depth L1 of the first opening 1301 can be made smaller than the thickness L2 of the spacer layer 13, reducing the thickness of the second spacer structure 142 during film deposition, and avoiding the phenomenon of etching residue due to the too thick thickness of the second spacer structure 142 during film deposition, further improving the yield of the display panel.

[0080] In addition, the embodiment of the present invention provides a display device, which includes the display panel described in the above embodiment.

[0081] In one embodiment, the display device may further include a backlight module, and the display panel is disposed on the light-emitting side of the backlight module.

[0082] Since the display device provided by the embodiment of the present invention has the same display panel as that in the above embodiment, the display device provided by the embodiment of the present invention has the same beneficial effects as those of the display panel described in the above embodiment, which will not be elaborated here.

[0083] In one embodiment, the display device may include a mobile phone, a television, a tablet, a computer, or a VR device.

[0084] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0085] The above has introduced in detail a display panel and a display device provided by an embodiment of the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present invention; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, it includes: an array substrate; a counter substrate, which is disposed opposite to the array substrate; support pillars, which are disposed between the array substrate and the counter substrate; wherein, the array substrate includes a first substrate, a thin film transistor layer disposed on a side of the first substrate close to the counter substrate, a first spacer structure disposed on a side of the thin film transistor layer close to the counter substrate, a spacer layer disposed on a side of the first spacer structure close to the counter substrate, a first opening formed in the spacer layer and located on a side of the first spacer structure close to the counter substrate, and a second spacer structure, the second spacer structure fills the first opening and protrudes from a surface of the spacer layer close to the counter substrate, the support pillars are disposed between the counter substrate and the second spacer structure, and a depth of the first opening is less than a thickness of the spacer layer; the spacer layer includes a color filter layer disposed on a side of the thin film transistor layer away from the first substrate, the color filter layer includes a plurality of color filter blocks, and the first spacer structure and the second spacer structure are disposed between adjacent color filter blocks.

2. The display panel according to claim 1, characterized in that, the spacer layer includes a planarization layer covering the color filter layer, and the first opening is formed in the planarization layer.

3. The display panel according to claim 1, characterized in that, the counter substrate includes a second substrate and a black matrix layer disposed on a side of the second substrate close to the array substrate, and a positive projection of the first spacer structure and the second spacer structure on the second substrate is located within a positive projection of the black matrix layer on the second substrate.

4. The display panel according to claim 3, characterized in that, the support pillars are disposed on a side of the black matrix layer away from the second substrate and are located between the black matrix layer and the second spacer structure.

5. The display panel according to claim 3, characterized in that, the array substrate further includes a light shielding layer disposed on a side of the color filter layer away from the thin film transistor layer, the light shielding layer includes a plurality of first light shielding portions arranged along a first direction and extending along a second direction, the first direction intersects with the second direction, the black matrix layer includes a plurality of second light shielding portions arranged along the second direction and extending along the first direction, and the plurality of first light shielding portions and the plurality of second light shielding portions intersect with each other to define a plurality of sub-pixel regions, and the plurality of color filter blocks are disposed in the plurality of sub-pixel regions.

6. The display panel according to claim 5, characterized in that, a material of the light shielding layer is a conductive material, or a material of the light shielding layer is the same as a material of the black matrix layer.

7. The display panel according to claim 5, characterized in that, The thin film transistor layer includes a plurality of data lines arranged along the first direction and extending along the second direction, and a plurality of scan lines arranged along the second direction and extending along the first direction. The orthographic projection of the data lines on the first substrate is located within the orthographic projection of the first light-shielding portion on the first substrate, and the orthographic projection of the scan lines on the first substrate is located within the orthographic projection of the second light-shielding portion on the first substrate.

8. The display panel according to any one of claims 5 to 7, wherein, the array substrate further includes a third spacer structure disposed between the thin film transistor layer and the spacer layer, a second opening formed in the spacer layer and located on a side of the third spacer structure close to the counter substrate, and a fourth spacer structure, and the fourth spacer structure fills the second opening, and a surface of the fourth spacer structure close to the counter substrate does not extend beyond a surface of the spacer layer close to the counter substrate.

9. The display panel according to claim 8, wherein, the thin film transistor layer further includes a plurality of thin film transistors disposed on the first substrate and corresponding to a plurality of the sub-pixel regions. The plurality of thin film transistors include a first thin film transistor, and the first thin film transistor includes a first active layer, a first gate, and a first source and a first drain respectively connected to two sides of the first active layer. One end of the first drain is connected to the first active layer, and the other end extends to a surface of the first spacer structure away from the first substrate.

10. The display panel according to claim 9, wherein, the plurality of thin film transistors further includes a second thin film transistor, and the second thin film transistor includes a second active layer, a third gate, and a second source and a second drain respectively connected to two sides of the second active layer. One end of the second drain is connected to the second active layer, and the other end extends to a surface of the third spacer structure away from the first substrate.

11. The display panel according to claim 10, wherein, the array substrate further includes a first electrode layer disposed on a side of the spacer layer away from the thin film transistor layer. The first electrode layer includes a first electrode connected to the first thin film transistor and a second electrode connected to the second thin film transistor. The plurality of sub-pixel regions include a first sub-pixel region corresponding to the first thin film transistor and a second sub-pixel region corresponding to the second thin film transistor; wherein, one end of the first electrode extends into the first opening and is connected to the first drain, and the other end extends into the first sub-pixel region, and the second spacer structure is located on a side of the first electrode away from the first substrate; one end of the second electrode extends into the second opening and is connected to the second drain, and the other end extends into the second sub-pixel region, and the fourth spacer structure is located on a side of the second electrode away from the first substrate.

12. The display panel according to claim 11, wherein, The color of the color filter block in the first sub-pixel region is blue, and the color of the color filter block in the second sub-pixel region is red or green.

13. The display panel according to claim 11, wherein, the array substrate further includes: a second electrode layer disposed on a side of the first electrode layer away from the spacer layer; an insulating layer disposed on a side of the second electrode layer away from the first electrode layer; a third electrode layer disposed on a side of the insulating layer away from the second electrode layer; wherein, the first electrode layer is connected to the second electrode layer and forms a storage capacitor structure with the third electrode layer.

14. The display panel according to claim 1, wherein, the spacer layer covers a part of the first spacer structure, the aperture of the first opening near the first spacer structure is smaller than the width of the first spacer structure in a direction parallel to the first substrate, and the first opening is spaced apart from the color filter block.

15. The display panel according to claim 1, wherein, the materials of the first spacer structure and the second spacer structure both include organic materials.

16. A display device, wherein, the display device includes the display panel according to any one of claims 1 to 15 and a backlight module, and the display panel is disposed on a light-emitting side of the backlight module.

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