A cross-clock domain processing device, processing method and chiplet integration system
By using local synchronous clock generation link and sampling synchronization circuit in the core-grain integrated system for cross-clock domain processing, the problems of data transmission delay and energy consumption between core-grain are solved, and low latency and high throughput are achieved Data transmission improves system performance.
Patent Information
- Application Number
- CN202410159864.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-04
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2044-02-04
AI Technical Summary
In the core-grain integrated system, the data transmission clock frequency mismatch between different core-grained particles, resulting in additional clock cycles required for cross-clock domain processing, which increases data transmission delay, making it difficult to meet the low-latency requirements of high-speed data transmission, and Increases energy consumption and reduces system performance.
The local co-frequency clock generation link and sampling synchronization circuit are adopted to generate local co-frequency clocks through a multi-phase reset generator and frequency divider for cross-clock processing, simplifying the data transmission path, reducing delays and hardware overhead.
It significantly reduces data delay, improves the throughput and robustness of data transmission between cores and particles, meets the needs of low latency, reduces hardware resources and energy consumption, and improves the performance of high-performance computing systems.
Smart Images
Figure CN117970994B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to a cross-clock domain processing device, a processing method and a core particle integration system. Background Art
[0002] As the requirements for computing power in high-performance computing continue to increase, a chiplet integrated system is needed to meet high-performance computing needs. In a chiplet integrated system, high-frequency data interaction is required between different chiplets to complete related calculations. However, the operating clock frequency of the chiplet integrated system is much lower than the data transmission rate of the chiplet high-speed data interface, and the system operating clock is not synchronized with the local high-speed serial clock.
[0003] Therefore, when the on-chip system needs to send or receive data, the data needs to be processed across clock domains between the system clock domain and the local clock domain. The cross-clock domain processing process requires clock synchronization, which takes extra clock cycles and significantly increases the delay of data in the transmission path, making it difficult to meet the low-latency requirements of high-speed data transmission between chiplets. At the same time, the larger data path delay will also increase the energy consumed in the data transmission process, thereby reducing the performance of the entire high-performance computing system. Summary of the invention
[0004] The object of the present invention is to provide a cross-clock domain processing device, a processing method and a chip integration system, which can simplify the structure of the chip integration system, improve the performance of the system, and meet the low latency requirements of data transmission between chiplets.
[0005] To achieve the above object, the present invention provides a cross-clock domain processing device, which at least includes:
[0006] A local same-frequency clock generation link divides the local high-frequency clock to generate a local same-frequency clock according to the phase control word; and
[0007] The sampling synchronization circuit is electrically connected to the output end of the local same-frequency generation link, uses the local same-frequency clock as the input clock or sampling clock, samples the input data, obtains the output data, and completes the cross-clock domain processing of the input data.
[0008] In one embodiment of the present invention, the local same-frequency clock generation link includes a multi-phase reset generator, and the multi-phase reset generator is driven by the local high-frequency clock and generates a phase-controlled reset signal according to the phase control word.
[0009] In an embodiment of the present invention, the local same-frequency clock generation link includes a frequency divider, and the frequency divider divides the high-frequency clock according to the phase-controlled reset signal to generate a local same-frequency clock.
[0010] In one embodiment of the present invention, the multi-phase reset generator includes:
[0011] A counter, inputting an asynchronous reset signal and the local high-frequency clock, and when the asynchronous reset signal is established, the counter counts under the drive of the high-frequency clock and outputs a plurality of bit counting results;
[0012] A plurality of XOR gates, one input end of each XOR gate is electrically connected to the output end of the counter, the other input end of each XOR gate is input with the phase control word, the plurality of XOR gates perform an XOR operation on each bit counting result output by the counter and the phase control word, and obtain a plurality of XOR operation results;
[0013] a multi-input AND gate, each input end of the multi-input AND gate being electrically connected to an output end of an XOR gate, the multi-input AND gate generating a phase-controlled clock according to the result of a plurality of XOR operations, and
[0014] A D flip-flop, wherein a clock input terminal of the D flip-flop is electrically connected to an output terminal of the multi-input AND gate, a data input terminal of the D flip-flop inputs the asynchronous reset signal, and the D flip-flop samples the asynchronous reset signal under the phase-controlled clock to obtain the phase-controlled reset signal.
[0015] In one embodiment of the present invention, the counter is a bit counter, and the number of bits of the counter is equal to or greater than the number of bits of the phase control word.
[0016] In one embodiment of the present invention, the number of the XOR gates is equal to or greater than the number of bits of the phase control word.
[0017] In an embodiment of the present invention, the number of inputs of the multi-input AND gate is equal to or greater than the number of bits of the phase control word.
[0018] The present invention also provides a cross-clock domain processing method, comprising the following steps:
[0019] According to the phase control word, the local high-frequency clock is divided to generate a local same-frequency clock; and
[0020] The local same-frequency clock is used as an input clock or a sampling clock to sample input data, obtain output data, and complete the cross-clock domain processing of the input data.
[0021] The present invention also provides a chiplet integration system, comprising a plurality of chiplets, wherein the cross-clock domain processing device as described above is arranged in a data transmission path of the chiplets, and the local same-frequency clock is used as a sampling clock of the sampling synchronization circuit.
[0022] The present invention also provides a chiplet integration system, comprising a plurality of chiplets, wherein the cross-clock domain processing device as described above is arranged in a data receiving path of the chiplet, and the local same-frequency clock is used as an input clock of the sampling synchronization circuit.
[0023] In summary, the cross-clock domain processing device, processing method and core grain integrated system provided by the present invention use a simple synchronous sampling circuit instead of a first-in first-out stack in the data path, which shortens the path of the data, significantly reduces the data delay, and also significantly reduces the hardware overhead. At the same time, a local same-frequency clock generation link composed of a multi-phase reset generator and a frequency divider is used, which can generate clocks of different phases under different configurations of the external phase control word, ensuring that the synchronization process of the synchronous sampling circuit meets the timing requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.
[0025] Figure 1 It is a schematic diagram of the structure of a cross-clock domain processing device in an embodiment.
[0026] Figure 2 It is a structural diagram of a cross-clock domain processing device in one embodiment of the present application.
[0027] Figure 3 It is a signal timing diagram of a cross-clock domain processing device in one embodiment of the present application.
[0028] Figure 4 yes Figure 2 A schematic diagram of the structure of a multi-phase reset generator in a cross-clock domain processing device.
[0029] Figure 5 It is a schematic diagram of the application of a cross-clock domain processing device in a data transmission path in one embodiment of the present application.
[0030] Figure 6 It is a schematic diagram of the application of the cross-clock domain processing device in a data receiving path in one embodiment of the present application.
[0031] Description of labels:
[0032] 101. Sampling synchronization circuit; 102. Local same-frequency clock generation link; 1021. Multi-phase reset generator; 1022. Frequency divider; 201. Counter; 202. XOR gate; 203. Multi-input AND gate; 204. D flip-flop. DETAILED DESCRIPTION
[0033] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0035] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
[0036] As the requirements for computing power of high-performance computing continue to increase, it is increasingly difficult for a single chip system to meet the performance requirements of high-performance computing. At the same time, the area of a single computing chip that can provide greater computing power is getting larger and larger, which poses a greater challenge to the yield of the chip. In this case, the solution of using a chip integration system to meet the challenges of high-performance computing has become an important means to solve the above problems. In the solution of the chip integration system, high-frequency data interaction is required between different chiplets to complete related calculations. Due to the large amount of calculation in high-performance computing, the amount of data transmission between chiplets is huge. In order to prevent data transmission from becoming a bottleneck for high-performance computing, the high-speed data interface between chiplets needs to meet the two requirements of high bandwidth and low latency. In order to achieve the high bandwidth requirements between chiplets, the high-speed data interface needs to transmit data at a higher rate on the interconnection line between chiplets, which can generally be as high as 16 to 32Gbps. However, the logic circuit in the chiplet is difficult to work at such a high clock frequency, so it is necessary to process high-speed signals in the physical layer circuit. When the system on chip needs to send high-speed data to the outside, the data needs to be sent from the system side through the physical layer circuit. When the system on chip needs to receive high-speed data from the outside, the data is transmitted back to the system from the outside through the physical circuit layer. Since the system clock and the local clock used by the physical layer circuit are usually not synchronized, when receiving and sending data, the data will undergo cross-clock domain processing between the system clock domain and the local clock domain of the physical layer circuit. The cross-clock domain processing of data requires clock synchronization, and the clock synchronization process will take additional clock cycles. The time for clock synchronization will significantly increase the delay of data in the transmission path, making it difficult to meet the low-delay requirements of high-speed data transmission between core particles. At the same time, the larger data path delay will also increase the energy consumed in the data transmission process, thereby reducing the performance of the entire high-performance computing system.
[0037] See also Figure 1As shown, in some embodiments, in order to realize cross-clock domain processing of data, a first-in, first-out (FIFO) stack is set in the high-speed data interface as a cross-clock domain processing device. On one side of the first-in, first-out stack, write data and write clock are input, and the write data is synchronized with the write clock. At the same time, the first-in, first-out stack also inputs the read clock and reads data under the read clock. After the first-in, first-out stack, the data is converted from the write clock domain to the read clock domain. When the first-in, first-out stack is configured on the sending path, the write clock is the system clock and the read clock is the local clock. When the first-in, first-out stack is configured on the data receiving path, the write clock is the local clock and the read clock is the system clock. And the write clock and the read clock of the first-in, first-out stack on the sending path and the receiving path are of the same frequency but different phases. However, a first-in-first-out stack is inserted between the logic layer and the electrical physical layer of the high-speed data interface, that is, the data is synchronized from the local clock domain where the electrical physical layer is located to the system clock domain where the logic layer is located, or the data is synchronized from the system clock domain where the logic layer is located to the local clock domain where the electrical physical layer is located. The method of using a first-in-first-out stack for clock synchronization requires at least 2 additional clock cycles, and the resulting delay overhead is large, which is difficult to meet the low-delay requirements of high-speed data transmission between core particles. The method of using a first-in-first-out stack for data cross-clock domain synchronization requires more hardware resources such as triggers, pointer generators and other circuit modules, which is not conducive to the demand for chip miniaturization and increases chip costs. In addition, inserting a first-in-first-out stack between the electrical physical layer and the logic layer requires adding more control signals between the electrical physical layer and the logic layer, which increases the complexity of the interface between the logic layer and the electrical physical layer, and is not conducive to the timing convergence of the logic layer, increases the design difficulty, and even limits the operating frequency of the logic layer, sacrificing system performance.
[0038] See also Figure 2 As shown, in one embodiment of the present invention, a cross-clock domain processing device is also provided, and the cross-clock domain processing device includes a sampling synchronization circuit 101 and a local same-frequency clock generation link 102. The sampling synchronization circuit 101 sets the sampling clock as needed, samples the input data, obtains the output data, matches the output data with the sampling clock, and completes the cross-clock domain processing of the input data. The local same-frequency clock generation link 102 generates a local same-frequency clock based on the local high-frequency clock as the sampling clock or input clock of the sampling synchronization circuit 101, and adjusts the phase difference between the sampling circuit input clock and the sampling clock to improve the throughput or robustness of the high-speed data interface.
[0039] See also Figure 2As shown, in one embodiment of the present invention, the local simultaneous clock generation link includes a multi-phase reset generator 1021 and a frequency divider 1022. Driven by the local high-frequency clock, the multi-phase reset generator 1021 generates a phase-controlled reset signal according to the input phase control word. The frequency divider 1022 is electrically connected to the output end of the multi-phase reset generator 1021, and divides the high-frequency clock according to the phase-controlled reset signal generated by the multi-phase reset generator 1021 to generate a local same-frequency clock. The local same-frequency clock is the same frequency as the system clock.
[0040] For details, please refer to Figure 2 and Figure 3 As shown, in one embodiment of the present invention, the multi-phase reset generator 1021 has two input signals, namely, a local high-frequency clock and a phase control word. The local high-frequency clock is a high-frequency clock whose frequency is an integer multiple of the frequency of the system clock, and the physical layer of the high-speed data interface works on the local high-frequency clock. The phase control word is a set of configuration signals, which can be dynamically configured by hardware or software, or can be used as a static configuration after initialization. The multi-phase reset generator 1021 can generate a phase-controlled reset signal according to the input phase control word under the drive of the local high-frequency clock. Figure 3 As shown, the phase-controlled reset signal is a signal that rises from a low level to a high level, and the phase-controlled reset signal can be established at the rising edge of the local high-frequency clock. That is, the rising edge of the phase-controlled reset signal can be located at any rising edge of the local high-frequency clock, which can be specifically controlled by the phase control word. That is, the position of the rising edge of the phase-controlled reset signal is determined by the value of the phase control word, and the phase of the local same-frequency clock is determined by controlling the rising edge position of the phase-controlled reset signal.
[0041] See also Figure 2 and Figure 4 As shown, in one embodiment of the present invention, the multi-phase reset generator 1021 includes a counter 201, a plurality of XOR gates 202, a multi-input AND gate 203 and a D flip-flop 204. The counter 201 is a bit counter 201, and the number of bits of the counter 201 is equal to the number of bits of the phase control word, or the number of bits of the counter 201 is greater than the number of bits of the phase control word. The number of XOR gates 202 is equal to the number of bits of the phase control word, or the number of XOR gates 202 is greater than the number of bits of the phase control word. The number of inputs of the multi-input AND gate 203 is equal to the number of bits of the phase control word, and the number of inputs of the multi-input AND gate 203 is greater than the number of bits of the phase control word. In a specific embodiment of the present invention, the number of bits of the phase control word is k, and 2 k ≥N, where N is the number of optional phases. For example, when k is equal to 3, there are 2 3phases are optional, that is, 8 phases are optional. At this time, the phase control word can be 0 to 7. When the number of bits of the phase control word is k, the multi-phase reset generator 1021 includes a k-bit counter 201, k XOR gates 202, a k-input AND gate and a D flip-flop 204.
[0042] See also Figure 4 As shown, in one embodiment of the present invention, the counter 201 inputs an asynchronous reset signal and a local high-frequency clock. One input end of each XOR gate 20 in the multiple XOR gates 202 is electrically connected to the output end of the counter 201, and the other input end is input with a phase control word. Each input end of the multi-input AND gate 203 is electrically connected to the output end of each XOR gate 202. The output end of the multi-input AND gate 203 is electrically connected to the clock input end of the D flip-flop 204, and the data input end of the D flip-flop 204 inputs an asynchronous reset signal. When the asynchronous reset signal is established, the counter 201 counts under the drive of the local high-frequency clock and outputs k-bit counting results, and each bit counting result is input into an AND gate. Then each counting result output by the counter 201 is XORed with the phase control word to obtain the results of k XOR operations. The results of the k XOR operations are input into the multi-input AND gate 203, and the multi-input AND gate 203 generates a phase-controlled clock according to the results of the multiple XOR operations. The phase-controlled clock output by the multi-input AND gate 203 is input to the clock input terminal of the D flip-flop 204, and the D flip-flop 204 samples the asynchronous reset signal under the phase-controlled clock, that is, obtains the phase-controlled reset signal. In summary, the multi-phase reset generator 1021 compares the counting result output by the counter 201 with the phase control word, generates a phase-controlled clock at the phase specified by the phase control word, and generates a phase-controlled reset signal at this clock. Specifically, when k is equal to 3, there are 8 phases to choose from, the phase control word can be 0 to 7, and when the phase control word is 4, it is necessary to generate a phase-controlled reset signal in the 5th phase. That is, when the counter 201 counts from 0 to 4, the phase-controlled clock generates a rising edge sampling asynchronous reset signal, that is, a high-level phase-controlled reset signal is generated in the 5th phase. The present application does not limit the specific form of the multi-phase reset generator 1021, and other multi-phase reset generators that can achieve this function can also be used.
[0043] See also Figure 2 and Figure 3 As shown, in one embodiment of the present invention, the input end of the frequency divider 1022 is electrically connected to the multi-phase reset generator 1021, and under the action of the phase-controlled reset signal, the local high-frequency clock is divided to generate a local same-frequency clock. Figure 3As shown, at the rising edge of the phase-controlled reset signal, the rising edge of the local same-frequency clock is generated, thereby generating the required local same-frequency clock. The local same-frequency clock obtained by the sampling method can be configured into N different phases for use by the sampling synchronization circuit 101. Among them, the phase control word can be set according to the required clock phase. It should be noted that the phase-controlled reset signal in this application is used to control the phase of the local same-frequency clock, and the division ratio of the local high-frequency clock and the local same-frequency clock is determined by other control signals.
[0044] See also Figure 5 and Figure 6 As shown, in one embodiment of the present invention, the cross-clock domain data processing method proposed by the present invention can be used in the data transmission path or the data receiving path. In the chiplet integrated system, when the method proposed by the present invention is used in the data transmission path, such as Figure 5 As shown, the input data of the sampling synchronization circuit 101 is the system data to be sent, and the input clock is synchronized with the system clock, and the system data to be sent is synchronized with the system clock. The local same-frequency clock generated by the local same-frequency clock generation link 102 is used as the sampling clock of the sampling synchronization circuit 101. The sampling synchronization circuit 101 uses the local same-frequency clock to sample and obtain local synchronization data for subsequent local data processing. Since the local same-frequency clock has N phases to choose from, the user can select the phase with smaller delay or the phase with the largest timing margin for sampling according to system requirements, which can improve the throughput or robustness of the high-speed data interface.
[0045] See also Figure 6 As shown, in one embodiment of the present invention, in a chiplet integrated system, when the method proposed by the present invention is used in a data receiving path. Figure 6 As shown, the input data of the sampling synchronization circuit 101 is local synchronization data, and the input clock is a local co-frequency clock, and the local synchronization data is synchronized with the local co-frequency clock. At this time, the system clock is used as the sampling clock of the sampling synchronization circuit 101 to sample the local synchronization data, thereby generating system data to be received that is synchronized with the system clock, and transmitting it to the system side for subsequent processing. Although the phase of the sampling clock of the sampling synchronization circuit 101 is determined, the input clock of the sampling synchronization circuit 101 can be selected from N phases, so the local synchronization data synchronized therewith can be switched among the N phases accordingly, ensuring the timing requirements of the system clock for its sampling. Similarly, the user can select a data phase with a smaller delay or a data phase with the largest timing margin for the system clock sampling according to system requirements, thereby improving the throughput or robustness of the high-speed data interface.
[0046] In summary, the cross-clock domain processing device, processing method and core grain integration system provided by the present invention include a local same-frequency clock generation link and a sampling synchronization circuit. Among them, the local same-frequency clock generation link divides the local high-frequency clock to generate a local same-frequency clock based on the phase control word. The sampling synchronization circuit uses the local same-frequency clock as the input clock or sampling clock, samples the input data, obtains the output data, and completes the cross-clock domain processing of the input data. And the phase of the output local same-frequency clock can be controlled by adjusting the phase control word input to the local same-frequency clock generation link, thereby adjusting the phase difference between the input clock and the sampling clock of the sampling circuit to improve the throughput or robustness of the high-speed data interface.
[0047] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A cross-clock domain processing device, characterized in that: At least: The local same-frequency clock generation link divides the local high-frequency clock to generate a local same-frequency clock according to the phase control word; as well as A sampling synchronization circuit is electrically connected to the output end of the local same-frequency generation link, uses the local same-frequency clock as the input clock or sampling clock, samples the input data, obtains the output data, and completes the cross-clock domain processing of the input data; Wherein, the local same-frequency clock generation link includes a multi-phase reset generator, and the multi-phase reset generator includes: A counter, inputting an asynchronous reset signal and the local high-frequency clock, and when the asynchronous reset signal is established, the counter counts under the drive of the high-frequency clock and outputs a plurality of bit counting results; A plurality of XOR gates, one input end of each XOR gate is electrically connected to the output end of the counter, the other input end of each XOR gate is input with the phase control word, the plurality of XOR gates perform an XOR operation on each bit counting result output by the counter and the phase control word, and obtain a plurality of XOR operation results; a multi-input AND gate, each input end of the multi-input AND gate being electrically connected to an output end of an XOR gate, the multi-input AND gate generating a phase-controlled clock according to the result of a plurality of XOR operations, and A D flip-flop, wherein a clock input terminal of the D flip-flop is electrically connected to an output terminal of the multi-input AND gate, a data input terminal of the D flip-flop inputs the asynchronous reset signal, and the D flip-flop samples the asynchronous reset signal under the phase-controlled clock to obtain a phase-controlled reset signal; Among them, the counter is a bit counter, and the number of bits of the counter is equal to or greater than the number of bits of the phase control word; the number of the XOR gates is equal to or greater than the number of bits of the phase control word; the number of inputs of the multi-input AND gate is equal to or greater than the number of bits of the phase control word.
2. The cross-clock domain processing device according to claim 1, characterized in that: The local same-frequency clock generation link includes a multi-phase reset generator. The multi-phase reset generator is driven by the local high-frequency clock and generates a phase-controlled reset signal according to the phase control word.
3. The cross-clock domain processing device according to claim 2, characterized in that: The local same-frequency clock generation link includes a frequency divider, and the frequency divider divides the high-frequency clock according to the phase-controlled reset signal to generate a local same-frequency clock.
4. A cross-clock domain processing method, characterized in that: The following steps are involved: According to the phase control word, the local high-frequency clock is divided to generate a local same-frequency clock; as well as Using the local same-frequency clock as the input clock or sampling clock, sampling the input data, obtaining the output data, and completing the cross-clock domain processing of the input data; Wherein, when generating the local same-frequency clock, a multi-phase reset generator is first used to generate a phase-controlled reset signal according to a phase control word, and the multi-phase reset generator includes: A counter, inputting an asynchronous reset signal and the local high-frequency clock, and when the asynchronous reset signal is established, the counter counts under the drive of the high-frequency clock and outputs a plurality of bit counting results; A plurality of XOR gates, one input end of each XOR gate is electrically connected to the output end of the counter, the other input end of each XOR gate is input with the phase control word, the plurality of XOR gates perform an XOR operation on each bit counting result output by the counter and the phase control word, and obtain a plurality of XOR operation results; a multi-input AND gate, each input end of the multi-input AND gate being electrically connected to an output end of an XOR gate, the multi-input AND gate generating a phase-controlled clock according to the result of a plurality of XOR operations, and A D flip-flop, wherein a clock input terminal of the D flip-flop is electrically connected to an output terminal of the multi-input AND gate, a data input terminal of the D flip-flop inputs the asynchronous reset signal, and the D flip-flop samples the asynchronous reset signal under the phase-controlled clock to obtain the phase-controlled reset signal; Among them, the counter is a bit counter, and the number of bits of the counter is equal to or greater than the number of bits of the phase control word; the number of the XOR gates is equal to or greater than the number of bits of the phase control word; the number of inputs of the multi-input AND gate is equal to or greater than the number of bits of the phase control word.
5. A core particle integration system, characterized in that: It comprises a plurality of core particles, wherein the cross-clock domain processing device as claimed in any one of claims 1 to 3 is arranged in the data transmission path of the core particles, and the local same-frequency clock is used as the sampling clock of the sampling synchronization circuit.
6. A core particle integration system, characterized in that: It comprises a plurality of core particles, wherein the cross-clock domain processing device as described in any one of claims 1 to 3 is arranged in the data receiving path of the core particles, and the local same-frequency clock is used as the input clock of the sampling synchronization circuit.