A computing device and information interaction method

Abstract

The application discloses a kind of computing device and information interaction method, it is related to computer technical field.Therein, the computing device includes: first chip, programmable device and flash memory, the programmable device is connected between the first chip and the flash memory;The programmable device receives the first operation command of the first chip after sending to the flash memory, the first operation command is translated into second operation command, and the second operation command is sent to the flash memory, and the second operation command is the operation command matched with the model of the flash memory.The programmable device plays the role of translation of operation command, can translate the operation command sent by the first chip into the operation command matched with the model of the flash memory, improve the compatibility between chip and flash memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a computing device and an information interaction method. BACKGROUND

[0002] At present, commonly used flash memories include Nor Flash and NAND Flash. The Nor Flash supports eXecute In Place (XIP), that is, firmware of a chip can be stored on the Nor Flash, and the firmware code can be directly executed on the Nor Flash without copying to the memory. The chip can read, erase or write data stored on the Flash by sending operation instructions to the Nor Flash.

[0003] However, at present, the number of manufacturers of the Nor Flash is large, and the driving instructions of the Nor Flash produced by different manufacturers are not completely universal. When the chip is used to access or erase data of the Nor Flash, in order to adapt the operation instructions sent by the chip to the Nor Flash to the Nor Flash of a new manufacturer or a new model, the firmware version of the chip needs to be constantly updated, otherwise the firmware of the old version will not be compatible with the Nor Flash of the new model. SUMMARY

[0004] In order to solve the above technical problems in the prior art, the embodiments of the present application provide a computing device and an information interaction method, which improve the compatibility between the chip and the flash memory.

[0005] In a first aspect, the embodiments of the present application provide a computing device, which comprises a first chip, a programmable device and a flash memory. The programmable device is connected between the first chip and the flash memory. After receiving a first operation command for the flash memory sent by the first chip, the programmable device translates the first operation command into a second operation command, and sends the second operation command to the flash memory, the second operation command being an operation command matched with the model of the flash memory.

[0006] The flash memory can be a Nor flash, and the Nor flash can store firmware of the first chip. According to the scheme provided in the embodiments of the present application, the first chip is no longer directly connected with the flash memory, but a programmable device is added between the first chip and the flash memory. The programmable device plays a role of translating operation commands, and translates the operation commands sent by the first chip into operation commands matching the model of the flash memory, so that the first chip can perform reading, writing, erasing and other operations on the flash memory, thereby the first chip can be compatible with flash memories of multiple models without upgrading firmware, and the selection of the flash memory is not limited.

[0007] The scheme of the embodiments of the present application decouples the firmware version of the chip and the model of the flash memory by using the programmable device, and the programmable device can support translation of operation commands of multiple firmware versions at the same time, and has better compatibility and inheritance.

[0008] In addition, the computing device can also update the firmware of the programmable device according to needs, increase the number of types of operation commands that can be translated by the programmable device, that is, the firmware of the programmable device can be updated to enable the programmable device to translate operation commands into operation commands matching the new model of the flash memory, further improve compatibility and inheritance, and alleviate the selection limitation of the flash memory.

[0009] In a possible implementation, the programmable device includes a plurality of translation channels, and the programmable device is specifically configured to determine a first translation channel matching the model of the flash memory, the first translation channel being one of the plurality of translation channels, and after receiving a first operation command for the flash memory sent by the first chip, the first operation command is translated into a second operation command by using the first translation channel.

[0010] In this implementation, the programmable device includes a plurality of translation channels, and the plurality of translation channels can respectively translate operation commands of multiple firmware versions, for example, the plurality of translation channels can include a first translation channel and a second translation channel, the first translation channel is configured to translate operation commands into operation commands matching a first model of the flash memory, and the second translation channel is configured to translate operation commands into operation commands matching a second model of the flash memory. The programmable device can determine a channel for translating operation commands according to the model of the flash memory before the first chip issues a first operation command.

[0011] In a possible implementation, the computing device further includes a management controller. The management controller is connected with the programmable device. The management controller is configured to update the firmware version of the programmable device to a first version, and add a first translation channel in the firmware of the first version.

[0012] In this implementation, the addition of the translation channel through the firmware update enables the programmable device to be compatible with the new type of flash memory while retaining the compatibility with the old type of flash memory. Even if the programmable device is connected to the old type of flash memory again, the firmware does not need to be updated again.

[0013] In a possible implementation, the computing device further includes a management controller. The management controller is connected to the programmable device. The management controller is configured to update the firmware version of the programmable device to the first version, and the firmware of the first version updates one of the plurality of translation channels to the first translation channel.

[0014] In this implementation, the replacement of the translation channel through the firmware update, i.e., replacing the unused translation channel with the required translation channel, can save the resources of the programmable device.

[0015] In a possible implementation, the management controller is connected to the programmable device through a Joint Test Action Group (JTAG) interface or a Serial Peripheral Interface (SPI) interface.

[0016] In a possible implementation, the computing device further includes a second chip. The programmable device is connected to the second chip. The programmable device is further configured to, after receiving a third operation command for the flash memory sent by the second chip, translate the third operation command into a fourth operation command using the first translation channel, and send the fourth operation command to the flash memory, the fourth operation command being an operation command matching the type of the flash memory.

[0017] In this implementation, different chips can send operation commands corresponding to different types of flash memory to the programmable device, i.e., the chip that issues the operation command to the programmable device can be replaced, but the flash memory connected to the programmable device does not need to be replaced. This enables the number of programmable devices to no longer correspond to the number of chips, reducing the number of programmable devices required and thereby reducing the hardware cost. In some special scenarios, for example, the first chip and the second chip are redundant chips in terms of function, but the firmware versions are different, resulting in different control commands issued. After applying the technical solutions of the embodiments of the present application, when the second chip is enabled after the first chip fails, the flash memory does not need to be replaced, but can be directly compatible.

[0018] In a possible implementation, the programmable device comprises a first multiplexer (MUX) and a second multiplexer (MUX), the first MUX is in communication with the first chip, and the second MUX is in communication with the flash memory. The programmable device is specifically configured to read a model number of the flash memory, determine a translation channel that matches the model number from a plurality of translation channels as a first translation channel, and generate a first translation channel switching instruction. The first translation channel switching instruction is used to instruct the first MUX and the second MUX to both communicate with the first translation channel. The first MUX and the second MUX are configured to both communicate with the first translation channel when the first translation channel switching instruction is received.

[0019] In a possible implementation, the first chip is any one of the following: a network card chip, a redundant array of independent disks (RAID) chip, a peripheral component interconnect express (PCIe) switch chip, a serial attached small computer system interface (SAS) host controller chip, a SAS expansion chip, a serial advanced technology attachment (SATA) host controller chip, a SATA expansion chip, a non-volatile memory express (NVMe) chip, and a central processing unit (CPU) chip.

[0020] The second chip can also be any one of the chip types described above.

[0021] In a possible implementation, the programmable device is a field programmable gate array (FPGA) or a complex programmable logic device (CPLD).

[0022] In a possible implementation, the first operation command is a write command, a read command, or an erase command.

[0023] In a second aspect, an information interaction method is also provided in the embodiments of the present application, and the method comprises the following steps:

[0024] The programmable device receives a first operation command for the flash memory sent by the first chip.

[0025] The programmable device translates the first operation command into a second operation command, and sends the second operation command to the flash memory, where the second operation command is an operation command that matches a model number of the flash memory.

[0026] The method provided by the embodiments of the present application utilizes a programmable device to play a role of translating operation commands, translates the operation commands sent by the first chip into operation commands matching the model of the flash memory, and then realizes reading, writing, erasing and other operations on the flash memory. The scheme of the embodiments of the present application decouples the firmware version of the chip from the model of the flash memory by using the programmable device, and the programmable device can simultaneously support the translation of operation commands of multiple firmware versions, and has better compatibility and inheritance. In addition, the firmware of the programmable device can be updated according to requirements, the number of types of operation commands that can be translated by the programmable device is increased, and the compatibility and inheritance are further improved, thereby relieving the selection limitation of the flash memory.

[0027] In a possible implementation, the programmable device includes a plurality of translation channels, and the programmable device translates the first operation command into the second operation command, specifically including:

[0028] The programmable device determines a first translation channel matching the model of the flash memory, and the first translation channel is one of the plurality of translation channels.

[0029] After receiving the first operation command for the flash memory sent by the first chip, the programmable device translates the first operation command into the second operation command by using the first translation channel.

[0030] The programmable device includes a plurality of translation channels, and the plurality of translation channels can respectively translate operation commands of a plurality of firmware versions. The programmable device can determine a channel for translating operation commands according to the model of the flash memory before the first chip issues the first operation command.

[0031] In a possible implementation, before the programmable device determines the first translation channel matching the model of the flash memory, the method further includes:

[0032] The management controller updates the firmware version of the programmable device to a first version, and adds the first translation channel in the firmware of the first version. The management controller is connected with the programmable device.

[0033] In this implementation, the firmware of the programmable device is updated by using the management controller, and the number of types of operation commands that can be translated by the programmable device is increased, that is, the number of translation channels can be increased by updating the firmware of the programmable device, and the compatibility and inheritance are further improved.

[0034] In a possible implementation, before the programmable device determines the first translation channel matching the model of the flash memory, the method further includes:

[0035] The management controller updates a firmware version of the programmable device to a first version, and a translation channel in the firmware of the first version is updated to a first translation channel.

[0036] In this implementation, the replacement of the translation channel is realized through the firmware update, i.e., the unused translation channel is replaced by the required translation channel, and the resources of the programmable device can be saved.

[0037] In a possible implementation, the programmable device determines the first translation channel matching the model of the flash memory, specifically including: the programmable device reads the model of the flash memory, determines a translation channel matching the model in the plurality of translation channels as the first translation channel, and generates a first translation channel switching instruction; the first translation channel switching instruction is used to indicate that the first multiplexer MUX and the second multiplexer MUX are both in communication with the first translation channel; after receiving the first translation channel switching instruction, the first MUX and the second MUX are both in communication with the first translation channel.

[0038] In this implementation, the programmable device includes the first MUX and the second MUX, the first MUX is in communication with the first chip, and the second MUX is in communication with the flash memory. The selective conduction of the plurality of translation channels is realized by using the first MUX and the second MUX.

[0039] In a possible implementation, the method further includes: after receiving a third operation command for the flash memory sent by the second chip, the programmable device translates the third operation command into a fourth operation command by using the first translation channel, and sends the fourth operation command to the flash memory, the fourth operation command being an operation command matching the model of the flash memory.

[0040] In this implementation, different chips can send operation commands corresponding to different models of flash memories to the programmable device, i.e., the chip issuing the operation command to the programmable device can be replaced, but the flash memory connected to the programmable device does not need to be replaced.

[0041] In a possible implementation, the first operation command is a write command, a read command, or an erase command. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A scene schematic diagram provided for an embodiment of the present application;

[0043] Figure 2 A schematic diagram of a computing device provided for an embodiment of the present application;

[0044] Figure 3 A schematic diagram of another computing device provided for an embodiment of the present application;

[0045] Figure 4A Another schematic diagram of a computing device provided by an embodiment of the present application;

[0046] Figure 4B Another schematic diagram of a computing device provided by an embodiment of the present application;

[0047] Figure 5 Another schematic diagram of a computing device provided by an embodiment of the present application;

[0048] Figure 6 A flowchart of an information interaction method provided by an embodiment of the present application;

[0049] Figure 7 A flowchart of another information interaction method provided by an embodiment of the present application;

[0050] Figure 8 A schematic diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0051] The operation method provided by the embodiments of the present application can be used for a computer device, and the computer device is not specifically limited in application scenarios. For example, the computer device is introduced by taking a server as an example, and the type of the server is not specifically limited, for example, it can be a rack server or an edge server. The server can be located in a data center or other areas, and the embodiments of the present application do not make specific limitations.

[0052] A server belongs to a type of computer device, and the server runs faster and has higher load than an ordinary computer. The server provides computing or application services for other clients (such as PC, smart phone and other devices) in a network. The server has high-speed CPU operation ability, long-time reliable operation, powerful external data throughput capacity and better scalability. The server is divided into rack type, blade type, tower type and cabinet type according to the appearance.

[0053] Flash, a kind of memory like electrically erasable programmable read-only memory, allows multiple deletions, additions or overwrites of data. Commonly used Flash types include Nor Flash and NAND Flash. Among them, Nor Flash supports XIP, that is, the firmware can be stored on the Nor Flash, and the firmware code can be executed directly on the Nor Flash without copying to the memory. This is because the interface of Nor Flash is completely the same as that of random access memory (RAM), and any address data can be randomly accessed. Nor Flash has very high efficiency in read operation, but the efficiency of erase and write operation is relatively low, in addition, the capacity of Nor Flash is generally small. NAND Flash has higher efficiency in erase and write operation, and larger capacity. Generally speaking, Nor Flash is used to store programs, and NAND Flash is used to store data. Devices based on NAND Flash usually also need to be matched with Nor Flash to store programs.

[0054] The server can include a central processing unit (CPU) and various application-specific integrated circuits (ASIC) chips. These chips need to interact with Nor Flash for data.

[0055] At present, there are many manufacturers of Nor Flash, and the driving instructions of Nor Flash produced by different manufacturers are not completely universal. For Nor Flash produced by different manufacturers, the chip interacting with the Nor Flash needs to adapt to the driving instructions of the Nor Flash.

[0056] In the embodiments of the present application, the interaction scenarios of the chip and the Nor Flash include at least the following two cases:

[0057] One is that the chip interacts with the Nor Flash;

[0058] The other is that the chip is connected with a device including Nor Flash, and the chip needs to interact with the Nor Flash in the device.

[0059] The embodiments of the present application do not emphasize or distinguish the above two scenarios in the following description. It can be understood that the following solutions of the embodiments of the present application can be applied to the above two scenarios.

[0060] Referring to Figure 1Fig. 1 is a schematic diagram of a scenario according to an embodiment of the present application.

[0061] In the current solution, the chip manufacturer generally releases a new version of firmware to adapt the chip to a new manufacturer or a new model of Flash. For example, when the firmware version is V1.0, only the chip can operate the A model of Flash. After the firmware is updated, the firmware version is updated from V1.0 to V1.1, so that the chip can operate the A model and the B model of Flash.

[0062] However, this way of updating the firmware needs to constantly update the firmware version of the chip. If the update is not timely, the old version of the firmware does not have the ability of backward compatibility, or causes the device using the new model of Flash to be abnormal.

[0063] To solve the above technical problems, the embodiments of the present application provide a computing device and an information interaction method. Compared with directly connecting the first chip with the flash memory, the first chip and the flash memory are connected through a programmable device in the embodiments of the present application. The programmable device plays a role of translating operation commands. The programmable device is used to translate the operation commands sent by the first chip into operation commands matched with the model of the flash memory according to the model of the flash memory, so as to realize the read, write, and erase operations on the flash memory. When it is needed to be compatible with the new model of the flash memory, only the firmware of the programmable device needs to be updated, so that the programmable device can translate the operation commands sent by the first chip into operation commands matched with the model of the new model of the flash memory according to the model of the new model of the flash memory, so as to realize the read, write, and erase operations on the new model of the flash memory, solve the compatibility problem caused by the difference of the operation commands between different manufacturers of the flash memory, and make the chip be compatible with the new model of the flash memory without modifying the firmware.

[0064] The implementation mode of the embodiments of the present application will be described in detail below with reference to the drawings.

[0065] In order to make the personnel in the technical field more clearly understand the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0066] The words "first", "second", and the like used in the description of the embodiments of the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features.

[0067] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be fixed connection, can be detachable connection, or can be integrated; can be direct connection, or can be indirect connection through an intermediate medium.

[0068] Referring toFigure 2 Fig. 1 is a schematic diagram of a computing device according to an embodiment of the present application.

[0069] The computing device can include a first chip 10, a programmable device 20, and a memory 30.

[0070] The memory 30 can be a Nor Flash or include a Nor Flash.

[0071] The programmable device 20 is connected between the first chip 10 and the memory 30.

[0072] The first chip 10 includes a serial peripheral interface (SPI) controller 11. The programmable device 20 includes an SPI controller 21. The first chip 10 and the programmable device 20 communicate through an SPI bus.

[0073] The first chip 10 can issue an operation command for the memory 30 to the programmable device through the SPI bus. The SPI bus is a high-speed full-duplex synchronous communication bus.

[0074] The programmable device 20 can further include a first multiplexer (MUX) 22 and a second MUX 24, and include one or more translation channels.

[0075] The first MUX 22 communicates with the first chip 10, and the second MUX 24 communicates with the memory 30.

[0076] The first MUX 22 and the second MUX 24 are used to select a command translation channel matching the current memory 30 from the plurality of command translation channels.

[0077] The translation channel functions to parse and translate the operation command issued by the first chip 10 before the memory 30, and then obtain an operation command matching the first chip 10.

[0078] The number of translation channels of the programmable device 20 and the chip type matched by the translation channels are related to the firmware of the programmable device 20. The programmable device 20 is configured to actively read the model of the memory 30 after being powered on and starting to work.

[0079] The computing device can further include a management processor 40 connected with the programmable device 20, used to update the firmware of the programmable device 20, and then realize the addition and modification of the translation channels, which will be described in detail below.

[0080] In an initial state, in one possible implementation, the programmable device 20 can not include any command translation channel. The programmable device 20 is connected to the first type of memory through the SPI bus. At this time, if the programmable device 20 receives an operation command sent by the first chip for operating the second type of memory, the programmable device 20 cannot translate the operation command.

[0081] In another possible implementation, the programmable device 20 can include one or a preset number of initial command translation channels. Taking an example of including one initial command translation channel 23a, the command translation channel 23a can be a channel matched to the second type of memory. At this time, if the programmable device 20 is connected to the second type of memory through the SPI bus, the command translation channel 23a is enabled, and when the programmable device 20 receives an operation command sent by the first chip, the operation command is translated into an operation command matched to the second type of memory through the command translation channel 23a, and then sent to the second type of memory. It can be understood that if the operation command sent by the first chip is itself an operation command matched to the second type of memory, the programmable device 20 still performs a translation operation on the operation command, but the operation command generated by the translation operation is the same as the original command. If the programmable device 20 is connected to the first type of memory through the SPI bus, the corresponding translation channel cannot be matched to perform translation of the operation command.

[0082] The translation channels in the programmable device 20 can be updated by the management processor 40 through firmware update.

[0083] When the computing device replaces the memory of the new type, since the programmable device 20 does not have a translation channel corresponding to the new type of memory, the programmable device 20 cannot translate the operation command sent by the first chip into an operation command corresponding to the new type of memory, at this time, the management processor 40 needs to update the firmware of the programmable device 20. Or, when the programmable device has not been configured with any translation channel, the management processor also needs to upgrade the firmware of the programmable device.

[0084] In some embodiments, the operator can configure the firmware of the programmable device in advance through the management processor, so that the programmable device has a plurality of translation channels, and the plurality of translation channels have a matched translation channel for any type of memory.

[0085] In some embodiments, after a memory of a certain model is connected to the programmable device 20, the programmable device 20 can acquire the model of the memory, and in the case that the programmable device 20 is confirmed to have a translation channel matching the model of the memory, the programmable device 20 translates the operation command sent by the chip to the memory through the translation channel. In the case that the programmable device is confirmed to not have a translation channel matching the model of the memory, the programmable device can send a firmware update request to the management processor to request the management processor to update the firmware of the programmable device so that the programmable device includes a translation channel matching the model of the memory.

[0086] In some embodiments, after a memory of a certain model is connected to the programmable device 20, the programmable device 20 can acquire the model of the memory, and in the case that the programmable device is confirmed to not have a translation channel matching the model of the memory, the programmable device can prompt an operator to update the firmware of the programmable device. The operator can update the firmware of the programmable device through the management processor according to the model of the memory, so that the programmable device includes a translation channel matching the model of the memory.

[0087] For example, in order to enable the programmable device 20 to translate the operation command matching the first model of the memory, the first translation channel corresponding to the command translation channel 23b in the figure is added to the programmable device 20 through firmware update.

[0088] The command translation channel 23b is used to translate the operation command into an operation command matching the first model of the memory.

[0089] At this time, when the programmable device 20 is connected to the memory of the first model through the SPI bus and the programmable device 20 is powered on to start working, the model of the memory is acquired and the translation channel corresponding to the model is gated, that is, the programmable device 20 gates the command translation channel 23b. When the programmable device 20 receives the first operation command sent by the first chip, the first operation command is translated into a second operation command matching the first model of the memory by using the command translation channel 23b. It can be understood that if the first operation command sent by the first chip is itself an operation command matching the first model of the memory, the command translation channel 23b will still perform a translation operation on the first operation command, but the operation command generated by the translation operation is the same as the original command.

[0090] The above describes the implementation mode when the first model of the memory is compatible. When it is desired to be compatible with other models, for example, the third model of the memory, the translation channel in the programmable device 20 needs to be updated again by using the management processor 40. The following will be specifically described with reference to the accompanying drawings.

[0091] In a possible implementation, referring to Figure 3 Fig. 3 is a schematic diagram of another computing device provided by an embodiment of the present application.

[0092] The management processor 40 updates the firmware of the programmable device 20 to update the command translation channel 23a of the programmable device 20 to the command translation channel 23c, which is used to translate the operation command into an operation command matched with the third type of memory.

[0093] In this implementation, the replacement of the translation channel is realized through the firmware update, that is, the unused translation channel is replaced by the required translation channel, which can save the resources of the programmable device 20.

[0094] When the programmable device 20 is connected to the third type of memory through the SPI bus and is powered on to start working, the programmable device 20 actively reads the type of the memory device. The programmable device 20 determines that the current matched translation channel is the command translation channel 23c according to the third type of the read memory, and then selects the command translation channel 23c.

[0095] When the programmable device 20 receives the operation command sent by the first chip, the original operation command is translated through the command translation channel 23c to obtain an operation command matched with the third type of memory and sent to the third type of memory.

[0096] In another possible implementation, referring to Figure 4A Fig. 4 is a schematic diagram of another computing device provided by an embodiment of the present application.

[0097] The management processor 40 updates the firmware of the programmable device 20 to add the command translation channel 23c in the programmable device 20, which is used to translate the operation command into an operation command matched with the third type of memory.

[0098] In this implementation, the addition of the translation channel is realized through the firmware update, so that the programmable device 20 is compatible with the new type of memory while retaining the compatibility for the old type of memory. Even if the programmable device 20 is connected to the second type of memory through the SPI bus later, it is not necessary to update the firmware again.

[0099] When the programmable device 20 is connected with the third type of memory through the SPI bus, and the programmable device 20 is powered on and starts to work, the programmable device 20 actively reads the type of the memory device. According to the third type of the memory read, the programmable device 20 determines that the current matching translation channel is the command translation channel 23c, and then selects the command translation channel 23c. When the programmable device 20 receives the operation command sent by the first chip, the original operation command is translated through the command translation channel 23c to obtain the operation command matched with the third type of memory and sent to the third type of memory.

[0100] The above embodiment illustrates the process that the programmable device 20 is compatible with various types of memories through firmware update. In another possible implementation, continuing to refer to Figure 4A , the initial firmware version of the programmable device has configured multiple translation channels for different types of memories. As Figure 4A indicated, the command translation channel 23a is configured for the first type of memory, the command translation channel 23b is configured for the second type of memory, and the command translation channel 23c is configured for the third type of memory. The number of translation channels in the embodiments of the present application is not limited. For example, the programmable device can be configured with all types of flash memories of all mainstream flash memory manufacturers.

[0101] At this time, the programmable device 20 can translate the operation signals matched with multiple types of memories. The following will be described in combination with specific operation commands.

[0102] Table 1: Operation commands corresponding to different types of memories

[0103]

[0104] Table 2: Read manufacturer ID / type ID commands corresponding to different types of memories

[0105] Memory Model Model A Model B Operation Command Type Read Manufacturer / Device ID Manufacturer / Device ID Byte 1 90H 90h Byte 2 00H 00H Byte 3 00H 00H Byte 4 00H 00h Byte 5 (MID7-MID0) (MF7-MF0) Byte 6 (ID7-ID0) (ID7-ID0) Byte 7 (cont.) Byte 8 Byte 9 Byte 10

[0106] It can be seen from the data in Table 1 that the two types of memories are different in read manufacturer ID / device ID, fast read with 4-byte address (Fast Read Quad I / O with 4-Byte Address), fast read with 4-byte address (Fast Read Quad I / O with 4-Byte Address) and other instructions.

[0107] After using the scheme in the embodiments of the present application, the programmable device undertakes the operation command selection work.

[0108] In a possible implementation, referring to Figure 4BFig. 4 is a schematic diagram of still another computing device according to an embodiment of the present application.

[0109] The programmable device 20 further comprises a controller 25, which can communicate with the memory through an SPI bus. The controller 25 is further connected to the first MUX 22 and the second MUX 24. The controller 25 is configured to output a translation channel switching instruction to the first MUX 22 and the second MUX 24, so as to control the first MUX 22 and the second MUX 24 to communicate with the translation channel indicated by the translation channel switching instruction.

[0110] Specifically, when the programmable device 20 is powered on, the controller 25 actively reads the signal of the memory 30, i.e., reads the model of the memory. The controller 25 determines a translation channel in the plurality of translation channels that matches the current memory model as a first translation channel, and generates a switching instruction of the first translation channel. In practical applications, the field specification of the operation command issued by the first chip and the field specification corresponding to the currently used memory may not differ greatly in most cases, e.g., there is a difference of 1 to 2 Bytes. Therefore, the programmable device can be configured to support translation of the operation command of the commonly used memory on the market. For example, the operation command issued by the first chip corresponds to a memory model A. When the programmable device supports translation of the operation command of the A model memory, the programmable device can translate the operation command into the operation command corresponding to the current first chip, and then issue the translated operation command to the memory.

[0111] For example, in combination with Table 1 and Table 2, it is assumed that the first chip supports the A model memory, and when performing dual-line fast reading, the address line needs to have a function code of M7-M0. This function code can make the memory determine whether the first chip needs to issue the Read Dual I / O instruction code of the memory in the next instruction period. The B model memory does not support this function when performing dual-line fast reading.

[0112] According to the scheme of the embodiments of the present application, the function code M7-M0 of the address line in the dual-line fast reading instruction is eliminated through the translation channel corresponding to the B model memory, and the difference of the instruction is eliminated, so that the operation command of the A model memory issued by the first chip can match the B model memory.

[0113] The flash memory 30 can be a Nor Flash. The flash memory 30 can store the firmware of the first chip and other programs, and can also store other data.

[0114] In the embodiments of the present application, the operation command issued by the first chip 10 can be a write command, a read command or an erase command. The read command can be used to read firmware code or read the manufacturer ID / device ID of the memory.

[0115] In the above embodiments, the programmable device 20 reads the model of the memory 30 to select the translation channel. In another possible implementation, the manufacturer ID or device ID of the memory 30 can indicate the model of the current memory 30, and then the programmable device 20 can read the manufacturer ID or device ID of the memory 30, determine the model of the memory 30 according to the manufacturer ID or device ID, and then select the corresponding translation channel.

[0116] The programmable device 20 in the above embodiments can be a field-programmable gate array (FPGA), a complex programmable logic device (CPLD) or any combination thereof, and the embodiments of the present application are not limited thereto.

[0117] In one possible implementation, the programmable device 20 can be connected to the management processor 40 through an SPI bus to implement firmware upgrade, for example, upgrade the firmware of the programmable device 20 to a first version compatible with the operation command of the target chip.

[0118] In another possible implementation, the programmable device 20 can be connected to the management processor 40 through a joint test action group (JTAG) interface to implement firmware upgrade.

[0119] The management processor 40 can be an application specific integrated circuit (ASIC), a programmable logic device (PLD), a digital signal processor (DSP) or a combination thereof. The PLD can be a CPLD, an FPGA, a GAL or any combination thereof, and the embodiments of the present application are not limited thereto.

[0120] The first chip above can be a central processing unit (CPU) or an application-specific integrated circuit (ASIC) chip.

[0121] The ASIC chip can be a network card chip, a redundant array of independent disks (RAID) chip, a peripheral component interconnect express switch (PCIe Switch) chip, a Nonvolatile Memory Express (NVMe) chip, a serial attached small computer system interface (SAS) host chip, a SAS Expander chip, a Serial Advanced Technology Attachment (SATA) host chip, a SATA Expander chip, or the like.

[0122] To sum up, the computing device provided in the embodiments of the present application no longer directly connects the first chip with the flash memory, but increases a programmable device between the first chip and the flash memory. The programmable device plays a role of translating operation commands. The programmable device can match a first translation channel suitable for the model of the flash memory, and then translate the operation commands sent by the first chip into operation commands suitable for the model of the flash memory. When it is necessary to be compatible with a new model of flash memory, it is only necessary to update the firmware of the programmable device, so that the programmable device includes a translation channel corresponding to the new model of flash memory, thereby solving the compatibility problem caused by the difference in operation commands between different flash memory manufacturers, and enabling the chip to be compatible with the new model of flash memory without modifying the firmware.

[0123] In the above embodiments, the programmable device is connected with one chip through the SPI bus, that is, the operating system of the flash memory includes one chip. The implementation manner when the operating system of the flash memory includes multiple chips is described below.

[0124] Referring to Figure 5 The figure is a schematic diagram of another computing device provided in the embodiments of the present application.

[0125] In the embodiments of the present application, two chips, that is, chip 10 and chip 50, are included in the system. When more chips are included, the implementation manner is similar, and thus will not be described here.

[0126] Taking the model of the memory 30 currently connected with the programmable device 20 as an example, the model is model A.

[0127] After the current programmable device 20 is powered on and completes initialization, the type of the memory 30 is read, and a matched command translation channel is selected according to the type of the Flash memory 30. For example, the current command translation channel 23a can translate an operation command into a command corresponding to the A-type memory, and the command translation channel 23a is selected.

[0128] The selection module 13 is configured to select an enabled chip. For example, the chip 10 and the chip 50 can be chips with the same function, that is, the chip 10 and the chip 50 are redundantly designed, and when the chip 10 is enabled, the computing device detects that the chip 10 fails, and the chip 50 can be selected.

[0129] When the chip 10 is enabled, after the programmable device 20 receives a first operation command of the chip 10, the first operation command is translated into a second operation command matched with the A-type memory through the command translation channel 23a, and the second operation command is sent to the memory 30.

[0130] When the chip 50 is enabled, after the programmable device 20 receives a third operation command of the chip 50, the third operation command is translated into a fourth operation command matched with the A-type memory through the command translation channel 23a, and the fourth operation command is sent to the Flash memory 30.

[0131] The operation commands issued by the chip 10 and the chip 50 can correspond to different types of memories, for example, the operation command issued by the chip 10 can correspond to the B-type memory, and the operation command issued by the chip 50 can correspond to the C-type memory, but after being translated through the command translation channel 23a, they will all be translated into operation commands matched with the A-type memory.

[0132] As can be seen from the above embodiments, the scheme of the embodiments of the present application can make one memory compatible with multiple chips through the programmable device 20, and different chips can send operation commands corresponding to different types of memories to the programmable device 20, and the number of memories no longer needs to correspond to the number of chips, reducing the number of required memories, and thereby reducing the hardware cost.

[0133] In some special scenarios, for example, the chip 10 and the chip 50 are functionally redundant chips, but the firmware versions are different, resulting in different control commands issued, and after the technical scheme of the embodiments of the present application is applied, when the chip 50 is enabled after the chip 10 fails, it is no longer necessary to replace the memory, but can directly realize compatibility, having high practicability.

[0134] Further, in another possible implementation, the computing device provided by the embodiment of the present application can also include a plurality of memories and a plurality of chips, each chip can correspond to one memory, and the programmable device can translate the operation command issued by each chip into an operation command matched with the memory corresponding to the chip. The specific principle is similar to that in the above embodiment, and thus will not be described here again.

[0135] Based on the computing device provided by the above embodiment, the embodiment of the present application further provides an information interaction method, which will be specifically described below with reference to the accompanying drawings.

[0136] Referring to Figure 6 , the figure is a flowchart of an information interaction method provided by the embodiment of the present application.

[0137] In the following embodiment, the model of the memory is A model, and the programmable device includes no first translation channel matched with the A model in the initial state is taken as an example for description, and the method includes the following steps:

[0138] S11: The management processor is started and runs a main program.

[0139] When the computing device replaces a memory of a new model, since the programmable device has no translation channel corresponding to the memory of the new model, the programmable device cannot translate the operation command sent by the first chip into an operation command corresponding to the memory of the new model, and thus the management processor needs to update the firmware of the programmable device.

[0140] Or, when the programmable device has not been configured with any translation channel, the management processor also needs to upgrade the firmware of the programmable device.

[0141] After the main program is run, the management processor is used to upgrade the firmware of the programmable device. S12: The management processor upgrades the firmware of the programmable device, so that the programmable device includes the first translation channel.

[0142] The first translation channel is used to translate the operation command into an operation command corresponding to the A model memory.

[0143] In some embodiments, the operator or the main program can configure the firmware of the programmable device in advance, so that the programmable device has a plurality of translation channels, and the plurality of translation channels have a translation channel matched with any model of memory, that is, the plurality of translation channels include the first translation channel.

[0144] In some embodiments, after a memory of a certain model is connected to the programmable device 20, the programmable device 20 can acquire the model of the A model memory, and confirm that the programmable device 20 has a translation channel matching the memory model, and translate the operation instruction sent by the chip to the memory through the translation channel. In the case of confirming that the programmable device does not have a translation channel matching the memory model, the programmable device can send a firmware update request to the management processor to request the management processor to update the firmware of the programmable device so that the programmable device includes a first translation channel matching the memory model.

[0145] In some embodiments, before or after a memory of a certain model is connected to the programmable device 20, an operator or the programmable device 20 can acquire the model of the A model memory, and in the case of confirming that the programmable device does not have a translation channel matching the memory model, the programmable device can prompt the operator to update the firmware of the programmable device. The operator can update the firmware of the programmable device through the management processor according to the model of the memory, so that the programmable device includes a translation channel matching the memory model.

[0146] In a possible implementation, the management processor updates the firmware version of the programmable device to a first version, and updates one of the plurality of translation channels to the first translation channel by updating the firmware of the first version. In this implementation, the replacement of the translation channel is realized through the firmware update, that is, the unused translation channel is replaced by the required translation channel, which can save the resources of the programmable device.

[0147] In another possible implementation, the management processor updates the firmware version of the programmable device to a first version, and adds the first translation channel on the basis of the original plurality of translation channels by updating the firmware of the first version. In this implementation, the compatibility for the memory of the old model is also retained, that is, even if the programmable device is connected to the memory of the old model again, the firmware does not need to be updated again.

[0148] S13: The programmable device is powered on and initialized.

[0149] Wherein, the initialization refers to the method of assigning initial values to data objects, variables or semaphores, etc., and how to initialize depends on the firmware of the programmable device. After the initialization of the programmable device is completed, the programmable device can start reading the model of the memory.

[0150] S14: The programmable device reads the model of the memory.

[0151] At this time, the model of the memory read is the A model.

[0152] S15: The programmable device determines a translation channel matching the memory model from the plurality of translation channels as the first translation channel.

[0153] In a possible implementation, the programmable device stores a mapping relationship table, which is used to represent a mapping relationship between the memory model and each translation channel. When the programmable device reads the model of the memory, the corresponding translation channel is matched according to the mapping relationship table.

[0154] When the programmable device performs firmware upgrade, the mapping relationship table also needs to be maintained. For example, when the first translation channel is added by the firmware upgrade, the first translation channel is used to translate the operation command of the memory of the first model, and the mapping relationship between the first translation channel and the first model also needs to be added in the mapping relationship table.

[0155] S16: The programmable device controls the first MUX and the second MUX to be connected to the first translation channel.

[0156] In a possible implementation, after the programmable device determines the first translation channel, the programmable device can generate a first translation channel switching instruction.

[0157] The programmable device includes the first MUX and the second MUX, the first MUX communicates with the first chip, and the second MUX communicates with the flash memory. The first translation channel switching instruction is used to instruct the first MUX and the second MUX in the programmable device to communicate with the first translation channel, so that the programmable device selects the first translation channel.

[0158] When the first MUX and the second MUX receive the first translation channel switching instruction, they communicate with the first translation channel.

[0159] S17: The first chip issues a first operation command to the programmable device.

[0160] The first operation command can be a write command, a read command or an erase command, which is not limited in the embodiments of the present application.

[0161] S18: The programmable device translates the first operation command into a second operation command by using the first translation channel.

[0162] The second operation command is an operation command matching the model of the memory, that is, an operation command corresponding to the A model memory.

[0163] S19: The programmable device sends the second operation command to the memory.

[0164] When the first operation command and the second operation command are read commands, the memory can also send the read data to the first chip through the first translation channel.

[0165] It can be understood that the above method steps provided by the embodiments of the present application are only for the convenience of description, and do not constitute a limitation on the technical solutions of the present application. In actual application, the firmware updating steps S11 and S12 of the programmable device do not need to be performed every time the first chip operates the memory.

[0166] Through the above method, the programmable device plays a role of translating operation commands, and is no longer directly connected with the flash memory. When it is necessary to be compatible with a new model of flash memory, it is only necessary to update the firmware of the programmable device, so that the programmable device includes a translation channel corresponding to the new model of flash memory, thereby solving the compatibility problem caused by the difference in operation commands between different flash memory manufacturers, and enabling the chip to be compatible with the new model of flash memory without modifying the firmware.

[0167] Referring to Figure 7 , the figure is a flowchart of another information interaction method provided by the embodiments of the present application.

[0168] Through Figure 6 , the compatibility with the A model memory has been realized. The following describes a method for the second chip to operate the flash memory, which includes the following steps.

[0169] S21: The programmable device is powered on and initialized.

[0170] S22: The programmable device reads the model of the memory.

[0171] At this time, the model of the read memory is the A model.

[0172] S23: The programmable device determines a translation channel matching the model of the memory as a first translation channel from a plurality of translation channels.

[0173] S24: The programmable device controls the first MUX and the second MUX to be connected with the first translation channel.

[0174] The programmable device includes the first MUX and the second MUX, the first MUX communicates with the first chip, and the second MUX communicates with the flash memory.

[0175] In a possible implementation, after the programmable device determines the first translation channel, the programmable device can generate a first translation channel switching instruction. The first translation channel switching instruction is used to indicate that the first MUX and the second MUX in the programmable device are both connected with the first translation channel, so as to enable the programmable device to select the first translation channel.

[0176] When the first MUX and the second MUX receive the first translation channel switching instruction, they are both connected with the first translation channel.

[0177] S25: The second chip is powered on.

[0178] At this time, the computing device includes a first chip and a second chip. The first chip and the second chip can be chips with the same function, that is, a chip and a chip redundancy design. When the computing device detects that the chip fails during the chip enabling process, the gating module of the computing device can gate the second chip.

[0179] S26: The second chip issues a third operation command to the programmable device.

[0180] The third operation command and the first operation command sent by the first chip can be operation commands corresponding to different models of memories. For example, the first operation command sent by the first chip can correspond to a B model memory, and the third operation command sent by the second chip can correspond to a C model memory.

[0181] S27: The programmable device translates the third operation command into a fourth operation command using a first translation channel.

[0182] The fourth operation command is an operation command matching the model of the flash memory, that is, an operation command corresponding to an A model memory.

[0183] S28: The programmable device sends the fourth operation command to the memory.

[0184] When the third operation command and the fourth operation command are read commands, the memory can also send the read data to the second chip through the first translation channel.

[0185] The order of the first chip and the second chip in the embodiments of the present application can be exchanged.

[0186] Through the above method, one memory is compatible with multiple chips through the programmable device, and different chips can send operation commands corresponding to different models of memories to the programmable device. The number of memories no longer needs to correspond to the number of chips, reducing the number of required memories, and thereby reducing the hardware cost. In some special scenarios, for example, the first chip and the second chip are redundant chips in function, but the firmware versions are different, resulting in different control commands issued. After applying the technical solution of the embodiments of the present application, when the second chip is enabled after the first chip fails, it is no longer necessary to replace the memory, but can directly realize compatibility, having high practicality.

[0187] The embodiments of the present application also provide a computer device.

[0188] Referring to Figure 8 , the figure is a schematic diagram of a computer device provided by the embodiments of the present application.

[0189] The computer device 80 includes m components, which are component 81, component 82, …, and component 8m in sequence.

[0190] With reference to the above embodiments, the specific working principles and descriptions of the first chip 10, the programmable device 20 and the memory 30 will not be repeated here. Figure 2 Each component in the embodiments of the present application includes the first chip 10, the programmable device 20 and the memory 30. The programmable device 20 is connected between the first chip 10 and the memory 30.

[0191] With reference to the above embodiments, the specific working principles and descriptions of the first chip 10, the programmable device 20 and the memory 30 will not be repeated here.

[0192] The chip in each component can be different chips.

[0193] For example, it can be a network card chip, a RAID chip, a PCIe Switch chip, a SAS master chip, a SAS expansion chip, a SATA master chip, a SATA expansion chip, an NVMe chip or a central processing unit (CPU) chip.

[0194] The computer device 80 can be a server, for example, a rack server or an edge server. The server can be located in a data center or other areas, and the embodiments of the present application do not make specific limitations. The server can be applied to a public cloud, or other networks that provide hardware services to users remotely, such as a private cloud, a hybrid cloud, and the like.

[0195] After the computer device applies the component, the compatibility problem caused by the difference in operation commands between different flash memory manufacturers is solved, so that the chip can be compatible with new models of flash memory without modifying the firmware, and the selection of the flash memory by the computer device is no longer limited.

[0196] It should be understood that in the embodiments of the present application, “at least one” refers to one or more, and “multiple” refers to two or more. “And / or” is used to describe the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, “A and / or B” can represent three cases of only A, only B and A and B existing at the same time, wherein A and B can be singular or plural. The character “ / ” generally represents an “or” relationship between the associated objects. “At least one of the following” or the like means any combination of these items, including single item or any combination of multiple items. For example, at least one of a, b or c can represent a, b, c, “a and b”, “a and c”, “b and c”, or “a and b and c”, wherein a, b and c can be single or multiple.

[0197] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. The device embodiments described above are merely illustrative, and the units and modules described as separate components may or may not be physically separate. Furthermore, some or all of the units and modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0198] The above description is only a specific embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A computing device, comprising: The computing device comprises a first chip, a programmable device and a flash memory, the programmable device being connected between the first chip and the flash memory; communication between the first chip and the programmable device and between the programmable device and the flash memory is realized through a serial peripheral interface (SPI) bus; The programmable device, after receiving a first operation command for the flash memory sent by the first chip, acquires a first field specification of the first operation command and a second field specification corresponding to the flash memory; in the case that a gap between the first field specification and the second field specification is within a preset range, the first operation command is translated into a second operation command in a manner of eliminating the difference between the first field specification and the second field specification, and the second operation command is sent to the flash memory, the second operation command being an operation command matching the model of the flash memory.

2. The computing device of claim 1, wherein, The programmable device comprises a plurality of translation channels, and is specifically used for determining a first translation channel matching the model of the flash memory, the first translation channel being one of the plurality of translation channels, and translating the first operation command into a second operation command by using the first translation channel after receiving the first operation command for the flash memory sent by the first chip.

3. The computing device of claim 2, wherein, The computing device further comprises a management controller; The management controller is connected with the programmable device; The management controller is configured to update a firmware version of the programmable device to a first version, and add the first translation channel in the firmware of the first version.

4. The computing device of claim 2, wherein, The computing device further comprises a second chip; The programmable device is connected with the second chip; The programmable device is further configured to translate a third operation command for the flash memory sent by the second chip into a fourth operation command by using the first translation channel, and send the fourth operation command to the flash memory, the fourth operation command being an operation command matching the model of the flash memory.

5. The computing device of any of claims 2-4, wherein, The programmable device comprises a first multiplexer (MUX) and a second MUX, the first MUX being in communication with the first chip, and the second MUX being in communication with the flash memory; The programmable device is specifically configured to read the model of the flash memory, determine a translation channel matching the model in the plurality of translation channels as the first translation channel, and generate a first translation channel switching instruction, the first translation channel switching instruction being used to indicate that the first MUX and the second MUX are both in communication with the first translation channel; The first MUX and the second MUX are configured to be both in communication with the first translation channel after receiving the first translation channel switching instruction.

6. The computing device of any of claims 1-5, wherein, The first chip is any one of the following: The network card chip, the redundant array of independent disks (RAID) chip, the peripheral component interconnect express (PCIe) switch chip, the serial attached small computer system (SAS) host controller chip, the SAS expansion chip, the serial advanced technology attachment (SATA) host controller chip, the SATA expansion chip, the non-volatile memory express (NVMe) chip, and the central processing unit (CPU) chip.

7. The computing device of any of claims 1-6, wherein, The programmable device is a field programmable gate array (FPGA) or a complex programmable logic device (CPLD).

8. An information interaction method, characterized in that, The communication between the first chip and the programmable device and between the programmable device and the flash memory is implemented through a serial peripheral interface (SPI) bus, the programmable device is connected between the first chip and the flash memory, and the method comprises the following steps: The programmable device receives a first operation command for the flash memory sent by the first chip. A first field specification of the first operation command and a second field specification corresponding to the flash memory are obtained. When a gap between the first field specification and the second field specification is within a preset range, the programmable device translates the first operation command into a second operation command in a manner of eliminating the difference between the first field specification and the second field specification, and sends the second operation command to the flash memory, the second operation command being an operation command matched with the model of the flash memory.

9. The method of claim 8, wherein, The programmable device comprises a plurality of translation channels, and the programmable device translates the first operation command into the second operation command, specifically comprising the following steps: The programmable device determines a first translation channel matched with the model of the flash memory, the first translation channel being one of the plurality of translation channels. After receiving the first operation command for the flash memory sent by the first chip, the programmable device translates the first operation command into the second operation command by using the first translation channel.

10. The method of claim 9, wherein, Before the programmable device determines the first translation channel matched with the model of the flash memory, the method further comprises the following steps: The management controller updates the firmware version of the programmable device to a first version, and adds the first translation channel in the firmware of the first version, the management controller being connected with the programmable device.

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