Compiler optimization method for embedded applications based on digital signal processors
By optimizing the compiler for digital signal processors in the LLVM architecture and replacing OR and AND instructions with BST and BCLR instructions, the inefficiency caused by multiple instructions in the prior art is solved, and more efficient code execution is achieved.
Patent Information
- Application Number
- CN202410135787.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-31
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2044-01-31
AI Technical Summary
In the existing technology, when compiling C code for register configuration, loops, conditional statements, calls, and returns, the compiler of a digital signal processor requires multiple instructions to perform bit assignment, resulting in low code execution efficiency.
By adding a translation pass to the LLVM architecture, leveraging the hardware characteristics of digital signal processors, the C code for register configuration, loops, conditional statements and calls, and returns is optimized. The OR and AND instructions are replaced with BST and BCLR instructions, and the delay slot NOP after jump instructions is optimized.
It achieves smaller compiled file size and higher execution efficiency, reduces CPU idle time, and improves code execution efficiency.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to embedded applications, in particular to a compiler optimization method for embedded applications based on a digital signal processor. BACKGROUND
[0002] With the proposal of Industry 4.0 and the rapid development of new energy automobile industry, the demand for chips capable of low-delay processing of motors, power supplies and other embedded applications has increased significantly. QX320F280049C chip is a digital signal processor developed to further reduce delay and improve real-time control performance, which has the hardware characteristics of adding two delay slots NOP after the bit assignment instruction BST, BCLR and jump instruction. The compiler of the digital signal processor is designed and implemented based on the open source architecture LLVM.
[0003] LLVM (Low Level Virtual Machine) is an open source project launched by the University of Illinois in 2000, initially led by Dr. Chris Lattner of the University of Illinois at Urbana-Champaign. LLVM consists of a main project and many different sub-projects. Its compiler framework system has strong optimization capabilities and easy extensibility. When implementing the compilation system, the compiler is organized into several passes (Pass). Each compilation pass takes the result of the previous compilation pass (or the source code) as input, analyzes and converts it to obtain new intermediate code or target program. From the perspective of the compilation pass itself, it can be divided into analysis pass and conversion pass. Compilation passes are usually independent, so you can insert the required pass at any location according to actual needs, which is very convenient for optimization.
[0004] The original LLVM compiler of the above-mentioned digital signal processor will translate the register configuration C code into 3 instructions: MOVIGL instruction + MOVIGH instruction + OR instruction or AND instruction, while using BST instruction and BCLR instruction can reduce it to 1 instruction to achieve bit assignment. In addition, the LLVM compiler will take the two instructions after the jump instruction and execute the result because of the hardware pipeline, so two empty delay slots NOP need to be inserted, which makes the CPU idle time longer and the code execution efficiency lower. SUMMARY
[0005] (I) Technical problems solved
[0006] In view of the above-mentioned defects of the prior art, the present application provides a compiler optimization method for embedded applications based on a digital signal processor, which can effectively overcome the defects of the prior art, i.e., the need for multiple instructions to implement bit assignment and the low code execution efficiency.
[0007] (II) Technical solutions
[0008] To achieve the above object, the present application is implemented by the following technical solutions:
[0009] The compiler optimization method for embedded applications based on a digital signal processor adds a translation pass in the LLVM architecture, utilizes the hardware characteristics of the digital signal processor, and performs compiler-level optimization on C code for register configuration, loops, judgments, calls, and returns of embedded applications.
[0010] Preferably, the compiler-level optimization on the C code for register configuration, loops, judgments, calls, and returns of embedded applications comprises:
[0011] The C code for register configuration is translated into OR instructions and AND instructions of an intermediate representation IR, and through instruction selection processing of the OR instructions and the AND instructions to BST instructions and BCLR instructions specific to the digital signal processor, the optimization purpose is achieved;
[0012] The C code for loops, judgments, calls, and returns is translated into jump instructions such as JMP, JN, JNC, CALL, and RET, and through instruction replacement of NOP after the jump instructions of the digital signal processor, the optimization purpose is achieved.
[0013] Preferably, the C code for register configuration is translated into OR instructions and AND instructions of an intermediate representation IR, and through instruction selection processing of the OR instructions and the AND instructions to BST instructions and BCLR instructions specific to the digital signal processor, the optimization purpose is achieved, comprising:
[0014] All nodes in an instruction dependency acyclic directed graph of the intermediate representation IR are traversed, and OR operators and AND operators are analyzed, and if they can be simplified into BST instructions and BCLR instructions, instruction selection processing is performed.
[0015] Preferably, all nodes in an instruction dependency acyclic directed graph are traversed, and OR operators and AND operators are analyzed, and if they can be simplified into BST instructions and BCLR instructions, instruction selection processing is performed, comprising:
[0016] S11, all nodes in an instruction dependency acyclic directed graph of the intermediate representation IR are traversed, and if a getOpcode() of a node is found to be an OR operator or an AND operator, analysis is performed:
[0017] S12, if the operator is OR operator, assign its second operand to SecondOperand; if the operator is AND operator, take the complement of its second operand and assign it to SecondOperand, and analyze SecondOperand:
[0018] S13, if the operator is OR operator, create a new BST operator node; if the operator is AND operator, create a new BCLR operator node;
[0019] S14, delete the OR operator node or AND operator node from the instruction dependency acyclic directed graph, and insert the newly created BST operator node or BCLR operator node into the corresponding position;
[0020] wherein the first operand of the newly created BST operator or BCLR operator is the value of the first operand getOperand(0) of the OR operator or AND operator, and the second operand is the number of cyclic right shifts Count.
[0021] Preferably, if the getOpcode() of the node is found to be OR operator or AND operator in S11, the analysis is performed, including:
[0022] The second operand of the OR operator or AND operator is obtained through getOperand(1), if the operand is of ISD:Constant type of intermediate representation IR, enter S12; otherwise, end the optimization of the operator node.
[0023] Preferably, the analysis of SecondOperand in S12 includes:
[0024] The SecondOperand and (SecondOperand-1) are ANDed, if the AND result is 0, the SecondOperand is cyclically right shifted until the value after right shift is 1, and the number of cyclic right shifts Count is recorded, and S13 is entered; otherwise, the optimization of the operator node is ended.
[0025] Preferably, the C code of loop, judgment, call, and return is translated into JMP, JN, JNC, CALL, and RET jump instructions, and the optimization is achieved by replacing the NOP instructions after the jump instructions of the digital signal processor, including:
[0026] Traverse all basic blocks, analyze the JMP, JN, JNC, CALL, RET jump instructions, if there are instructions in front of the jump instruction and no data correlation, use the previous instruction to replace the NOP after the jump instruction.
[0027] Preferably, the traversal of all basic blocks, for the JMP, JN, JNC, CALL, RET jump instructions are analyzed, if there are instructions in front of the jump instruction and no data correlation, use the previous instruction to replace the NOP after the jump instruction, including:
[0028] Traverse all basic blocks for each function block, and judge each MachineInstr, if its getOpcode() is JN, JNC conditional jump operator, then:
[0029] Get the first instruction before the JN, JNC jump instruction by prev(MachineInstr, 1), if the instruction is not a comparison instruction and not empty, replace the first delay slot NOP after the JN, JNC jump instruction with prev(MachineInstr, 1), and go to the next step; otherwise, end the optimization of the basic block;
[0030] Get the second instruction before the JN, JNC jump instruction by prev(MachineInstr, 2), if the instruction is not a comparison instruction and not empty, replace the second delay slot NOP after the JN, JNC jump instruction with prev(MachineInstr, 2), and optimize the next basic block; otherwise, end the optimization of the basic block.
[0031] Preferably, the traversal of all basic blocks, for the JMP, JN, JNC, CALL, RET jump instructions are analyzed, if there are instructions in front of the jump instruction and no data correlation, use the previous instruction to replace the NOP after the jump instruction, including:
[0032] Traverse all basic blocks for each function block, and judge each MachineInstr, if its getOpcode() is JN, JNC conditional jump operator, then:
[0033] If the first instruction before the JN or JNC jump instruction is not a comparison instruction and is not empty, the first NOP after the JN or JNC jump instruction is replaced by the first instruction before the JN or JNC jump instruction, and the optimization of the next basic block is performed; otherwise, the optimization of the basic block is ended.
[0034] If the second instruction before the JN or JNC jump instruction is not a comparison instruction and is not empty, the second NOP after the JN or JNC jump instruction is replaced by the second instruction before the JN or JNC jump instruction, and the optimization of the next basic block is performed; otherwise, the optimization of the basic block is ended.
[0035] (Three) beneficial effects
[0036] Compared with the prior art, the compiler optimization method for embedded applications based on a digital signal processor provided by the application performs optimization at the compiler level for embedded applications based on the use of BST instructions and BCLR instructions of the digital signal processor and the instruction replacement of the NOP after the jump instruction, so that the size of the file compiled from the C code of register configuration, loop, judgment, call and return is smaller, the execution efficiency is higher, and the cycle number during running is less than that of the file compiled by the original compiler before optimization. The original compiler implements bit assignment through MOVIGL instructions, MOVIGH instructions, OR instructions and AND instructions, and after optimization, bit assignment can be implemented by only one BST instruction or BCLR instruction. The jump instructions such as JMP, JN, JNC, CALL and RET are optimized to be filled with useful instructions instead of the idle delay slot NOP filled by the original compiler, so that the CPU idle time is shortened and the code execution efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.
[0038] Figure 1 The flowchart of the application;
[0039] Figure 2 The five types of code examples contained in the general embedded application C program;
[0040] Figure 3A diagram for the BST instruction and the BCLR instruction in the present application;
[0041] Figure 4 A test code in the detailed description of the present application;
[0042] Figure 5 A comparison diagram of the assembly codes obtained before and after optimization for the bit assignment instruction;
[0043] Figure 6 A comparison diagram of the assembly codes obtained before and after optimization for the conditional jump instruction;
[0044] Figure 7 A comparison diagram of the assembly codes obtained before and after optimization for the unconditional jump instruction. DETAILED DESCRIPTION
[0045] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.
[0046] The compiler optimization method for embedded applications based on a digital signal processor adds a translation pass in the LLVM architecture, utilizes the hardware characteristics of the digital signal processor, and performs compiler-level optimization on C codes (such as Figure 2 shown) for register configuration, loops, judgments, calls, and returns of embedded applications.
[0047] Specifically, the compiler-level optimization on C codes for register configuration, loops, judgments, calls, and returns of embedded applications includes:
[0048] The C code for register configuration is translated into OR instructions and AND instructions of the intermediate expression IR, and the optimization purpose is achieved by performing instruction selection processing on the OR instructions and the AND instructions to the BST instructions and the BCLR instructions specific to the digital signal processor;
[0049] The C code for loops, judgments, calls, and returns is translated into jump instructions such as JMP, JN, JNC, CALL, and RET, and the optimization purpose is achieved by performing instruction replacement on the delay slot NOP after the jump instructions of the digital signal processor.
[0050] The C code of register configuration is essentially assigning a value to a bit of a peripheral register, and a digital signal processor (such as QX320F280049C) has bit assignment instructions: BST instruction and BCLR instruction, which can set a bit to 0 or 1 (as shown in Figure 3 The intermediate representation IR of the LLVM compiler open source architecture does not have a bit assignment instruction, and the bit assignment is realized by OR instruction and AND instruction. Register OR a number is to set the position of a bit to 1 in the binary representation of the number, and register AND a number is to set the position of a bit to 0 in the binary representation of the number. Therefore, the number of used assembly instructions is more than that of directly using bit assignment instructions, so it is necessary to perform instruction selection processing on the OR instruction and the AND instruction to the BST instruction and the BCLR instruction specific to the digital signal processor to achieve optimization.
[0051] The C code of loop, judgment, call and return is compiled into assembly level jump instructions: JMP, JN, JNC, CALL and RET. Due to the pipeline of the digital signal processor (such as QX320F280049C), the next two instructions will be fetched and executed, so two empty delay slots NOP need to be inserted. In order to utilize the two delay slots NOP, instruction replacement needs to be performed on the delay slots NOP after the jump instruction of the digital signal processor to achieve optimization.
[0052] The specific optimization process of the present application will be described in detail in three parts in combination with the test code shown in Figure 4
[0053] I. Optimization process of C code of register configuration at compiler level
[0054] The C code of register configuration is translated into OR instruction and AND instruction of intermediate representation IR, and instruction selection processing is performed on the OR instruction and the AND instruction to the BST instruction and the BCLR instruction specific to the digital signal processor to achieve optimization, including:
[0055] All nodes in the instruction dependency acyclic directed graph of the intermediate representation IR are traversed, and the OR operator and the AND operator are analyzed. If it can be simplified into BST instruction and BCLR instruction, instruction selection processing is performed.
[0056] Specifically, all nodes in the instruction dependency acyclic directed graph are traversed, and the OR operator and the AND operator are analyzed. If it can be simplified into BST instruction and BCLR instruction, instruction selection processing is performed, as shown in Figure 1 , including:
[0057] S11, traverse all nodes in the instruction dependence acyclic directed graph of the intermediate representation IR, and if the getOpcode() of a node is found to be an OR operator or an AND operator, analyze it;
[0058] S12, if the operator is an OR operator, assign its second operand to SecondOperand; if the operator is an AND operator, take the complement of its second operand and assign it to SecondOperand, and analyze SecondOperand;
[0059] S13, if the operator is an OR operator, create a new BST operator node; if the operator is an AND operator, create a new BCLR operator node;
[0060] S14, delete the OR operator node or the AND operator node from the instruction dependence acyclic directed graph, and insert the newly created BST operator node or the newly created BCLR operator node into the corresponding position;
[0061] wherein the first operand of the newly created BST operator or BCLR operator is the value of the first operand getOperand(0) of the OR operator or the AND operator, and the second operand is the number of cyclic right shifts Count.
[0062] S11, if the getOpcode() of a node is found to be an OR operator or an AND operator, analyze it, as shown in Figure 1 , which includes:
[0063] Get the second operand of the OR operator or the AND operator through getOperand(1), and if the operand is of the ISD:Constant type of the intermediate representation IR, go to S12; otherwise, end the optimization of the operator node.
[0064] S12, analyze SecondOperand, as shown in Figure 1 , which includes:
[0065] Perform an AND operation on SecondOperand and (SecondOperand-1), and if the result of the AND operation is 0, perform a cyclic right shift operation on SecondOperand until the value after the right shift is 1, record the number of cyclic right shifts Count, and go to S13; otherwise, end the optimization of the operator node.
[0066] Figure 5For the comparison chart of the assembly codes obtained before and after optimization of the bit assignment instruction, the benefit of the present application is that the bit assignment realized by the original MOVIGL instruction+MOVIGH instruction+OR instruction or AND instruction three assembly instructions is optimized into a bit assignment instruction BST instruction or BCLR instruction through instruction selection, thereby reducing the file size and the number of cycles during running.
[0067] The C code of loop, judgment, call and return is translated into the jump instructions of JMP, JN, JNC, CALL and RET, and the NOP after the jump instruction of the digital signal processor is replaced by the instruction to achieve the optimization purpose, including:
[0068] All basic blocks are traversed, and the jump instructions of JMP, JN, JNC, CALL and RET are analyzed, if the previous instruction exists and has no data correlation with the jump instruction, the NOP after the jump instruction is replaced by the instruction in the previous instruction.
[0069] II. Optimization process of the C code of loop and judgment at the compiler level
[0070] All basic blocks are traversed, and the jump instructions of JMP, JN, JNC, CALL and RET are analyzed, if the previous instruction exists and has no data correlation with the jump instruction, the NOP after the jump instruction is replaced by the instruction in the previous instruction, as shown in the following formula: Figure 1 including:
[0071] All basic blocks of each function block are traversed, and each MachineInstr is judged, if getOpcode() of the MachineInstr is the conditional jump operator of JN and JNC, then:
[0072] The first instruction before the JN and JNC jump instructions is obtained through prev(MachineInstr, 1), if the instruction is not a comparison instruction and is not empty, then prev(MachineInstr, 1) is used to replace the first NOP after the JN and JNC jump instructions, and the next step is entered; otherwise, the optimization of the basic block is ended.
[0073] The second instruction before the JN and JNC jump instructions is obtained through prev(MachineInstr, 2), if the instruction is not a comparison instruction and is not empty, then prev(MachineInstr, 2) is used to replace the second NOP after the JN and JNC jump instructions, and the optimization of the next basic block is performed; otherwise, the optimization of the basic block is ended.
[0074] Figure 6For the comparison chart of the assembly codes obtained by compiling before and after the conditional jump instruction is optimized, the benefits of the present application are as follows: as shown by the arrow in Figure 6 , the idle delay slot NOP after the original conditional jump instruction is replaced by the useful instruction in front of the conditional jump instruction, so that the number of delay slot NOPs is reduced, the CPU idle time is shortened, and thus the size of the compiled file and the cycle number during running are reduced.
[0075] III. Optimization process of the C code of the waiting loop, call and return at the compiler level
[0076] All basic blocks are traversed, and the jump instructions such as JMP, JN, JNC, CALL and RET are analyzed, if there is an instruction in front of the jump instruction and the jump instruction has no data correlation with the instruction, the instruction in front of the jump instruction is used to replace the delay slot NOP after the jump instruction, as shown in Figure 1 , including:
[0077] All basic blocks of each function block are traversed, and each MachineInstr is judged, if the getOpcode() of the MachineInstr is the unconditional jump operator such as JMP, CALL and RET, then:
[0078] The first instruction in front of the JMP, CALL and RET jump instruction is obtained by prev(MachineInstr, 1), if the instruction is not empty, the first delay slot NOP after the JMP, CALL and RET jump instruction is replaced by prev(MachineInstr, 1), and the next step is entered; otherwise, the optimization of the basic block is ended;
[0079] The second instruction in front of the JMP, CALL and RET jump instruction is obtained by prev(MachineInstr, 2), if the instruction is not empty, the second delay slot NOP after the JMP, CALL and RET jump instruction is replaced by prev(MachineInstr, 2), and the optimization of the next basic block is performed; otherwise, the optimization of the basic block is ended.
[0080] Figure 7 For the comparison chart of the assembly codes obtained by compiling before and after the unconditional jump instruction is optimized, the benefits of the present application are as follows: as shown by the arrow in Figure 7 , the idle delay slot NOP after the original unconditional jump instruction is replaced by the useful instruction in front of the unconditional jump instruction, so that the number of delay slot NOPs is reduced, the CPU idle time is shortened, and thus the size of the compiled file and the cycle number during running are reduced.
[0081] The above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalent features; and these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A compiler optimization method for embedded applications based on digital signal processors, characterized in that: By adding a translation pass in the LLVM architecture, the hardware characteristics of the digital signal processor are utilized, and the C code related to register configuration, loops, judgments, calls, and returns in embedded applications is optimized at the compiler level. The C code related to register configuration, loops, judgments, calls, and returns in embedded applications is optimized at the compiler level, including: The C code related to register configuration is translated into OR instructions and AND instructions of the intermediate representation IR, and the optimization is achieved by performing instruction selection processing on the OR instructions and AND instructions to the BST instructions and BCLR instructions specific to the digital signal processor, including: All nodes in the instruction dependency acyclic directed graph of the intermediate representation IR are traversed, and the OR operator and the AND operator are analyzed. If they can be simplified into BST instructions and BCLR instructions, instruction selection processing is performed, including: S11, all nodes in the instruction dependency acyclic directed graph of the intermediate representation IR are traversed, and if the getOpcode() of the node is found to be an OR operator or an AND operator, it is analyzed: S12, if the operator is an OR operator, the second operand is assigned as SecondOperand; if the operator is an AND operator, the second operand is negated and then assigned as SecondOperand, and SecondOperand is analyzed: S13, if the operator is an OR operator, a new BST operator node is created; if the operator is an AND operator, a new BCLR operator node is created; S14, the OR operator node or the AND operator node is deleted from the instruction dependency acyclic directed graph, and the newly created BST operator node or BCLR operator node is inserted into the corresponding position; Wherein, the first operand of the newly created BST operator or BCLR operator is the value of the first operand getOperand(0) of the OR operator or AND operator, and the second operand is the loop right shift count Count; The analysis of SecondOperand in S12 includes: SecondOperand and (SecondOperand-1) are ANDed, if the AND result is 0, the loop right shift operation is performed on SecondOperand until the right shifted value is 1, the loop right shift count Count is recorded, and S13 is entered; otherwise, the optimization of the operator node is ended.
2. The Digital Signal Processor based compiler optimization method for embedded applications as claimed in claim 1 wherein: The C code related to register configuration, loops, judgments, calls, and returns in embedded applications is optimized at the compiler level, including: The C code related to loops, judgments, calls, and returns is translated into jump instructions such as JMP, JN, JNC, CALL, and RET, and the delay slot NOP after the jump instructions of the digital signal processor is replaced by instructions to achieve the optimization goal.
3. The Digital Signal Processor based compiler optimization method for embedded applications as claimed in claim 1 wherein: The analysis in S11 includes: The second operand of the OR operator or the AND operator is obtained by getOperand(1), and if the operand is of ISD:Constant type of the intermediate expression IR, S12 is entered; otherwise, the optimization of the operator node is ended.
4. The Digital Signal Processor based compiler optimization method for embedded applications as claimed in claim 2 wherein: The C code of the loop, judgment, calling and returning is translated into the jump instructions of JMP, JN, JNC, CALL and RET, and the instruction replacement is performed on the delay slot NOP after the jump instruction of the digital signal processor to achieve the optimization purpose, including: All basic blocks are traversed, and the jump instructions of JMP, JN, JNC, CALL and RET are analyzed, if there is a previous instruction and there is no data correlation with the jump instruction, the previous instruction is used to replace the delay slot NOP after the jump instruction.
5. The Digital Signal Processor based compiler optimization method for embedded applications as claimed in claim 4 wherein: All basic blocks are traversed, and the jump instructions of JMP, JN, JNC, CALL and RET are analyzed, if there is a previous instruction and there is no data correlation with the jump instruction, the previous instruction is used to replace the delay slot NOP after the jump instruction, including: All basic blocks of each function block are traversed, and each MachineInstr is judged, if getOpcode() of the MachineInstr is the conditional jump operator of JN and JNC, then: The first instruction before the JN and JNC jump instruction is obtained by prev(MachineInstr, 1), if the instruction is not a comparison instruction and is not empty, the first delay slot NOP after the JN and JNC jump instruction is replaced by prev(MachineInstr, 1), and the next step is entered; otherwise, the optimization of the basic block is ended; The second instruction before the JN and JNC jump instruction is obtained by prev(MachineInstr, 2), if the instruction is not a comparison instruction and is not empty, the second delay slot NOP after the JN and JNC jump instruction is replaced by prev(MachineInstr, 2), and the optimization of the next basic block is performed; otherwise, the optimization of the basic block is ended.
6. The Digital Signal Processor based compiler optimization method for embedded applications as claimed in claim 4 wherein: All basic blocks are traversed, and the jump instructions of JMP, JN, JNC, CALL and RET are analyzed, if there is a previous instruction and there is no data correlation with the jump instruction, the previous instruction is used to replace the delay slot NOP after the jump instruction, including: All basic blocks of each function block are traversed, and each MachineInstr is judged, if getOpcode() of the MachineInstr is the unconditional jump operator of JMP, CALL and RET, then: The first instruction before the JMP, CALL and RET jump instruction is obtained by prev(MachineInstr, 1), if the instruction is not empty, the first delay slot NOP after the JMP, CALL and RET jump instruction is replaced by prev(MachineInstr, 1), and the next step is entered; otherwise, the optimization of the basic block is ended; prev(MachineInstr, 2) is used to get the second instruction before the JMP, CALL, or RET jump instruction. If the instruction is not empty, the second delay slot NOP after the JMP, CALL, or RET jump instruction is replaced by prev(MachineInstr, 2), and the optimization of the next basic block is performed. Otherwise, the optimization of the basic block is ended.
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