A semiconductor device and a method for detecting N-type well offset thereof

Abstract

The present application provides a semiconductor device and a method for detecting an N-type well offset thereof, wherein a P-type well, a first N-type well, a second N-type well, and an isolation structure are all disposed in a substrate; the first N-type well and the second N-type well are respectively located on either side of the P-type well and are both spaced apart from the P-type well; both sides of the isolation structure are respectively in contact with the first N-type well and the second N-type well, and the bottom of the isolation structure is in contact with the P-type well; in a direction from the isolation structure toward the P-type well, an area where the orthographic projection of the first N-type well does not overlap with the orthographic projection of the isolation structure and overlaps with the orthographic projection of the substrate is a first overlap area, and an area where the orthographic projection of the second N-type well does not overlap with the orthographic projection of the isolation structure and overlaps with the orthographic projection of the substrate is a second overlap area; a testing portion includes a first test pad and a second test pad, the first test pad and the second test pad being located at upper and lower ends of the first overlap area and the second overlap area, respectively, to improve the detection efficiency of the N-type well offset.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for detecting an N-type well offset of a semiconductor device. Background Art

[0002] In IC manufacturing, photolithography is the most complex and critical process step, and overlay accuracy is one of the important performance indicators. As the feature size of the photolithography process in integrated circuit manufacturing continues to decrease, the requirements for overlay accuracy are gradually increasing. If the overlay accuracy does not meet the design rules, the circuits between the components of each layer of the device cannot be accurately connected, and short circuits or open circuits may occur, resulting in loss of production yield and device performance. Only by accurately measuring the true overlay error (OVL) can we try to effectively compensate and correct it in subsequent processes. The offset is also called overlay error, which is an important parameter that describes the overlay accuracy between the rear and front layer patterns. In manufacturing, the ideal overlay error value is 0, that is, each photolithography layer can be completely aligned, but due to various process factors, it is basically impossible to achieve the ideal state. At present, the method used to detect overlay error is relatively cumbersome and difficult to operate, resulting in low detection efficiency. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor device and a method for detecting an N-type well offset thereof, so as to improve the detection efficiency of the N-type well offset.

[0004] The present application provides a semiconductor device, comprising:

[0005] substrate;

[0006] A P-type well is provided in the substrate;

[0007] A first N-type well and a second N-type well are provided in the substrate, wherein the first N-type well and the second N-type well are respectively located on both sides of the P-type well and are spaced apart from the P-type well;

[0008] an isolation structure disposed in the substrate, wherein two sides of the isolation structure are respectively in contact with the first N-type well and the second N-type well, and a bottom of the isolation structure is in contact with the P-type well; in a direction from the isolation structure toward the P-type well, an area where the orthographic projection of the first N-type well does not overlap with the orthographic projection of the isolation structure and overlaps with the orthographic projection of the substrate is a first overlapping area, and an area where the orthographic projection of the second N-type well does not overlap with the orthographic projection of the isolation structure and overlaps with the orthographic projection of the substrate is a second overlapping area;

[0009] The testing portion includes at least one first test pad and at least one second test pad arranged at intervals, wherein the first test pad is located at one of the upper end and the lower end of the first overlapping area and the second overlapping area, and the second test pad is located at the other of the upper end and the lower end of the first overlapping area and the second overlapping area.

[0010] In some embodiments, the semiconductor device further includes an isolation ring disposed in the substrate. The isolation ring is located on a side of the first N-type well and the second N-type well away from the P-type well and is spaced apart from the first N-type well and the second N-type well.

[0011] In some embodiments, a distance between the bottom of the first N-type well and the second N-type well and the bottom of the isolation structure is smaller than a distance between the P-type well and the bottom of the isolation structure.

[0012] In some embodiments, the semiconductor device further includes a first contact hole and a second contact hole, the first contact hole exposing the first overlapping area, the second contact hole exposing the second overlapping area, the first test pad filling the first contact hole, and the second test pad filling the second contact hole.

[0013] In some embodiments, the shapes of the first test pad and the second test pad include at least one of square, rectangle, circle, and triangle.

[0014] The present application also provides a method for detecting an N-type well offset of a semiconductor device, which is used to detect the semiconductor device as described above, comprising:

[0015] electrically connecting a low-voltage terminal and a high-voltage terminal of a test device to a first test pad and a second test pad located on a first overlap region, respectively, to measure a first resistance value of the first overlap region;

[0016] electrically connecting the low voltage end and the high voltage end of the test device to the first test pad and the second test pad located on the second overlap area, respectively, to measure a second resistance value of the second overlap area;

[0017] Calculating a first resistance difference between the first resistance value and the second resistance value and a sum of the first resistances of the first resistance value and the second resistance value, wherein the product of the first resistance difference and a first preset length of the first overlapping area is a first resistance product value;

[0018] The offsets of the first N-type well and the second N-type well relative to the first direction of the substrate are obtained according to a first ratio of the first resistance product to the sum of the first resistances.

[0019] In some embodiments, the low voltage end and the high voltage end of the testing device are electrically connected to the first test pad and the second test pad located on the second overlap region, respectively. After measuring the second resistance value of the second overlap region, the resistance difference between the first resistance value and the second resistance value and the sum of the resistances of the first resistance value and the second resistance value are calculated, and before the product of the resistance difference and the first predetermined length of the first overlap region is calculated as the resistance product value, the method further includes:

[0020] The semiconductor device is rotated 90 degrees, and the low voltage end and the high voltage end of the test device are electrically connected to the first test pad and the second test pad located on the first overlap area respectively, and a third resistance value of the first overlap area is measured.

[0021] In some embodiments, after rotating the semiconductor device 90°, electrically connecting the low-voltage terminal and the high-voltage terminal of the test device to the first test pad and the second test pad located on the first overlap region, respectively, and measuring the third resistance value of the first overlap region, the method further includes:

[0022] The low voltage end and the high voltage end of the test device are electrically connected to the first test pad and the second test pad located on the second overlap area respectively, and a fourth resistance value of the second overlap area is measured.

[0023] In some embodiments, after electrically connecting the low voltage terminal and the high voltage terminal of the test device to the first test pad and the second test pad located on the second overlap region, respectively, and measuring the fourth resistance value of the second overlap region, the method further includes:

[0024] Calculating a second resistance difference between the third resistance value and the fourth resistance value and a sum of the second resistances of the third resistance value and the fourth resistance value, wherein the product of the second resistance difference and a first preset width of the first overlapping area is a second resistance product value;

[0025] The offsets of the first N-type well and the second N-type well relative to a second direction of the substrate are obtained according to a second ratio of the second resistance product to the sum of the second resistances, where the first direction is perpendicular to the second direction.

[0026] In some embodiments, whether the first ratio is 0 is used to determine whether the first N-type well and the second N-type well are offset in a first direction relative to the substrate.

[0027] The present application provides a semiconductor device and a method for detecting an N-type well offset thereof, wherein the semiconductor device includes a substrate, a P-type well, a first N-type well, a second N-type well, an isolation structure, and a testing portion; the P-type well is provided in the substrate; the first N-type well and the second N-type well are provided in the substrate, the first N-type well and the second N-type well are respectively located on both sides of the P-type well and are spaced apart from the P-type well; the isolation structure is provided in the substrate, the two sides of the isolation structure are respectively in contact with the first N-type well and the second N-type well, and the bottom of the isolation structure is in contact with the P-type well; a test portion is provided from the isolation structure toward the P-type well. In the direction of the N-type well, the area where the orthographic projection of the first N-type well does not overlap with the orthographic projection of the isolation structure and overlaps with the orthographic projection of the substrate is a first overlap area, and the area where the orthographic projection of the second N-type well does not overlap with the orthographic projection of the isolation structure and overlaps with the orthographic projection of the substrate is a second overlap area; the testing section includes at least one first test pad and at least one second test pad arranged at intervals, the first test pad is located at one of the upper end and the lower end of the first overlap area and the second overlap area, and the second test pad is located at the other of the upper end and the lower end of the first overlap area and the second overlap area. By arranging the testing section on both the first overlap area and the second overlap area, the resistance of the first overlap area and the second overlap area can be measured when the testing device is electrically connected to the first test pad and the second pad, so that the left and right offset of the N-type well relative to the substrate can be calculated based on the resistance changes of the first overlap area and the second overlap area, thereby improving the detection efficiency of the N-type well offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 is a schematic diagram of a top view of the semiconductor device provided by the present application;

[0030] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure of the semiconductor device along line AB;

[0031] Figure 3 It is a flow chart of a method for detecting an N-type well offset of a semiconductor device provided in the present application.

[0032] Reference numerals:

[0033] 10. Semiconductor device; 100. Substrate; 200. P-type well; 300. First N-type well; 400. Second N-type well; 500. Isolation structure; 600. Test unit; 610. First test pad; 620. Second test pad; 700. First overlap region; 800. Second overlap region. DETAILED DESCRIPTION

[0034] The following, in conjunction with the accompanying drawings, clearly and completely describes the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of this application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items. The terms "connected", "electrically connected", and "electrically connected" as used herein include any direct and indirect electrical or structural connection means. Therefore, if the text describes a first device as being coupled / connected / electrically connected to a second device, it means that the first device can be directly electrically / structurally connected to the second device, or indirectly electrically / structurally connected to the second device through other devices or connection means.

[0037] The present application provides a semiconductor device, comprising a substrate, a P-type well, a first N-type well, a second N-type well, an isolation structure, and a testing section. The P-type well is disposed in the substrate. The first N-type well and the second N-type well are disposed in the substrate, the first N-type well and the second N-type well being located on either side of the P-type well, respectively, and both being spaced apart from the P-type well. The isolation structure is disposed in the substrate, the two sides of the isolation structure being in contact with the first N-type well and the second N-type well, respectively, and the bottom of the isolation structure being in contact with the P-type well. In a direction from the isolation structure toward the P-type well, an area where the orthographic projection of the first N-type well does not overlap with the orthographic projection of the isolation structure but overlaps with the orthographic projection of the substrate is a first overlapping area, and an area where the orthographic projection of the second N-type well does not overlap with the orthographic projection of the isolation structure but overlaps with the orthographic projection of the substrate is a second overlapping area. The testing section comprises at least one first test pad and at least one second test pad spaced apart from each other. The first test pad is located at one of an upper end and a lower end of the first overlapping area and the second overlapping area, and the second test pad is located at the other of an upper end and a lower end of the first overlapping area and the second overlapping area.

[0038] In the present application, by setting up a test section on both the first overlap area and the second overlap area, when the test device is electrically connected to the first test pad and the second test pad, the resistance of the first overlap area and the second overlap area can be measured, and the left and right offsets of the N-type well relative to the substrate are calculated based on the resistance changes of the first overlap area and the second overlap area, that is, the detection efficiency of the N-type well offset is improved, so that it is possible to quickly check whether the impact is caused by the N-type well offset, reduce the steps required for inspection, and enable other semiconductor devices to correct the position between their N-type wells and the substrate based on the obtained offset, ensure the connection relationship between the N-type well and the substrate is accurate, and reduce the risk of semiconductor devices being scrapped. In addition, adopting this design can facilitate monitoring whether the N-type well in each semiconductor device is offset.

[0039] See also Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a top view of the semiconductor device provided by the present application; Figure 2 yes Figure 1Schematic diagram of the cross-sectional structure of the semiconductor device along line AB in the figure. The present application provides a semiconductor device 10, which includes a substrate 100, a P-type well 200, a first N-type well 300, a second N-type well 400, an isolation structure 500, and a testing unit 600; the P-type well 200 is arranged in the substrate 100; the first N-type well 300 and the second N-type well 400 are arranged in the substrate 100, and the first N-type well 300 and the second N-type well 400 are respectively located on both sides of the P-type well 200 and are spaced apart from the P-type well 200; the isolation structure 500 is arranged in the substrate 100, and the two sides of the isolation structure 500 are respectively in contact with the first N-type well 300 and the second N-type well 400, and the bottom of the isolation structure 500 is in contact with the P-type well 200; in the direction from the isolation structure 500 toward the P-type well 200, the first N-type well 300 and the second N-type well 400 are spaced apart from the P-type well 200. The area where the orthographic projection of the N-type well 300 does not overlap with the orthographic projection of the isolation structure 500 and overlaps with the orthographic projection of the substrate 100 is the first overlapping area 700, and the area where the orthographic projection of the second N-type well 400 does not overlap with the orthographic projection of the isolation structure 500 and overlaps with the orthographic projection of the substrate 100 is the second overlapping area 800; the testing portion 600 includes at least one first test pad 610 and at least one second test pad 620 arranged at intervals, the first test pad 610 is located at one of the upper and lower ends of the first overlapping area 700 and the second overlapping area 800, and the second test pad 620 is located at the other of the upper and lower ends of the first overlapping area 700 and the second overlapping area 800, and the arrangement direction of the first test pad 610 and the second test pad 620 is perpendicular to the second direction y. Optionally, the first N-type well 300 and the second N-type well 400 are formed by implanting N-type ions into the substrate 100, the P-type well 200 is formed by implanting P-type ions into the substrate 100, and the test portion 600 is formed of a conductive material. The shapes of the first test pad 610 and the second test pad 620 include at least one of square, rectangular, circular, and triangular.

[0040] In one embodiment, the semiconductor device 10 further includes an isolation ring, which is made of an insulating material, such as a silicon nitride or silicon oxide layer. The isolation ring is disposed in the substrate 100. The isolation ring is located on a side of the first N-type well 300 and the second N-type well 400 away from the P-type well 200 and is spaced apart from the first N-type well 300 and the second N-type well 400.

[0041] In one embodiment, the distance between the bottom of the first N-type well 300 and the second N-type well 400 and the bottom of the isolation structure 500 is smaller than the distance between the P-type well 200 and the bottom of the isolation structure 500 .

[0042] In one embodiment, the semiconductor device 10 further includes a first contact hole and a second contact hole, the first contact hole exposing the first overlapping area 700 , the second contact hole exposing the second overlapping area 800 , the first test pad 610 filling the first contact hole, and the second test pad 620 filling the second contact hole.

[0043] The present application improves a semiconductor device 10, by setting a test part 600 on both the first overlapping area 700 and the second overlapping area 800, so that when the test device is electrically connected to the first test pad 610 and the second pad, the resistance of the first overlapping area 700 and the second overlapping area 800 can be measured, so that the left and right offsets of the N-type well relative to the substrate 100 can be calculated based on the resistance changes of the first overlapping area 700 and the second overlapping area 800, that is, the detection efficiency of the film layer offset is improved, so that it is possible to quickly check whether the impact is caused by the N-type well offset, reduce the steps required for inspection, and enable other semiconductor devices 10 to correct the position between their N-type wells and the substrate 100 according to the obtained offset, thereby ensuring that the connection relationship between the N-type well and the substrate 100 is accurate and reducing the risk of the semiconductor device 10 being scrapped. Furthermore, after rotating the semiconductor device 10 by 90°, the test device is electrically connected to the first test pad 610 and the second test pad 620, and the resistance of the first overlap region 700 and the second overlap region 800 can be measured. Based on the resistance changes in the first overlap region 700 and the second overlap region 800, the vertical offset of the N-type well relative to the substrate 100 can be calculated. This improves the efficiency of detecting film offset, allowing for quicker verification of whether the N-type well offset is causing an impact, reducing the number of inspection steps required, and allowing other semiconductor devices 10 to correct their positions between the N-type well and the substrate 100 based on the obtained offset, thereby reducing the risk of semiconductor device 10 being scrapped. Furthermore, this design facilitates monitoring of whether the N-type well in each semiconductor device 10 is offset.

[0044] See also Figure 3 , Figure 3 This is a flow chart of a method for detecting an N-type well offset of a semiconductor device provided by the present application. This application also provides a method for detecting an N-type well offset of a semiconductor device, which is used to detect a film layer offset of the semiconductor device provided by the present application, and the method comprises:

[0045] S11 , electrically connecting the low voltage end and the high voltage end of the test device to the first test pad and the second test pad located on the first overlap area respectively, and measuring the first resistance value of the first overlap area.

[0046] Please continue reading Figure 1 and Figure 2The first N-type well 300 and the second N-type well 400 are pre-set to have a first preset length L of overlap with the substrate 100, and the width of the substrate 100 is measured to be a first width W. The first preset length L and the first width W are both fixed values, wherein the first width W is a fixed value, i.e., ensuring that during the fabrication of the semiconductor device 10, the first N-type well 300 and the second N-type well 400 only have leftward or upward offsets, which are control variables. If the first N-type well 300 and the second N-type well 400 have a first direction x offset relative to the substrate 100, i.e., the film layers are offset leftward or rightward, and assuming that the first N-type well 300 and the second N-type well 400 are offset to the right by a distance ΔL, the overlap length of the first N-type well 300 and the substrate 100 becomes L-ΔL, and the overlap length of the second N-type well 400 and the substrate 100 becomes L+ΔL, i.e., the length of the first overlap region 700 becomes L-ΔL, and the length of the second overlap region 800 becomes L+ΔL.

[0047] At this time, the first test pad 610 and the second test pad 620 are spaced apart along the second direction y, the first N-type well 300 and the second N-type well 400 are arranged along the first direction x, and the first test pad 610 and the second test pad 620 are respectively located at the upper end and the lower end of the first overlap area 700 and the second overlap area 800. Optionally, the positions of the first test pad 610 and the second test pad 620 can be interchanged. The low voltage end and the high voltage end of the test device can be connected to the first test pad 610 and the second test pad 620 located on the first overlap area 700 to measure the first resistance value R1 of the first overlap area 700. Optionally, the low voltage end and the high voltage end of the test device can be connected to the first test pad 610 and the second test pad 620 located on the first overlap area 700 at interchangeable positions.

[0048] S12 , electrically connecting the low voltage end and the high voltage end of the test device to the first test pad and the second test pad located on the second overlap area respectively, and measuring a second resistance value of the second overlap area.

[0049] Specifically, the low-voltage terminal and the high-voltage terminal of the test device are electrically connected to the first test pad 610 and the second test pad 620 located on the second overlap region 800, respectively, to measure the second resistance value R2 of the second overlap region 800. Optionally, the low-voltage terminal and the high-voltage terminal of the test device can be connected to the first test pad 610 and the second test pad 620 located on the second overlap region 800 at interchangeable positions.

[0050] S13, calculating a first resistance difference between the first resistance value and the second resistance value and a sum of the first resistances of the first resistance value and the second resistance value, wherein the product of the first resistance difference and the preset length of the first overlapping area is a first resistance product.

[0051] Specifically, based on the first resistance value R1 and the second resistance value R2, the first resistance difference R1-R2 between the first resistance value R1 and the second resistance value R2 and the first resistance sum R1+R2 of the first resistance value R1 and the second resistance value R2 are calculated. The product of the first resistance difference R1-R2 and the preset length L of the first overlapping area 700 is the first resistance product value (R1-R2)*L.

[0052] According to the resistance formula:

[0053] R1 = ρ*W / ((L-ΔL)*t), R2 = ρ*W / ((L+ΔL)*t), where ρ is the resistivity of the material of which the resistor is made.

[0054] Dividing the two resistance formulas of R1 and R2, we get R1 / R2=(L+△L) / (L-△L), △L=(R1-R2)*L / (R1+R2), R1-R2 is the first resistance difference between the first resistance value R1 and the second resistance value R2, R1+R2 is the sum of the first resistances of the first resistance value R1 and the second resistance value R2, and (R1-R2)*L is the product of the first resistance difference (R1-R2) and the preset length L of the first overlapping area as the first resistance product value.

[0055] S14 , obtaining offsets of the first N-type well and the second N-type well relative to a first direction of the substrate according to a first ratio of the first resistance product to the sum of the first resistances.

[0056] Whether the first ratio is 0 is used to determine whether the first N-type well and the second N-type well are offset relative to the first direction x of the substrate 100. If the first ratio is 0, then the first N-type well and the second N-type well are not offset relative to the first direction x of the substrate 100, and the processes for forming the N-type wells and the substrate 100 in other semiconductor devices 10 do not need to be changed. If the first ratio is not 0, then the first N-type well and the second N-type well are offset relative to the first direction x of the substrate 100, and the processes for forming the N-type wells and the substrate 100 in other semiconductor devices 10 need to be adjusted based on the offset, thereby reducing the risk of semiconductor devices 10 being scrapped.

[0057] In one embodiment, after step S12 and before step S13, the method further includes:

[0058] The semiconductor device 10 is rotated 90°. At this time, the first test pad 610 and the second test pad 620 are arranged at intervals along the first direction x, and the first N-type well 300 and the second N-type well 400 are arranged at intervals along the second direction y. The overlap width of the first N-type well 300 and the second N-type well 400 with the substrate 100 is preset to be a first preset width L. The length of the substrate 100 is measured to be a first length W. The first preset width L and the first length W are both determined values. The first length W is a fixed value, which ensures that during the fabrication process of the semiconductor device 10, the first N-type well 300 and the second N-type well 400 only have leftward or upward and downward offsets, thereby controlling the variables.

[0059] If the first N-type well 300 and the second N-type well 400 are offset in the second direction y relative to the substrate 100, that is, the film layers are offset up and down; assuming that the distance the first N-type well 300 and the second N-type well 400 are offset downward is ΔL, the overlapping width of the first N-type well 300 and the substrate 100 becomes L-ΔL, and the overlapping width of the second N-type well 400 and the substrate 100 becomes L+ΔL, that is, the width of the first overlapping area 700 becomes L-ΔL, and the width of the second overlapping area 800 becomes L+ΔL.

[0060] The low-voltage end and the high-voltage end of the test device are electrically connected to the first test pad 610 and the second test pad 620 located on the first overlapping area 700, respectively, and the third resistance value R3 of the first overlapping area 700 is measured; then, the low-voltage end and the high-voltage end of the test device are electrically connected to the first test pad 610 and the second test pad 620 located on the second overlapping area 800, respectively, and the fourth resistance value R4 of the second overlapping area 800 is measured.

[0061] Then, the second resistance difference R3-R4 between the third resistance value R3 and the fourth resistance value R4 and the second resistance sum R3+R4 of the third resistance value R3 and the fourth resistance value R4 are calculated using the measured third resistance value R3 and the fourth resistance value R4. The product of the second resistance difference R3-R4 and the first predetermined width L of the first overlap area 700 is the second resistance product (R3-R4). Specifically, the measured third resistance value R3 and the fourth resistance value R4 are calculated. Then, the two resistance formulas of R3 and R4 are divided to obtain R3 / R4=(L+△L) / (L-△L), △L=(R3-R4)*L / (R3+R4), and the second resistance difference R3-R4 between the third resistance value R3 and the fourth resistance value R4 and the sum of the second resistance R3+R4 of the third resistance value R3 and the fourth resistance value R4 are obtained. The product of the second resistance difference R3-R4 and the first preset width L of the first overlapping area 700 is the second resistance product value (R3-R4).

[0062] Then, based on the second ratio of the second resistance product (R3-R4)*L to the second resistance sum R3+R4, the offset of the N-type well relative to the substrate 100 in the second direction y is obtained, where the first direction x is perpendicular to the second direction y. Based on whether the second ratio is 0, it is determined whether the N-type well is offset relative to the substrate 100 in the second direction y. If the second ratio is 0, then the first N-type well and the second N-type well are not offset relative to the substrate 100 in the second direction y, and the processes for forming the N-type well and the substrate 100 in other semiconductor devices 10 do not need to be changed. If the second ratio is not 0, then the first N-type well and the second N-type well are offset relative to the substrate 100 in the second direction y, and the processes for forming the N-type well and the substrate 100 in other semiconductor devices 10 need to be adjusted based on the offset, thereby reducing the risk of semiconductor devices 10 being scrapped.

[0063] The present application improves a method for detecting the offset of the N-type well of a semiconductor device 10. By connecting a test device to a test portion 600 located on a first overlap region 700 and a second overlap region 800, the resistance of the first overlap region 700 and the second overlap region 800 can be measured. The left and right and up and down offsets of the N-type well relative to the substrate 100 are calculated based on the resistance changes of the first overlap region 700 and the second overlap region 800. This improves the efficiency of detecting the offset of the film layer, so that it is possible to quickly check whether the offset of the N-type well has caused an impact, reduce the number of inspection steps required, and enable other semiconductor devices 10 to correct the position between their N-type wells and the substrate 100 based on the obtained offset, thereby ensuring that the connection relationship between the N-type well and the substrate 100 is accurate and reducing the risk of the semiconductor device 10 being scrapped. In addition, adopting this design can facilitate monitoring whether the N-type well in each semiconductor device 10 is offset.

[0064] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; A P-type well is provided in the substrate; A first N-type well and a second N-type well are provided in the substrate, wherein the first N-type well and the second N-type well are respectively located on both sides of the P-type well and are spaced apart from the P-type well; an isolation structure disposed in the substrate, wherein two sides of the isolation structure are respectively in contact with the first N-type well and the second N-type well, and a bottom of the isolation structure is in contact with the P-type well; in a direction from the isolation structure toward the P-type well, an area where the orthographic projection of the first N-type well does not overlap with the orthographic projection of the isolation structure and overlaps with the orthographic projection of the substrate is a first overlapping area, and an area where the orthographic projection of the second N-type well does not overlap with the orthographic projection of the isolation structure and overlaps with the orthographic projection of the substrate is a second overlapping area; The testing portion includes at least one first test pad and at least one second test pad arranged at intervals, wherein the first test pad is located at one of the upper end and the lower end of the first overlapping area and the second overlapping area, and the second test pad is located at the other of the upper end and the lower end of the first overlapping area and the second overlapping area.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes an isolation ring disposed in the substrate. The isolation ring is located on a side of the first N-type well and the second N-type well away from the P-type well and is spaced apart from the first N-type well and the second N-type well.

3. The semiconductor device according to claim 1, wherein The distances between the bottoms of the first N-type well and the second N-type well and the bottom of the isolation structure are smaller than the distance between the P-type well and the bottom of the isolation structure.

4. The semiconductor device according to claim 1, wherein The semiconductor device further includes a first contact hole and a second contact hole, the first contact hole exposing the first overlap region, the second contact hole exposing the second overlap region, the first test pad filling the first contact hole, and the second test pad filling the second contact hole.

5. The semiconductor device according to claim 1, wherein The shapes of the first test pad and the second test pad include at least one of square, rectangle, circle and triangle.

6. A method for detecting an N-type well offset of a semiconductor device, characterized in that: For detecting an N-type well offset of a semiconductor device according to any one of claims 1 to 5, comprising: electrically connecting a low-voltage terminal and a high-voltage terminal of a test device to a first test pad and a second test pad located on a first overlap region, respectively, to measure a first resistance value of the first overlap region; electrically connecting the low voltage end and the high voltage end of the test device to the first test pad and the second test pad located on the second overlap area, respectively, to measure a second resistance value of the second overlap area; Calculating a first resistance difference between the first resistance value and the second resistance value and a sum of the first resistances of the first resistance value and the second resistance value, wherein the product of the first resistance difference and a first preset length of the first overlapping area is a first resistance product value; The offsets of the first N-type well and the second N-type well relative to the first direction of the substrate are obtained according to a first ratio of the first resistance product to the sum of the first resistances.

7. The method for detecting an N-type well offset of a semiconductor device according to claim 6, wherein: After electrically connecting the low voltage terminal and the high voltage terminal of the test device to the first test pad and the second test pad located on the second overlap area, respectively, and measuring the second resistance value of the second overlap area, the resistance difference between the first resistance value and the second resistance value and the sum of the resistances of the first resistance value and the second resistance value are calculated, and before the product of the resistance difference and the first preset length of the first overlap area is calculated as the resistance product value, the method further includes: The semiconductor device is rotated 90 degrees, and the low voltage end and the high voltage end of the test device are electrically connected to the first test pad and the second test pad located on the first overlap area respectively, and a third resistance value of the first overlap area is measured.

8. The method for detecting an N-type well offset of a semiconductor device according to claim 7, wherein: After rotating the semiconductor device by 90 degrees, electrically connecting the low-voltage terminal and the high-voltage terminal of the test device to the first test pad and the second test pad located on the first overlap area, respectively, and measuring the third resistance value of the first overlap area, the method further includes: The low voltage end and the high voltage end of the test device are electrically connected to the first test pad and the second test pad located on the second overlap area respectively, and a fourth resistance value of the second overlap area is measured.

9. The method for detecting an N-type well offset of a semiconductor device according to claim 8, wherein: After electrically connecting the low voltage end and the high voltage end of the test device to the first test pad and the second test pad located on the second overlap area respectively and measuring the fourth resistance value of the second overlap area, the method further includes: Calculating a second resistance difference between the third resistance value and the fourth resistance value and a sum of the second resistances of the third resistance value and the fourth resistance value, wherein the product of the second resistance difference and a first preset width of the first overlapping area is a second resistance product value; The offsets of the first N-type well and the second N-type well relative to a second direction of the substrate are obtained according to a second ratio of the second resistance product to the sum of the second resistances, where the first direction is perpendicular to the second direction.

10. The method for detecting an N-type well offset of a semiconductor device according to claim 6, wherein: According to whether the first ratio is 0, it is determined whether the first N-type well and the second N-type well are offset in a first direction relative to the substrate.

Images