A single-longitudinal-mode silicon-based iii-v sub-micron wire laser and a method of fabricating the same

Abstract

The application discloses a single-longitudinal-mode silicon-based III-V submicron wire laser and a preparation method thereof, and belongs to the technical field of optoelectronic devices. The laser comprises a doped silicon layer, a silicon oxide layer, a groove, a III-V submicron wire epitaxial structure, a first electrode and a second electrode. The groove comprises a selected-area groove penetrating through the silicon oxide layer and a V-shaped groove in the doped silicon layer, and the selected-area groove is provided with a refractive index perturbation structure on the side surface. The application further discloses a preparation method of the laser. The grating structure of the laser is automatically formed in the process of etching the selected-area groove with the refractive index perturbation structure and growing the III-V submicron wire epitaxial structure, and an additional grating preparation process is not needed, so that the process steps are reduced, the manufacturing cost of the laser is greatly reduced, and the batch production of the single-longitudinal-mode silicon-based III-V submicron wire laser is more facilitated.

Description

Technical Field

[0001] This application relates to the field of optoelectronic device technology, and in particular to a single-longitudinal-mode silicon-based III-V submicron line laser and its fabrication method. Background Technology

[0002] Silicon-based opto-electronic integrated circuit (OEIC) technology has demonstrated significant application value and market potential in fields such as optical communication, biosensing, quantum computing, and optical computing. Based on microelectronics technology, OEIC technology utilizes existing complementary metal-oxide-semiconductor (CMOS) processes to develop silicon photonic devices. Using photons as the information transmission carrier, it combines microelectronics and optoelectronics, leveraging the advantages of advanced and mature microelectronic processes, high-density integration, and low cost, while also taking advantage of photons' high transmission rate, high interference immunity, and low power consumption. A complete silicon-based OEIC chip system requires the integration of components such as lasers, optical modulators, optical switches, optical filters, optical waveguides, and photodetectors within a CMOS circuit. Because silicon is an indirect bandgap material, its luminous efficiency is very low, making high-efficiency lasers on silicon one of the major technical challenges hindering the integration of silicon-based optoelectronics.

[0003] Silicon-based bonded lasers have been commercialized, but they struggle to meet the demands of large-scale integration. Aspect-ratio trapping (ART) technology, which uses small-area selective epitaxy of III-V direct bandgap semiconductor materials on silicon, allows for the fabrication of III-V submicron line lasers at arbitrary locations on the wafer. This is highly beneficial for promoting large-scale, high-density integration of silicon-based OEIC chips. However, silicon has a diamond structure, making it difficult to obtain natural cleavage surfaces through slicing operations like indium phosphide (InP) and other zincblende structures. Furthermore, cleavage methods hinder silicon-based III-V submicron line lasers from leveraging their ease of large-scale integration. Therefore, it is necessary to develop methods to obtain optical resonators for silicon-based III-V submicron line lasers without wafer dicing. Current methods for fabricating optical resonators using focused ion beam (FIB) technology suffer from physical damage to III-V submicron lines, resulting in significant optical loss at the etched cavity surface. Furthermore, FIB grating etching is complex, time-consuming, and expensive. Therefore, low-cost, high-performance grating fabrication is one of the urgent problems to be solved in silicon-based III-V submicron line lasers. Summary of the Invention

[0004] To address the shortcomings of the existing technologies, this application provides a single-longitudinal-mode silicon-based III-V submicron line laser and its fabrication method. The purpose is to solve or alleviate the problems of complex operation, long time consumption, and high cost in the process of fabricating silicon-based III-V submicron line lasers using FIB etching process.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] In a first aspect, this application provides a single-longitudinal-mode silicon-based III-V submicron line laser, comprising:

[0007] Doped silicon layer;

[0008] A silicon oxide layer disposed on the surface of the doped silicon layer;

[0009] The trenches are disposed within the doped silicon layer and the silicon oxide layer; the trenches are divided into interconnected selected area trenches and V-shaped trenches. The selected area trenches penetrate the silicon oxide layer, and the sides of the selected area trenches are provided with refractive index perturbation structures. The V-shaped trenches are disposed in the doped silicon layer and are composed of two Si{111} planes. The width of the V-shaped trenches at the contact surface with the selected area trenches is not less than the width of the selected area trenches.

[0010] A III-V submicron line epitaxial structure disposed inside the trench; the III-V submicron line epitaxial structure and the refractive index perturbation structure together form a grating structure;

[0011] A first electrode is disposed on the surface of the doped silicon layer; the first electrode forms an ohmic contact with the doped silicon layer;

[0012] A second electrode is disposed on the surface of the silicon oxide layer and the III-V submicron epitaxial structure, and the second electrode forms an ohmic contact with the III-V submicron epitaxial structure.

[0013] Furthermore, the doped silicon layer is the top silicon layer of a silicon substrate or an SOI substrate, or the bottom silicon layer of an SOI substrate.

[0014] Furthermore, the silicon oxide layer is silicon dioxide (SiO2).

[0015] Furthermore, the III-V group submicron line epitaxial structure includes at least a doped buffer layer, a lower cladding layer, a multi-quantum well active region, an upper cladding layer, and a doped contact layer in a direction away from the doped silicon layer, wherein the multi-quantum well active region is located within the region of the selected trench.

[0016] Secondly, this application provides a method for fabricating a single-longitudinal-mode silicon-based III-V submicron line laser, comprising the following steps:

[0017] Select the top silicon layer of the silicon substrate, the top silicon layer of the SOI substrate, and the bottom silicon layer of the SOI substrate as the doped silicon layer.

[0018] Prepare a silicon dioxide layer to form a silicon oxide layer;

[0019] Selective trenches with reflectivity perturbation structures are fabricated in the silicon oxide layer, and the selected trenches penetrate the silicon oxide layer;

[0020] A V-shaped trench is formed in the doped silicon layer; the V-shaped trench is connected to the selected area trench to form an integral trench;

[0021] In the trench, at least a doped buffer layer, a lower cladding layer, a multi-quantum well active region, an upper cladding layer, and a doped contact layer are grown sequentially in a direction away from the V-shaped trench to form a III-V group submicron line epitaxial structure.

[0022] A first electrode is formed in an ohmic contact with the doped silicon layer on the surface of the doped silicon layer, and a second electrode is formed in an ohmic contact with the doped contact layer on the surface of the silicon oxide layer and the III-V submicron line epitaxial structure.

[0023] Furthermore, when the doped silicon layer is the bottom silicon layer of the SOI substrate, the fabrication method further includes the step of removing the top silicon layer of the SOI substrate before fabricating the selected area trench.

[0024] This application provides a single-longitudinal-mode silicon-based III-V submicron line laser and its fabrication method, which has at least the following advantages compared with the prior art:

[0025] (1) In the single-longitudinal-mode silicon-based III-V submicron line laser provided in this application, the grating structure is automatically formed during the process of etching selected trenches with refractive index perturbation structure and growing III-V submicron line epitaxial structure. No additional grating fabrication process is required, which reduces the process steps and significantly reduces the manufacturing cost of the laser.

[0026] (2) Compared with etching DBR gratings using FIB process, the grating fabrication method provided in this application will not cause physical damage to the III-V submicron line epitaxial structure and is conducive to the mass production of single-longitudinal-mode silicon-based III-V submicron line lasers. Attached Figure Description

[0027] The present application will be described in further detail below with reference to the accompanying drawings and preferred embodiments. However, those skilled in the art will understand that these drawings are drawn only for the purpose of explaining the preferred embodiments and therefore should not be construed as limiting the scope of the present application. Furthermore, unless specifically indicated, the drawings are only schematic representations of the composition or structure of the described objects and may contain exaggerated depictions, and the drawings are not necessarily drawn to scale.

[0028] Figure 1 A schematic cross-sectional view of a single-longitudinal-mode silicon-based III-V submicron line laser provided in an embodiment of this application along the YZ plane;

[0029] Figure 2 A cross-sectional view of the trench along the YZ plane of a single-longitudinal-mode silicon-based III-V submicron line laser provided in an embodiment of this application;

[0030] Figure 3 A schematic cross-sectional view of the selected area trench with a first refractive index perturbation structure along the XY plane provided in an embodiment of this application;

[0031] Figure 4 A cross-sectional schematic diagram along the XY plane of a portion of the grating structure provided in the embodiments of this application;

[0032] Figure 5 A schematic cross-sectional view of the selected area trench with a second refractive index perturbation structure along the XY plane provided in an embodiment of this application;

[0033] Figure 6 A schematic cross-sectional view of the distributed feedback grating structure provided in the embodiments of this application along the XY plane;

[0034] Figure 7 A schematic cross-sectional view along the YZ plane of the III-V group submicron line epitaxial structure provided in the embodiments of this application;

[0035] Figure 8 A schematic cross-sectional view of a single-longitudinal-mode silicon-based III-V submicron line laser along the YZ plane, provided for an embodiment of this application;

[0036] Figure 9 A cross-sectional schematic diagram along the YZ plane of another single-longitudinal-mode silicon-based III-V submicron line laser provided for embodiments of this application;

[0037] Wherein, 1 is a doped silicon layer; 2 is a silicon oxide layer; 21 is a silicon dioxide layer; 22 is a buried oxide layer of the SOI substrate; 3 is a trench; 31 is a selected area trench; 32 is a V-shaped trench; 33 is a refractive index perturbation structure; 4 is a III-V group submicron line epitaxial structure; 41 is a doped buffer layer; 42 is a lower cladding layer; 43 is a multi-quantum well active region; 44 is an upper cladding layer; 45 is a doped contact layer; 5 is the first electrode; 6 is the second electrode. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description, in conjunction with the accompanying drawings and embodiments, further illustrates the concept and technical effects of this application, so as to fully understand the objectives, features, and effects of this application. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. Other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of this application.

[0039] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function and effect, solely for the purpose of clearly describing the technical solutions of the embodiments of the present invention, and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. In the embodiments of this application, the terms "upper," "lower," "top," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, solely for the convenience of describing the present invention and simplifying the description, and not indicating or implying that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In the embodiments of this application, the expression "specific numerical value" or "left and right" should be understood as a range of values ​​fluctuating around the specific numerical value, generally within the range of -10% to 10%, unless otherwise explicitly and specifically defined.

[0040] This application provides a single-longitudinal-mode silicon-based III-V submicron line laser and its fabrication method, wherein the fabrication method is as follows:

[0041] A selected area trench 31 with a refractive index perturbation structure 33 is etched in the silicon oxide layer 2 above the doped silicon layer 1. A V-shaped trench 32 composed of two Si{111} surfaces is etched on the doped silicon layer 1 at the bottom of the selected area trench 31. The V-shaped trench 32 and the selected area trench 31 are connected to form a trench 3. A III-V submicron line epitaxial structure 4 is epitaxially grown on the Si{111} surface in the trench 3. The refractive index perturbation structure 33 on the selected area trench 31 and the III-V submicron line epitaxial structure 4 together form the grating structure of the laser. A first electrode 5 is prepared on the upper or lower surface of the doped silicon layer 1. A second electrode 6 is prepared on the silicon oxide layer 2 and the upper surface of the III-V submicron line epitaxial structure 4, thus completing the fabrication of a single-longitudinal-mode silicon-based III-V submicron line laser. In the aforementioned preparation method, the grating structure of the silicon-based III-V submicron line laser is automatically formed during the etching of the selected trench 31 of the refractive index perturbation structure 33 and the growth of the III-V submicron line epitaxial structure 4. This eliminates the need for additional grating fabrication processes, reduces the number of process steps, significantly lowers the manufacturing cost of the laser, and facilitates mass production, thus possessing promising application prospects.

[0042] Based on this, embodiments of this application provide a single-longitudinal-mode silicon-based III-V submicron line laser (such as...). Figure 1 As shown), the single-longitudinal-mode silicon-based III-V submicron line laser includes: a doped silicon layer 1, a silicon oxide layer 2, a trench 3, a III-V submicron line epitaxial structure 4, a first electrode 5, and a second electrode 6; the trench 3 is disposed in the doped silicon layer 1 and the silicon oxide layer 2 (e.g., Figure 2 As shown), the trench 3 is divided into interconnected selected area trenches 31 and V-shaped trenches 32. The selected area trenches 32 penetrate the silicon oxide layer 2. The selected area trenches 31 are provided with refractive index perturbation structures 33 (e.g., Figure 3 and Figure 5 As shown), the V-shaped trench 32 is disposed on the doped silicon layer 1, and the top width of the V-shaped trench 32 is not less than the width of the selected area trench 31; the III-V submicron line epitaxial structure 4 is disposed inside the trench 3 (e.g., Figure 7 As shown), the III-V group submicron line epitaxial structure 4 and the refractive index perturbation structure 33 together form a grating structure (as shown). Figure 4 and Figure 6 (as shown); the first electrode 5 is disposed on the lower or upper surface of the doped silicon layer 1, and the first electrode 5 forms an ohmic contact with the doped silicon layer 1; the second electrode 6 is disposed on the upper surface of the silicon oxide layer 2 and the III-V submicron epitaxial structure 4, and the second electrode 6 forms an ohmic contact with the III-V submicron epitaxial structure 4.

[0043] In some embodiments, the doped silicon layer 1 is the top silicon layer of the SOI substrate, and the silicon oxide layer 2 is a silicon dioxide layer deposited on the doped silicon layer 1 with a thickness of 800-2000 nm.

[0044] In some embodiments, the doped silicon layer 1 is the bottom silicon layer of the SOI substrate. In this case, the silicon oxide layer 2 consists of a buried oxide layer 22 of the SOI substrate and a silicon dioxide layer 21 deposited on the surface of the buried oxide layer 22 (e.g., Figure 8 (As shown).

[0045] In some embodiments, the doped silicon layer 1 is a silicon substrate, and the silicon oxide layer 2 is a silicon dioxide layer deposited on the doped silicon layer 1 (e.g., ...). Figure 9 As shown in the figure, its thickness is 800-2000 nm.

[0046] In some embodiments, the narrowest width of the selected area trench 31 ranges from 500 to 1000 nm, the widest width is 20 to 500 nm greater than the narrowest width, the length of the selected area trench 31 is between 10 and 500 μm, and the ratio of the depth of the selected area trench 31 to the narrowest width of the selected area trench 31 is greater than 1; the refractive index perturbation structure 33 is a trench structure that is wider than the narrowest width of the selected area trench 31.

[0047] In some embodiments, the refractive index perturbation structure 33 and the III-V submicron line epitaxial structure 4 together form a partial grating structure (e.g., Figure 4 (as shown); In some embodiments, the refractive index perturbation structure 33 and the III-V group submicron line epitaxial structure 4 together form a distributed feedback grating structure (e.g. Figure 6 (As shown).

[0048] In some embodiments, the III-V submicron epitaxial structure 4, in a direction away from the doped silicon layer 1, includes at least a doped buffer layer 41, a lower cladding layer 42, a multiple quantum well active region 43, an upper cladding layer 44, and a doped contact layer 45 (e.g., ...). Figure 7 (as shown); wherein the multi-quantum well active region 43 is located within the region of the selection trench 31.

[0049] In some embodiments, the material of the doped buffer layer 41 is N-type GaAs, the material of the lower cladding layer 42 and the upper cladding layer 44 is InP, the material of the multi-quantum well active region 43 is InGaAs / InP or InGaAs / InGaAsP or other types, as long as the materials of the quantum wells and barriers are matched with the InP lattice, and the material of the doped contact layer 45 is P-type InGaAs.

[0050] In some embodiments, the first electrode 5 is located on the upper surface of the doped silicon layer 1, and the metal in the first electrode 5 is the same as the metal in the second electrode 6 (e.g., Figure 1 As shown), for example, both the first electrode 5 and the second electrode 6 are titanium / gold (Ti / Au), and the metal can form an ohmic contact with both the doped silicon layer 1 and the doped contact layer 45. In some embodiments, the first electrode 5 is located on the upper surface of the doped silicon layer 1 and is composed of a first metal layer and a second metal layer deposited on the first metal layer, wherein the second metal layer is consistent with the metal of the second electrode 6 (e.g., Figure 8 As shown), for example, the first metal layer is antimony / gold (Sb / Au), and the metals of the second metal layer and the second electrode 6 are both titanium / gold (Ti / Au). The metal in the first electrode 5 can form an ohmic contact with the doped silicon layer 1, and the metal in the second electrode 6 can form an ohmic contact with the doped contact layer 45. In some embodiments, the first electrode 5 is located on the lower surface of the doped silicon layer 1 (e.g., Figure 9 (As shown).

[0051] Based on this, this application also provides a method for fabricating a single-longitudinal-mode silicon-based III-V submicron line laser, comprising the following steps: selecting a silicon substrate, a top silicon layer of an SOI substrate, and a bottom silicon layer of an SOI substrate as a doped silicon layer 1; fabricating a silicon dioxide layer 21 to form a silicon oxide layer 2; fabricating a selected area trench 31 with a refractive index perturbation structure 33 in the silicon oxide layer 2, the selected area trench 31 penetrating the silicon oxide layer 2; fabricating a V-shaped trench 32 in the doped silicon layer 1; the V-shaped trench 32 and the selected area trench 3... A trench 3 is formed by connecting the two layers. At least a doped buffer layer 41, a lower cladding layer 42, a multi-quantum well active region 43, an upper cladding layer 44, and a doped contact layer 45 are epitaxially grown sequentially in the trench 3 in a direction away from the V-shaped trench 32 to form a III-V submicron line epitaxial structure 4. A first electrode 5 is formed with an ohmic contact with the doped silicon layer 1 on the surface of the doped silicon layer 1. A second electrode 6 is formed with an ohmic contact with the doped contact layer 45 on the upper surface of the silicon oxide layer 2 and the III-V submicron line epitaxial structure 4.

[0052] In some embodiments, when the doped silicon layer 1 is the bottom silicon layer of an SOI substrate, the fabrication method further includes the step of removing the top silicon layer of the SOI substrate before fabricating the selected area trench 31.

[0053] In some embodiments, another method is used to prepare the first electrode 5. After the growth of the III-V submicron line epitaxial structure 4 is completed, a first metal layer (such as Sb / Au) that can form an ohmic contact with the doped silicon layer 1 is first prepared on the surface of the doped silicon layer 1. Then, during the preparation of the second electrode 6, the second metal layer (such as Ti / Au) on the first metal layer is retained. The first metal layer and the second metal layer together form the first electrode 5.

[0054] The technical solutions provided in this application will be further illustrated by more specific embodiments below.

[0055] Example 1

[0056] This embodiment provides a method for fabricating a single-longitudinal-mode silicon-based III-V submicron line laser, the specific steps of which are as follows:

[0057] (1) The bottom silicon layer of the SOI substrate is selected as doped silicon layer 1, the doping type of the bottom silicon layer of the SOI substrate is N-type doping, and the thickness of the buried oxide layer 22 of the SOI substrate is 1000nm.

[0058] (2) Using photolithography and wet etching techniques, the top silicon layer of the SOI substrate near the preparation area of ​​the selected trench 31 is removed.

[0059] (3) A silicon dioxide layer 21 with a thickness of 1000 nm is deposited using plasma enhanced chemical vapor deposition (PECVD) technology. The silicon dioxide layer 21 in the selected trench to be prepared region is located on the upper surface of the buried oxide layer 22 of the SOI substrate.

[0060] (4) Using photolithography and dry etching techniques, a selected area trench 31 is etched along the Si<110> direction of the bottom silicon layer of the SOI substrate on the silicon oxide layer 2 composed of the silicon dioxide layer 21 and the buried oxide layer 22 of the SOI substrate; wherein, the two sides of the selected area trench 31 have refractive index perturbation structures 33 (such as... Figure 3 As shown, the narrowest part of the selected area trench 31 has a width of 500 nm, the widest part of the selected area trench 31 has a width of 650 nm, and the depth of the selected area trench 31 is equal to the thickness of the silicon oxide layer 2, that is, the depth of the selected area trench 31 is 2000 nm.

[0061] (5) Etch the bottom silicon layer 1 of the SOI substrate with KOH solution to form a V-shaped trench 32 below the selected area trench 31 (e.g., Figure 2 As shown), the top width of the etched V-shaped trench 32 is greater than the width of the selected area trench 31; the formed device is immersed in dilute HCl for 1 to 2 minutes to remove the chemical reaction products of KOH solution and Si adhering to the sidewall of trench 3, and then the wafer is cleaned with deionized water.

[0062] (6) Using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), a III-V submicron epitaxial structure 4 is sequentially grown in trench 3 along the direction away from the doped silicon layer 1: an N-type GaAs buffer layer (i.e., doped buffer layer 41), an InP lower cladding layer (i.e., lower cladding layer 42), an InGaAs / InGaAsP multi-quantum-well active region (i.e., multi-quantum-well active region 43), an InP upper cladding layer (i.e., upper cladding layer 44), and a P-type InGaAs contact layer (doped contact layer 45) (e.g.) Figure 7 (as shown); wherein, the height of the multi-quantum-well active region 43 does not exceed the height of the selected area trench 31; the refractive index perturbation structure 33 on the selected area trench 31 and the III-V submicron line epitaxial structure 4 together constitute a partial grating structure (as shown). Figure 4 (As shown).

[0063] (7) Using photoresist as a mask, etch away part of the silicon dioxide layer 21 and part of the buried oxide layer 22 of the SOI substrate, that is, etch away part of the silicon oxide layer 2, expose part of the bottom silicon layer of the SOI substrate, and deposit the N electrode metal Sb / Au (first metal layer) that can form an ohmic contact with the N-type doped silicon material, wherein the thickness of Sb is 20-200nm and the thickness of Au is 100-1000nm. The N electrode metal is stripped off with photoresist to obtain the N electrode metal pattern.

[0064] (8) Silicon dioxide is deposited using PECVD technology. An electrode window is opened above the III-V submicron epitaxial structure 4 and the N metal electrode pattern. A P-electrode metal Ti / Au that can form an ohmic contact with the P-type InGaAs contact layer (i.e., doped contact layer 45) is sputtered. The thickness of Ti is 20-200 nm and the thickness of Au is 100-1000 nm. The P-electrode metal Ti / Au on the upper surface of the III-V submicron epitaxial structure 4 is retained by photolithography and wet etching techniques to obtain the P electrode (second electrode 6). The P-electrode metal Ti / Au above the N electrode metal pattern is retained. The P-electrode metal Ti / Au in this electrode region is in contact with the N electrode metal Sb / Au to form the N electrode (first electrode 5). The P-electrode metal on the N electrode is not in contact with the P-electrode metal above the III-V submicron epitaxial structure 4 (e.g., ...). Figure 8 As shown in the figure, a single-longitudinal-mode silicon-based III-V submicron line laser is obtained through the above steps.

[0065] Example 2

[0066] This embodiment provides another method for fabricating a single-longitudinal-mode silicon-based III-V submicron line laser. The specific steps are as follows:

[0067] (1) An N-type doped silicon substrate is selected as the doped silicon layer 1.

[0068] (2) A silicon dioxide layer 2 with a thickness of 1500 nm was deposited using PECVD technology.

[0069] (3) Using photolithography and dry etching techniques, selected area trenches 31 are etched on the silicon dioxide layer 21 (silicon oxide layer 2) along the Si<110> direction of the substrate silicon layer of the SOI substrate; wherein, the two sides of the selected area trenches 31 have refractive index perturbation structures 33 (such as... Figure 5 As shown, the narrowest part of the selected area trench 31 has a width of 500 nm, the widest part of the selected area trench 31 has a width of 650 nm, and the depth of the selected area trench 31 is equal to the thickness of the silicon oxide layer 2, that is, the depth of the selected area trench 31 is 1500 nm.

[0070] (4) Etch the doped silicon layer 1 with KOH solution to form a V-shaped trench 32 below the selected area trench 31 (e.g., ...). Figure 2 As shown), the top width of the etched V-shaped trench 32 is greater than the width of the selected area trench 31; the formed device is immersed in dilute HCl for 1 to 2 minutes to remove the chemical reaction products of KOH solution and Si adhering to the sidewall of trench 3, and then the wafer is cleaned with deionized water.

[0071] (5) Using MOCVD or MBE, grow the following III-V submicron epitaxial structure 4 sequentially in trench 3 along the direction away from the doped silicon layer 1: N-type GaAs buffer layer (i.e., doped buffer layer 41), InP lower cladding layer (i.e., lower cladding layer 42), InGaAs / InGaAsP multi-quantum-well active region (i.e., multi-quantum-well active region 43), InP upper cladding layer (i.e., upper cladding layer 44), and P-type InGaAs contact layer (doped contact layer 45) (e.g.) Figure 7 (as shown); wherein, the height of the multi-quantum-well active region 43 does not exceed the height of the selected area trench 31; the refractive index perturbation structure 33 on the selected area trench 31 and the III-V submicron line epitaxial structure 4 together constitute the distributed feedback grating structure (as shown). Figure 6 (As shown).

[0072] (6) Silicon dioxide is deposited using PECVD technology to open an electrode window above the III-V submicron epitaxial structure 4. A P-electrode metal Ti / Au that can form an ohmic contact with the P-type InGaAs contact layer (i.e., doped contact layer 45) is sputtered, wherein the thickness of Ti is 20-200 nm and the thickness of Au is 100-1000 nm. The P-electrode metal Ti / Au on the upper surface of the III-V submicron epitaxial structure 4 is retained by photolithography and wet etching techniques, thus obtaining the P-electrode (second electrode 6).

[0073] (7) Thinning the thickness of the doped silicon layer 1 to 50–200 μm from its lower surface, and preparing an N-electrode metal Sb / Au capable of forming an ohmic contact with the N-type doped silicon material on the lower surface of the doped silicon layer 1, wherein the Sb thickness is 20–200 nm and the Au thickness is 100–1000 nm, thus obtaining the first electrode 5 (e.g., ...). Figure 9 As shown in the figure, a single-longitudinal-mode silicon-based III-V submicron line laser is obtained through the above steps.

[0074] Both the fabrication methods provided in Examples 1 and 2 can fabricate single-longitudinal-mode silicon-based III-V submicron line lasers. In both methods, the grating structure of the laser is automatically formed during the etching of the selected trench 31 of the refractive index perturbation structure 33 and the growth of the III-V submicron line epitaxial structure 4. This can be achieved by setting different refractive index perturbation structures 33 (such as...). Figure 3 and Figure 5 As shown), different grating structures can be achieved (such as...). Figure 4 and Figure 6 As shown in the figure, the method for fabricating a single-longitudinal-mode silicon-based III-V submicron line laser provided in this application does not require an additional grating fabrication process, thus reducing the number of process steps and significantly lowering the manufacturing cost of the laser, and has good application prospects.

[0075] The present application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present application. The descriptions of the embodiments above are only for the purpose of helping to understand the present application and its core ideas. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A single-longitudinal-mode silicon-based III-V submicron line laser, characterized in that, include: Doped silicon layer; A silicon oxide layer disposed on the surface of the doped silicon layer; An integral trench disposed within the doped silicon layer and the silicon oxide layer; The integral trench is divided into interconnected selected area trenches and V-shaped trenches. The selected area trenches penetrate the silicon oxide layer, and the sides of the selected area trenches are provided with refractive index perturbation structures. The V-shaped trenches are disposed in the doped silicon layer and are composed of two Si{111} planes. The width of the V-shaped trenches at the contact surface with the selected area trenches is not less than the width of the selected area trenches. A III-V submicron line epitaxial structure is disposed inside the integral trench; the III-V submicron line epitaxial structure and the refractive index perturbation structure together form a grating structure; A first electrode is disposed on the surface of the doped silicon layer; the first electrode forms an ohmic contact with the doped silicon layer; A second electrode is disposed on the surface of the silicon oxide layer and the III-V submicron epitaxial structure, and the second electrode forms an ohmic contact with the III-V submicron epitaxial structure.

2. The single-longitudinal-mode silicon-based III-V submicron line laser according to claim 1, characterized in that, The width of the selected area trench is 500~1000 nm at its narrowest point, and the width at its widest point is 20~500 nm greater than the width at its narrowest point. The length of the selected area trench is between 10~500 μm, and the ratio of the depth of the selected area trench to the width at its narrowest point is greater than 1.

3. The single-longitudinal-mode silicon-based III-V submicron line laser according to claim 1, characterized in that, The III-V group submicron line epitaxial structure, in the direction away from the doped silicon layer, includes at least: a doped buffer layer, a lower cladding layer, a multi-quantum-well active region, an upper cladding layer, and a doped contact layer; wherein the doping type of the doped buffer layer is the same as that in the doped silicon layer and opposite to that in the doped contact layer, and the doped contact layer forms an ohmic contact with the second electrode.

4. The single-longitudinal-mode silicon-based III-V submicron line laser according to claim 3, characterized in that, The multi-quantum-well active region is located within the selected trench region.

5. The single-longitudinal-mode silicon-based III-V submicron line laser according to claim 1, characterized in that, The doped silicon layer is the top silicon layer of a silicon substrate or an SOI substrate.

6. The single-longitudinal-mode silicon-based III-V submicron line laser according to claim 1, characterized in that, The doped silicon layer is the bottom silicon layer of the SOI substrate, and the silicon oxide layer consists of a buried oxide layer of the SOI substrate and a silicon dioxide layer deposited on the surface of the buried oxide layer.

7. The single-longitudinal-mode silicon-based III-V submicron line laser according to claim 1, characterized in that, The grating structure is a distributed feedback grating or a partial grating structure.

8. A method for fabricating a single-longitudinal-mode silicon-based III-V submicron line laser, characterized in that, Includes the following steps: Choose any one of the following as the doped silicon layer: the top silicon layer of a silicon substrate, the top silicon layer of an SOI substrate, or the bottom silicon layer of an SOI substrate. Prepare a silicon dioxide layer to form a silicon oxide layer; Selected trenches with refractive index perturbation structures are fabricated in the silicon oxide layer, and the selected trenches penetrate the silicon oxide layer; A V-shaped trench is formed in the doped silicon layer; the V-shaped trench is connected to the selected area trench to form an integral trench; In the integral trench, at least a doped buffer layer, a lower cladding layer, a multi-quantum well active region, an upper cladding layer, and a doped contact layer are grown sequentially in a direction away from the V-shaped trench to form a III-V group submicron line epitaxial structure. A first electrode is prepared on the surface of the doped silicon layer to form an ohmic contact with the doped silicon layer, and a second electrode is prepared on the surface of the silicon oxide layer and the III-V submicron line epitaxial structure to form an ohmic contact with the doped contact layer.

9. The preparation method according to claim 8, characterized in that, When the doped silicon layer is the bottom silicon layer of the SOI substrate, the fabrication method further includes the step of removing the top silicon layer of the SOI substrate before fabricating the selected area trench.

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