An imaging signal sampling circuit and method

Abstract

This application provides an imaging signal sampling circuit and method. The circuit includes: a first sampling module that samples the imaging signal N times under the control of N first sampling signals and a second sampling signal to obtain 2N reset voltages; a second sampling module that samples the imaging signal N times under the control of N third sampling signals and a fourth sampling signal to obtain 2N signal voltages; during each cycle of the imaging signal, when sampling the imaging signal, a reset operation is performed by an amplification module controlled by a reset signal; after sampling, the 2N reset voltages and 2N signal voltages are differentially amplified 2N-1 times to obtain 2N-1 sampled signals. On the one hand, by sampling the imaging signal multiple times through two sampling modules, the noise suppression strength of the circuit is enhanced; on the other hand, the reset voltages and signal voltages obtained from multiple samplings are amplified sequentially to obtain multiple sampled signals, and the offset error of the output signal is reduced by multiple averaging.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and specifically to an imaging signal sampling circuit and method. Background Technology

[0002] A CCD (Charge-Coupled Device) is an image sensor that converts light signals into electrical signals through photoelectric conversion. As a mature imaging technology, CCDs have a wide range of applications. They are characterized by high image quality, high sensitivity, low noise, fast response, high resolution, high pixel integration, and precise size. They are widely used in astronomy, medical imaging equipment, microscope images, and optical recognition. In related technologies, traditional imaging signal sampling circuits mainly amplify the reset level and signal level of the imaging signal after each sampling. Imaging signals contain noise, and traditional imaging signal sampling circuits have weak noise suppression capabilities. Although noise can be reduced by increasing the sampling capacitor, the chip area also increases accordingly. Due to differences in integrated circuit manufacturing processes, traditional imaging signal sampling circuits output a sampling signal with offset errors.

[0003] Therefore, how to provide an imaging signal sampling circuit with strong noise suppression capability and reduced misalignment error is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the present invention provides an imaging signal sampling circuit and method to solve at least one of the above-mentioned technical problems.

[0005] To achieve the above and other related objectives, the technical solution provided in this application is as follows.

[0006] According to one aspect of the embodiments of this application, an imaging signal sampling circuit is provided, comprising:

[0007] The first sampling module receives an imaging signal, a first reference voltage, N first sampling signals, and a second sampling signal. Under the control of the N first sampling signals and the second sampling signals, it samples the imaging signal N times based on the first reference voltage to obtain 2N reset voltages.

[0008] The second sampling module receives the imaging signal, the first reference voltage, N third sampling signals, and a fourth sampling signal. Under the control of the N third sampling signals and the fourth sampling signal, it samples the imaging signal N times based on the first reference voltage to obtain 2N signal voltages.

[0009] An amplification module is connected to the first sampling module, the second sampling module, 2N-1 differential connection signals, a first amplified signal, a second amplified signal, and a reset signal. Within each cycle of the imaging signal, the amplification module alternately performs a reset operation and differential amplification processing. When the reset signal controls the amplification module to perform a reset operation, it synchronously controls the first sampling module or the second sampling module to sample the imaging signal. After sampling, under the control of the 2N-1 differential connection signals, the first amplified signal, and the second amplified signal, 2N reset voltages and 2N signal voltages are differentially amplified 2N-1 times to obtain 2N-1 sampled signals. During the i-th amplification, the i-th reset voltage and the i-th signal voltage are differentially amplified to obtain the i-th sampled signal.

[0010] Where i and N are integers, N≥2, 1≤i≤2N-1.

[0011] In one embodiment of the present invention, the first sampling module includes 2N reset sampling units and a first reference unit. The reset sampling unit is connected to the first sampling signal and samples the imaging signal based on the first sampling signal to obtain the reset voltage. The first reference unit is connected to the reset sampling unit, the first reference voltage and the second sampling signal, and uses the first reference voltage as a reference value of the reset sampling unit based on the second sampling signal.

[0012] In one embodiment of the present invention, the reset sampling unit includes a first sampling switch and a first sampling capacitor. One end of the first sampling switch is connected to the imaging signal, and the other end of the first sampling switch is connected to one end of the first sampling capacitor. The control terminal of the first sampling switch is connected to the first sampling signal. The first reference unit includes a second sampling switch. One end of the second sampling switch is connected to the other end of the first sampling capacitor, and the other end of the second sampling switch is connected to the first reference voltage. The control terminal of the second sampling switch is connected to the second sampling signal.

[0013] In one embodiment of the present invention, the second sampling module includes 2N signal sampling units and a second reference unit. The signal sampling units are connected to the third sampling signal and perform N samplings on the imaging signal based on the third sampling signal to obtain the signal voltage. The second reference unit is connected to the signal sampling units, the first reference voltage, and the fourth sampling signal, and uses the first reference voltage as a reference value for the signal sampling units based on the fourth sampling signal.

[0014] In one embodiment of the present invention, the signal sampling unit includes a third sampling switch and a second sampling capacitor. One end of the third sampling switch is connected to the imaging signal, and the other end of the third sampling switch is connected to one end of the second sampling capacitor. The control terminal of the third sampling switch is connected to the third sampling signal. The second reference unit includes a fourth sampling switch. One end of the fourth sampling switch is connected to the other end of the second sampling capacitor, and the other end of the fourth sampling switch is connected to the first reference voltage. The control terminal of the fourth sampling switch is connected to the fourth sampling signal.

[0015] In one embodiment of the present invention, the amplification module includes a differential processing unit and an amplification unit. The differential processing unit is connected to 2N-1 differential connection signals and the first amplified signal. Under the control of the 2N-1 differential connection signals and the first amplified signal, 2N reset voltages and 2N signal voltages are connected one-to-one to obtain 2N-1 differential signals. The amplification unit is connected to the differential processing unit, the second amplified signal, and the reset signal. When the reset signal controls the amplification unit to perform a reset operation, it synchronously controls the first sampling module or the second sampling module to sample the imaging signal. After sampling is completed, under the control of the second amplified signal, the 2N-1 differential signals are amplified sequentially to obtain 2N-1 sampled signals.

[0016] In one embodiment of the present invention, the differential processing unit includes 2N-1 differential connection switches, a first amplification switch, and a second amplification switch; one end of the i-th differential connection switch is connected to one end of the i-th first sampling capacitor, the other end of the i-th first sampling capacitor is connected to one end of the first amplification switch, the other end of the i-th differential connection switch is connected to one end of the i-th second sampling capacitor, the other end of the i-th second sampling capacitor is connected to one end of the second amplification switch, the control terminal of the i-th differential connection switch is connected to the i-th differential connection signal, and the control terminals of the first amplification switch and the second amplification switch are connected to the first amplification signal. The other end of the first amplification switch is the first output terminal of the differential processing unit, and the other end of the second amplification switch is the second output terminal of the differential processing unit.

[0017] In one embodiment of the present invention, the amplification unit includes a first reset switch, a second reset switch, a third reset switch, a fourth reset switch, a fifth reset switch, a sixth reset switch, a third amplification switch, a fourth amplification switch, a fifth amplification switch, a sixth amplification switch, a first feedback capacitor, a second feedback capacitor, and an operational amplifier. One end of the first reset switch is connected to the non-inverting input terminal of the operational amplifier, and the other end of the first reset switch is connected to the inverting input terminal of the operational amplifier. The non-inverting input terminal of the operational amplifier is connected to the inverting output terminal of the operational amplifier after passing through the third amplification switch, the first feedback capacitor, and the fourth amplification switch in series. The inverting input terminal of the operational amplifier is connected to the non-inverting output terminal of the operational amplifier after passing through the fifth amplification switch, the second feedback capacitor, and the sixth amplification switch in series. The inverting output terminal of the operational amplifier is connected to the non-inverting output terminal of the operational amplifier after passing through the second reset switch in series. The second reference voltage is connected to the first feedback capacitor after passing through the third reset switch in series. One end of the capacitor is connected to the other end of the first feedback capacitor via the third reference voltage connected in series with the fourth reset switch. The second reference voltage is connected to one end of the second feedback capacitor via the fifth reset switch connected in series. The fourth reference voltage is connected to the other end of the second feedback capacitor via the sixth reset switch connected in series. The control terminals of the first, second, third, fourth, fifth, and sixth reset switches are connected to the reset signal. The control terminals of the third, fourth, fifth, and sixth amplification switches are connected to the second amplification signal. The non-inverting input terminal of the operational amplifier is connected to the first output terminal of the differential processing unit, and the inverting input terminal of the operational amplifier is connected to the second output terminal of the differential processing unit. The non-inverting and inverting output terminals of the operational amplifier cooperate to output the sampling signal.

[0018] According to another aspect of the embodiments of this application, an imaging signal sampling method is also provided, applied to the imaging signal sampling circuit as described above, including:

[0019] During the first half of the imaging signal period, the imaging signal is sampled N times, and each sample is sampled through M sampling capacitors to obtain M*N reset voltages.

[0020] During the second half-cycle of the imaging signal, the imaging signal is sampled N times, and each sample is taken through M sampling capacitors to obtain M*N signal voltages.

[0021] Within each cycle, reset operations and differential amplification are performed alternately, and 2N sampling operations are performed sequentially and at least synchronously with some of the reset operations. M*N reset voltages and M*N signal voltages are subjected to M*N-1 differential amplification operations to obtain M*N-1 sampled signals. During the t-th differential amplification, the t-th reset voltage and the t-th signal voltage are differentially amplified to obtain the t-th sampled signal.

[0022] Where t, N, and M are integers, N≥2, M≥2, and 1≤t≤M*N-1.

[0023] This application provides an imaging signal sampling circuit and method. The circuit includes: a first sampling module that samples the imaging signal N times under the control of N first sampling signals and a second sampling signal to obtain 2N reset voltages; a second sampling module that samples the imaging signal N times under the control of N third sampling signals and a fourth sampling signal to obtain 2N signal voltages; during each period of the imaging signal, when sampling the imaging signal, a reset signal controls an amplification module to perform a reset operation; after sampling, the 2N reset voltages and 2N signal voltages are differentially amplified 2N-1 times to obtain 2N-1 sampled signals. This application uses two sampling modules to sample the imaging signal multiple times to enhance the sampling circuit's ability to suppress imaging signal noise. The reset voltages and signal voltages obtained from multiple samplings are sequentially amplified to obtain multiple sampled signals. By averaging multiple times, the offset error of the output signal is reduced. The sampling circuit enhances noise suppression and reduces output signal error, thereby improving the accuracy and precision of signal sampling.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0025] Figure 1 This is a specific structure of a conventional imaging signal sampling circuit shown in an exemplary embodiment of the present invention;

[0026] Figure 2 This is a timing diagram of a conventional imaging signal sampling circuit shown in an exemplary embodiment of the present invention;

[0027] Figure 3 This is an exploded view of sampling and differential amplification of a conventional imaging signal sampling circuit, as illustrated in an exemplary embodiment of the present invention.

[0028] Figure 4 This is a block diagram illustrating an imaging signal sampling circuit according to an exemplary embodiment of the present invention;

[0029] Figure 5This is a detailed structural diagram of an imaging signal sampling circuit shown in an exemplary embodiment of the present invention;

[0030] Figure 6 This is a timing diagram of an imaging signal sampling circuit shown in an exemplary embodiment of the present invention;

[0031] Figure 7 This is an exploded view of the imaging signal sampling circuit sampling and differential amplification, as illustrated in an exemplary embodiment of the present invention.

[0032] Figure 8 This is a comparison diagram illustrating a conventional sampling signal and the sampling signal of this application, shown in an exemplary embodiment of the present invention;

[0033] Figure 9 This is a detailed structural diagram of an imaging signal sampling circuit shown in another exemplary embodiment of the present invention;

[0034] Figure 10 This is a timing control diagram of an imaging signal sampling circuit shown in another exemplary embodiment of the present invention. Detailed Implementation

[0035] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0036] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0038] CCD (Charge-Coupled Device) imaging technology is a mature and widely used imaging technology. Its characteristics include high image quality, high sensitivity, low noise, fast response, high resolution, high pixel integration, and precise size. It has wide applications in astronomy, medical imaging equipment, microscopic images, and optical recognition. These characteristics make CCD imaging a commonly used image sensor in the field of machine vision.

[0039] Please see Figure 1 , Figure 1 This is a specific structure of a conventional imaging signal sampling circuit shown in an exemplary embodiment of the present invention.

[0040] Please see Figure 2 , Figure 2 This is a timing diagram of a conventional imaging signal sampling circuit illustrated in an exemplary embodiment of the present invention.

[0041] Please see Figure 3 , Figure 3 This is an exploded view of the sampling and differential amplification of a conventional imaging signal sampling circuit, as illustrated in an exemplary embodiment of the present invention.

[0042] like Figure 1 As shown, a traditional imaging signal sampling circuit includes switches S11, S13, S15, S22, S23 and a sampling capacitor C. S1_1 and C S1_2 The first sampling network consists of switches S11', S13', S15, S22', S23 and sampling capacitor C. S2_1 C S2_2 The second sampling network consists of a feedback capacitor (Cf) and an operational amplifier (AMP) that amplifies the sampled signal. Figure 1 and Figure 2 As shown, when the imaging signal V CCD During the Nth period, the imaging signal V CCD The first state is the imaging signal V. CCD When the value is the reset level Vr, sampling is performed through the first sampling network, and switch S11 is turned on through signal K11. The first sampling capacitor Cs1_1 samples the imaging signal V. CCD Sampling is performed, and simultaneously, switch S22' is turned on via signal K22', and switch S23 is turned on via signal K23. The operational amplifier AMP processes the imaging signal V obtained from the previous cycle. CCD The operational amplifier AMP is amplified, and its output voltage is VOP'-VON'. The imaging signal sampling circuit samples the imaging signal V... CCD The equivalent circuit diagram for sampling the first state is as follows: Figure 3 As shown in (a).

[0043] Secondly, if the imaging signal V CCD In the second state, i.e., the imaging signal V CCD The value is the signal level V. S1 At that time, switch S13 is turned on via signal K13, and the second sampling capacitor C... S1_2 For imaging signal V CCD signal level V S1 Sampling is performed by turning on switch S15 via signal K15, putting operational amplifier AMP in a reset state. The equivalent circuit diagram of the imaging signal sampling circuit in the reset state is shown below. Figure 3 As shown in (b). At this time, the first sampling capacitor C S1_1 Second sampling capacitor C S2_1 The reset level Vr and signal level V of the imaging signal were respectively completed. S1 Sampling.

[0044] Next, when the imaging signal V CCD During the (N+1)th cycle, the imaging signal V CCD The first state is the imaging signal V. CCD When the value is the reset level Vr, the switch S11' is turned on through the signal K11', and the third sampling capacitor C... S2_1 For imaging signal V CCD The reset level Vr is sampled, and switch S22 is turned on via signal K22. Switch S23 is turned on via signal K23. Operational amplifier AMP differentially amplifies the reset level and signal level sampled in the Nth cycle. The output voltage of operational amplifier AMP is VOP-VON. The imaging signal sampling circuit samples the imaging signal Vr. CCD The equivalent circuit diagram for sampling the first state is as follows: Figure 3 As shown in (c).

[0045] Then, the imaging signal V CCD The second state is the imaging signal V. CCD The value is the signal level V. S2 At that time, the switch S13' is turned on through signal K13', and the fourth sampling capacitor C S2_2 For imaging signal V CCD signal level V S2 Sampling is performed by turning on switch S15 via signal K15, putting the operational amplifier AMP in a reset state. The equivalent circuit diagram of the imaging signal sampling circuit in the reset state is shown below. Figure 3 As shown in (d).

[0046] As can be seen from traditional imaging signal sampling circuits, they perform one sampling and one amplification for each state of the imaging signal. Therefore, there are two main problems: firstly, because the imaging signal itself contains noise, the traditional imaging signal sampling circuit has relatively weak noise suppression capabilities; secondly, to improve the noise reduction of the imaging signal sampling device, a sampling capacitor needs to be added, but this increases the chip area; and thirdly, the operational amplifier (AMP) and the subsequent analog-to-digital converter (ADC) both contain noise, which the traditional imaging signal sampling circuit cannot suppress. Furthermore, because it uses switches S11, S13, S15, S22, S23 and sampling capacitor C... S1_1 and C S1_2 The first set of sampling networks consists of switches S11', S13', S15, S22', S23 and sampling capacitor C. S2_1 and C S2_2 The second sampling network consists of two sets of sampling networks. Due to errors in the integrated circuit manufacturing process, there is a mismatch between these two sets of sampling networks. As a result, the sampling signal obtained by the operational amplifier (AMP) in the amplification state has an inherent offset error.

[0047] Please see Figure 4 , Figure 4 This is a block diagram illustrating an imaging signal sampling circuit according to an exemplary embodiment of the present invention.

[0048] like Figure 4 As shown, in an exemplary embodiment, an imaging signal sampling circuit includes:

[0049] The first sampling module is connected to the imaging signal V. CCD The system consists of a first reference voltage V1, N first sampling signals K11_j, and a second sampling signal K2. Under the control of the N first sampling signals K11_j and the second sampling signal K2, the imaging signal V is processed based on the first reference voltage V1. CCD Perform N samplings to obtain 2N reset voltages;

[0050] The second sampling module is connected to the imaging signal V. CCD The system consists of a first reference voltage V1, N third sampling signals K13_j, and a fourth sampling signal K4. Under the control of the N third sampling signals K13_j and the fourth sampling signal K4, the imaging signal V is processed based on the first reference voltage V1. CCD Perform N samplings to obtain 2N signal voltages;

[0051] The amplification module is connected to a first sampling module, a second sampling module, 2N-1 differential connection signals K22_i, a first amplified signal K22, a second amplified signal K23, and a reset signal K15. Within each cycle of the imaging signal, the amplification module alternately performs a reset operation and differential amplification processing. When the reset signal K15 controls the amplification module to perform a reset operation, it synchronously controls either the first or second sampling module to amplify the imaging signal V. CCD During sampling, after sampling is completed, under the control of 2N-1 differential connection signals K22_i, the first amplification signal K22 and the second amplification signal K23, 2N-1 differential amplification processes are performed on 2N-1 reset voltages and 2N signal voltages to obtain 2N-1 sampled signals. During the i-th amplification, the i-th reset voltage and the i-th signal voltage are differentially amplified to obtain the i-th sampled signal.

[0052] Where i and N are integers, N≥2, 1≤i≤2N-1.

[0053] It should be noted that j is an integer. 1 ≤ j ≤ N.

[0054] Example 1

[0055] Please see Figure 5 , Figure 5 This is a structural diagram of an imaging signal sampling circuit shown in an exemplary embodiment of the present invention.

[0056] In detail, the first sampling module includes 2N reset sampling units and a first reference unit. The reset sampling units are connected to a first sampling signal and sample the imaging signal based on the first sampling signal to obtain a reset voltage. The first reference unit is connected to the reset sampling units, the first reference voltage, and the second sampling signal, and uses the first reference voltage as a reference value for the reset sampling units based on the second sampling signal. Specifically, as shown... Figure 5 As shown, the first sampling module includes four reset sampling units and a first reference unit. The first and second reset sampling units are connected to the first first sampling signal K11_1, and the second and third reset sampling units are connected to the second first sampling signal K11_2. Under the control of the first first sampling signal K11_1 and the second first sampling signal K11_2, the imaging signal V is processed. CCD Two sampling operations are performed to obtain four reset voltages. The first reference unit is connected to four reset sampling units, the first reference voltage V1, and the second sampling signal K2. During sampling, the first reference voltage V1 is used as the reference value of the reset sampling unit based on the control of the second sampling signal K2.

[0057] More specifically, the reset sampling unit includes a first sampling switch and a first sampling capacitor. One end of the first sampling switch is connected to the imaging signal, and the other end of the first sampling switch is connected to one end of the first sampling capacitor. The control terminal of the first sampling switch is connected to the first sampling signal. The first reference unit includes a second sampling switch. One end of the second sampling switch is connected to the other end of the first sampling capacitor, and the other end of the second sampling switch is connected to the first reference voltage. The control terminal of the second sampling switch is connected to the second sampling signal.

[0058] Specifically, such as Figure 5 As shown, the first reset sampling unit includes a first sampling switch S11_11 and a first sampling capacitor C. S1_1 One end of the first sampling switch S11_11 is connected to the imaging signal V. CCD The other end of the first sampling switch S11_11 is connected to the first sampling capacitor C. S1_1 At one end, the control terminal of the first sampling switch S11_11 is connected to the first sampling signal K11_1; the second reset sampling unit includes the first sampling switch S11_12 and the first sampling capacitor C. S1_2 One end of the first sampling switch S11_12 is connected to the imaging signal V. CCD The other end of the first sampling switch S11_12 is connected to the first sampling capacitor C. S1_2 One end of the first sampling switch S11_12 is connected to the first sampling signal K11_1.

[0059] Similarly, the third reset sampling unit includes the first sampling switch S11_21 and the first sampling capacitor C. S1_3 One end of the first sampling switch S11_21 is connected to the imaging signal V. CCD The other end of the first sampling switch S11_21 is connected to the first sampling capacitor C. S1_3 At one end, the control terminal of the first sampling switch S11_21 is connected to the second first sampling signal K11_2; the fourth reset sampling unit includes the first sampling switch S11_22 and the first sampling capacitor C. S1_4 One end of the first sampling switch S11_22 is connected to the imaging signal V. CCD The other end of the first sampling switch S11_22 is connected to the first sampling capacitor C. S1_4 One end of the first sampling switch S11_22 is connected to the control terminal of the second first sampling signal K11_2. The first reference unit includes a second sampling switch S1_1, one end of which is connected to the first sampling capacitor (C). S1_1 C S1_2 C S1_3 C S1_4 At the other end of the second sampling switch S1_1, the other end is connected to the first reference voltage V1, and the control terminal of the second sampling switch S1_1 is connected to the second sampling signal K2.

[0060] In detail, the second sampling module includes 2N signal sampling units and a second reference unit. The signal sampling units are connected to a third sampling signal and sample the imaging signal based on the third sampling signal to obtain a signal voltage. The second reference unit is connected to the signal sampling units, a first reference voltage, and a fourth sampling signal, and uses the first reference voltage as a reference value for the signal sampling units based on the fourth sampling signal. Figure 5 As shown, the second sampling module includes four signal sampling units and a second reference unit. The first and second signal sampling units are connected to the first third sampling signal K13_1, and the third and fourth signal sampling units are connected to the second third sampling signal K13_2. Under the control of the first third sampling signal K13_1 and the second third sampling signal K13_2, the imaging signal V is processed. CCD Two samplings are performed to obtain four signal voltages. The second reference unit is connected to four signal sampling units, the first reference voltage V1, and the fourth sampling signal K4. During sampling, the first reference voltage V1 is used as the reference value of the signal sampling unit based on the control of the fourth sampling signal K4.

[0061] More specifically, the signal sampling unit includes a third sampling switch and a second sampling capacitor. One end of the third sampling switch is connected to the imaging signal, and the other end of the third sampling switch is connected to one end of the second sampling capacitor. The control terminal of the third sampling switch is connected to the third sampling signal. The second reference unit includes a fourth sampling switch. One end of the fourth sampling switch is connected to the other end of the second sampling capacitor, and the other end of the fourth sampling switch is connected to the first reference voltage. The control terminal of the fourth sampling switch is connected to the fourth sampling signal.

[0062] Specifically, such as Figure 5 As shown, the first signal sampling unit includes a third sampling switch S13_11 and a second sampling capacitor C. S2_1 One end of the third sampling switch S13_11 is connected to the imaging signal V. CCD The other end of the third sampling switch S13_11 is connected to the second sampling capacitor C. S2_1 At one end, the control terminal of the third sampling switch S13_11 is connected to the first third sampling signal K13_1; the second signal sampling unit includes the third sampling switch S13_12 and the second sampling capacitor C. S2_2 One end of the third sampling switch S13_12 is connected to the imaging signal V. CCD The other end of the third sampling switch S13_12 is connected to the second sampling capacitor C. S2_2 One end of the third sampling switch S13_12 is connected to the first third sampling signal K13_1.

[0063] Similarly, the third signal sampling unit includes a third sampling switch S13_21 and a second sampling capacitor C.S2_3 One end of the third sampling switch S13_21 is connected to the imaging signal V. CCD The other end of the third sampling switch S13_21 is connected to the second sampling capacitor C. S2_3 One end of the third sampling switch S13_21 is connected to the control terminal of the second third sampling signal K13_2; the fourth signal sampling unit includes the third sampling switch S13_22 and the second sampling capacitor C. S2_4 One end of the third sampling switch S13_22 is connected to the imaging signal V. CCD The other end of the third sampling switch S13_22 is connected to the second sampling capacitor C. S2_4 One end of the third sampling switch S13_22 is connected to the control terminal of the second third sampling signal K13_2. The second reference unit includes a fourth sampling switch S1_2, one end of which is connected to the second sampling capacitor (C). S2_1 C S2_2 C S2_3 C S2_4 At the other end of the circuit, the other end of the fourth sampling switch S1_2 is connected to the first reference voltage V1, and the control terminal of the fourth sampling switch S1_2 is connected to the fourth sampling signal K4.

[0064] It should be noted that the capacitance value of the first sampling capacitor is equal to the capacitance value of the second sampling capacitor.

[0065] In detail, the amplification module includes a differential processing unit and an amplification unit. The differential processing unit is connected to 2N-1 differential connection signals and a first amplified signal. Under the control of the 2N-1 differential connection signals and the first amplified signal, it connects 2N reset voltages and 2N signal voltages one-to-one to obtain 2N-1 differential signals. The amplification unit is connected to the differential processing unit, a second amplified signal, and a reset signal. When the reset signal controls the amplification unit to perform a reset operation, it synchronously controls the first sampling module or the second sampling module to sample the imaging signal. After sampling, under the control of the second amplified signal, the 2N-1 differential signals are amplified sequentially to obtain 2N-1 sampled signals. It should be noted that, as Figure 5 As shown, the amplification module includes a differential processing unit and an amplification unit. The differential processing unit is connected to three differential connection signals K22_i and a first amplification signal K22. Under the control of the three differential connection signals K22_i and the first amplification signal K22, three reset voltages are connected one-to-one with three signal voltages to obtain three differential signals. The amplification unit is connected to a second amplification signal K23 and a reset signal K15. When the reset signal K15 controls the amplification unit to perform a reset operation, it simultaneously controls the first sampling module to process the imaging signal V. CCD Perform sampling or control the second sampling module to sample the imaging signal V CCDSampling is performed. After sampling is completed, the three differential signals are amplified sequentially under the control of the second amplification signal K23 to obtain three sampled signals.

[0066] More specifically, the differential processing unit includes N-1 differential connection switches, a first amplification switch, and a second amplification switch; one end of the i-th differential connection switch is connected to one end of the i-th first sampling capacitor, the other end of the i-th first sampling capacitor is connected to one end of the first amplification switch, the other end of the i-th differential connection switch is connected to one end of the i-th second sampling capacitor, the other end of the i-th second sampling capacitor is connected to one end of the second amplification switch, the control terminal of the i-th differential connection switch is connected to the i-th differential connection signal, and the control terminals of the first amplification switch and the second amplification switch are connected to the first amplification signal. The other end of the first amplification switch is the first output terminal of the differential processing unit, and the other end of the second amplification switch is the second output terminal of the differential processing unit.

[0067] Specifically, such as Figure 5 As shown, the differential processing unit includes a first differential connection switch S21_1, a second differential connection switch S21_2, a third differential connection switch S21_3, a first amplification switch S22_1, and a second amplification switch S22_2. One end of the first differential connection switch S21_1 is connected to the first sampling capacitor C. S1_1 One end, the first sampling capacitor C S1_1 The other end is connected to one end of the first amplifying switch S22_1, and the other end of the first differential connection switch S21_1 is connected to the first second sampling capacitor C. S2_1 One end, the first second sampling capacitor C S2_1 The other end is connected to one end of the second amplifying switch S22_2; the control terminal of the first differential connection switch S21_1 is connected to the first differential connection signal K21_1; one end of the second differential connection switch S21_2 is connected to the second first sampling capacitor C. S1_2 One end, the second first sampling capacitor C S1_2 The other end is connected to one end of the first amplifying switch S22_1, and the other end of the second differential connection switch S21_2 is connected to the second second sampling capacitor C. S2_2 One end, the second sampling capacitor C S2_2 The other end is connected to one end of the second amplifying switch S22_2; the control terminal of the second differential connection switch S21_2 is connected to the second differential connection signal K21_2; one end of the third differential connection switch S21_3 is connected to the third first sampling capacitor C. S1_3 At one end, the third first sampling capacitor C S1_3 The other end is connected to one end of the first amplifying switch S22_1, and the other end of the third differential connection switch S21_3 is connected to the third second sampling capacitor C. S2_3One end, the third second sampling capacitor C S2_3 The other end is connected to one end of the second amplifying switch S22_2, the control end of the third differential connection switch S21_3 is connected to the third differential connection signal K21_3, the control end of the first amplifying switch S22_1 and the control end of the second amplifying switch S22_2 are connected to the first amplifying signal K22, wherein the other end of the first amplifying switch S22_1 is the first output end of the differential processing unit, and the other end of the second amplifying switch S22_2 is the second output end of the differential processing unit.

[0068] More in detail, such as Figure 5As shown, the amplification unit includes a first reset switch S15_1, a second reset switch S15_2, a third reset switch S15_3, a fourth reset switch S15_4, a fifth reset switch S15_5, a sixth reset switch S15_6, a third amplification switch S23_1, a fourth amplification switch S23_2, a fifth amplification switch S23_3, a sixth amplification switch S23_4, a first feedback capacitor C1, a second feedback capacitor C2, and an operational amplifier AMP. One end of the first reset switch S15_1 is connected to the non-inverting input terminal of the operational amplifier AMP, and the other end of the first reset switch S15_1 is connected to the inverting input terminal of the operational amplifier AMP. The non-inverting input of the AMP is connected to the inverting output of the operational amplifier AMP via a series connection of the third amplification switch S23_1, the first feedback capacitor C1, and the fourth amplification switch S23_2. The inverting output of the operational amplifier AMP is then connected to the non-inverting output via a series connection of the fifth amplification switch S23_3, the second feedback capacitor C2, and the sixth amplification switch S23_4. The inverting output of the operational amplifier AMP is then connected to the non-inverting output via a series connection of the second reset switch S15_2. The second reference voltage V2 is connected to one end of the first feedback capacitor C1 via a series connection of the third reset switch S15_3. The third reference voltage... V3 is connected to the other end of the first feedback capacitor C1 via the fourth reset switch S15_4 connected in series. The second reference voltage V2 is connected to one end of the second feedback capacitor C2 via the fifth reset switch S15_5 connected in series. The fourth reference voltage V4 is connected to the other end of the second feedback capacitor C2 via the sixth reset switch S15_6 connected in series. The control terminals of the first reset switch S15_1, the second reset switch S15_2, the third reset switch S15_3, the fourth reset switch S15_4, the fifth reset switch S15_5, and the sixth reset switch S15_6 are connected to the reset signal K15. The third amplification switch S2... The control terminals of 3_1, the fourth amplification switch S23_2, the fifth amplification switch S23_3, and the sixth amplification switch S23_4 are connected to the second amplified signal K23. The non-inverting input terminal of the operational amplifier AMP is connected to the first output terminal of the differential processing unit. The non-inverting input terminal of the operational amplifier AMP is connected to the other end of the first amplification switch S22_1. The inverting input terminal of the operational amplifier AMP is connected to the second output terminal of the differential processing unit. The inverting input terminal of the operational amplifier AMP is connected to the other end of the second amplification switch S22_2. The non-inverting output terminal and the inverting output terminal of the operational amplifier AMP work together to output the sampling signal.

[0069] like Figures 4-7 As shown, the principle of the imaging signal sampling circuit in one embodiment of this application is as follows:

[0070] When N is 2, the first sampling module includes 4 reset sampling units. The control terminals of the first sampling switches in the first and second reset sampling units are connected to the first first sampling signal K11_1, and the control terminals of the first sampling switches in the third and fourth reset sampling units are connected to the second first sampling signal K11_2. The second sampling module includes 4 signal sampling units. The control terminals of the third sampling switches in the first and second reset sampling units are connected to the first third sampling signal K13_1, and the control terminals of the third sampling switches in the third and fourth reset sampling units are connected to the second third sampling signal K13_2.

[0071] like Figure 6 As shown, the imaging signal V CCD During the Nth period, the imaging signal V CCD The first state is the imaging signal V. CCD When the value is the reset level Vr, the first sampling signal K11_1 and the second sampling signal K2 are set to high level, the reset signal K15 is set to high level, the first sampling switch S11_11 and the second sampling switch S11_12 are turned on, the second sampling switch S1_1 is turned on, based on the first sampling capacitor C S1_1 and the second first sampling capacitor C S1_2 For imaging signal V CCD Two samples are taken, and the operational amplifier AMP is reset according to the reset signal K15. The equivalent circuit diagram for imaging signal sampling is as follows: Figure 7 As shown in (a).

[0072] After sampling, the third differential connection signal K21_3 is set to high level, and the first amplified signal K22 and the second amplified signal K23 are also set to high level. The third differential connection switch S21_3 is turned on, and the first amplified switch S22_1, the second amplified switch S22_2, the third amplified switch S23_1, the fourth amplified switch S23_2, the fifth amplified switch S23_3, and the sixth amplified switch S23_4 are also turned on. This turns on the third first sampling capacitor C in the (N-1)th cycle. S1_3 The reset voltage and the third second sampling capacitor C S2_3 The signal voltage is differentially amplified to obtain the sampling signal, which is VOP1'-VON1'. The equivalent circuit diagram for sampling the imaging signal is shown below. Figure 7 As shown in (b).

[0073] After amplification, the second first sampling signal K11_2 and the second sampling signal K2 are set to high level, the reset signal K15 is set to high level, the third first sampling switch S11_21 and the fourth first sampling switch S11_22 are turned on, the second sampling switch S1_1 is turned on, based on the third first sampling capacitor C S1_3 and the fourth first sampling capacitor C S1_4 For imaging signal V CCD Two samples are taken, and the operational amplifier AMP is reset according to the reset signal K15. The equivalent circuit diagram for imaging signal sampling is as follows: Figure 7 As shown in (c).

[0074] After sampling is completed, the imaging signal V CCD During the Nth period, the imaging signal V CCD It changes to the second state, i.e., the imaging signal V CCD The value is the signal level V. S1 At this time, the first third sampling signal K13_1 and the fourth sampling signal K4 are set to high level, the reset signal K15 is set to high level, the first third sampling switch S13_11 and the second third sampling switch S13_12 are turned on, the fourth sampling switch S1_2 is turned on, based on the first second sampling capacitor C S2_1 and the second sampling capacitor C S2_2 For imaging signal V CCD Two samples are taken, and the operational amplifier AMP is reset according to the reset signal K15. The equivalent circuit diagram for imaging signal sampling is as follows: Figure 7 As shown in (d).

[0075] After sampling, the first differential connection signal K21_1 is set to high level, and the first amplified signal K22 and the second amplified signal K23 are also set to high level. The first differential connection switch S21_1 is turned on, and the first amplified switch S22_1, the second amplified switch S22_2, the third amplified switch S23_1, the fourth amplified switch S23_2, the fifth amplified switch S23_3, and the sixth amplified switch S23_4 are also turned on. This turns on the first sampling capacitor C in the Nth period. S1_1 The reset voltage and the first second sampling capacitor C S2_1 The signal voltage is differentially amplified to obtain the sampled signal, which is VOP0-VON0. The equivalent circuit diagram for imaging signal sampling is shown below. Figure 7 As shown in (e).

[0076] After amplification, the second and third sampling signals K13_2 and K4 are set to high level, the reset signal K15 is set to high level, the third and fourth sampling switches S13_21 and S13_22 are turned on, the fourth sampling switch S1_2 is turned on, and the third sampling capacitor C is used for amplification. S2_3 and the fourth second sampling capacitor C S2_4 For imaging signal V CCD Two samples are taken, and the operational amplifier AMP is reset according to the reset signal K15. The equivalent circuit diagram for imaging signal sampling is as follows: Figure 7 As shown in (f).

[0077] After sampling, the second differential connection signal K21_2 is set to high level, and the first amplified signal K22 and the second amplified signal K23 are also set to high level. The second differential connection switch S21_2 is turned on, and the first amplified switch S22_1, the second amplified switch S22_2, the third amplified switch S23_1, the fourth amplified switch S23_2, the fifth amplified switch S23_3, and the sixth amplified switch S23_4 are also turned on. This turns on the second first sampling capacitor C in the Nth period. S1_2 and the second sampling capacitor C S2_2 Differential amplification is performed to obtain the sampled signal, which is VOP1-VON1. The equivalent circuit diagram for sampling the imaging signal is shown below. Figure 7 As shown in (g).

[0078] It should be noted that the sampling signal in the Nth period is determined as shown in expression (1) or (2):

[0079] VOP-VON=C1 / C S1_m ((Vr-V S1 (1) - (V3-V4)

[0080] VOP-VON=C2 / C S2_m ((Vr-V S1 (2)

[0081] In expressions (1) and (2), VOP-VON is the sampled signal, C1 is the first feedback capacitor, C2 is the second feedback capacitor, and C... S1_m C is the first sampling capacitor. S2_m Vr is the second sampling capacitor, and Vr is the reset voltage of the imaging signal in the first state. S1 V1 is the signal voltage of the imaging signal in the second state, V2 is the third reference voltage, V3 is the fourth reference voltage, and m is an integer, 1≤m≤2N.

[0082] Similarly, the principle of determining the sampling signal in other periods is the same, except that the signal voltage value is different when the imaging signal is in the second state, which will not be elaborated here.

[0083] Please see Figure 8 , Figure 8 This is a comparison diagram illustrating a conventional sampling signal and the sampling signal of this application, as shown in an exemplary embodiment of the present invention.

[0084] Under the same conditions, simulations were performed on a traditional imaging signal sampling circuit and the imaging signal sampling circuit provided in this application, such as... Figure 8 As shown, the sampling signal of a traditional imaging signal sampling circuit is as follows: Figure 8 As shown in (a), it can be seen that after the two sampling networks sample alternately, there is a significant offset between the output signals of the operational amplifier AMP. Simultaneously, after sampling by the same sampling network, the output signal of the operational amplifier AMP exhibits considerable noise. The sampling signal output of the imaging signal sampling circuit provided in this application is as follows: Figure 8 As shown in (b), through Figure 8 (b) It can be seen that the noise of the output signal is significantly suppressed, and the imbalance caused by the traditional imaging signal sampling circuit is eliminated.

[0085] Example 2

[0086] Please see Figure 9 , Figure 9 This is a structural diagram of an imaging signal sampling circuit shown in another exemplary embodiment of the present invention.

[0087] Please see Figure 10 , Figure 10 This is a timing control diagram of an imaging signal sampling circuit shown in another exemplary embodiment of the present invention.

[0088] In detail, such as Figure 9 As shown, when N is 3, the first sampling module includes 6 reset sampling units and a first reference unit. The first and second reset sampling units are connected to the first first sampling signal K11_1, the third and fourth reset sampling units are connected to the second first sampling signal K11_2, and the fifth and sixth reset sampling units are connected to the third first sampling signal K11_3. Under the control of the first first sampling signal K11_1, the second first sampling signal K11_2, and the third first sampling signal K11_3, the imaging signal V is processed. CCD Three samplings are performed to obtain six reset voltages. The first reference unit is connected to the six reset sampling units, the first reference voltage V1, and the second sampling signal K2. During sampling, based on the control of the second sampling signal K2, the first reference voltage V1 is used as the reference value for the six reset sampling units.

[0089] More in detail, such as Figure 9 As shown, the first reset sampling unit includes a first sampling switch S11_11 and a first sampling capacitor C. S1_1 One end of the first sampling switch S11_11 is connected to the imaging signal V. CCD The other end of the first sampling switch S11_11 is connected to the first sampling capacitor C. S1_1 At one end, the control terminal of the first sampling switch S11_11 is connected to the first sampling signal K11_1; the second reset sampling unit includes the first sampling switch S11_12 and the first sampling capacitor C. S1_2 One end of the first sampling switch S11_12 is connected to the imaging signal V. CCD The other end of the first sampling switch S11_12 is connected to the first sampling capacitor C. S1_2 One end of the first sampling switch S11_12 is connected to the first sampling signal K11_1.

[0090] like Figure 9 As shown, the third reset sampling unit includes a first sampling switch S11_21 and a first sampling capacitor C. S1_3 One end of the first sampling switch S11_21 is connected to the imaging signal V. CCD The other end of the first sampling switch S11_21 is connected to the first sampling capacitor C. S1_3 At one end, the control terminal of the first sampling switch S11_21 is connected to the second first sampling signal K11_2; the fourth reset sampling unit includes the first sampling switch S11_22 and the first sampling capacitor C. S1_4 One end of the first sampling switch S11_22 is connected to the imaging signal V. CCD The other end of the first sampling switch S11_22 is connected to the first sampling capacitor C. S1_4 One end of the first sampling switch S11_22 is connected to the control terminal of the second first sampling signal K11_2.

[0091] like Figure 9 As shown, the fifth reset sampling unit includes a first sampling switch S11_31 and a first sampling capacitor C. S1_5 One end of the first sampling switch S11_31 is connected to the imaging signal V. CCD The other end of the first sampling switch S11_31 is connected to the first sampling capacitor C. S1_5 At one end, the control terminal of the first sampling switch S11_31 is connected to the third first sampling signal K11_3; the sixth reset sampling unit includes the first sampling switch S11_32 and the first sampling capacitor C. S1_6 One end of the first sampling switch S11_32 is connected to the imaging signal V. CCD The other end of the first sampling switch S11_32 is connected to the first sampling capacitor C. S1_6One end of the first sampling switch S11_32 is connected to the control terminal of the third first sampling signal K11_3. The first reference unit includes a second sampling switch S1_1, one end of which is connected to the first sampling capacitor (C). S1_1 C S1_2 C S1_3 C S1_4 C S1_5 C S1_6 At the other end of the second sampling switch S1_1, the other end is connected to the first reference voltage V1, and the control terminal of the second sampling switch S1_1 is connected to the second sampling signal K2.

[0092] In detail, such as Figure 9 As shown, the second sampling module includes six signal sampling units and a second reference unit. The first and second signal sampling units are connected to the first third sampling signal K13_1, the third and fourth signal sampling units are connected to the second third sampling signal K13_2, and the fifth and sixth signal sampling units are connected to the third third sampling signal K13_3. Under the control of the first third sampling signal K13_1, the second third sampling signal K13_2, and the third third sampling signal K13_3, the imaging signal V is processed. CCD Three samplings are performed to obtain six signal voltages. The second reference unit is connected to the six signal sampling units, the first reference voltage V1, and the fourth sampling signal K4. During sampling, based on the control of the fourth sampling signal K4, the first reference voltage V1 is used as the reference value of the signal sampling unit.

[0093] More in detail, such as Figure 9 As shown, the first signal sampling unit includes a third sampling switch S13_11 and a second sampling capacitor C. S2_1 One end of the third sampling switch S13_11 is connected to the imaging signal V. CCD The other end of the third sampling switch S13_11 is connected to the second sampling capacitor C. S2_1 At one end, the control terminal of the third sampling switch S13_11 is connected to the first third sampling signal K13_1; the second signal sampling unit includes the third sampling switch S13_12 and the second sampling capacitor C. S2_2 One end of the third sampling switch S13_12 is connected to the imaging signal V. CCD The other end of the third sampling switch S13_12 is connected to the second sampling capacitor C. S2_2 One end of the third sampling switch S13_12 is connected to the first third sampling signal K13_1.

[0094] like Figure 9 As shown, the third signal sampling unit includes a third sampling switch S13_21 and a second sampling capacitor C. S2_3One end of the third sampling switch S13_21 is connected to the imaging signal V. CCD The other end of the third sampling switch S13_21 is connected to the second sampling capacitor C. S2_3 One end of the third sampling switch S13_21 is connected to the control terminal of the second third sampling signal K13_2; the fourth signal sampling unit includes the third sampling switch S13_22 and the second sampling capacitor C. S2_4 One end of the third sampling switch S13_22 is connected to the imaging signal V. CCD The other end of the third sampling switch S13_22 is connected to the second sampling capacitor C. S2_4 One end of the third sampling switch S13_22 is connected to the control terminal of the second third sampling signal K13_2.

[0095] like Figure 9 As shown, the fifth signal sampling unit includes a third sampling switch S13_31 and a second sampling capacitor C. S2_5 One end of the third sampling switch S13_31 is connected to the imaging signal V. CCD The other end of the third sampling switch S13_31 is connected to the second sampling capacitor C. S2_5 At one end, the control terminal of the third sampling switch S13_31 is connected to the third sampling signal K13_3; the sixth signal sampling unit includes the third sampling switch S13_32 and the second sampling capacitor C. S2_6 One end of the third sampling switch S13_32 is connected to the imaging signal V. CCD The other end of the third sampling switch S13_32 is connected to the second sampling capacitor C. S2_6 One end of the third sampling switch S13_32 is connected to the third sampling signal K13_3. The second reference unit includes a fourth sampling switch S1_2, one end of which is connected to the second sampling capacitor (C). S2_1 C S2_2 C S2_3 C S2_4 C S2_5 C S2_6 At the other end of the circuit, the other end of the fourth sampling switch S1_2 is connected to the first reference voltage V1, and the control terminal of the fourth sampling switch S1_2 is connected to the fourth sampling signal K4.

[0096] More in detail, such as Figure 9 As shown, the differential processing unit includes a first differential connection switch S21_1, a second differential connection switch S21_2, a third differential connection switch S21_3, a fourth differential connection switch S21_4, a fifth differential connection switch S21_5, a first amplification switch S22_1, and a second amplification switch S22_2. One end of the first differential connection switch S21_1 is connected to the first sampling capacitor C. S1_1One end, the first sampling capacitor C S1_1 The other end is connected to one end of the first amplifying switch S22_1, and the other end of the first differential connection switch S21_1 is connected to the first second sampling capacitor C. S2_1 One end, the first second sampling capacitor C S2_1 The other end is connected to one end of the second amplifying switch S22_2; the control terminal of the first differential connection switch S21_1 is connected to the first differential connection signal K21_1; one end of the second differential connection switch S21_2 is connected to the second first sampling capacitor C. S1_2 One end, the second first sampling capacitor C S1_2 The other end is connected to one end of the first amplifying switch S22_1, and the other end of the second differential connection switch S21_2 is connected to the second second sampling capacitor C. S2_2 One end, the second sampling capacitor C S2_2 The other end is connected to one end of the second amplification switch S22_2, and the control terminal of the second differential connection switch S21_2 is connected to the second differential connection signal K21_2.

[0097] Similarly, one end of the third differential connection switch S21_3 is connected to the third first sampling capacitor C. S1_3 At one end, the third first sampling capacitor C S1_3 The other end is connected to one end of the first amplifying switch S22_1, and the other end of the third differential connection switch S21_3 is connected to the third second sampling capacitor C. S2_3 One end, the third second sampling capacitor C S2_3 The other end is connected to one end of the second amplification switch S22_2; the control terminal of the third differential connection switch S21_3 is connected to the third differential connection signal K21_3; one end of the fourth differential connection switch S21_4 is connected to the fourth first sampling capacitor C. S1_4 At one end, the fourth first sampling capacitor C S1_4 The other end is connected to one end of the first amplifying switch S22_1, and the other end of the fourth differential connection switch S21_4 is connected to the fourth second sampling capacitor C. S2_4 At one end, the fourth second sampling capacitor C S2_4 The other end is connected to one end of the second amplification switch S22_2; the control terminal of the fourth differential connection switch S21_4 is connected to the fourth differential connection signal K21_4; one end of the fifth differential connection switch S21_5 is connected to the fifth first sampling capacitor C. S1_5 At one end, the fifth first sampling capacitor C S1_5 The other end is connected to one end of the first amplifying switch S22_1, and the other end of the fifth differential connection switch S21_5 is connected to the fifth second sampling capacitor C. S2_5 At one end, the fifth second sampling capacitor C S2_5The other end is connected to one end of the second amplifying switch S22_2, the control end of the fifth differential connection switch S21_5 is connected to the fifth differential connection signal K21_5, the control end of the first amplifying switch S22_1 and the control end of the second amplifying switch S22_2 are connected to the first amplifying signal K22, wherein the other end of the first amplifying switch S22_1 is the first output end of the differential processing unit, and the other end of the second amplifying switch S22_2 is the second output end of the differential processing unit.

[0098] like Figure 9-10 As shown, the principle of the imaging signal sampling circuit in another embodiment provided in this application is as follows:

[0099] In the first half of the Nth period of the imaging signal, combined with Figure 9 and Figure 10 The first sampling module, under the control of three first sampling signals and the second sampling signal K2, processes the imaging signal V. CCD The reset level Vr is sampled:

[0100] The first sampling signal K11_1 and the second sampling signal K2 are both high. Using the first voltage V1 as a reference, the imaging signal V is processed through the first and second reset sampling units. CCD Two samples are taken, resulting in two reset voltages. Simultaneously, under the control of reset signal K15, the amplification unit is in a reset state. After sampling, the first amplification signal K22, the second amplification signal K23, and the fourth differential connection signal K21_4 are at high levels. The amplification unit samples the reset voltage of the N-1th cycle (the fourth first sampling capacitor C). S1_4 Storage voltage) and signal voltage (fourth second sampling capacitor C) S2_4 The stored voltage is amplified to obtain a sampled signal.

[0101] The second sampling signal K11_2 and the second sampling signal K2 are both high. Using the first voltage V1 as a reference, the imaging signal V is processed through the third and fourth reset sampling units. CCD Two samples are taken, resulting in two reset voltages. Simultaneously, under the control of reset signal K15, the amplification unit is in a reset state. After sampling, the first amplification signal K22, the second amplification signal K23, and the fifth differential connection signal K21_5 are at high levels. The amplification unit samples the reset voltage of the N-1th cycle (the fifth first sampling capacitor C). S1_5 Storage voltage) and signal voltage (fifth second sampling capacitor C) S2_5 The stored voltage is amplified to obtain a sampled signal.

[0102] The third first sampling signal K11_3 and the second sampling signal K2 are at a high level. Taking the first voltage V1 as a reference, the imaging signal V is processed through the fifth and sixth reset sampling units. CCD Two samples are taken to obtain two reset voltages. Simultaneously, under the control of reset signal K15, the amplification unit is in a reset state. After sampling is completed, as follows... Figure 9 As shown, the imaging signal V CCD Entering the second half of the cycle.

[0103] In the second half of the Nth period of the imaging signal, the second sampling module, under the control of three third sampling signals and a fourth sampling signal, samples the imaging signal V. CCD signal level V S1 Perform sampling:

[0104] The first second sampling signal K13_1 and the fourth sampling signal K4 are at high level. Taking the first voltage V1 as a reference, the imaging signal V is processed through the first signal sampling unit and the second signal sampling unit. CCD Two samples are taken, resulting in two signal voltages. Simultaneously, under the control of the reset signal K15, the amplification unit is in a reset state. After sampling, the first amplified signal K22, the second amplified signal K23, and the first differential connection signal K21_1 are at a high level. The amplification unit receives the reset voltage of the Nth cycle sample (the first sampling capacitor C). S1_1 Storage voltage) and signal voltage (first and second sampling capacitor C) S2_1 The stored voltage is amplified to obtain a sampled signal.

[0105] The second sampling signal K13_2 and the fourth sampling signal K4 are at a high level. Using the first voltage V1 as a reference, the imaging signal V is processed through the third and fourth signal sampling units. CCD Two samples are taken, resulting in two signal voltages. Simultaneously, under the control of the reset signal K15, the amplification unit is in a reset state. After sampling, the first amplified signal K22, the second amplified signal K23, and the second differential connection signal K21_2 are at high levels. The amplification unit then samples the reset voltage of the Nth cycle (the second first sampling capacitor C). S1_2 Storage voltage) and signal voltage (second sampling capacitor C) S2_2 The stored voltage is amplified to obtain a sampled signal.

[0106] The third second sampling signal K13_3 and the fourth sampling signal K4 are at a high level. Taking the first voltage V1 as a reference, the imaging signal V is processed through the fifth and sixth signal sampling units. CCDTwo samples are taken, resulting in two signal voltages. Simultaneously, under the control of the reset signal K15, the amplification unit is in a reset state. After sampling, the first amplified signal K22, the second amplified signal K23, and the third differential connection signal K21_3 are at high levels. The amplification unit then performs a reset on the Nth cycle sample (the third first sampling capacitor C). S1_3 Storage voltage) and signal voltage (third second sampling capacitor C) S2_3 The stored voltage is amplified to obtain a sampled signal.

[0107] In summary, the imaging signal sampling circuit in Example 2 samples the voltage of the upper half-cycle and the lower half-cycle of the imaging signal six times, and performs differential amplification processing on the sampled voltages five times to obtain five sampled signals. This process suppresses noise in the output sampled signal to a certain extent and eliminates the misalignment caused by traditional imaging signal sampling circuits.

[0108] It should be noted that in the imaging signal sampling circuit provided in this application, since the difference between the reset voltage and the signal voltage sampled by the 2Nth first sampling capacitor and the 2Nth second sampling capacitor has not yet been amplified, the first sampling capacitor C... S1_2 and the first second sampling capacitor C S2_2 Another sampling is required, so only the imaging signal from the 2N-1th sampling is amplified. The 2Nth first sampling capacitor and the 2Nth second sampling capacitor are placed in the circuit as matching capacitors.

[0109] Furthermore, based on the same inventive concept as the imaging signal sampling circuit described above, the present invention also provides an imaging signal sampling method, comprising:

[0110] During the first half of the imaging signal cycle, the imaging signal is sampled N times. Each sample is taken through M sampling capacitors to obtain M*N reset voltages.

[0111] During the second half of the imaging signal cycle, the imaging signal is sampled N times, and each sample is sampled through M sampling capacitors to obtain M*N signal voltages.

[0112] Within each cycle, reset operations and differential amplification are performed alternately, and 2N sampling operations are performed sequentially and at least synchronously with some of the reset operations. M*N reset voltages and M*N signal voltages are subjected to M*N-1 differential amplification operations to obtain M*N-1 sampled signals. During the t-th differential amplification, the t-th reset voltage and the t-th signal voltage are differentially amplified to obtain the t-th sampled signal.

[0113] Where t, N, and M are integers, N≥2, M≥2, and 1≤t≤M*N-1.

[0114] This application provides an imaging signal sampling circuit and method. The circuit includes: a first sampling module that samples the imaging signal N times under the control of N first sampling signals and a second sampling signal to obtain 2N reset voltages; a second sampling module that samples the imaging signal N times under the control of N third sampling signals and a fourth sampling signal to obtain 2N signal voltages; during each period of the imaging signal, when sampling the imaging signal, a reset signal controls an amplification module to perform a reset operation; after sampling, the 2N reset voltages and 2N signal voltages are differentially amplified 2N-1 times to obtain 2N-1 sampled signals. This application uses two sampling modules to sample the imaging signal multiple times to enhance the sampling circuit's ability to suppress imaging signal noise. The reset voltages and signal voltages obtained from multiple samplings are sequentially amplified to obtain multiple sampled signals. By averaging multiple times, the offset error of the output signal is reduced. The sampling circuit enhances noise suppression and reduces output signal error, thereby improving the accuracy and precision of signal sampling.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An imaging signal sampling circuit, characterized in that, include: The first sampling module receives an imaging signal, a first reference voltage, N first sampling signals and a second sampling signal. Under the control of the N first sampling signals and the second sampling signals, it samples the imaging signal N times based on the first reference voltage to obtain 2N reset voltages. The second sampling module receives the imaging signal, the first reference voltage, N third sampling signals and a fourth sampling signal. Under the control of the N third sampling signals and the fourth sampling signal, it samples the imaging signal N times based on the first reference voltage to obtain 2N signal voltages. An amplification module is connected to the first sampling module and the second sampling module. The amplification module receives 2N-1 differential connection signals, a first amplified signal, a second amplified signal, and a reset signal. In each cycle of the imaging signal, the amplification module alternately performs a reset operation and differential amplification processing. When the reset signal controls the amplification module to perform a reset operation, it synchronously controls the first sampling module or the second sampling module to sample the imaging signal. After sampling is completed, under the control of the 2N-1 differential connection signals, the first amplified signal, and the second amplified signal, 2N reset voltages and 2N signal voltages are differentially amplified 2N-1 times to obtain 2N-1 sampled signals. During the i-th amplification, the i-th reset voltage and the i-th signal voltage are differentially amplified to obtain the i-th sampled signal. Where i and N are integers, N≥2, 1≤i≤2N-1.

2. The imaging signal sampling circuit according to claim 1, characterized in that, The first sampling module includes 2N reset sampling units and a first reference unit. The reset sampling unit receives the first sampling signal and samples the imaging signal based on the first sampling signal to obtain the reset voltage. The first reference unit is connected to the reset sampling unit and receives the first reference voltage and the second sampling signal. Based on the second sampling signal, the first reference voltage is used as the reference value of the reset sampling unit.

3. The imaging signal sampling circuit according to claim 2, characterized in that, The reset sampling unit includes a first sampling switch and a first sampling capacitor. One end of the first sampling switch receives the imaging signal, and the other end of the first sampling switch is connected to one end of the first sampling capacitor. The control terminal of the first sampling switch receives the first sampling signal. The first reference unit includes a second sampling switch. One end of the second sampling switch is connected to the other end of the first sampling capacitor. The other end of the second sampling switch receives the first reference voltage, and the control terminal of the second sampling switch receives the second sampling signal.

4. The imaging signal sampling circuit according to claim 3, characterized in that, The second sampling module includes 2N signal sampling units and a second reference unit. The signal sampling units receive the third sampling signal and sample the imaging signal based on the third sampling signal to obtain the signal voltage. The second reference unit is connected to the signal sampling units and receives the first reference voltage and the fourth sampling signal. Based on the fourth sampling signal, the second reference unit uses the first reference voltage as a reference value for the signal sampling units.

5. The imaging signal sampling circuit according to claim 4, characterized in that, The signal sampling unit includes a third sampling switch and a second sampling capacitor. One end of the third sampling switch receives the imaging signal, and the other end of the third sampling switch is connected to one end of the second sampling capacitor. The control terminal of the third sampling switch receives the third sampling signal. The second reference unit includes a fourth sampling switch. One end of the fourth sampling switch is connected to the other end of the second sampling capacitor. The other end of the fourth sampling switch receives the first reference voltage, and the control terminal of the fourth sampling switch receives the fourth sampling signal.

6. The imaging signal sampling circuit according to claim 5, characterized in that, The amplification module includes a differential processing unit and an amplification unit. The differential processing unit receives the 2N-1 differential connection signals and the first amplified signal. Under the control of the 2N-1 differential connection signals and the first amplified signal, it connects 2N reset voltages and 2N signal voltages one-to-one to obtain 2N-1 differential signals. The amplification unit is connected to the differential processing unit. The amplification unit receives the second amplified signal and the reset signal. When the reset signal controls the amplification unit to perform a reset operation, it synchronously controls the first sampling module or the second sampling module to sample the imaging signal. After sampling is completed, under the control of the second amplified signal, the 2N-1 differential signals are amplified sequentially to obtain 2N-1 sampled signals.

7. The imaging signal sampling circuit according to claim 6, characterized in that, The differential processing unit includes 2N-1 differential connection switches, a first amplification switch, and a second amplification switch. One end of the i-th differential connection switch is connected to one end of the i-th first sampling capacitor, the other end of the i-th first sampling capacitor is connected to one end of the first amplification switch, the other end of the i-th differential connection switch is connected to one end of the i-th second sampling capacitor, the other end of the i-th second sampling capacitor is connected to one end of the second amplification switch, the control terminal of the i-th differential connection switch receives the i-th differential connection signal, and the control terminals of the first amplification switch and the second amplification switch receive the first amplified signal. The other end of the first amplification switch is the first output terminal of the differential processing unit, and the other end of the second amplification switch is the second output terminal of the differential processing unit.

8. The imaging signal sampling circuit according to claim 6, characterized in that, The amplification unit includes a first reset switch, a second reset switch, a third reset switch, a fourth reset switch, a fifth reset switch, a sixth reset switch, a third amplification switch, a fourth amplification switch, a fifth amplification switch, a sixth amplification switch, a first feedback capacitor, a second feedback capacitor, and an operational amplifier. One end of the first reset switch is connected to the non-inverting input of the operational amplifier, and the other end of the first reset switch is connected to the inverting input of the operational amplifier. The non-inverting input of the operational amplifier is connected to the inverting output of the operational amplifier via the third amplification switch, the first feedback capacitor, and the fourth amplification switch connected in series. The inverting input of the operational amplifier is connected to the non-inverting output of the operational amplifier via the fifth amplification switch, the second feedback capacitor, and the sixth amplification switch connected in series. The inverting output of the operational amplifier is connected to the non-inverting output of the operational amplifier via the second reset switch connected in series. The second reference voltage is connected to one end of the first feedback capacitor via the third reset switch connected in series. The third reference voltage is connected to the other end of the first feedback capacitor via the fourth reset switch connected in series. The second reference voltage is connected to one end of the second feedback capacitor via the fifth reset switch connected in series. The fourth reference voltage is connected to the other end of the second feedback capacitor via the sixth reset switch connected in series. The control terminals of the first, second, third, fourth, fifth, and sixth reset switches receive the reset signal. The control terminals of the third, fourth, fifth, and sixth amplification switches receive the second amplified signal. The non-inverting input of the operational amplifier is connected to the first output of the differential processing unit, and the inverting input of the operational amplifier is connected to the second output of the differential processing unit. The non-inverting and inverting outputs of the operational amplifier cooperate to output the sampled signal.

9. An imaging signal sampling method, characterized in that, The imaging signal sampling circuit as described in any one of claims 1-8 includes: During the first half of the imaging signal period, the imaging signal is sampled N times, and each sample is sampled through M sampling capacitors to obtain M*N reset voltages. During the second half-cycle of the imaging signal, the imaging signal is sampled N times, and each sample is sampled through M sampling capacitors to obtain M*N signal voltages; Within each cycle, reset operations and differential amplification are performed alternately, and 2N sampling operations are performed sequentially and at least synchronously with some of the reset operations. M*N reset voltages and M*N signal voltages are subjected to M*N-1 differential amplification operations to obtain M*N-1 sampled signals. During the t-th differential amplification, the t-th reset voltage and the t-th signal voltage are differentially amplified to obtain the t-th sampled signal. Where t, N, and M are integers, N≥2, M≥2, and 1≤t≤M*N-1.

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