Memory block and its manufacturing method, memory cell

Abstract

The application provides a memory block, a manufacturing method thereof and a memory cell. The method comprises the following steps: providing a semiconductor substrate; forming a plurality of word line holes on the semiconductor substrate to divide each memory subarray layer on the semiconductor substrate into a plurality of column drain region semiconductor strips, channel semiconductor strips and source region semiconductor strips along a row direction; forming a floating gate memory structure on at least one side of the part of the channel semiconductor strip exposed by the word line hole; and filling a gate material in each word line hole to form a plurality of gate strips, at least part of each gate strip overlaps with the projection of the corresponding channel semiconductor strip in a projection plane, and the part of the gate strip, the corresponding part of the channel semiconductor strip, the part of the floating gate memory structure sandwiched between the gate strip and the channel semiconductor strip, the part of the drain region semiconductor strip adjacent to the corresponding part of the channel semiconductor strip and the part of the source region semiconductor strip constitute a memory cell. The memory block manufactured by the method has a high memory density.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a memory block, a process method thereof and a memory cell. BACKGROUND

[0002] Two-dimensional (2D) memory blocks are prevalent in electronic devices and can include, for example, NOR flash memory arrays, NAND flash memory arrays, dynamic random-access memory (DRAM) arrays, and the like. However, 2D memory arrays are approaching scaling limits and further improvements in memory density are not possible. SUMMARY

[0003] The memory block, the process method thereof and the memory cell provided by the present application are aimed at solving the problem that the existing 2D memory array is approaching a scaling limit and further improvements in memory density are not possible.

[0004] To solve the above technical problems, one technical solution adopted by the present application is to provide a process method of a memory block. The method comprises: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a plurality of memory subarray layers formed on the substrate, the plurality of memory subarray layers are sequentially stacked in a height direction perpendicular to the substrate, and each memory subarray layer comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked in the height direction; a plurality of word line holes are formed on the semiconductor substrate to divide each memory subarray layer into a plurality of columns of drain semiconductor strips, channel semiconductor strips and source semiconductor strips in a row direction, wherein the plurality of word line holes are arranged in a matrix in the row direction and the column direction, each word line hole extends in the height direction, and at least one side of each word line hole exposes part of at least one column of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips of the plurality of memory subarray layers; a floating gate storage structure is formed on at least one side of the part of the channel semiconductor strips exposed by the word line hole; and a gate material is filled in each word line hole to form a plurality of gate strips, wherein at least part of each gate strip overlaps with a projection of a corresponding channel semiconductor strip in a projection plane in the height direction and the column direction, the part of the gate strip, the corresponding part of the channel semiconductor strip, the part of the corresponding floating gate storage structure sandwiched between the part of the gate strip and the corresponding part of the channel semiconductor strip, the part of the drain semiconductor strip adjacent to the corresponding part of the channel semiconductor strip, and the part of the source semiconductor strip constitute a memory cell.

[0005] In one embodiment, the providing a semiconductor substrate comprises:

[0006] providing the substrate;

[0007] forming a plurality of memory subarray layers on the substrate in sequence along the height direction;

[0008] forming a first hard mask layer on the plurality of memory subarray layers, and forming a plurality of isolation barrier wall holes in the first hard mask layer and the plurality of memory subarray layers, and filling the isolation barrier wall holes with an insulator to form a plurality of isolation walls, to form the semiconductor substrate, wherein the isolation barrier wall holes are arranged in a matrix in the row direction and the column direction, and each of the isolation barrier wall holes extends along the height direction to the substrate.

[0009] In one embodiment, the substrate is a single crystal substrate;

[0010] the forming a plurality of memory subarray layers on the substrate in sequence along the height direction comprises:

[0011] forming a first single crystal sacrificial semiconductor layer or a dummy memory subarray layer on the substrate by epitaxial growth;

[0012] alternately forming two layers of memory subarray layers and a second single crystal sacrificial semiconductor layer on the first single crystal sacrificial semiconductor layer by epitaxial growth in sequence until forming the uppermost two layers of memory subarray layers, or alternately forming a second single crystal sacrificial semiconductor layer and two layers of memory subarray layers on the dummy memory subarray layer by epitaxial growth in sequence.

[0013] In one embodiment, two adjacent layers of memory subarray layers share a source region, and the forming of each of the two layers of memory subarray layers sharing a source region comprises:

[0014] forming a first single crystal semiconductor layer of a first doping type on the first single crystal sacrificial semiconductor layer or the second single crystal sacrificial semiconductor layer below by epitaxial growth;

[0015] forming a second single crystal semiconductor layer of a second doping type on the first single crystal semiconductor layer by epitaxial growth;

[0016] forming a third single crystal semiconductor layer of the first doping type on the second single crystal semiconductor layer by epitaxial growth;

[0017] forming a fourth single crystal semiconductor layer of the second doping type on the third single crystal semiconductor layer by epitaxial growth;

[0018] forming a fifth single crystal semiconductor layer of the first doping type on the fourth single crystal semiconductor layer by epitaxial growth;

[0019] wherein the first monocrystalline semiconductor layer and the fifth monocrystalline semiconductor layer of the first doping type are used as the drain semiconductor layer, the second monocrystalline semiconductor layer and the fourth monocrystalline semiconductor layer of the second doping type are used as the channel semiconductor layer, and the third monocrystalline semiconductor layer of the first doping type is used as the source semiconductor layer;

[0020] The first monocrystalline semiconductor layer, the second monocrystalline semiconductor layer, and the third monocrystalline semiconductor layer constitute one of the memory subarray layers; the third monocrystalline semiconductor layer, the fourth monocrystalline semiconductor layer, and the fifth monocrystalline semiconductor layer constitute another of the memory subarray layers; and the two memory subarray layers share the third monocrystalline semiconductor layer as a shared source semiconductor layer.

[0021] In one embodiment, the step of forming a plurality of word line holes in the semiconductor substrate comprises:

[0022] forming a plurality of word line openings in the first hard mask layer, wherein the plurality of word line openings are arranged in a matrix in the row direction and the column direction;

[0023] using the first hard mask layer with the word line openings as a mask to etch the plurality of memory subarray layers under the first hard mask layer to form a plurality of word line holes, wherein the plurality of word line holes cooperate with the plurality of isolation walls to divide each of the memory subarray layers into a plurality of columns of drain semiconductor strips, channel semiconductor strips, and source semiconductor strips in the row direction.

[0024] In one embodiment, the method further comprises:

[0025] using the word line holes to remove the first monocrystalline sacrificial semiconductor layer and the second monocrystalline sacrificial semiconductor layer;

[0026] depositing in the regions where the first monocrystalline sacrificial semiconductor layer and the second monocrystalline sacrificial semiconductor layer are removed to fill the regions with an insulating material, thereby replacing the first monocrystalline sacrificial semiconductor layer and the second monocrystalline sacrificial semiconductor layer with insulating isolation layers.

[0027] In one embodiment, the step of using the word line holes to form a floating gate memory structure on at least one side of the portion of the channel semiconductor strip exposed comprises:

[0028] using the word line holes to form a first insulating dielectric layer on at least one side of the portion of the channel semiconductor strip exposed;

[0029] forming a floating gate on a side surface of the first insulating medium layer away from the portion of the channel semiconductor strip;

[0030] forming a second insulating medium layer on a sidewall in each word line hole, the second insulating medium layer cooperating with the first insulating medium layer to wrap any surface of the floating gate, wherein the first insulating medium layer, the floating gate and the second insulating medium layer constitute the floating gate storage structure.

[0031] In one embodiment, the forming the first insulating medium layer on at least one side of the portion of the channel semiconductor strip exposed by the word line hole respectively comprises:

[0032] removing the portion of the channel semiconductor strip exposed by each word line hole to form a first recess;

[0033] filling the first insulating medium in the first recesses;

[0034] removing the portion of the drain semiconductor strip and the portion of the source semiconductor strip exposed by each word line hole to form second recesses; the second recesses expose portions of the first insulating medium;

[0035] forming a second insulating medium in the second recesses;

[0036] removing the first insulating medium of the layer where the channel semiconductor strip is located to expose the first recesses, and depositing a first insulating medium layer on a sidewall of the first recesses; the first insulating medium layer defines a floating gate groove; the floating gate is formed in the floating gate groove.

[0037] In one embodiment, the removing the portion of the channel semiconductor strip exposed by each word line hole comprises:

[0038] removing the portion of the channel semiconductor strip exposed by each word line hole by etching;

[0039] the filling the first insulating medium in the first recesses comprises

[0040] filling the first insulating medium in the first recesses by deposition.

[0041] In one embodiment, the forming the floating gate on a side surface of the first insulating medium layer away from the portion of the channel semiconductor strip comprises:

[0042] depositing a floating gate material in the floating gate groove to form the floating gate;

[0043] wherein the floating gate material comprises polysilicon material.

[0044] In one embodiment, a second insulating medium layer is formed on the sidewall of each word line hole, comprising:

[0045] A portion of the first hard mask layer around each word line hole and a portion of the second insulating medium in each second groove are removed to widen each word line hole and expose a portion of each floating gate.

[0046] A second insulating medium layer is formed on the sidewall of each widened word line hole to wrap the exposed portion of each floating gate.

[0047] To solve the above technical problems, another technical solution adopted by the present application is to provide a memory block. The memory block comprises: a memory array comprising a plurality of memory cells distributed in a three-dimensional array, wherein the memory array comprises a plurality of stack structures distributed along a row direction, each stack structure respectively extends along a column direction, and each stack structure respectively comprises a drain semiconductor strip, a channel semiconductor strip and a source semiconductor strip stacked along a height direction, each of the drain semiconductor strip, the channel semiconductor strip and the source semiconductor strip respectively extends along the column direction; two sides of the stack structure are respectively provided with a plurality of gate strips distributed along the column direction, each of the gate strips extends along the height direction; in the height direction, at least a portion of each of the gate strips overlaps with a portion of a corresponding channel semiconductor strip in a projection plane, the projection plane extends along the height direction and the column direction; the portion of the gate strip, the corresponding portion of the channel semiconductor strip, the portion of the drain semiconductor strip adjacent to the corresponding portion of the channel semiconductor strip and the portion of the source semiconductor strip are used to constitute a memory cell; a floating gate memory structure is arranged between each of the gate strips and the drain semiconductor strip, the channel semiconductor strip and the source semiconductor strip in a plurality of memory subarray layers.

[0048] In one embodiment, each of the drain semiconductor strip, the channel semiconductor strip and the source semiconductor strip is a single crystal semiconductor strip.

[0049] In one embodiment, each column of the stack structure comprises a plurality of stack substructures, each stack substructure comprises a drain semiconductor strip, a channel semiconductor strip, a source semiconductor strip, a channel semiconductor strip and a drain semiconductor strip stacked in sequence along the height direction to share the same source semiconductor strip.

[0050] In one embodiment, an interlayer isolation strip is arranged between two adjacent stack substructures to isolate each other.

[0051] In one embodiment, two sides of the stack structure are respectively provided with a plurality of isolation walls distributed along the column direction, each of the isolation walls extends along the height direction and the row direction to separate at least part of two adjacent columns of the stack structure.

[0052] In one embodiment, in the column direction, the gate strip is filled between two adjacent isolation walls of the same column.

[0053] Part of two adjacent columns of the stack structure shares the same gate strip.

[0054] In one embodiment, the isolation wall near the column direction edge of the memory block is a T-shaped isolation wall or extends to the column direction edge of the memory block in the column direction to completely separate two adjacent columns of the stack structure.

[0055] In one embodiment, the floating gate storage structure includes a plurality of first insulating medium layers, a plurality of floating gates and a second insulating medium layer, wherein each of the first insulating medium layers is located at least between a corresponding channel semiconductor strip and a corresponding floating gate, the floating gate is located between the first insulating medium layer and the second insulating medium layer, and the second insulating medium layer is located at least between the floating gate and the gate strip.

[0056] In one embodiment, part of the second insulating medium layer covers five surfaces of the floating gate, wherein at least part of four of the five surfaces of the floating gate are covered by part of the second insulating medium layer.

[0057] To solve the above technical problems, another technical solution adopted by the present application is to provide a memory cell, which comprises a drain region part, a channel part, a source region part and a gate part, wherein the drain region part, the channel part and the source region part are stacked along a height direction, the gate part is located on one side of the drain region part, the channel part and the source region part and extends along the height direction; wherein in the height direction, a projection of the gate part and the channel part on a projection plane extending along the height direction and the extension direction of the drain region part, the channel part and the source region part at least partially overlaps, and a floating gate storage structure part is arranged between the gate part and the drain region part, the channel part and the source region part.

[0058] In one embodiment, the drain region part, the channel part and the source region part are single-crystal semiconductors.

[0059] In one embodiment, the floating gate storage structure portion includes a first insulating medium layer, a floating gate, and a portion of a second insulating medium layer, wherein the first insulating medium layer is located at least between the channel portion and the floating gate, the floating gate is located between the first insulating medium layer and the portion of the second insulating medium layer, the first insulating medium layer and the portion of the second insulating medium layer completely wrap the floating gate, and the second insulating medium layer is located at least between the floating gate and the gate portion.

[0060] In one embodiment, the portion of the second insulating medium layer covers five surfaces of the floating gate, wherein at least a portion of four of the five surfaces of the floating gate are covered by the portion of the second insulating medium layer.

[0061] In one embodiment, the gate portion wraps the five surfaces of the floating gate through the second insulating medium layer, wherein at least a portion of four of the five surfaces of the floating gate are wrapped by the gate portion through the second insulating medium layer.

[0062] In one embodiment, the portion of the second insulating medium layer includes a multi-layer structure, the multi-layer structure including a portion of a silicon oxide layer, a portion of a silicon nitride layer, and a portion of another silicon oxide layer.

[0063] The beneficial effects of the present application are distinguished from the prior art: the process method for the storage block provided by the present application, by providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a plurality of storage subarray layers formed on the substrate, the plurality of storage subarray layers are sequentially stacked along the height direction perpendicular to the substrate, each storage subarray layer comprises a drain region semiconductor layer, a channel semiconductor layer and a source region semiconductor layer stacked along the height direction; then a plurality of word line holes are opened on the semiconductor substrate to divide each layer of storage subarray layer into a plurality of columns of drain region semiconductor strips, channel semiconductor strips and source region semiconductor strips along the row direction, wherein the plurality of word line holes are arranged in a matrix in the row direction and the column direction, each word line hole extends along the height direction, and at least one side of each word line hole exposes part of at least one column of drain region semiconductor strips, channel semiconductor strips and source region semiconductor strips of the plurality of storage subarray layers; then a floating gate storage structure is formed on at least one side of the part of the channel semiconductor strip exposed by the word line hole; a gate material is filled in each word line hole to form a plurality of gate strips, wherein at least part of each gate strip coincides with the projection of a corresponding channel semiconductor strip in each layer of storage subarray layer in a projection plane, the projection plane extends along the height direction and the column direction, the part of the gate strip, the corresponding part of the channel semiconductor strip, the part of the corresponding floating gate storage structure sandwiched between the part of the gate strip and the corresponding part of the channel semiconductor strip, the part of the drain region semiconductor strip adjacent to the corresponding part of the channel semiconductor strip and the part of the source region semiconductor strip constitute a storage cell. The storage density of the storage block prepared by the method is higher. BRIEF DESCRIPTION OF DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort.

[0065] Figure 1 The structural diagram of the storage device provided by the embodiments of the present application;

[0066] Figures 2a to 4 The three-dimensional structural schematic diagram of the storage array provided by the present application;

[0067] Figure 5 The three-dimensional structural schematic diagram of the storage unit provided by an embodiment of the present application;

[0068] Figure 6 The three-dimensional structural schematic diagram illustrating that two storage units share the same column of drain region semiconductor strips, channel semiconductor strips and source region semiconductor strips;

[0069] Figure 7A perspective view of a storage unit according to another embodiment of the present application is provided;

[0070] Figure 8 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0071] Figure 9 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0072] Figure 10 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0073] Figure 11 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0074] Figure 12 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0075] Figure 13 A perspective view of a storage unit according to another embodiment of the present application is provided; Figure 11 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0076] Figure 14 A perspective view of a storage unit according to another embodiment of the present application is provided; Figure 11 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0077] Figure 15 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0078] Figure 16 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0079] Figure 17 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0080] Figures 18-39 A perspective view of a storage unit according to another embodiment of the present application is provided;

[0081] Explanation of reference numerals

[0082] Memory block 10; memory array 1; memory subarray layer 1a; drain semiconductor strip 11; bit line connection line 11a; channel semiconductor strip 12; well connection line 12a; common well line 12b; source semiconductor strip 13; source connection line 13a; common source line 13b; interlayer isolation strip 14a; second single-crystal sacrificial semiconductor layer 14; insulating isolation layer 14'; body structure 15a; protruding portion 15b; support column 16; one column of semiconductor strip-shaped structures 1b; gate strip 2; isolation wall 3; isolation barrier hole 31; word line hole 4; memory structure 5; first dielectric layer 51; charge storage layer 52; second dielectric layer 53; floating gate 54; first insulating dielectric layer 56; odd digit line 8a; even digit line 8b; word line connection line 7; drain region portion 11'; channel portion 12'; source region portion 13'; gate portion 2'; memory structure portion 5'; substrate 81; first single-crystal sacrificial semiconductor layer 82; first hard mask layer 83; word line opening 831; first recess 84; second recess 84'; third recess 84a; first insulating dielectric 85; first insulating dielectric layer 85a; second insulating dielectric layer 85b; second insulating dielectric 86; drain semiconductor layer 11c; channel semiconductor layer 12c; source semiconductor layer 13c. DETAILED DESCRIPTION

[0083] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0084] The terms "first", "second", "third" in the present application are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0085] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combinable with other embodiments.

[0086] The application will be described in detail below with reference to the attached drawings and embodiments.

[0087] In the present embodiment, reference is made to Figure 1 , Figure 1 A structural diagram of a memory device provided in the present embodiment is shown. A memory device is provided, which can be specifically a non-volatile memory device. The memory device can include one or more memory blocks 10. The specific structure and function of the memory block 10 can be referred to the relevant description of the memory block 10 provided in any of the embodiments below. Those skilled in the art can understand that the memory array 1 includes a structure of a three-dimensional array arrangement of a plurality of memory cells; and the memory block 10, in addition to including the memory array 1 formed by the array arrangement of a plurality of memory cells, can also include other elements, such as various types of conductive lines (or connection lines) and the like, so that the memory block 10 can implement various memory operations.

[0088] Please refer to Figures 2a to 3 A three-dimensional structural schematic diagram of a memory array provided in the present embodiment is shown; in the present embodiment, a memory block 10 is provided, which includes a memory array 1. The memory array 1 includes a plurality of memory cells arranged in a three-dimensional array.

[0089] As shown in Figure 2a , the memory array 1 includes a plurality of memory sub-array layers 1a stacked in sequence along a height direction Z, each memory sub-array layer 1a including a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked along the height direction Z. The drain semiconductor layer, the channel semiconductor layer, and the source semiconductor layer can be single-crystal semiconductor layers grown by epitaxy. The height direction Z is a direction perpendicular to a substrate (such as the substrate 81 of Figure 9 ). In sequence stacked means arranged from bottom to top on the substrate, and stacked represents arrangement, without explicitly or implicitly indicating the up-down relationship of the structures or layers.

[0090] In each layer of the memory subarray layer 1a, the drain semiconductor layer (D) includes a plurality of drain semiconductor strips 11 spaced apart along the row direction X, each drain semiconductor strip 11 extending along the column direction Y; the channel semiconductor layer (CH) includes a plurality of channel semiconductor strips 12 spaced apart along the row direction X, each channel semiconductor strip 12 extending along the column direction Y. The source semiconductor layer (S) includes a plurality of source semiconductor strips 13 spaced apart along the row direction X, each source semiconductor strip 13 extending along the column direction Y. Each of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 is a single-crystal semiconductor strip. Those skilled in the art can understand that each of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 can be a single-crystal semiconductor strip formed by processing the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer formed by epitaxy. As shown in Figures 2a-3 each column of the drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13 is provided with a plurality of gate strips 2 (G), the plurality of gate strips 2 distributed on one side of each column of the drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13 are spaced apart along the column direction Y, and each gate strip 2 extends along the height direction Z, so that the corresponding parts of the plurality of drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13 in the same column in the plurality of memory subarray layers 1a share the same gate strip 2.

[0091] As shown in Figure 2b of the plurality of gate strips 2, each gate strip 2 in the same column is staggered with a corresponding gate strip 2 in the adjacent column in the row direction X. For example, each gate strip 2 in the first column of the gate strips 2 is staggered with each gate strip 2 in the second column in the column direction Y. Of course, as shown in Figure 2a each gate strip 2 in the same column can also be aligned with a corresponding gate strip 2 in the adjacent column in the row direction X. Among them, staggered arrangement can reduce the influence of the electric field between the corresponding two gate strips 2 in the adjacent column.

[0092] In the height direction Z, at least part of each gate strip 2 overlaps the projection of the corresponding channel semiconductor strip 12 in each layer of the memory subarray layer 1a in a projection plane. Among them, the projection plane is the plane defined by the height direction Z and the column direction Y, that is, the projection plane extends along the height direction Z and the column direction Y. As shown in Figures 2a-3As shown, for ease of description, the following definitions, each layer of the storage subarray layer 1a in a column of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 constitute a semiconductor strip structure; the adjacent two layers of the storage subarray layer 1a can adopt a common source design, that is, the adjacent two layers of the storage subarray layer 1a share the same source semiconductor layer (S), and the specific is as follows, therefore, the two semiconductor strip structures corresponding to the adjacent two layers of the storage subarray layer 1a share the same source semiconductor strip 13; of course, those skilled in the art can understand that the adjacent two layers of the storage subarray layer 1a can also adopt a non-common source design, that is, each layer of the storage subarray layer 1a has an independent source semiconductor layer, therefore, the two semiconductor strip structures 1b corresponding to the adjacent two layers of the storage subarray layer 1a have their own independent source semiconductor strips 13 respectively. The plurality of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in the same column in the plurality of layers of the storage subarray layer 1a constitute a column of semiconductor strip structures 1b, that is, a stack structure 1b. As shown in Figures 2a-3 , the column of semiconductor strip structures 1b includes two semiconductor strip structures, but those skilled in the art should know that the column of semiconductor strip structures 1b can include a plurality of stacked semiconductor strip structures, such as Figure 4 , as shown, Figure 4 , the column of semiconductor strip structures 1b includes three semiconductor strip structures.

[0093] In other words, those skilled in the art can understand that the storage array 1 includes a plurality of stacked structures 1b distributed along the row direction X, and each stacked structure 1b extends along the column direction Y respectively; and each stacked structure 1b includes the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 stacked along the height direction Z respectively, and each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 extends along the column direction Y respectively; and each stacked structure 1b is provided with a plurality of gate strips 2 distributed along the column direction Y on both sides respectively, and each gate strip 2 extends along the height direction Z.

[0094] The projection of a part of each semiconductor strip structure and a corresponding part of a gate strip 2 on the projection plane coincides, in particular, the projection of a part of the channel semiconductor strip 12 in each semiconductor strip structure and a part of a corresponding gate strip 2 on the projection plane coincides, therefore, the part of the gate strip 2, the corresponding part of the channel semiconductor strip 12, the part of the drain semiconductor strip 11 adjacent to the corresponding part of the channel semiconductor strip 12 and the part of the source semiconductor strip 13 constitute a storage cell. For example, as shown in Figures 2a-3As shown, portions of the gate strips 2 in the first column along the row direction X and the first row along the column direction Y coincide with projections on the projection plane of corresponding portions of the drain semiconductor strips 11, the channel semiconductor strips 12, and the source semiconductor strips 13 (a semiconductor strip structure of a D / CH / S structure) in the first column of the first storage sub-array layer 1a along the row direction X. Portions of the gate strips 2 in the first column and the first row, corresponding portions of the channel semiconductor strips 12 in the first column of the first storage sub-array layer 1a in the height direction Z, and portions of the drain semiconductor strips 11 and the source semiconductor strips 13 in the first storage sub-array layer 1a in the height direction Z that match the corresponding portions of the channel semiconductor strips 12 in the first column are used to form a storage unit.

[0095] It is understood by those skilled in the art that in a semiconductor device, a channel needs to be formed in the semiconductor region between the semiconductor drain region and the semiconductor source region; and a gate is provided on one side of the semiconductor region between the semiconductor drain region and the semiconductor source region to form a semiconductor device. Figures 2a-3 As shown, the portion of each gate strip 2 that overlaps with a channel semiconductor strip 12 in an adjacent stacked structure 1b on the above-mentioned projection plane is used as a gate, that is, the control gate of the corresponding memory cell; the portion of the channel semiconductor strip 12 that overlaps with the gate strip 2 on the above-mentioned projection plane is the corresponding portion of the channel semiconductor strip 12, which serves as a channel region (well region) for forming a channel therein; and the drain semiconductor strip 11 and the source semiconductor strip 13 adjacent to the channel semiconductor strip 12, respectively, have portions that are exactly arranged above or below the corresponding portions of the channel semiconductor strip 12, that is, they exactly match the corresponding portions of the channel semiconductor strip 12, serving as the semiconductor drain region and the semiconductor source region, with the corresponding portion of the channel semiconductor strip 12 sandwiched in between, cooperating with the portion of the gate strip 2 serving as the control gate, thereby forming a memory cell.

[0096] Therefore, if Figures 2a-3 As shown, the memory array 1 of the present application comprises a plurality of memory cells arranged in an array by means of drain semiconductor strips 11, channel semiconductor strips 12, source semiconductor strips 13, and gate strips 2. In particular, the memory array 1 of the present application comprises a plurality of memory sub-array layers 1a stacked sequentially along the height direction Z. Each memory sub-array layer 1a comprises a layer of drain semiconductor strips 11, channel semiconductor strips 12, source semiconductor strips 13, and a portion of the gate strips 2 matching the layer. Therefore, each layer of memory sub-array layer 1a comprises a layer of memory cells arranged in an array, and the plurality of memory sub-array layers 1a stacked along the height direction Z constitute a plurality of memory cells arranged in an array along the height direction Z.

[0097] In the present application, each of the drain region semiconductor strips 11 is a semiconductor strip of a first doping type, for example, an N-type doped semiconductor strip; in a specific embodiment, each of the drain region semiconductor strips 11 is a bit line (BL) of a memory block.

[0098] Each of the channel semiconductor strips 12 is a semiconductor strip of a second doping type, for example, a P-type doped semiconductor strip; in a specific embodiment, each of the channel semiconductor strips 12 is a well region of a memory cell.

[0099] Each of the source region semiconductor strips 13 is also a semiconductor strip of the first doping type, for example, an N-type doped semiconductor strip; in a specific embodiment, each of the source region semiconductor strips 13 is a source line (SL) of a memory block.

[0100] Of course, those skilled in the art can understand that in other types of memory devices, each of the drain region semiconductor strips and each of the source region semiconductor strips can also be a P-type doped semiconductor strip, and each of the channel semiconductor strips 12 is an N-type doped semiconductor strip. The present application does not limit this.

[0101] Please continue to refer to Figures 2a-3 In the height direction Z, two adjacent memory subarray layers 1a include, in sequence, a drain region semiconductor layer, a channel semiconductor layer, a source region semiconductor layer, a channel semiconductor layer, and a drain region semiconductor layer to share the same source region semiconductor layer. As shown in Figures 2a-3 In the height direction Z, a common source region semiconductor strip 13 is arranged between two channel semiconductor strips 12 in the same column, and a drain region semiconductor strip 11 is arranged on both sides of the two channel semiconductor strips 12. That is, in the height direction Z, the same column semiconductor strip structure 1b of the two adjacent memory subarray layers 1a includes, in sequence, a drain region semiconductor strip 11, a channel semiconductor strip 12, a source region semiconductor 13, a channel semiconductor strip 12, and a drain region semiconductor strip 11, thereby forming two semiconductor strip structures, and the two semiconductor strip structures share the same source region semiconductor strip 13. In this way, the storage density of the memory block 10 can be further improved while reducing costs and reducing processes.

[0102] Please refer to 4 together, the memory array 1 includes a plurality of memory subarray layers 1a stacked in sequence along the height direction Z, and each memory subarray layer 1a includes a drain region semiconductor layer, a channel semiconductor layer, and a source region semiconductor layer stacked along the height direction Z.

[0103] In each memory subarray layer 1a, the drain region semiconductor layer, the channel semiconductor layer, and the source region semiconductor layer respectively include a plurality of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 distributed at intervals along the row direction X.

[0104] Two adjacent storage subarray layers 1a include, in sequence, a drain region semiconductor layer, a channel semiconductor layer, a source region semiconductor layer, a channel semiconductor layer, and a drain region semiconductor layer, to share the same source region semiconductor layer.

[0105] An interlayer isolation layer is arranged between every two layers of storage subarray layers 1a to isolate the other two layers of storage subarray layers 1a from each other. For example, in the height direction Z, an interlayer isolation layer is arranged between the first layer of storage subarray layers 1a and the second layer of storage subarray layers 1a and the third layer of storage subarray layers 1a and the fourth layer of storage subarray layers 1a; another interlayer isolation layer is arranged between the third layer of storage subarray layers 1a and the fourth layer of storage subarray layers 1a and the fifth layer of storage subarray layers 1a and the sixth layer of storage subarray layers 1a, and so on. It can be understood that one of the interlayer isolation layers is arranged between the second layer of storage subarray layers 1a and the third layer of storage subarray layers 1a; the other interlayer isolation layer is arranged between the fourth layer of storage subarray layers 1a and the fifth layer of storage subarray layers 1a.

[0106] Specifically, as shown in Figure 4 In the height direction Z, an interlayer isolation strip 14a is arranged between every two semiconductor strip structures in the same column of semiconductor strip structures. Similarly, an interlayer isolation strip 14a is arranged between every two semiconductor strip structures in other columns of semiconductor strip structures. Those skilled in the art can understand that a plurality of interlayer isolation strips 14a in the same horizontal plane constitute an interlayer isolation layer to isolate the semiconductor strip structures in the other two layers of storage subarray layers 1a from each other.

[0107] In other words, in the present application, each stack structure 1b can include a plurality of groups of stacked substructures, each group of stacked substructures including, in sequence along the height direction Z, a drain region semiconductor strip 11, a channel semiconductor strip 12, a source region semiconductor strip 13, a channel semiconductor strip 12, and a drain region semiconductor strip 11, thereby sharing the same source region semiconductor strip 13. In the stack structure 1b, an interlayer isolation strip 14a is arranged between adjacent two groups of stacked substructures to isolate each other. That is, the drain region semiconductor strip 11, the channel semiconductor strip 12, the source region semiconductor strip 13, the channel semiconductor strip 12, and the drain region semiconductor strip 11 in the same column in the two adjacent storage subarray layers 1a constitute a stacked substructure, and therefore the adjacent two storage subarray layers 1a share a source region semiconductor strip 13.

[0108] Please continue to refer to Figure 4 or Figure 2a In the storage array 1, a plurality of isolation walls 3 are also distributed, and the plurality of isolation walls 3 are arranged in a matrix in the row direction X and the column direction Y. As shown in Figure 2aAs shown, multiple isolation walls 3 distributed along the column direction Y are provided on both sides of each column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13. Each isolation wall 3 extends adjacently along the height direction Z and the row direction X to separate at least portions of two adjacent columns of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13. In other words, multiple isolation walls 3 distributed along the column direction Y are provided on both sides of each stacked structure 1b to separate at least portions of two adjacent columns of stacked structures 1b. In specific embodiments, particularly during the manufacturing process of the memory block 10, the isolation walls 3 can further serve as support structures, supporting two adjacent columns of stacked structures 1b during and / or after manufacturing. Furthermore, support columns (not shown, but described in detail below) are provided on portions of both sides of each stacked structure 1b to support the two adjacent columns of stacked structures 1b during and / or after manufacturing of the memory array 1.

[0109] In the column direction Y, the area between two adjacent isolation walls 3 in the same column is used to form wordline holes 4. That is, any two adjacent isolation walls 3 in the same column, in conjunction with the two columns of semiconductor strip structures 1b (i.e., stacked structures 1b) on either side thereof, can define multiple areas for forming wordline holes 4. These areas are then processed to form corresponding wordline holes 4. Specifically, multiple columns of source semiconductor strips 11, channel semiconductor strips 12, and drain semiconductor strips 13 extending along the column direction Y are intersected by multiple rows of isolation walls 3 extending along the row direction X, thereby cooperating with the multiple isolation walls 3 to define multiple wordline holes 4. Each wordline hole 4 extends along the height direction Z.

[0110] Each word line hole 4 is used to be filled with a gate material to form a gate strip 2. That is, in the column direction Y, a gate strip 2 is filled between two adjacent isolation walls 3 in the same column.

[0111] Please also refer to Figure 5 ,in, Figure 5 FIG. 1 is a schematic diagram of a three-dimensional structure of a storage unit provided in one embodiment of the present application. Figure 5 As shown, the memory cell includes a drain region 11', a channel region 12', a source region 13', and a gate region 2'. The drain region 11', the channel region 12', and the source region 13' are stacked along a height direction Z. The channel region 12' is located between the drain region 11' and the source region 13'. The gate region 2' is located on one side of the drain region 11', the channel region 12', the source region 13', and the gate region 2' and extends along the height direction Z. The drain region 11', the channel region 12', and the source region 13' are each single crystal semiconductor.

[0112] Furthermore, in the height direction Z, the gate portion 2' and the channel portion 12' at least partially overlap in a projection plane. The projection plane is located on one side of the drain portion 11', the channel portion 12' and the source portion 13' and extends in the height direction Z and in the extension direction of the drain portion 11', the channel portion 12' and the source portion 13'.

[0113] As Figure 5 is readily understood by the skilled person, the drain portion 11' is part of one of the drain semiconductor strips 11, the channel portion 12' is part of one of the channel semiconductor strips 12, the source portion 13' is part of one of the source semiconductor strips 13 and the gate portion 2' is part of one of the gate strips 2. Thus, in the height direction Z, the plurality of memory subarray layers la comprises a plurality of memory cells. Figures 2a-4 Figures 2a-4 Figures 2a-4 Figures 2a-4

[0114] Furthermore, as Figure 5 is readily understood by the skilled person, between the gate portion 2' and the drain portion 11', the channel portion 12' and the source portion 13', a memory structure portion 5' is provided, wherein the memory structure portion 5' can be used to store electrical charges; the gate portion 2', the drain portion 11', the channel portion 12', the source portion 13' and the memory structure portion 5' sandwiched between the gate portion 2' and the channel portion 12' form a memory cell. The memory cell can represent a logic data 1 or a logic data 0 by the presence or absence of a stored electrical charge in the memory structure portion 5', thereby enabling the storage of data. The memory structure portion 5' can comprise a charge-trapping memory structure portion, a floating gate memory structure portion or another type of capacitive memory structure portion.

[0115] Thus, as Figures 2a-4 is readily understood by the skilled person, in the memory array 1, between the gate strips 2 and the drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13, a memory structure 5 is also provided, so that each memory cell can store electrical charges using its respective memory structure portion 5'.

[0116] Furthermore, it is noted that the dimensions of the drain portion 11', the channel portion 12', the source portion 13', the gate portion 2' and the memory structure portion 5' as Figure 5 shown in the figures are only for the purpose of illustration and do not represent the actual dimensions or proportions.

[0117] ​​​​Those skilled in the art will understand that, as described above, the portion of the gate strip 2 where the projections overlap with the adjacent channel semiconductor strip 12 on the above-mentioned projection plane is used as the control gate of the memory cell. Therefore, the gate portion 2' of the gate strip 2 is the portion where the projections overlap with the channel semiconductor 12 on the projection plane; the portion where the projections overlap with the gate strip 12 on the above-mentioned projection plane is the corresponding portion of the channel semiconductor strip 12, serving as a well region. Therefore, the channel portion 12' of the channel semiconductor strip 12 is the portion where the projections overlap with the gate strip 2 on the projection plane; the drain portion 11' and the source portion 13' of the drain semiconductor strip 11 and the source semiconductor strip 13 are the portions of the drain semiconductor strip 11 and the source semiconductor strip 13 that are arranged above or below the channel portion 12, serving as the semiconductor drain region and the semiconductor source region.

[0118] Similarly, the memory structure portion 5 ′ is the portion of the memory structure 5 located between the channel portion 12 ′ and the gate portion 2 ′.

[0119] Please continue reading Figures 2a to 4 Two adjacent columns of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 are distributed on both sides of a gate strip 2; therefore, these two adjacent columns of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 share the same gate strip 2. In other words, for a gate strip 2, in one memory sub-array layer 1a, its corresponding portions with the drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 on the left side constitute a memory cell, and its corresponding portions with the drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 on the right side constitute another memory cell. In other words, in the same row, two gate strips 2 are provided on the left and right sides of a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in a layer of storage sub-array layer 1a. Therefore, the portion of the gate strip 2 that cooperates with the left side thereof constitutes a storage unit, and the portion of the gate strip 2 that cooperates with the right side thereof constitutes another storage unit. That is to say, in the same row, a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in a layer of storage sub-array layer 1a is shared by the two gate strips 2 on its left and right sides.

[0120] For details, please refer to Figure 6 , Figure 6 The diagram shows a three-dimensional structure in which two memory cells share the same column of drain semiconductor strips, channel semiconductor strips and source semiconductor strips; Figure 6As shown, the source region portion 13', the channel portion 12', the drain region portion 11', the gate portion 2' on the left side of the source region portion 13', the channel portion 12' and the drain region portion 11', and the storage structure portion 5' between the source region portion 13' and the channel portion 12' form a storage unit; similarly, the drain region portion 11', the channel portion 12', the source region portion 13', the gate portion 2' on the right side of the source region portion 13', the channel portion 12' and the drain region portion 11', and the storage structure portion 5' between the source region portion 13' and the channel portion 12' form another storage unit, thus, the two storage units share the same drain region portion 11', the channel portion 12' and the source region portion 13'.

[0121] For the convenience of understanding, it can be considered that the source region portion 13', the channel portion 12', the drain region portion 11', the gate portion 2' on the left side of the source region portion 13', the channel portion 12' and the drain region portion 11', and the storage structure portion 5' between the source region portion 13' and the channel portion 12' form a storage unit (bit); the source region portion 13', the channel portion 12', the drain region portion 11', the gate portion 2' on the right side of the source region portion 13', the channel portion 12' and the drain region portion 11', and the storage structure portion 5' between the source region portion 13' and the channel portion 12' form another storage unit (bit).

[0122] Therefore, returning to continue referring to Figures 2a-4 It can be understood by those skilled in the art that the left and right sides of each word line hole 4 are first provided with the storage structure 5, and then the gate material is filled in the word line hole 4 to form the gate strip 2, that is, two columns of adjacent drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 share the same gate strip 2 with the storage structure 5.

[0123] In combination with Figures 2a-3 and Figures 5-6 In an embodiment, each of the above-mentioned drain region semiconductor strip 11, the channel semiconductor strip 12 and the source region semiconductor strip 13 is a standard strip structure. That is, the cross section of each position of each of the drain region semiconductor strip 11, the channel semiconductor strip 12 and the source region semiconductor strip 13 along the respective extension direction is a standard rectangular cross section. The storage unit corresponding to this embodiment can be specifically referred to Figure 5 and Figure 6 .

[0124] In another embodiment, in combination with Figure 4 and Figure 7 , Figure 7A perspective view of a storage unit according to another embodiment of the present application is provided. Each of the drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13 includes a body structure 15a and a plurality of protruding portions 15b. The body structure 15a extends along the column direction Y and has a strip shape. The plurality of protruding portions 15b are arranged in two columns on both sides of the body structure 15a, and each column includes a plurality of protruding portions 15b arranged at intervals. Each of the protruding portions 15b extends from the body structure 15a along the row direction X and away from the body structure 15a towards the corresponding gate strip 2 (word line hole 4). That is, in each of the drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13, the two columns of protruding portions 15b extend from the strip-shaped body structure 15a towards the gate strips 2 (word line holes 4) on both sides. Therefore, those skilled in the art can understand that the surface of the storage structure 5 and the gate strip 2 formed in the word line hole 4 near the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 is a curved concave surface.

[0125] As shown in Figure 7 , for the storage unit, the drain portion 11', the channel portion 12' and the source portion 13' have a body portion 15a' and a protruding portion 15b', and the storage structure portion 5' and the gate portion 2' have a concave surface corresponding to the protruding portion 15b' to wrap the surface of the protruding portion 15b away from the body structure 15a.

[0126] In the present application, by making each of the drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13 include protruding portions 15b protruding towards both sides, the surface area of each of the drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13 can be increased to increase the area of the corresponding region of the channel portion 12' and the gate portion 2' in each storage unit, thereby enhancing the performance of the storage block 10.

[0127] Specifically, the convex surface of the protruding portion 15b away from the body structure 15a can be an arc surface or other forms of convex surfaces, wherein the arc surface can include a cylindrical semicircular surface, and the protruding portions 15b of each of the drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13 form a cylindrical semicircular column. The gate strip 2 corresponding to the protruding portion 15b has a concave surface facing the surface of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13, and the concave surface is an arc surface corresponding to the convex surface of the protruding portion 15b to ensure that the gate strip 2 and the channel semiconductor strip 12 at the corresponding position match each other.

[0128] In a specific embodiment, as shown in Figure 4As shown, the storage structure 5 extends within the wordline hole 4 along the height direction Z and is disposed between the gate strip 2 and the adjacent drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13, thereby forming a plurality of storage cells with portions of the drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 at corresponding locations. In the present application, the storage structure 5 can be a charge trapping storage structure, a floating gate storage structure, or other types of capacitive dielectric structures.

[0129] See also Figure 8 , Figure 8 FIG. 1 is a schematic diagram of a three-dimensional structure of a storage unit provided in another embodiment of the present application; in this embodiment, the storage structure 5 adopts a charge trapping storage structure. Figure 8 As shown, the storage structure portion 5' of the memory cell includes a first dielectric portion 51, a charge storage portion 52, and a second dielectric portion 53. The first dielectric portion 51 is located between the charge storage portion 52 and the stacked drain region 11', channel region 12', and source region 13'. The charge storage portion 52 is located between the first dielectric portion 51 and the second dielectric portion 53. The second dielectric portion 53 is located between the charge storage portion 52 and the gate portion 2'. The charge storage portion 52 is used to store charge, enabling the memory cell to store data.

[0130] Therefore, reference Figure 8 , those skilled in the art will understand that, this application Figures 2a-4 The storage structure 5 in the storage array shown includes a first dielectric layer, a charge storage layer and a second dielectric layer. The first dielectric layer is located between the charge storage layer and the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13. The charge storage layer is located between the first dielectric layer and the second dielectric layer. The second dielectric layer is located between the charge storage layer and the gate strip 2.

[0131] The first dielectric layer (first dielectric portion 51) and the second dielectric layer (second dielectric portion 53) can be made of an insulating material, such as silicon oxide. The charge storage layer (charge storage portion 52) can be made of a storage material having charge-trapping properties. In particular, the charge storage layer is made of silicon nitride. Therefore, the first dielectric layer (first dielectric portion 51), the charge storage layer (charge storage portion 52), and the second dielectric layer (second dielectric portion 53) form an ONO storage structure. For more details, please refer to the following process method for manufacturing a storage block with a charge-trapping storage structure.

[0132] In another specific embodiment, see Figure 9 , Figure 9This is a partial schematic diagram of the three-dimensional structure of a memory block 10 provided in another embodiment of the present application. In this embodiment, the memory structure 5 is a floating gate memory structure, at least part of which extends within the wordline hole 4 along the height direction Z and is disposed between the gate strip 2 and the drain semiconductor strip 11, the channel semiconductor strip 12, and the source semiconductor strip 13.

[0133] Specific, combined Figures 9-10 , Figure 10 This is a schematic diagram of a three-dimensional structure of a memory cell provided in another embodiment of the present application; for each memory cell, the floating gate memory structure includes a plurality of floating gates 54 and an insulating medium wrapping the plurality of floating gates 54. Figure 9 As shown, it can be seen through the word line hole 4 that a plurality of floating gates 54 are spaced apart along the height direction Z. Each floating gate 54 is disposed on one side of the channel semiconductor strip 12 along the row direction X and corresponds to a corresponding portion of the channel semiconductor strip 12. Figure 10 As shown, the insulating medium wrapping the floating gate 54 includes a first insulating medium layer 56 between the channel semiconductor strip 12 and the floating gate 54 (see also the following Figure 38 The first insulating dielectric layer 85a shown in the figure, and the second insulating dielectric layer covering the other surfaces of the floating gate 54 (not shown, refer to the following Figure 38 In other words, an insulating dielectric is present between the floating gate 54 and corresponding portions of the channel semiconductor strip 12, between two adjacent floating gates 54, and between the floating gate 54 and the gate strip 2. The insulating dielectric wraps around any surface of the floating gate 54 to completely isolate the floating gate 54 from other structures.

[0134] The floating gate 54 is made of polysilicon. The insulating medium can be made of insulating materials such as silicon oxide. For details, please refer to the following process method for manufacturing a memory block with a floating gate memory structure.

[0135] exist Figure 8 and Figures 2a-4 In the memory cell of the charge trapping memory structure shown, the memory structure 5 uses a first dielectric layer (first dielectric portion 51 ), a charge storage layer (charge storage portion 52 ) and a second dielectric layer (second dielectric portion 53 ) to form an ONO memory structure.

[0136] Since the characteristic of the ONO storage structure is that the injected charge can be fixed near the injection point, the floating gate storage structure (such as Figures 9-11The characteristic of using polycrystalline silicon (poly) as the floating gate is that the injected charge can be evenly distributed across the entire floating gate 54. That is, in an ONO storage structure, charge can only move in the injection / removal direction, meaning the stored charge is fixed near the injection point and cannot move arbitrarily within the charge storage layer, particularly in the direction in which the charge storage layer extends. Therefore, for an ONO storage structure, the charge storage layer only needs to be provided with insulating dielectric on its front and back surfaces. The charge stored in each storage cell is fixed near the injection point of the charge storage portion 52 and will not move along the charge storage layer to the charge storage portion 52 of another storage cell within the same layer. In contrast, in a floating gate storage structure, charge can move not only in the injection / removal direction but also arbitrarily within the floating gate 54. Therefore, if the floating gate 54 is a continuous whole, the stored charge can move along the extension direction of the floating gate 54, thereby moving to the floating gate 54 of another storage cell. Therefore, for the floating gate storage structure, the floating gate 54 of each storage cell is independent, and each surface of each floating gate needs to be covered by an insulating medium to isolate each other to prevent the charge stored on the floating gate 54 in a storage cell from moving to the floating gate 54 in other storage cells.

[0137] That is to say, for Figure 8 and Figures 2a-4 In the memory cell and memory block of the charge trapping memory structure shown, the memory structure 5 can extend from top to bottom in the word line hole 4 , and a first dielectric layer and a second dielectric layer can be provided on both sides of the charge storage layer.

[0138] And in Figures 9-11 In the floating gate storage structure shown, the floating gate 54 of each storage cell is independent, and each surface of each floating gate 54 needs to be covered by an insulating medium to isolate each other to prevent the charge stored on the floating gate 54 in a storage cell from moving to the floating gate in other storage cells.

[0139] Those skilled in the art will appreciate that some portions of the insulating dielectric (e.g., the second insulating dielectric layer 85b mentioned above) in the insulating dielectric are interconnected, as long as the floating gate 54 of each memory cell is independent of each other and the surface of each floating gate 54 is wrapped by the insulating dielectric. Therefore, in the word line hole 4, the portion of the insulating dielectric (e.g., the second insulating dielectric layer 85b mentioned above) that wraps the floating gate 54 can extend substantially in the height direction, wrapping the floating gate 54 of each memory cell. Specifically, the memory block 10 having a floating gate memory structure can refer to the process method for manufacturing a memory block having a floating gate memory structure described below.

[0140] Furthermore, it is understood by those skilled in the art that the storage structure 5 can also be of other types of storage structures, such as ferroelectric or variable resistance, etc. other types of capacitive storage structures,

[0141] In an embodiment, referring to Figure 11 , Figure 11 A perspective view of the storage block 10 is provided in another embodiment of the present application. In Figure 11 only 3 layers of the storage subarray layers la are shown, which is only for illustration, and it is understood by those skilled in the art that the storage block 10 includes multiple layers of the storage subarray layers la, and each two layers of the storage subarray layers la are separated from each other by an interlayer isolation layer (formed by multiple interlayer isolation strips 14a). The storage block 10 also includes multiple word lines (WL) and multiple word line connection lines 7.

[0142] As mentioned above, the portion of the gate strip 2 that is projected to coincide with the channel semiconductor strip 12 in the adjacent stack structure lb in the projection plane is used as the control gate of the corresponding memory cell; therefore, each gate strip 2 is used to form the control gates (CG) of multiple memory cells. It is known that the control gates of a row of memory cells need to be connected to a corresponding word line, and the voltage is applied to the control gates of the row of memory cells through the word line, so as to control the memory cells to perform various memory operations.

[0143] In the present application, as shown in Figure 11 , multiple word lines are arranged above the multiple storage subarray layers la and are spaced apart in the column direction Y, and each word line extends in the row direction X. Each word line is connected to multiple word line connection lines 7. The multiple word line connection lines 7 connected to the same word line respectively extend in the height direction Z and respectively extend to the gate strips 2 in the multiple word line holes 4 in the same row, so as to be connected to the gate strips 2 in the corresponding word line holes 4, thereby realizing the connection of the current word line and the control gates of the multiple memory cells in the same row in the multiple storage subarray layers la. It is understood that the multiple word line holes 4 and the multiple word line connection lines 7 are arranged one-to-one.

[0144] Specifically, the word line in the same row can be a single word line connected to the gate strips 2 in each word line hole 4 in the same row. Of course, the word line in the same row can also include multiple types of word lines; the gate strips 2 in the multiple word line holes 4 in the same row can be respectively connected to different types of word lines in the corresponding row. In a specific embodiment, as shown in Figure 11As shown, the multiple gate strips 2 of the same row are respectively used to connect two corresponding word lines, i.e. each row of word lines includes two types of odd number word lines 8a and even number word lines 8b. It should be noted that in this application, one odd number word line 8a and one even number word line 8b connected with the multiple gate strips 2 of the same row are defined as one row of word lines, which corresponds to one row of gate strips 2.

[0145] Specifically, in the multi-layer storage subarray layer 1a, a part of the storage units of the same row are respectively connected to the corresponding odd number word line 8a of the same row through the odd number word line hole 4 of the same row; the remaining part of the storage units of the same row in the multi-layer storage subarray layer 1a are respectively connected to the corresponding even number word line 8b of the same row through the even number word line hole 4 of the same row. For example, the first part of the storage units of the first row are respectively connected to the odd number word line 8a of the first row through the first word line hole 4, the third word line hole 4, the fifth word line hole 4, …, the n-1th word line hole 4 of the first row; the second part of the storage units of the first row are respectively connected to the even number word line 8b of the first row through the second word line hole 4, the fourth word line hole 4, the sixth word line hole 4, …, the n-th word line hole 4 of the first row. Wherein, n is an even number greater than 1. That is to say, the odd number word line 8a of the same row of word lines connects the multiple storage units (the first part of the storage units) in the multi-layer storage subarray layer 1a corresponding to the odd number word line hole 4 of the same row; the even number word line 8b of the same row of word lines connects the multiple storage units (the second part of the storage units) in the multi-layer storage subarray layer 1a corresponding to the even number word line hole 4 of the same row.

[0146] As described above, since one side of each column of drain region semiconductor strip 11, channel semiconductor strip 12, source region semiconductor strip 13 is distributed with odd number word line hole 4, and the other side is distributed with even number word line hole 4, therefore, each drain region semiconductor strip 11, channel semiconductor strip 12, source region semiconductor strip 13 in each layer of storage subarray layer 1a can be used to form a storage unit (i.e. the first storage unit) in cooperation with the odd number gate strip 2 in the odd number word line hole 4 on one side and the storage structure 5 arranged therebetween; each drain region semiconductor strip 11, channel semiconductor strip 12, source region semiconductor strip 13 in each layer of storage subarray layer 1a can be used to form another storage unit (i.e. the second storage unit) in cooperation with the even number gate strip 2 in the even number word line hole 4 on the other side and the storage structure 5 arranged therebetween.

[0147] In other words, the gate strip 2 filled in each word line hole 4 can be used to form a storage unit (bit) in cooperation with the left drain region semiconductor strip 11, channel semiconductor strip 12, source region semiconductor strip 13 and storage structure 5 in each layer of storage subarray layer 1a; or can be used to form another storage unit (bit) in cooperation with the right drain region semiconductor strip 11, channel semiconductor strip 12, source region semiconductor strip 13 and storage structure 5 in each layer of storage subarray layer 1a.

[0148] Thus, for odd digit line holes 4, each of the drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 in each layer of the storage subarray layer la cooperate with the gate strips 2 in the corresponding odd digit line hole 4 to form a first storage cell. Specifically, in each layer of the storage subarray layer la, each column of the drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13, for example, the first column of drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 from left to right, the digit line hole 4 on the left side of the column cooperates with the gate strips 2 in the odd digit line hole 4 on the left side to form a first storage cell. The digit line hole 4 on the right side of the second column from left to right cooperates with the gate strips 2 in the odd digit line hole 4 on the left side to form a first storage cell.

[0149] Similarly, for even digit line holes 4, each of the drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 in each layer of the storage subarray layer la cooperate with the gate strips 2 in the corresponding even digit line hole 4 to form a second storage cell. Specifically, in each layer of the storage subarray layer la, each column of the drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13, for example, the first column of drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 from left to right, the digit line hole 4 on the right side of the column cooperates with the gate strips 2 in the even digit line hole 4 on the right side to form a second storage cell. The digit line hole 4 on the left side of the second column from left to right is an even digit line hole. The drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 in the column cooperate with the gate strips 2 in the even digit line hole 4 on the left side to form a second storage cell.

[0150] Therefore, in the present application, the gate strips 2 in the memory array 1 are connected to corresponding word lines, and the gate strips 2 in the same row are connected to the corresponding word lines in the row. Specifically, in the same row, the gate strips 2 disposed within the odd word line holes 4 are connected to the odd word lines 8a in the row; and the gate strips 2 disposed within the even word line holes 4 are connected to the even word lines 8b in the row. In other words, all first memory cells in the same row of the multi-layer memory sub-array layer 1a are connected to the odd word lines 8a of the corresponding row via the odd-numbered gate strips 2 in the odd word line holes 4 in the same row; and all second memory cells in the same row of the multi-layer memory sub-array layer 1a are connected to the even word lines 8b of the corresponding row via the even-numbered gate strips 2 in the even word line holes 4 in the same row.

[0151] Of course, in other embodiments, three, four, or five adjacent word line holes 4 on the same row may be connected as a group, and each row of word lines may include three, four, or five different types of word lines, and the gate bars 2 in each word line hole 4 in each group may be connected to different types of word lines.

[0152] In addition, if Figure 11 As shown, in this application, the number of word line rows can be defined to be consistent with the number of word line holes 4. Figure 11 As shown, although the gate bars 2 in the wordline holes 4 in the same row are connected to a corresponding odd wordline 8a and a corresponding even wordline 8b, an odd wordline 8a and an even wordline 8b corresponding to the wordline holes 4 in the same row can be defined as a row of wordlines, corresponding to a row of gate bars 2 (wordline holes 4). That is, each row of wordlines includes two types of wordlines, one odd wordline 8a and one even wordline 8b, and the number of wordline rows is consistent with the number of wordline holes 4. In addition, it should be noted that, if Figure 11 As shown, in each row, the left and right sides of the non-head and non-end wordline holes 4 correspond to a column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13. However, from left to right, for the head wordline hole 4, only the right side corresponds to a column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13; for the end wordline hole 4, only the left side corresponds to a column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13. Therefore, those skilled in the art will understand that in each row, the head wordline hole 4 and the end wordline hole 4 functionally constitute a complete wordline hole.

[0153] like Figure 11 As shown, in this embodiment, a plurality of word lines 8 a or 8 b may be provided on the multi-layer memory sub-array layer 1 a in the memory block 10 , and connected to the corresponding word line holes 4 through word line connection lines 7 .

[0154] Of course, it is understood by those skilled in the art that a plurality of word lines 8a or 8b can also be provided on another stacked chip, which can be stacked and electrically connected with the chip where the memory block 10 is located in a stacked manner, for example, the stacked chip and the chip where the memory block 10 is located can be stacked in a hybrid bonding manner. The word line connection line 7 in the memory block 10 is away from one end of the gate strip 2 as a word line connection end of the memory block 10, which is used to connect with the stacked chip stacked together with the memory block 10 in the height direction Z.

[0155] In addition, as Figure 12 shown, in another embodiment, the memory block 10 can further include a plurality of word line lead-out lines 6a or 6b, each word line 8a or 8b further corresponds to one word line lead-out line 6a or 6b, respectively, the word line lead-out line 6a or 6b extends in the height direction Z and is away from the gate strip 2 relative to the word line connection line 7, and the word line lead-out line 6a or 6b is away from one end of the word line 8a or 8b as a word line connection end, which is used to connect with the stacked chip stacked together with the memory block 10 in the height direction Z, that is, the word line is arranged on the memory array chip, and the control circuit is arranged on another chip. Of course, it is understood by those skilled in the art that each word line 8a or 8b can also be connected with the control circuit on the chip where the memory block 10 is located through the corresponding word line lead-out line 6a or 6b, that is, the relevant lines, memory array and control circuit are arranged on the same chip.

[0156] Please continue to refer to Figure 12 , Figure 12 the circuit connection diagram of part of the storage units of the memory block shown in an embodiment of the present application. As Figure 12 shown, for each column of drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 of the multi-layer storage sub-array layer 1a, at the end thereof, a plurality of drain region semiconductor strips 11 of the same column are respectively led out through different bit line connection lines 11a, as Figure 12 shown, the bit line connection line 11a extends in the height direction Z. For example, the drain region semiconductor strip 11, the channel semiconductor strip 12 and the source region semiconductor strip 13 of the first column, the drain region semiconductor strip 11 in the first layer storage sub-array layer 1a is led out at the end thereof through a bit line connection line 11a, wherein the end of the bit line connection line 11a away from the drain region semiconductor strip 11 can be used as a bit line connection end; the drain region semiconductor strip 11 in the second layer storage sub-array layer 1a is led out at the end thereof through another bit line connection line 11a, and the end of the other bit line connection line 11a away from the corresponding drain region semiconductor strip 11 is used as another bit line connection end; and so on. Therefore, each drain region semiconductor strip 11 can be used as a bit line to receive a bit line voltage through the bit line connection end.

[0157] Those skilled in the art will appreciate that the memory block 10 can also be connected to other stacked chips stacked together in the height direction Z via the bit line connection terminals, and the other stacked chips can be used to provide bit line voltages to the drain semiconductor strips 11 serving as bit lines in the memory block 10 via the bit line connection terminals. Of course, the bit line connection terminals can also be used to connect to the control circuit on the chip where the memory block 10 is located, that is, the relevant circuits, memory array 1, and control circuit can be arranged on the same chip.

[0158] Similarly, for each column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 of the multi-layer storage sub-array layer 1a, at their ends, multiple source semiconductor strips 13 in the same column are respectively led out through corresponding source connection lines 13a, and the source connection lines 13a extend in the height direction Z.

[0159] like Figure 12 As shown, all source connection lines 13 a in the memory block 10 can be connected to the same common source line 13 b , and a source voltage is applied to the source semiconductor strips 13 in the memory block 10 through the common source line 13 b and the source connection line 13 a .

[0160] Of course, those skilled in the art will appreciate that, in other embodiments, the memory block 10 may also include multiple common source lines 13b, such as a preset number of common source lines 13b. The source semiconductor strips 13 in the multi-layer memory sub-array layer 1a may be connected to different common source lines 13b via corresponding source connection lines 13a according to a preset rule. Furthermore, similar to the bit line connection lines 11a corresponding to the drain semiconductor strips 11, the end of the source connection line 13a corresponding to each source semiconductor strip 13, away from the source semiconductor strip 13, may serve as a source connection terminal to receive a source voltage.

[0161] Please continue reading Figure 12 The memory block 10 may further include a common source lead line 13c, which is connected to the common source line 13b, wherein the common source line 13b is connected to all source connection lines 13a in the memory block 10. The common source lead line 13c is away from the memory array 1 in the memory block 10 and extends in the height direction Z, wherein one end of the common source lead line 13c away from the common source line 13b can serve as a common source connection terminal for connecting to other stacked chips of the memory block 10 stacked together in the height direction Z. Of course, the common source connection terminal can also be used to connect to the control circuit on the chip where the memory block 10 is located, that is, the related lines, memory array and control circuit are arranged on the same chip.

[0162] Of course, those skilled in the art will appreciate that the common source line 13b may also be provided in other stacked chips stacked together with the memory block 10 in the height direction Z. In other words, the end of the source connection line 13a away from the corresponding source semiconductor strip 13 may be used as a source connection end for connection to other stacked chips stacked together with the memory block 10 in the height direction Z, thereby providing the common source line 13b in other stacked chips.

[0163] Similarly, for each column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 of the multi-layer storage sub-array layer 1a, at their ends, multiple channel semiconductor strips 12 in the same column are respectively led out through corresponding well region connection lines 12a, and the well region connection lines 12a extend in the height direction Z.

[0164] like Figure 12 As shown, all the well connection lines 12a in the memory block 10 are respectively connected to the same common well line 12b. Therefore, a well voltage can be uniformly applied to all the channel semiconductor strips 12 in the memory block 10 through the common well line 12b.

[0165] Of course, those skilled in the art will appreciate that the well region connection line 12a corresponding to each channel semiconductor strip 12 in the memory block 10 can be connected to a plurality of independent well region voltage lines 12b, respectively, so as to apply a well region voltage to each channel semiconductor strip 12. For example, similar to the above, the end of the well region connection line 12a corresponding to each channel semiconductor strip 12, which is away from the channel semiconductor strip 12, serves as a well region connection terminal for receiving a separate well region voltage.

[0166] Please continue reading Figure 11The connection lines 12a of all the well regions in the memory block 10 are connected to the same common well region line 12b, respectively. The memory block 10 can further comprise a common well region lead-out line 12c connected to the common well region line 12b, which is away from the memory array 1 in the memory block 10 and extends in the height direction Z, wherein one end of the common well region lead-out line 12c away from the common well region line 12b can serve as a common well region connection end for other stacked chips stacked together in the height direction Z of the memory block 10. Of course, the common well region connection end can also be used for connection with the control circuit on the chip where the memory block 10 is located, i.e., the relevant circuit, memory array 1 and control circuit are arranged on the same chip. That is, all the channel semiconductor strips 12 in the memory block 10 can be connected together through the common well region line 12b to receive the same well region voltage. In this embodiment, the channel semiconductor strips 12 are p-type semiconductor strips forming p-wells, and all the channel semiconductor strips 12 in the memory block 10 are connected together through the common well region line 12b to receive the same well region voltage through the common well region line 12b. In addition, in this embodiment, the memory block 10 performs signal reading through the same common source line 13b.

[0167] Of course, those skilled in the art can understand that the common well region line 12b can also be arranged in other stacked chips stacked together in the height direction Z of the memory block 10. That is, the common well region line 12b can be arranged in other stacked chips by using one end of the well region connection line 12a away from the corresponding channel semiconductor strip 12 as a well region connection end for connection with other stacked chips stacked together in the height direction Z of the memory block 10.

[0168] In addition, it should be noted that, as Figures 13 to 16 and 13As shown, in the present application, various conducting lines, such as word lines 8a or 8b, word line connecting lines 7, word line leading-out lines 6a or 6b, common source lines 13b, common well region lines 12b, and the like, are all arranged on the same side of the memory array 1 in the memory block 10, i.e., above the memory array 1, thus ensuring that the drain region semiconductor strips 11, the channel semiconductor strips 12, and the source region semiconductor strips 13 in the memory array 1 can be formed as single-crystal semiconductor strips by epitaxial growth, while deposition can only form polycrystalline semiconductor strips. Compared with polycrystalline semiconductor strips formed by deposition, the drain region semiconductor strips 11, the channel semiconductor strips 12, and the source region semiconductor strips 13 formed by epitaxial growth in the present application can obtain superior device performance and greatly improve the performance of the related memory device. Specifically, a memory cell using single-crystal semiconductor (single-crystal drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13) has more interfaces than a memory cell using polycrystalline semiconductor. When electrons pass through polycrystalline semiconductor, they will move along the interfaces, i.e., the distance of electron movement increases, and the current will decrease significantly. According to actual experience, the current of a memory cell using polycrystalline semiconductor is only 1 / 10 of that of a memory cell using single-crystal semiconductor. Therefore, the memory block 10 of the present application uses a memory cell using single-crystal semiconductor, which can greatly improve the performance of the memory device. In addition, the small current of a memory cell using polycrystalline semiconductor will affect the read window between read and write operations (PGM) and erase operations (ERS) of the memory cell, which greatly affects the reliability of the memory device, especially the reliability of the NOR memory device. In addition, for a NOR memory device, if hot carrier injection (HCI) is used for read and write operations, single-crystal semiconductor must be used to complete the operations.

[0169] In addition, since the various conducting lines in the present application are arranged on the same side of the memory array 1 in the memory block 10, it is more convenient to perform three-dimensional bonding and stacking with stacked chips, thus improving the performance of the related memory device, separating the chips, optimizing the process, and reducing the manufacturing time.

[0170] As can be understood by those skilled in the art, in some embodiments, in order to obtain better performance of the memory block 10, the outermost memory cells can generally be dummy cells and do not participate in actual storage. For example, the memory cells contained in the lowermost memory subarray layer la can be dummy cells. In some embodiments, the memory block 10 is provided with a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 on the left and right sides, respectively. The memory cells formed by the left column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13, the gate strips 2 in the word line holes 4 on the right side of the left column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13, and the memory structure 5 between the left column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 and the gate strips 2 in the word line holes 4 on the right side of the left column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 are dummy cells and do not participate in actual storage.

[0171] Therefore, in the present application, unless otherwise specified, the memory subarray layer la referred to throughout the text does not include the lowermost memory subarray layer referred to by the dummy cells. The drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 also do not include the left and right columns of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 referred to by the dummy cells.

[0172] Therefore, as described above, in a row, from left to right, for the word line hole 4 at the beginning, only the right side corresponds to a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13. For the word line hole 4 at the end, only the left side corresponds to a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13. Therefore, as can be understood by those skilled in the art, in a row, the word line hole 4 at the beginning and the word line hole 4 at the end functionally constitute a complete word line hole.

[0173] Please refer to the combination of Figure 13 , Figure 11 for Figure 14 the circuit schematic diagram of the memory block 10 shown in FIG. 1; Figure 11 for Figure 15 the planar schematic diagram of the memory block 10 shown in FIG. 1; Figure 16 for the memory cells corresponding to each layer of bit lines; Figure 13 for the three-dimensional distribution of the word lines and bit lines.

[0174] As Figure 13 shown, the memory block 10 includes a plurality of memory subarray layers la (Figures 14-16 (Six layers are shown). The drain semiconductor strips 11 in the multi-layer storage sub-array layer 1a serve as bit lines, such as BL-1-1, BL-1-2, BL-1-3, BL-1-4, BL-1-5, and BL-1-6. Multiple columns of drain semiconductor strips 11 in each storage sub-array layer 1a constitute multiple columns of bit lines, such as BL-1-1, BL-2-1, and so on. The source semiconductors 13 in the multi-layer storage sub-array layers 1a in the storage block 10 are connected to a common source line 13b. The well semiconductors 12 in the multi-layer storage sub-array layers 1a in the storage block 10 are connected to a common well line 12b. Furthermore, a gate strip 2 in the same wordline hole 4, along with the drain semiconductor layers 11, channel semiconductor layers 12, and source semiconductor layers 13 on the left and right sides, respectively, form two columns of storage cells (as shown in the two middle columns of storage cells). The gate strips 2 corresponding to the odd-numbered holes 4 are connected to the odd word lines WL-a, for example, the first and fourth columns of memory cells, which correspond to the first and third word line holes; the gate strips 2 corresponding to the even-numbered holes 4 are connected to the even word lines WL-b, for example, the second and third columns of memory cells, which correspond to the second word line hole.

[0175] like Figure 16 As shown, in each memory sub-array layer 1a, drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 extend along the column direction. The semiconductor strip structures 1b in the same column form one memory cell (bit) with the gate strip 2 in the left wordline hole 4, and another memory cell (bit) with the gate strip 2 in the right wordline hole 4. The first row of odd wordline holes 4, such as hole-1, hole-3, ..., connect to the first row of odd wordline WL-1-a, and the first row of even wordline holes, such as hole-2, hole-4, ..., connect to the first row of even wordline WL-1-b.

[0176] like Figure 5 As shown, it is assumed that the memory block 10 includes a P-layer memory sub-array layer 1a, M rows of word lines, and N columns of bit lines. Each memory sub-array layer 1a then includes N columns of drain semiconductor strips 11 serving as bit lines, such as BL-1-1, ..., BL-N-1. For the P-layer memory sub-array layer 1a, such as BL-1-1, ..., BL-NP, the memory block 10 includes N*P drain semiconductor strips 11 serving as bit lines. The M rows of word lines, such as WL-1-a / b, ..., WL-Ma / b, respectively intersect with the projections of the N columns of bit lines on the projection plane defined by the row direction X and the column direction Y, forming a plurality of memory cells. P, M, and N are all natural numbers greater than 0.

[0177] According to the above conditions, one skilled in the art can understand that, in the same row direction X, the memory block 10 includes (N+1) word line holes 4, for example, WL-hole-1-1,..., WL-hole-1-(N+1) as shown; in the same column direction Y, the memory block 10 includes M word line holes 4, for example, WL-hole-1-(N+1),..., WL-hole-M-(N+1) as shown. One side of each column of drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 corresponds to M word line holes 4. Each row of word lines (one odd number word line 8a and one even number word line 8b) corresponds to (N+1) word line holes 4. As above, in the same row, the first and last word line holes 4 in each memory subarray layer la only correspond to one memory cell, and therefore, they can be functionally regarded as a complete word line hole 4; and the other word line holes 4 in each memory subarray layer la correspond to two memory cells (one on the left and one on the right). Therefore, each row of word lines corresponds to N*2*P memory cells. When N is even, one odd number word line 8a corresponds to (N / 2+1) word line holes, which includes the first and last word line holes 4 in the same row, that is, the odd number word line 8a also corresponds to N / 2 complete word line holes 4, corresponding to (N / 2)*P*2 memory cells; one even number word line 8b corresponds to N / 2 word line holes 4, corresponding to (N / 2)*P*2 memory cells. That is, the number of memory cells corresponding to the odd number word line 8a and the even number word line 8b is the same.

[0178] In a specific embodiment, assuming that the memory block 10 specifically includes 8 memory subarray layers la and 1024 rows of word lines, each row of word lines includes one odd number word line 8a and one even number word line 8b, and each memory subarray layer la includes 2048 columns of drain region semiconductor strips 11 as bit lines, the memory block 10 includes 2048*8 drain region semiconductor strips 11 as bit lines.

[0179] In the same row direction X, the memory block 10 includes (2048+1=2049) word line holes 4; in the same column direction Y, the memory block 10 includes 1024 word line holes 4. Each drain semiconductor strip 11 as a bit line corresponds to 1024 word line holes 4, and corresponds to 1024*2 memory cells. Each row of word lines corresponds to (2048+1=2049) word line holes 4, and the first and last word line holes 4 in each memory subarray layer la correspond to only one memory cell, thereby functionally forming a complete word line hole 4, which corresponds to 2048*2*8=32K memory cells. N is an even number 2048, so one odd number line 8a corresponds to (2048 / 2+1=1025) word line holes, which includes the first and last word line holes 4 in the same row, that is, the odd number line 8a also corresponds to 1024 complete word line holes 4, and corresponds to (2048 / 2)*8*2 memory cells; one even number line 8b corresponds to 2048 / 2 word line holes 4, and corresponds to (2048 / 2)*8*2 memory cells.

[0180] The memory block 10 can define 1024*2 memory cells corresponding to 1 / 8 word lines as a memory page (128 complete word line holes 4). The memory block 10 can define 32K memory cells corresponding to one row of word lines as a sector, and it can be understood that one sector corresponds to 2 word lines, (2048+1) word line holes 4 (2048 complete word line holes 4), and 2048*2*8 memory cells bit.

[0181] The memory block 10 can define 16 sectors to form a sub-memory block 10 (eblk), including 0.5M memory cells (2048*2*8*16=1024*2*2*8*16=1024*1024*0.5). In specific embodiments, the memory block 10 includes 64 sub-memory blocks 10, including 32M memory cells. Each memory block 10 shares one common source line 13b and one common well region line 12b.

[0182] The storage block 10 provided by the embodiment includes a storage array 1, and the storage array 1 includes a plurality of storage units arranged in a three-dimensional array. The storage array 1 includes a plurality of storage sub-array layers 1a stacked in sequence along a height direction Z, and each storage sub-array layer 1a includes a drain region semiconductor layer, a channel semiconductor layer and a source region semiconductor layer stacked along the height direction Z. The drain region semiconductor layer, the channel semiconductor layer and the source region semiconductor layer in each storage sub-array layer 1a respectively include a plurality of drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13 arranged along a row direction X, and each of the drain region semiconductor strips 11, the channel semiconductor strips 12 and the source region semiconductor strips 13 extends along a column direction Y. A plurality of gate strips 2 arranged along the column direction Y are arranged on both sides of each column of the drain region semiconductor strips 11, the channel semiconductor strips 12 and the source region semiconductor strips 13, and each gate strip 2 extends along the height direction Z. In the height direction Z, at least part of each gate strip 2 overlaps with a projection of a corresponding part of each channel semiconductor strip 12 in each storage sub-array layer 1a on a projection plane extending along the height direction Z and the column direction Y, and the part of the gate strip 2, the corresponding part of the channel semiconductor strip 12, a part of the drain region semiconductor strip 11 adjacent to the corresponding part of the channel semiconductor strip 12 and a part of the source region semiconductor strip 13 are used to form a storage unit. Compared with a two-dimensional storage array, the storage density of the storage block 10 is higher.

[0183] As described above, the storage block 10 of the present application includes two types of storage units. In an embodiment, in combination with Figure 7 、 Figure 8 、 Figure 10 and Figure 5 , a storage unit is provided, which includes a drain region part 11', a channel part 12', a source region part 13' and a gate part 2'. The drain region part 11', the channel part 12' and the source region part 13' are stacked along a height direction Z, the gate part 2' is located on one side of the drain region part 11', the channel part 12' and the source region part 13' and extends along the height direction Z. In the height direction Z, a projection of the gate part 2' and a projection of the channel part 12' on a projection plane extending along the height direction Z at least partially overlap, and a storage structure part 5' is arranged between the gate part 2' and the drain region part 11', the channel part 12' and the source region part 13'.

[0184] The drain region part 11', the channel part 12', the source region part 13' and the storage structure part 5' can refer to the specific structure, function and stacking mode of the drain region semiconductor layer, the channel semiconductor layer, the source region semiconductor layer and the storage structure 5 in each of the storage subarray layers 1a in the above embodiment, and can achieve the same or similar technical effects. Details are not described herein again.

[0185] When the drain region part 11', the channel part 12', the source region part 13' are in a strip structure, and the storage structure part 5' is a charge trapping storage structure part, the specific structure of the storage unit can refer to Figure 5 , and other structures of the storage unit can refer to the related descriptions of Figure 7 . When the drain region part 11', the channel part 12', the source region part 13' all include the body structure 15a and the plurality of protruding parts 15b, and the storage structure part 5' is a charge trapping storage structure part, the specific structure of the storage unit can refer to Figure 7 , and other structures of the storage unit can refer to the related descriptions of Figure 10 . When the storage structure part 5' is a floating gate storage structure part, the specific structure of the storage unit can refer to Figure 11 and Figure 10 , and other structures of the storage unit can refer to the related descriptions of Figure 11 and Figure 17 .

[0186] In another embodiment, referring to Figure 17 , Figures 9-11 is a flowchart of a process method of a storage block 10 provided in another embodiment of the present application. In the embodiment, the storage structure of the storage block 10 is a floating gate storage structure. Another process method of a storage block is provided, which can be used to prepare the storage block 10 with higher storage density corresponding to the above Figure 18 . The method specifically includes:

[0187] Step S31: providing a semiconductor substrate.

[0188] Referring to Figure 18 , Figure 18 is a side view of a semiconductor substrate provided in an embodiment of the present application. The semiconductor substrate includes a substrate 81, a first single-crystal sacrificial semiconductor layer 82 disposed on the substrate 81, two layers of storage subarray layers 1a and a second single-crystal sacrificial semiconductor layer 14 formed in sequence and alternately on the first single-crystal sacrificial semiconductor layer 82, until the uppermost two layers of storage subarray layers 1a are formed.

[0189] The substrate 81 can be a single crystal substrate 81, and specifically can be a single crystal silicon material. The first single crystal sacrificial semiconductor layer 82 and / or the second single crystal sacrificial semiconductor layer 14 can be silicon germanium (SiGe). The plurality of memory subarray layers 1a are sequentially stacked along a height direction Z perpendicular to the substrate 81. Each memory subarray layer 1a includes a drain semiconductor layer 11c, a channel semiconductor layer 12c, and a source semiconductor layer 13c sequentially stacked along the height direction Z. Moreover, along the height direction Z, two adjacent memory subarray layers 1a can share a source region, and include a drain semiconductor layer 11c, a channel semiconductor layer 12c, a source semiconductor layer 13c, a channel semiconductor layer 12c, and a drain semiconductor layer 11c sequentially stacked to share the same source semiconductor layer 13c. Therefore, for the memory subarray layers 1a sharing a source region, a second single crystal sacrificial semiconductor layer 14 is provided on every two memory subarray layers 1a to isolate the two memory subarray layers 1a from each other. The second single crystal sacrificial semiconductor layer 14 can be a silicon germanium (SiGe) semiconductor material.

[0190] It should be noted that, Figure 18 The structure shown only exemplarily shows part of the structure of the semiconductor substrate, and those skilled in the art can understand that, Figure 19 The first single crystal sacrificial semiconductor layer 82 and the second single crystal sacrificial semiconductor layer 14 shown are actually provided between two memory subarray layers 1a sharing a source semiconductor layer 13c. For the sake of simplicity of the drawing, only one memory subarray layer 1a is shown in the drawing, which is only illustrative.

[0191] In a specific embodiment, the step S31 can specifically include:

[0192] Step S311a: providing a substrate 81.

[0193] The substrate 81 can be a single crystal substrate 81, and specifically can be a single crystal silicon material.

[0194] Step S312a: sequentially forming a plurality of memory subarray layers 1a on the substrate 81 along a height direction Z.

[0195] The step S312a specifically includes:

[0196] Step a: forming a first single crystal sacrificial semiconductor layer 82 on the substrate 81 by epitaxial growth.

[0197] The first single crystal sacrificial semiconductor layer 82 can be silicon germanium (SiGe).

[0198] Step b: Two memory sub-array layers 1a and a second single-crystalline sacrificial semiconductor layer 14 are alternately formed on the first single-crystalline sacrificial semiconductor layer 82 by epitaxial growth. The two memory sub-array layers 1a are then formed, and the second single-crystalline sacrificial semiconductor layer 14 and the two memory sub-array layers 1a with a common source are repeatedly stacked until the topmost two memory sub-array layers with a common source are formed.

[0199] The material of the second single crystal sacrificial semiconductor layer 14 is the same as that of the first single crystal sacrificial semiconductor layer 82 , and may also be silicon germanium (SiGe).

[0200] Those skilled in the art will appreciate that the purpose of first providing the first single-crystal sacrificial semiconductor layer 82 on the substrate 81 is to prevent the multiple memory sub-array layers 1a thereon from directly contacting the substrate 81 and causing leakage. However, as described above, the device performance of the bottommost memory sub-array layer 1a in the memory block of the present application is poor. Therefore, the memory cells in the bottommost memory sub-array layer 1a generally serve as dummy memory cells and do not participate in actual memory operations. Therefore, those skilled in the art will appreciate that the substrate 81 may also be provided without providing the first single-crystal sacrificial semiconductor layer 82. Instead, a single memory sub-array layer 1a or two memory sub-array layers 1a with a common source may be formed directly on the substrate 81 as dummy memory cells. A second single-crystal sacrificial semiconductor layer 82 and two memory sub-array layers 1a with a common source may then be formed alternately thereon by epitaxial growth until the topmost memory sub-array layer 1a with a common source is formed. That is, the bottommost memory sub-array layer 1a or the two memory sub-array layers 1a with a common source as a virtual memory cell does not participate in the actual memory operation, and therefore, it can also prevent leakage to the substrate 81.

[0201] Two adjacent memory sub-array layers 1a share a source region, and the formation method of each of the two memory sub-array layers 1a sharing the source region includes:

[0202] Step b1: forming a first single crystal semiconductor layer of a first doping type on the underlying first single crystal sacrificial semiconductor layer 82 or the second single crystal sacrificial semiconductor layer 14 by epitaxial growth.

[0203] Specifically, a semiconductor material gas and a first-type dopant ion gas can be introduced simultaneously to form a first single-crystalline semiconductor layer of the first doping type by epitaxial growth on the underlying first single-crystalline sacrificial semiconductor layer 82 or the second single-crystalline sacrificial semiconductor layer 14. This first single-crystalline semiconductor layer serves as the drain region semiconductor layer 11c (or source region semiconductor layer 13c). The first dopant ions can be arsenic ions. The semiconductor material can be any existing semiconductor material used to form the drain region (or source region).

[0204] Step b2: forming a second monocrystalline semiconductor layer of a second doping type on the first monocrystalline semiconductor layer by epitaxial growth.

[0205] Specifically, semiconductor material gas and second type doping ion gas can be simultaneously introduced to form a second monocrystalline semiconductor layer of a second doping type on the first monocrystalline semiconductor layer by epitaxial growth. The second monocrystalline semiconductor layer serves as the channel semiconductor layer 12c. The second doping ion can be BF 2+ ion. The semiconductor material can be a semiconductor material used to form a well region.

[0206] Step b3: forming a third monocrystalline semiconductor layer of a first doping type on the second monocrystalline semiconductor layer by epitaxial growth.

[0207] Specifically, semiconductor material gas and first type doping ion gas can be simultaneously introduced to form a third monocrystalline semiconductor layer of a first doping type on the second monocrystalline semiconductor layer by epitaxial growth. The third monocrystalline semiconductor layer serves as the source semiconductor layer 13c (or the drain semiconductor layer 11c). The first doping ion can be arsenic ion. The semiconductor material can be a semiconductor material used to form a source region (or a drain region).

[0208] In the implementation of step S312a, a second monocrystalline sacrificial semiconductor layer 14 is further formed between every two layers of the storage subarray layer la. Moreover, every two adjacent layers of the storage subarray layer la separated by the second monocrystalline sacrificial semiconductor layer 14 in the height direction Z include, in sequence, the drain semiconductor layer 11c, the channel semiconductor layer 12c, the source semiconductor layer 13c, the channel semiconductor layer 12c, and the drain semiconductor layer 11c, to share the same source semiconductor layer 13c.

[0209] Step b4: forming a fourth monocrystalline semiconductor layer of a second doping type on the third monocrystalline semiconductor layer by epitaxial growth.

[0210] The implementation of step b4 is similar to step b2. The fourth monocrystalline semiconductor layer serves as the channel semiconductor layer 12c.

[0211] Step b5: forming a fifth monocrystalline semiconductor layer of a first doping type on the fourth monocrystalline semiconductor layer by epitaxial growth.

[0212] The implementation of step b5 is similar to step b1. The fifth monocrystalline semiconductor layer serves as the drain semiconductor layer 11c (or the source semiconductor layer 13c).

[0213] The first single-crystal semiconductor layer, the second single-crystal semiconductor layer and the third single-crystal semiconductor layer form a first memory sub-array layer 1a; the third single-crystal semiconductor layer, the fourth single-crystal semiconductor layer and the fifth single-crystal semiconductor layer form a second memory sub-array layer 1a; and the third single-crystal semiconductor layer is shared by the first memory sub-array layer 1a and the second memory sub-array layer 1a as a shared source semiconductor layer 13c.

[0214] It can be understood that, in the specific implementation process, after step b5, a second single-crystal sacrificial semiconductor layer 14 is formed on the fifth single-crystal semiconductor layer. Then, steps b1-b5 are continued to be performed on the second single-crystal sacrificial semiconductor layer 14 until a preset number of memory sub-array layers 1a are formed.

[0215] That is, a second single-crystal sacrificial semiconductor layer 14 is formed between every two memory sub-array layers 1a. Moreover, every two adjacent memory sub-array layers 1a separated by the second single-crystal sacrificial semiconductor layer 14 in the height direction Z include, in sequence, a drain semiconductor layer 11c, a channel semiconductor layer 12c, a source semiconductor layer 13c, a channel semiconductor layer 12c and a drain semiconductor layer 11c, so as to share the same source semiconductor layer 13c.

[0216] Step S313a: forming a first hard mask layer 83 on the plurality of memory sub-array layers 1a, and opening a plurality of isolation barrier wall holes 31 in the first hard mask layer 83 and the plurality of memory sub-array layers 1a, and filling the isolation barrier wall holes 31 with an insulating material to form a plurality of isolation walls 3, so as to form a semiconductor substrate.

[0217] The first hard mask layer 83 can be made of silicon dioxide or silicon nitride.

[0218] Specifically, referring to Figure 19 , Figure 20 is a top view of the semiconductor substrate 1 in which a plurality of isolation barrier wall holes 31 are opened in the memory sub-array layers 1a. The plurality of isolation barrier wall holes 31 can be opened by etching. The plurality of isolation barrier wall holes 31 are arranged in a matrix in the row direction X and the column direction Y, and each isolation barrier wall hole 31 extends along the height direction Z to the surface of the substrate 81. The specific structure of the isolation wall 3 formed in the isolation barrier wall hole 31 can be referred to Figure 20 , Figure 19 is Figure 21The plan view of the isolation wall holes 31 shown in the isolation walls 3 is formed. Specifically, the isolation wall 3 near the column direction Y edge of the storage block 10 is further extended to the column direction Y edge of the storage block 10 to ensure that the isolation wall 3 at the column direction Y edge can completely isolate the two adjacent column stacked structures 1b. Specifically, in some embodiments, the isolation wall 3 near the column direction Y edge of the storage block 10 is a T-shaped isolation wall 3, that is, it includes a transverse portion and a protruding portion towards the column direction Y edge of the storage block 10, and the protruding portion is connected with the column direction Y edge of the storage block 10 to completely isolate the two adjacent column stacked structures 1b, preventing short circuit between the two columns of drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13. The isolation wall 3 and the first hard mask layer 83 can be made of the same material.

[0219] In another embodiment, step S31 specifically includes:

[0220] Step S311b: providing a substrate 81.

[0221] Step S312b: forming a plurality of isolation walls 3 on the substrate 81, wherein the plurality of isolation walls 3 are arranged in a matrix in the row direction X and the column direction Y, and each isolation wall 3 extends along the height direction Z perpendicular to the substrate 81.

[0222] Step S313b: sequentially forming a plurality of storage subarray layers 1a on the substrate 81 and between the isolation walls 3 along the height direction Z.

[0223] Wherein, the specific implementation process of forming a plurality of storage subarray layers 1a is the same as or similar to the specific implementation process of forming a plurality of storage subarray layers 1a in step S312a described above, and can achieve the same or similar technical effects. For details, please refer to the above description.

[0224] Step S314b: forming a first hard mask layer 83 on the above structure to form a semiconductor substrate.

[0225] Specifically, the first hard mask layer 83 can be formed on the product structure after step S313b, and the first hard mask layer 83 is located on the side surface of the plurality of storage subarray layers 1a away from the substrate 81.

[0226] Step S32: forming a plurality of word line holes on the semiconductor substrate to divide each layer of storage subarray layer into a plurality of columns of drain region semiconductor strips, channel semiconductor strips and source region semiconductor strips along the row direction.

[0227] In the specific implementation process, step S32 specifically includes:

[0228] Step S321: forming a plurality of word line openings 831 on the first hard mask layer 83.

[0229] wherein, referring to Figure 21 , Figures 21 to 23 is a top view of forming a plurality of word line openings 831 and word line holes 4 on the semiconductor substrate; the plurality of word line openings 831 can be formed on the first hard mask layer 83 by etching. The plurality of word line openings 831 are arranged in a matrix in the row direction X and the column direction Y.

[0230] Step S322: etching the plurality of memory subarray layers 1a under the first hard mask layer 83 using the plurality of word line openings 831 as a mask to form a plurality of word line holes 4.

[0231] wherein, referring to Figure 22 , Figure 21 is a top view of forming a plurality of word line openings 831 and word line holes 4 on the semiconductor substrate; the plurality of word line openings 831 can be formed on the first hard mask layer 83 by etching. The plurality of word line openings 831 are arranged in a matrix in the row direction X and the column direction Y. Figure 23 is a cross-sectional view of the product corresponding to Figure 21 is a cross-sectional view of the product corresponding to Figure 21 . Specifically, the word line holes 4 can be processed by etching. As shown in Figure 22 , the plurality of word line holes 4 are arranged in a matrix in the row direction X and the column direction Y, and each layer of the memory subarray layer 1a is divided into a plurality of column drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 along the row direction X. As shown in Figure 22 , each word line hole 4 extends along the height direction Z, and the left and right sides (such as the left and right sides in the orientation shown in Figure 4 ) of each word line hole 4 at a non-edge position exposes part of the plurality of memory subarray layers 1a. Among them, the left and right sides of each word line hole 4 are the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13; the front and back sides are the isolation wall 3. In this step, an etching solution with high etching ratio for semiconductor material and low etching ratio for the isolation wall 3 can be used to process and form the word line hole 4. In addition, as shown in FIG. 2-4, the leftmost edge word line hole 4 has only one column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 on the right side; similarly, the rightmost edge word line hole 4 has only one column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 on the left side. However, those skilled in the art can understand that the leftmost edge word line hole 4 and the rightmost edge word line hole 4 can be considered as a complete word line hole, and the difference between the edge word line hole 4 will not be specifically pointed out later.

[0232] As shown in FIG. 2 and Figure 23, the plurality of word line holes 4 and the plurality of isolation walls 3 divide the drain region semiconductor layer 11c in each of the memory sub-array layers 1a into a plurality of drain region semiconductor strips 11 spaced apart along the row direction X; divide the channel semiconductor layer 12c into a plurality of channel semiconductor strips 12 spaced apart along the row direction X; and divide the source region semiconductor layer 13c into a plurality of source region semiconductor strips 13 spaced apart along the row direction X. The other specific structures and functions of each of the drain region semiconductor strips 11, the channel semiconductor strips 12, and the source region semiconductor strips 13 can be referred to the related descriptions above, and will not be described here again. In addition, as shown in Figures 24a to 24b , the inside of the isolation wall 3 can be made of silicon oxide, and the outside of the isolation wall 3 is wrapped with a layer of silicon nitride material. The silicon nitride material wrapped on the outside is of the same material as the first hard mask layer 83.

[0233] In the specific implementation process, referring to FIG. Figure 24a , Figure 21 is a schematic diagram of the structure shown in FIG. Figure 24b after the step S323 processing; Figure 24a is a schematic diagram of the structure shown in FIG. Figure 25a filled with insulating material; after step S322, it further includes:

[0234] Step S323: using the word line hole 4 to remove the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14.

[0235] Specifically, the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 can be removed by etching.

[0236] Step S324: depositing in the area where the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 are removed, to fill the insulating material in the area where the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 are removed, so as to replace the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 with the insulating isolation layer 14'.

[0237] Specifically, the insulating material can be filled by atomic layer deposition. The insulating material can be silicon oxide. Those skilled in the art can understand that after the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 are removed in step S323, the isolation wall 3 can sufficiently support the adjacent stacked structure 1b, so as to facilitate the subsequent execution of step S324.

[0238] In addition, those skilled in the art can understand that in some embodiments, the memory array 1 further includes a support column 16. Specifically, referring to Figure 25b and Figure 25a , Figure 25b is a schematic diagram of the three-dimensional structure of the memory array provided by an embodiment of the present application;Figure 25a A partial plan view of a storage array is provided for an embodiment of the present application.

[0239] As shown in Figures 26-27 and 25b The storage array 1 further comprises a plurality of support columns 16, which respectively extend along the height direction Z of the storage array 1.

[0240] As mentioned above, the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 need to be replaced by the insulating isolation layer 14'. In this step, the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 are partially replaced by the insulating isolation layer 14', but in the subsequent step, according to the need of electrical isolation, all the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 will be replaced by the insulating isolation layer 14'. That is, in the process of manufacturing the storage array 1, after the first single-crystal sacrificial semiconductor layer 82 and / or the second single-crystal sacrificial semiconductor layer 14 are etched away, the storage sub-array layer la in the relevant area is suspended, and in these relevant areas, if the isolation wall 3 is provided, the isolation wall 3 can fully support the suspended storage sub-array layer la in these areas, preventing the problem of collapse of the storage sub-array layer la.

[0241] However, in some areas, there may be no isolation wall 3, for example, in the drain / source lead-out area, the storage sub-array layer la in this area does not need to be manufactured into a storage cell, and the drain semiconductor strip 11, the source semiconductor strip 13 and / or the channel semiconductor strip 12 in the storage sub-array layer la in this area need to be led out and connected with the corresponding wires, therefore, in these areas, a plurality of support columns 16 need to be provided between the two columns of stacked structures lb, so that, in the process of manufacturing the storage array 1, after the first single-crystal sacrificial semiconductor layer 82 and / or the second single-crystal sacrificial semiconductor layer 14 in the stacked structure lb in these areas are etched, the support column 16 can fully support the suspended storage sub-array layer la, preventing the problem of collapse of the storage sub-array layer la, supporting the frame of the storage array 1, and maintaining the stability of the structure of the storage array 1.

[0242] Those skilled in the art can understand that the support column 16 can be made of the same material as the isolation wall 3 in the same process step. That is, the isolation wall 3 and the support column 16 are essentially similar, except that the isolation wall 3 is arranged in the region of the storage array 1 where the storage unit is needed to be made, and it plays a role of supporting and forming the word line hole 4 in the process of making the storage array 1; while the support column 16 is formed in other regions of the storage array 1 where the storage unit is not needed to be made, for example, the drain / source lead-out region, and it plays a role of supporting in the process of making the storage array 1. Of course, in other embodiments, the support column 16 can also be arranged in the region of the storage array 1 where the storage unit is needed to be made, for example, when the distance between two adjacent isolation walls 3 is relatively far, the isolation wall 3 cannot provide sufficient support, then the support column 16 can be arranged in this region as needed to assist the isolation wall 3 to provide support. The support column 16 can be arranged according to actual needs, and the present application does not make any limitation thereto.

[0243] The material of the support column 16 can be silicon oxide or silicon nitride.

[0244] It should be pointed out that the subsequent steps are related steps after the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 are converted into the insulating isolation layer 14' by using the word line hole 4. The related process steps at the front end of the present embodiment are the same as those of the previous embodiment, and will not be repeated here.

[0245] Step S33: Forming a floating gate storage structure by using the word line hole to expose at least one side of the part of the channel semiconductor strip.

[0246] Step S33 specifically includes:

[0247] Step S331: Forming a first insulating medium layer 85a in each word line hole 4 to expose at least one side of the part of the drain region semiconductor strip 11, the channel semiconductor strip 12 and the source region semiconductor strip 13.

[0248] In the specific implementation process, step S331 specifically includes:

[0249] Step A: Removing the part of the channel semiconductor strip 12 exposed by each word line hole 4 to form a first recess 84.

[0250] Referring to Figure 26 , Figure 24b for Figure 27 a schematic view of forming the first recess 84 for the structure shown in Figure 26 for Figure 26Specifically, the portions of the channel semiconductor strips 12 on both sides of each word line hole 4 exposed by etching can be removed to form the first groove 84, for example, by acid etching.

[0251] In this embodiment, etching can be performed using an etching solution that has a high etching ratio for the channel semiconductor strips 12 and the insulating isolation layer 14', but a low etching ratio for the drain semiconductor strips 11 and the source semiconductor strips 13. For example, if the drain semiconductor strips 11 and the source semiconductor strips 13 are N-type semiconductor strips, and the well semiconductor 12 is a P-type semiconductor strip, selective etching can be performed using an etching solution that has a high etching ratio for the P-type semiconductor material and a low etching ratio for the N-type semiconductor material, thereby only etching the portions of the well semiconductor 12 and the insulating isolation layer 14' on both sides exposed by each word line hole 4, thereby forming a first groove 84.

[0252] It is understood by those skilled in the art that when acid etching is performed on the channel semiconductor strip 12, the etching solution will also etch the insulating isolation layer 14' while etching the channel semiconductor strip 12, thereby forming the third groove 84a. Figure 26 Although this etching is disadvantageous, in subsequent steps, the third groove 84a will be backfilled, especially backfilled with the same material as the insulating isolation layer 14'.

[0253] Although Figures 28-29 In the embodiment, the third groove 84a is formed due to etching. However, in other embodiments, if the etching selectivity can be well controlled, the third groove 84a is not necessarily formed.

[0254] Step B: Filling the first grooves 84 with a first insulating medium 85 .

[0255] See also Figure 28 , Figure 26 for Figure 29 Schematic diagram of forming a first insulating medium 85 on the structure shown; Figure 28 for Figures 30-32 A cross-sectional view of the corresponding product along the F direction; specifically, the first insulating medium 85 can be filled into the first groove 84 by deposition. Simultaneously, the first insulating medium 85 is also filled into the third groove 84a by deposition. The first insulating medium 85 can be made of the same material as the insulating isolation layer 14', such as silicon oxide.

[0256] When the first groove 84 is filled with the first insulating dielectric 85, the third groove 84a formed by etching away the portion of the insulating isolation layer 14' is also filled with the first insulating dielectric 85. Since the first insulating dielectric 85 is made of silicon oxide, the same material as the insulating isolation layer 14', it does not affect device performance.

[0257] In the implementation process, refer to Figure 30 , Figure 28 for Figure 31 the structure shown in the second groove 84'after the formation of the schematic diagram; Figure 30 for Figure 32 the product corresponding to the F direction of the sectional view;

[0258] Figure 30 for Figure 30 the structure shown in the second insulating medium 86 of the schematic diagram. After step B, also includes:

[0259] Step C: remove the part of the drain region semiconductor strip 11 and the part of the source region semiconductor strip 13 exposed by each word line hole 4 to form a plurality of second grooves 84'; the second groove 84' exposes at least part of the first insulating medium 85.

[0260] In which, the second groove 84' can be formed by etching. After removing the part of the drain region semiconductor strip 11 and the part of the source region semiconductor strip 13 exposed by each word line hole 4 to form a plurality of second grooves 84', the vertical sectional view of the product can be seen from Figures 33a to 33b . Specifically, in this step, an etching liquid with a low etching ratio for the channel semiconductor strip 12 and a high etching ratio for the drain region semiconductor strip 11 and the source region semiconductor strip 13 can be used for etching; for example, the drain region semiconductor strip 11 and the source region semiconductor strip 13 are N-type semiconductor strips, and the well region semiconductor 12 is a P-type semiconductor strip, and an etching liquid with a high etching ratio for N-type semiconductor material and a low etching ratio for P-type semiconductor material can be selected for selective etching, so that only the part of the drain region semiconductor strip 11 and the part of the source region semiconductor strip 13 exposed by each word line hole 4 are etched to form the second groove 84'.

[0261] Step D: form a second insulating medium 86 in the second groove 84'.

[0262] In which, the second insulating medium 86 can be formed by deposition. The second insulating medium 86 is silicon nitride. After that, step E is performed.

[0263] Step E: remove the first insulating medium 85 of the layer where the channel semiconductor strip 12 is located to expose the first groove 84, and deposit a first insulating medium layer 85a on the groove wall of the first groove 84.

[0264] As shown in Figure 33a , Figure 33b is the structure schematic diagram after removing the first insulating medium 85 of the layer where the channel semiconductor strip 12 is located; Figure 32 for Figures 34-35The structure shown schematically illustrates the formation of a first insulating dielectric layer 85a. In this step, an etchant with a high etching ratio for the first insulating dielectric 85 and a low etching ratio for the second insulating dielectric 86 can be used. For example, an etchant with a high etching ratio for silicon oxide and a low etching ratio for silicon nitride can be used to etch away the first insulating dielectric 85. The amount of etchant, the etching rate, and the etching time are controlled to etch away the first insulating dielectric 85. Subsequently, within the first recess 84 where the first insulating dielectric 85 has been etched away, a first insulating dielectric layer 85a is formed by deposition or growth. The cross-section of the first insulating dielectric layer 85a is gate-shaped, defining the floating gate trench.

[0265] Step S332 : forming a floating gate 54 on a surface of a portion of the first insulating dielectric layer 85 a away from the channel semiconductor strip 12 .

[0266] The product structure after step S332 can be seen in Figure 34 As shown, Figure 33b for Figure 35 The structure shown is a schematic diagram of forming a floating gate 54; Figure 34 for Figure 36a A cross-sectional view of the corresponding product in another direction.

[0267] Specifically, a floating gate material is deposited in the floating gate trench to form the floating gate 54 ; wherein the floating gate material includes polysilicon material.

[0268] Step S333 : forming a second insulating dielectric layer 85 b on the sidewalls of each word line hole. The second insulating dielectric layer 85 b cooperates with the first insulating dielectric layer 85 a to wrap any surface of the floating gate 54 .

[0269] In the specific implementation process, see Figure 36a , Figures 36b to 37 This is a schematic diagram of the structure after removing the portion of the first hard mask layer around each word line hole and the portion of the second insulating medium in each second groove. Step S333 specifically includes:

[0270] Step 3331 : removing a portion of the first hard mask layer 83 around each word line hole 4 and a portion of the second insulating dielectric 86 in each second groove 84 ′ to widen each word line hole 4 and expose at least a portion of each floating gate 54 .

[0271] It can be understood that after step 3331 , the first insulating dielectric layer 85 a only wraps a portion of the floating gate 54 .

[0272] See also Figure 36b , Figure 37 Schematic diagram of forming the second insulating dielectric layer 85b; Figure 36b for Figure 36b The cross-sectional view of the corresponding product in the F direction.

[0273] Step 3332: Forming a second insulating medium layer 85b on the sidewall of each word line hole 4 so that the second insulating medium layer 85b covers the exposed part of each floating gate 54.

[0274] By Figure 36b As can be seen, the first insulating medium layer 85a and the second insulating medium layer 85b completely cover and isolate each surface of the floating gate 54. The second insulating medium layer 85b comprises a multi-layer structure, which comprises a silicon oxide layer, a silicon nitride layer and another silicon oxide layer. By widening the word line hole 4, it can be ensured that the second insulating medium layer 85b covers part of the five surfaces of each floating gate 54, and thus the second insulating medium layer 85b, together with the first insulating medium layer 85a, can completely cover any surface of the floating gate 54. Specifically, as shown in Figures 38-39 , the second insulating medium layer 85b covers part of the five surfaces of the floating gate 54, wherein at least part of four of the five surfaces of the floating gate 54 is covered by the part of the second insulating medium layer 85b, and one surface is completely covered by the second insulating medium layer 85b. In addition, the first insulating medium layer 85a covers part of the other four surfaces of the floating gate 54 in addition to covering the surface of the floating gate 54 close to the channel semiconductor strip 12. Therefore, the first insulating medium layer 85a, together with the second insulating medium layer 85b, completely covers all surfaces of the floating gate 54.

[0275] Step S34: Filling the gate material in each word line hole respectively to form a plurality of gate strips.

[0276] The structure of the product after step S34 can be seen from Figure 38 , Figure 39 is a schematic view of forming the gate strip 2; Figure 38 is Figure 10 another direction of the corresponding product. The gate strip 2 covers all surfaces of the floating gate 54 except the surface covered by the first insulating medium layer 85a to improve the coupling rate. That is, one surface of the gate strip 2 extends along the extension direction of the second insulating medium layer 85b to cover the five surfaces of the floating gate 54, and at least part of four of the five surfaces of the floating gate 54 is covered by the gate strip 2 through the second insulating medium layer 85b. The specific structure of each memory cell in the memory block 10 produced by the process method of the memory block 10 can be seen from ​ .

[0277] Each of the gate strips 2 has at least a portion thereof coinciding with a projection of a corresponding portion of each of the channel semiconductor strips 12 in a projection plane along the height direction Z and the column direction Y, the portion of the gate strip 2, the corresponding portion of the channel semiconductor strip 12, a portion of the drain semiconductor strip 11 and a portion of the source semiconductor strip 13 adjacent to the corresponding portion of the channel semiconductor strip 12, and a portion of the corresponding floating gate storage structure, constitute a storage cell.

[0278] In the present embodiment, the storage structure 5 is a floating gate storage structure. As mentioned above, the floating gate storage structure is characterized in that the injected charge can be uniformly distributed on the entire floating gate 54, and the charge can move not only in the injection / removal direction (substantially perpendicular to the extension direction of the floating gate), but also in the floating gate 54, particularly in the extension direction of the floating gate 54. Therefore, for the floating gate storage structure, the floating gate 54 of each storage cell is independent, and each surface of the floating gate 54 needs to be covered by an insulating medium to isolate each other and prevent the charge stored on the floating gate 54 in one storage cell from moving to the floating gate 54 in another storage cell. Therefore, in the process method thereof, the floating gate 54 of each storage cell is independent, and the insulating medium formed by the first insulating medium layer 85a and the second insulating medium layer 85b can completely wrap and isolate each surface of the floating gate 54, so that the floating gate 54 of each storage cell is independent of each other, and the charge stored in each floating gate 54 cannot move to the floating gate 54 of another storage cell.

[0279] Specifically, the process method of the storage block 10 can be used to prepare the storage block involved in the following embodiments. The storage block 10 includes a storage array 1. The storage array 1 includes a plurality of storage cells arranged in a three-dimensional array, wherein the storage array 1 includes a plurality of stacked structures 1b arranged along the row direction X, each of the stacked structures 1b extends along the column direction Y, and each of the stacked structures 1b includes a drain semiconductor strip 11, a channel semiconductor strip 12 and a source semiconductor strip 13 stacked along the height direction Z, each of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 extends along the column direction Y; and each of the drain semiconductor strip 11, the channel semiconductor strip 12 and the source semiconductor strip 13 is a single-crystal semiconductor strip.

[0280] Multiple gate strips 2 are disposed on both sides of the stacked structure 1b, distributed along the column direction Y. Each gate strip 2 extends along the height direction Z. In the height direction Z, at least a portion of each gate strip 2 overlaps with a projection of a corresponding portion of a channel semiconductor strip 11 on a projection plane extending along the height direction Z and the column direction Y. Portions of the gate strip 2, corresponding portions of the channel semiconductor strip 12, and portions of the drain semiconductor strip 11 and source semiconductor strip 13 adjacent to the corresponding portions of the channel semiconductor strip 12 form a single memory cell. Specifically, a floating gate memory structure is disposed between each gate strip 2 and the drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 in the multiple memory sub-array layers 1a. The floating gate storage structure includes a plurality of first insulating dielectric layers 85a, a plurality of floating gates 54 and a second insulating dielectric layer 85b, wherein each first insulating dielectric layer 85a is at least located between the corresponding channel semiconductor strip 12 and one of the corresponding floating gates 54, the floating gate 54 is located between the first insulating dielectric layer 85a and the second insulating dielectric layer 85b, and the second dielectric layer 85b is located between the floating gate 54 and the gate strip 2.

[0281] Specifically, each stacked structure 1b includes multiple groups of stacked substructures, each group of stacked substructures including a drain semiconductor strip 11, a channel semiconductor strip 12, a source semiconductor strip 13, a channel semiconductor strip 12, and a drain semiconductor strip 11 stacked sequentially along the height direction Z, sharing the same source semiconductor strip 13. Specifically, an interlayer isolation layer is provided between two adjacent groups of stacked substructures to isolate them from each other.

[0282] Each stacked structure 1b is provided with multiple isolation walls 3 distributed along the column direction Y on both sides. Each isolation wall 3 extends along the height direction Z and the row direction X to separate at least part of two adjacent columns of stacked structures 1b. The isolation walls 3 further serve as support structures for the two adjacent columns of stacked structures 1b. The isolation walls 3 near the edges of the memory blocks 10 are T-shaped to completely isolate the two adjacent columns of stacked structures 1b.

[0283] In the column direction Y, a gate strip 2 is filled between two adjacent isolation walls 3 in the same column; portions of two adjacent columns of stacked structures 1 b share the same gate strip 2 .

[0284] For other structures and functions of the memory block 10 provided in this embodiment, reference may be made to the specific description of the memory block 10 provided in any of the above embodiments in which the memory structure is a floating gate memory structure, and will not be repeated here.

[0285] The storage unit corresponding to the process method comprises a drain region part 11', a channel part 12', a source region part 13' and a gate part 2', wherein the drain region part 11', the channel part 12' and the source region part 13' are stacked along a height direction Z, the gate part 2' is located on one side of the drain region part 11', the channel part 12' and the source region part 13' and extends along the height direction Z; wherein, along the height direction Z, a projection of the gate part 2' and the channel part 12' on a projection plane extending along the height direction Z at least partially overlaps, the projection plane is located on one side of the drain region part 11', the channel part 12' and the source region part 13' and extends along the height direction Z and the extension direction of the drain region part 11', the channel part 12' and the source region part 13', and a floating gate storage structure part is arranged between the gate part 2' and the drain region part 11', the channel part 12' and the source region part 13'.

[0286] The floating gate storage structure part specifically comprises a first insulating medium layer 85a, a floating gate 54 and a part of a second insulating medium layer 85b, wherein the first insulating medium layer 85a is located between the channel part 12' and the floating gate 54, the floating gate 54 is located between the first insulating medium layer 85a and the part of the second insulating medium layer 85b, and the part of the second insulating medium layer 85b is located between the floating gate 54 and the gate strip 2. The part of the second insulating medium layer 85b covers five surfaces of the floating gate 54. One of the five surfaces of the floating gate 54 is completely covered by the second insulating medium layer 85b. The part of the second insulating medium layer 85b comprises a multi-layer structure, and the multi-layer structure comprises a part of a silicon oxide layer, a part of a silicon nitride layer and another part of a silicon oxide layer.

[0287] The other structures and functions of the storage unit can refer to the related descriptions of the storage unit with the storage structure part 5' being a floating gate storage structure part in the above-mentioned embodiments, which will not be described here.

[0288] The above is only an embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for manufacturing a memory block, characterized in that: include: A semiconductor substrate is provided, wherein the semiconductor substrate includes a substrate and a plurality of memory sub-array layers formed on the substrate, the plurality of memory sub-array layers are stacked in sequence along a height direction perpendicular to the substrate, each of the memory sub-array layers includes a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked along the height direction, wherein the drain semiconductor layer, the channel semiconductor layer, and the source semiconductor layer are respectively single crystal semiconductor layers; A plurality of word line holes are formed in the semiconductor substrate to divide each memory sub-array layer into a plurality of columns of drain semiconductor strips, channel semiconductor strips, and source semiconductor strips along a row direction, wherein the plurality of word line holes are arranged in a matrix in the row and column directions, each word line hole extends along the height direction, and at least one side of each word line hole exposes a portion of at least one column of the drain semiconductor strips, channel semiconductor strips, and source semiconductor strips of the plurality of memory sub-array layers; forming a floating gate storage structure on at least one side of a portion of the channel semiconductor strip exposed by utilizing the word line hole; A gate material is filled in each of the word line holes to form a plurality of gate strips, wherein at least a portion of each of the gate strips overlaps with a projection of a portion of a corresponding channel semiconductor strip in each storage sub-array layer on a projection plane, and the projection plane extends along the height direction and the column direction. The portion of the gate strip, the corresponding portion of the channel semiconductor strip, the portion of the corresponding floating gate storage structure sandwiched between the portion of the gate strip and the corresponding portion of the channel semiconductor strip, the portion of the drain semiconductor strip and the portion of the source semiconductor strip adjacent to the corresponding portion of the channel semiconductor strip constitute a storage unit.

2. The process method according to claim 1, wherein: The method provides a semiconductor substrate, comprising: providing the substrate; forming a plurality of storage sub-array layers on the substrate in sequence along the height direction; A first hard mask layer is formed on the multiple storage sub-array layers, and a plurality of isolation wall holes are opened in the first hard mask layer and the multiple storage sub-array layers. Insulators are filled in the isolation wall holes to form a plurality of isolation walls to form the semiconductor substrate, wherein the isolation wall holes are arranged in a matrix in the row direction and the column direction, and each isolation wall hole extends along the height direction to the substrate.

3. The process method according to claim 2, wherein: The substrate is a single crystal substrate; The step of sequentially forming a plurality of storage sub-array layers on the substrate along the height direction includes: forming a first single crystal sacrificial semiconductor layer or a dummy storage sub-array layer on the substrate by epitaxial growth; Two storage sub-array layers and a second single-crystal sacrificial semiconductor layer are formed alternately in sequence on the first single-crystal sacrificial semiconductor layer by epitaxial growth until the two uppermost storage sub-array layers are formed; or, a second single-crystal sacrificial semiconductor layer and two storage sub-array layers are formed alternately in sequence on the dummy storage sub-array layer by epitaxial growth.

4. The process method according to claim 3, wherein: Two adjacent memory sub-array layers share a source region, and each of the two memory sub-array layers sharing the source region is formed by: forming a first single crystal semiconductor layer of a first doping type on the first single crystal sacrificial semiconductor layer or the second single crystal sacrificial semiconductor layer in an epitaxial growth manner; forming a second single crystal semiconductor layer of a second doping type on the first single crystal semiconductor layer by epitaxial growth; forming a third single crystal semiconductor layer of the first doping type on the second single crystal semiconductor layer by epitaxial growth; forming a fourth single crystal semiconductor layer of the second doping type on the third single crystal semiconductor layer by epitaxial growth; forming a fifth single crystal semiconductor layer of the first doping type on the fourth single crystal semiconductor layer by epitaxial growth; The first single crystal semiconductor layer and the fifth single crystal semiconductor layer of the first doping type are used as the drain semiconductor layer, the second single crystal semiconductor layer and the fourth single crystal semiconductor layer of the second doping type are used as the channel semiconductor layer, and the third single crystal semiconductor layer of the first doping type is used as the source semiconductor layer; The first single crystal semiconductor layer, the second single crystal semiconductor layer and the third single crystal semiconductor layer constitute one storage sub-array layer; the third single crystal semiconductor layer, the fourth single crystal semiconductor layer and the fifth single crystal semiconductor layer constitute another storage sub-array layer; the two storage sub-array layers share the third single crystal semiconductor layer as a shared source semiconductor layer.

5. The process method according to claim 3, wherein: The method of forming a plurality of word line holes on the semiconductor substrate comprises: forming a plurality of word line openings on the first hard mask layer, wherein the plurality of word line openings are arranged in a matrix in row and column directions; Using the first hard mask layer having the word line openings as a mask, the plurality of storage sub-array layers below the first hard mask layer are etched to form a plurality of word line holes, wherein the plurality of word line holes cooperate with the plurality of isolation walls to divide each storage sub-array layer into a plurality of columns of drain semiconductor strips, channel semiconductor strips, and source semiconductor strips along a row direction.

6. The process method according to claim 5, wherein: Further including: Using the word line holes, removing the first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer; Deposition is performed in the area where the first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer are removed to fill the area where the first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer are removed, thereby replacing the first single crystal sacrificial semiconductor layer and the second single crystal sacrificial semiconductor layer with an insulating isolation layer.

7. The process method according to any one of claims 3 to 6, characterized in that: The method of forming a floating gate storage structure on at least one side of a portion of the channel semiconductor strip exposed by using the word line hole comprises: forming a first insulating dielectric layer on at least one side of a portion of the channel semiconductor strip exposed by utilizing the word line hole; forming a floating gate on a surface of a portion of the first insulating dielectric layer facing away from the channel semiconductor strip; A second insulating dielectric layer is formed on the sidewalls of each word line hole, and the second insulating dielectric layer cooperates with the first insulating dielectric layer to wrap any surface of the floating gate, wherein the first insulating dielectric layer, the floating gate and the second insulating dielectric layer constitute the floating gate storage structure.

8. The process method according to claim 7, wherein: The step of forming a first insulating dielectric layer on at least one side of a portion of the channel semiconductor strip exposed by using the word line hole comprises: removing a portion of the channel semiconductor strip exposed by each word line hole to form a first groove; Filling a first insulating medium in the first grooves; removing the portion of the drain semiconductor strip and the portion of the source semiconductor strip exposed by each word line hole to form a plurality of second grooves; the second grooves expose portions of the first insulating medium; forming a second insulating medium in the second groove; The first insulating dielectric layer of the channel semiconductor strip is removed to expose the first groove, and a first insulating dielectric layer is deposited on the groove wall of the first groove; the first insulating dielectric layer defines a floating gate groove; and the floating gate is formed in the floating gate groove.

9. The process method according to claim 8, wherein: The removing of the portion of the channel semiconductor strip exposed by each word line hole comprises: Removing the portion of the channel semiconductor strip exposed by each word line hole by etching; The step of filling the first insulating medium in the plurality of first grooves includes: The first insulating medium is filled in the first groove by deposition.

10. The process method according to claim 8, wherein: The forming of a floating gate on a surface of a portion of the first insulating dielectric layer facing away from the channel semiconductor strip comprises: depositing a floating gate material in the floating gate trench to form the floating gate; Wherein, the floating gate material includes polysilicon material.

11. The process method according to claim 8, wherein: A second insulating dielectric layer is formed on the sidewalls of each word line hole, comprising: removing a portion of the first hard mask layer around each word line hole and a portion of the second insulating medium in each second groove to widen each word line hole and expose a portion of each floating gate; The second insulating dielectric layer is formed on the sidewall of each of the widened word line holes, so that the second insulating dielectric layer wraps the exposed portion of each of the floating gates.

12. A storage block, characterized in that: include: A memory array comprising a plurality of memory cells distributed in a three-dimensional array, wherein the memory array comprises a plurality of stacked structures distributed along a row direction, each stacked structure extending along a column direction, and each stacked structure comprising a drain semiconductor strip, a channel semiconductor strip, and a source semiconductor strip stacked along a height direction, each of the drain semiconductor strip, the channel semiconductor strip, and the source semiconductor strip extending along the column direction; and a plurality of gate strips distributed along the column direction are disposed on both sides of the stacked structures, each of the gate strips extending along the height direction; In the height direction, at least a portion of each gate strip overlaps with a projection of a portion of a corresponding channel semiconductor strip on a projection plane, and the projection plane extends along the height direction and the column direction; the portion of the gate strip, the corresponding portion of the channel semiconductor strip, the portion of the drain semiconductor strip adjacent to the corresponding portion of the channel semiconductor strip, and the portion of the source semiconductor strip are used to form one memory cell; A floating gate storage structure is provided between each gate strip and the drain semiconductor strips, channel semiconductor strips and source semiconductor strips in the plurality of stacked structures; Each of the drain semiconductor strips, channel semiconductor strips and source semiconductor strips is a single crystal semiconductor strip.

13. The storage block according to claim 12, wherein: Each column of the stacked structure includes multiple groups of stacked substructures, and each group of stacked substructures includes drain semiconductor strips, channel semiconductor strips, source semiconductor strips, channel semiconductor strips and drain semiconductor strips stacked in sequence along the height direction to share the same source semiconductor strip.

14. The storage block according to claim 13, wherein: An interlayer isolation strip is provided between two adjacent groups of the stacked substructures to isolate them from each other.

15. The storage block according to claim 12, wherein: A plurality of isolation walls distributed along the column direction are respectively provided on both sides of the stacking structure, and each isolation wall extends along the height direction and the row direction to separate at least a portion of the stacking structures in two adjacent columns.

16. The storage block according to claim 15, characterized in that In the column direction, the gate strips are filled between two adjacent isolation walls in the same column; Parts of the stacked structures in two adjacent columns share the same gate strip.

17. The storage block according to claim 15, characterized in that The isolation wall close to the column-direction edge of the storage block is a T-shaped isolation wall or extends in the column direction to the column-direction edge of the storage block to completely isolate two adjacent columns of the stacking structures.

18. The storage block according to claim 12, wherein: The floating gate storage structure includes several first insulating dielectric layers, several floating gates and a second insulating dielectric layer, wherein each of the first insulating dielectric layers is located at least between the corresponding channel semiconductor strip and one of the corresponding floating gates, the floating gate is located between the first insulating dielectric layer and the second insulating dielectric layer, and the second insulating dielectric layer is located at least between the floating gate and the gate strip.

19. The storage block according to claim 18, characterized in that Part of the second insulating dielectric layer covers five surfaces of the floating gate, wherein four of the five surfaces of the floating gate are at least partially covered by part of the second insulating dielectric layer.

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