Pixel circuit, pixel driving method, display panel and display device

Abstract

The application discloses a pixel circuit, a pixel driving method, a display panel and a display device. The pixel circuit comprises a driving transistor, an initialization module, a reset module and a light-emitting module. The first electrode of the driving transistor is connected with a first power supply line. The initialization module is connected with an initialization signal line, the first gate and the first electrode of the driving transistor. The reset module is connected with a reset signal line, the second gate and the second electrode of the driving transistor. The light-emitting module is connected with the second electrode of the driving transistor and a second power supply line. The data writing stage and the compensation stage can be separated, so that the time of the compensation process is not limited by the data writing time, and the compensation is more sufficient. In the compensation process, the initialization module and the reset module use the initialization signal on the initialization signal line and the reset signal on the reset signal line, so that the threshold voltage Vth of the driving transistor can be kept unchanged after being drifted to 0, the compensation effect difference under different gray scales is avoided, and the display brightness uniformity of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to a pixel circuit, a pixel driving method, a display panel and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and flat display devices based on light emitting diode (LED) technology have been widely applied to mobile phones, televisions, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display devices.

[0003] However, the use performance of the current OLED display product needs to be improved. SUMMARY

[0004] Embodiments of the present application provide a pixel circuit, a pixel driving method, a display panel and a display device, which solve the problem of poor display brightness uniformity of the display panel caused by the limited compensation time of the pixel driving circuit and the difference in the compensation effect of the threshold voltage Vth at different gray scales.

[0005] In a first aspect, embodiments of the present application provide a pixel circuit, which includes a driving transistor, an initialization module, a reset module and a light emitting module.

[0006] The driving transistor includes a first gate, a second gate, a first electrode and a second electrode.

[0007] The first electrode of the driving transistor is connected to a first power supply line.

[0008] The initialization module is connected to an initialization signal line, the first gate and the first electrode of the driving transistor.

[0009] The reset module is connected to a reset signal line, the second gate and the second electrode of the driving transistor.

[0010] The light emitting module is connected to the second electrode of the driving transistor and a second power supply line.

[0011] The initialization module and the reset module are used to adjust the threshold voltage of the driving transistor by using the initialization signal on the initialization signal line and the reset signal on the reset signal line.

[0012] In a possible implementation of the first aspect, the initialization module includes a first initialization submodule and a second initialization submodule.

[0013] The first initialization submodule is connected to the initialization signal line and the first gate of the driving transistor.

[0014] The second initialization submodule connects to the first gate and the first electrode of the driving transistor;

[0015] Preferably, the control terminals of the first initialization submodule and the second initialization submodule are connected to the same scanning signal.

[0016] In one possible implementation of the first aspect, the reset module includes a first reset submodule and a second reset module;

[0017] The first reset submodule is connected to the second gate and the second electrode of the driving transistor;

[0018] The second reset submodule connects the reset signal line and the second gate of the drive transistor;

[0019] Preferably, the control terminals of the first reset submodule and the second reset submodule are connected to different scan signals.

[0020] In one possible implementation of the first aspect, the control terminal of the initialization module and the control terminal of the first reset submodule are both connected to the first scan line;

[0021] The control terminal of the second reset submodule is connected to the second scan line;

[0022] Preferably, the pixel circuit further includes a data writing module, which is connected to the data line and the first gate of the driving transistor;

[0023] Preferably, the control terminal of the data writing module is connected to the third scan line;

[0024] Preferably, the pixel circuit further includes a light-emitting control module, which is connected to the first power supply line and the first electrode of the driving transistor, and the control terminal of the light-emitting control module is connected to the light-emitting control signal line.

[0025] Preferably, the first scan signal on the first scan line is a line-by-line scan signal, used to sequentially activate the initialization module and the first reset submodule within one frame time;

[0026] Preferably, the second scan signal on the second scan line is a line-by-line scan signal, used to turn on the second reset submodule line by line within one frame.

[0027] In one possible implementation of the first aspect, the driving transistor includes a P-type transistor;

[0028] Preferably, the driving transistor includes a P-type low-temperature polysilicon transistor;

[0029] Preferably, the voltage value of the initialization signal is greater than the voltage value of the reset signal;

[0030] Preferably, the voltage value of the reset signal is less than 0;

[0031] Preferably, the initialization signal is greater than the minimum value of the data signal and less than the maximum value of the data signal;

[0032] Preferably, the difference between the minimum value of the initialization signal and the minimum value of the data signal is greater than or equal to a preset value, and the difference between the maximum value of the data signal and the initialization signal is greater than or equal to a preset value.

[0033] Preferably, the preset value is half the difference between the maximum value and the minimum value of the data signal;

[0034] Preferably, the initialization module and the reset module are used to adjust the threshold voltage of the driving transistor to a predetermined value;

[0035] Preferably, the predetermined value includes 0;

[0036] Preferably, the thickness of the second gate of the driving transistor is greater than or equal to the thickness of its first gate.

[0037] In one possible implementation of the first aspect, the pixel circuit further includes:

[0038] The first storage module is connected to the second gate of the driving transistor and the first power supply line;

[0039] The second storage module is connected to the first gate and the first electrode of the driving transistor;

[0040] Preferably, the second storage module is used to store the data signals transmitted via the data line;

[0041] Preferably, the first storage module is used to store a voltage signal that maintains the threshold voltage of the driving transistor at a predetermined value.

[0042] In one possible implementation of the first aspect;

[0043] The initialization module includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the initialization signal line, the second terminal of the first transistor is connected to the first gate of the driving transistor, and the gate of the first transistor is connected to the first scan line. The first terminal of the second transistor is connected to the first gate of the driving transistor, the second terminal of the second transistor is connected to the first terminal of the driving transistor, and the gate of the second transistor is connected to the first scan line.

[0044] The reset module includes a third transistor and a fourth transistor. The first terminal of the third transistor is connected to the second terminal of the driving transistor, the second terminal of the third transistor is connected to the second gate of the driving transistor, and the gate of the third transistor is connected to the first scan line. The first terminal of the fourth transistor is connected to the reset signal line, the second terminal of the fourth transistor is connected to the second gate of the driving transistor, and the gate of the fourth transistor is connected to the second scan line.

[0045] Secondly, embodiments of this application also provide a pixel circuit driving method for driving the pixel circuit described in any embodiment of the first aspect, the method comprising:

[0046] In the first stage, the initialization module transmits the initialization signal on the initialization signal line to the first gate and first electrode of the driving transistor, and the reset module transmits the reset signal on the reset signal line to the second gate and second electrode of the driving transistor.

[0047] In the second stage, the initialization module and the reset module respond to the initialization signal to turn on the driving transistor, and the first storage module stores the voltage of the second gate when the driving transistor is turned off, with the threshold voltage of the driving transistor fixed as a predetermined value.

[0048] In the third stage, the data writing module transmits the data signal on the data line to the first gate of the driving transistor.

[0049] In the fourth stage, the light-emitting control module is turned on, and the driving transistor generates a driving current based on the data signal to drive the light-emitting module to emit light.

[0050] Thirdly, embodiments of this application also provide a display panel, which includes the pixel circuit described in any of the embodiments of the first aspect.

[0051] Fourthly, embodiments of this application also provide a display device, which includes the display panel described in the third aspect.

[0052] The pixel circuit, pixel driving method, display panel, and display device of this application embodiment include a pixel circuit comprising a driving transistor, an initialization module, a reset module, and a light-emitting module; the driving transistor includes a first gate, a second gate, a first electrode, and a second electrode; the first electrode of the driving transistor is connected to a first power supply line; the initialization module is connected to an initialization signal line, the first gate and the first electrode of the driving transistor; the reset module is connected to a reset signal line, the second gate and the second electrode of the driving transistor; the light-emitting module is connected to the second electrode of the driving transistor and the second power supply line; wherein the initialization module and the reset module are used to adjust the voltage of the second gate of the driving transistor by using the initialization signal on the initialization signal line and the reset signal on the reset signal line, so as to adjust the threshold voltage of the driving transistor. The pixel driving circuit provided in this application embodiment can separate the data writing stage from the compensation stage, so that the compensation process time is not limited by the data writing time, and the compensation is more complete. At the same time, during the compensation process, the initialization module and the reset module can use the initialization signal on the initialization signal line and the reset signal on the reset signal line to adjust the voltage of the second gate of the driving transistor, so as to adjust the threshold voltage of the driving transistor. For example, if the top gate and source voltages of the driving transistor remain unchanged and the bottom gate voltage changes, the threshold voltage Vth of the driving transistor can be made to drift to 0 and remain unchanged. Since the threshold voltage Vth of all driving transistors in the display panel is 0, the difference in compensation effect under different gray levels is avoided, and the uniformity of display brightness of the display panel is improved. Attached Figure Description

[0053] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of a pixel circuit structure provided in an embodiment of this application;

[0055] Figure 2 This application provides a schematic diagram of an initialization module structure.

[0056] Figure 3 This is a schematic diagram of another initialization module structure provided in an embodiment of this application;

[0057] Figure 4 This is a schematic diagram of a reset module structure provided in an embodiment of this application;

[0058] Figure 5 This is a schematic diagram of another reset module structure provided in an embodiment of this application;

[0059] Figure 6A schematic diagram of a pixel circuit provided in an embodiment of this application;

[0060] Figure 7 This is another pixel circuit schematic diagram provided in the embodiments of this application;

[0061] Figure 8 This is another pixel circuit schematic diagram provided in the embodiments of this application;

[0062] Figure 9 Another pixel circuit schematic diagram provided in the embodiments of this application;

[0063] Figure 10 This is another pixel circuit schematic diagram provided in the embodiments of this application;

[0064] Figure 11 This is a schematic diagram of a pixel driving method provided in an embodiment of this application;

[0065] Figure 12 A signal timing diagram provided for an embodiment of this application;

[0066] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0067] in:

[0068] 100 - Pixel circuit; 110 - Driving transistor; 120 - Initialization module; 121 - First initialization submodule; 122 - Second initialization submodule; 130 - Reset module; 131 - First reset submodule; 132 - Second reset submodule; 140 - Light emission module; 150 - Data writing module; 160 - Light emission control module; 170 - First storage module; 180 - Second storage module;

[0069] Vini - Initialization signal; Vref - Reset signal; Vdata - Data signal; VDD - First power signal; VSS - Second power signal; RE - First scan signal; SNR - Second scan signal; SNW - Third scan signal; EM - Light emission control signal. Detailed Implementation

[0070] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0071] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0072] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0073] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0074] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0075] Low-temperature poly-silicon thin film transistors (LTPS TFTs) have advantages such as high mobility, strong driving capability, and mature technology, and are widely used in pixel driving circuits of display panels.

[0076] Traditional 7T1C LTPS pixel driver circuits suffer from limitations in threshold voltage compensation due to the simultaneous writing of data (Data) and compensation threshold voltage (Vth). Furthermore, variations in the Data signal lead to differences in Vth compensation at different grayscale levels, resulting in poor brightness uniformity. This problem is particularly severe in high-resolution and high-refresh-rate applications where the line scan time is shorter. Therefore, existing pixel driver circuits suffer from limited compensation time and inconsistent Vth compensation effects across different grayscale levels, ultimately contributing to poor brightness uniformity in the display panel.

[0077] Based on this, embodiments of this application provide a pixel circuit, a pixel driving method, a display panel, and a display device. By separating the compensation process from the data writing process, the compensation process time is not limited by the data writing time, resulting in more thorough compensation. At the same time, during the compensation process, the top gate and source voltages of the driving transistor remain unchanged, while the bottom gate voltage changes. This allows the threshold voltage Vth of the driving transistor to remain unchanged after drifting to 0V. Since the threshold voltage Vth of all driving transistors in the display panel is 0V, the difference in compensation effect under different gray levels (Data) is avoided, thus improving the uniformity of the display brightness of the display panel.

[0078] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0079] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application, such as... Figure 1 As shown, the pixel circuit 100 may include a driving transistor 110, an initialization module 120, a reset module 130, and a light-emitting module 140.

[0080] The driving transistor 110 includes a first gate G, a second gate BG, a first electrode S, and a second electrode D;

[0081] The first terminal of the driving transistor 110 is connected to the first power supply line;

[0082] The initialization module 120 is connected to the initialization signal line, the first gate G and the first electrode S of the driving transistor 110;

[0083] Reset module 130 is connected to reset signal line, second gate BG and second electrode D of drive transistor 110;

[0084] The light-emitting module 140 is connected to the second electrode D and the second power line Vss of the driving transistor 110.

[0085] It should be noted that the initialization signal line can be called L. ini Initialize signal line L iniThe initialization signal transmitted can be called Vini; the reset signal line can be called L. ref Reset signal line L ref The reset signal transmitted up can be called Vref; the data signal line can be called L. data Data signal line L data The data signal transmitted can be called Vdata; the first power line can be called L. vdd First power line L vdd The first power signal transmitted can be called VDD; the second power line can be called L. vss Second power line L vss The second power signal transmitted can be called VSS.

[0086] Driving transistor 110 (Driving TFT, or Tdrive for short) refers to a transistor used to drive the light-emitting module 140 to emit light. In this embodiment, the driving transistor can also be turned on during the compensation phase to raise the voltage of the second electrode D and the second gate BG of the driving transistor 110.

[0087] Specifically, such as Figure 1 As shown, the pixel circuit 100 may include a driving transistor 110, an initialization module 120, a reset module 130, and a light-emitting module 140.

[0088] The reset module 130 is connected to the reset signal line, the second gate BG and the second electrode D of the drive transistor 110, and can be used to write the reset signal on the reset signal line to the second gate BG and the second electrode D of the drive transistor Tdrive during the initialization phase.

[0089] The initialization module 120 is connected to the initialization signal line, the first gate G and the first electrode S of the driving transistor 110. It can be used to write the initialization signal on the initialization signal line to the first gate G and the first electrode S of the driving transistor Tdrive during the initialization phase. It can also be used to raise the voltage of the second electrode D and the second gate BG of the driving transistor 110 together with the driving transistor Tdrive during the compensation phase, so as to adjust the threshold voltage Vth of the driving transistor 110.

[0090] The driving transistor 110 includes a first gate G, a second gate BG, a first electrode S, and a second electrode D. It can be used to adjust the voltage of the second electrode D and the second gate BG of the driving transistor 110 together with the initialization module during the compensation phase. It can also be used to generate a driving current according to the data signal and the first power supply signal VDD during the light emission phase.

[0091] The light-emitting module 140 is connected to the second electrode D of the driving transistor 110 and the second power supply line, and is used to emit light according to the driving current during the light-emitting phase.

[0092] The initialization module 120 and the reset module 130 can be used to adjust the voltage of the second gate BG of the driving transistor 110 by using the initialization signal Vini on the initialization signal line and the reset signal Vref on the reset signal line, so as to adjust the threshold voltage Vth of the driving transistor 110.

[0093] The pixel driving circuit provided in this application embodiment can separate the data writing stage from the compensation stage, so that the compensation process time is not limited by the data writing time, and the compensation is more complete. At the same time, during the compensation process, the initialization module and the reset module can use the initialization signal on the initialization signal line and the reset signal on the reset signal line to adjust the voltage of the second gate of the driving transistor, so as to adjust the threshold voltage of the driving transistor. For example, if the top gate and source voltages of the driving transistor remain unchanged and the bottom gate voltage changes, the threshold voltage Vth of the driving transistor can be made to drift to 0 and remain unchanged. Since the threshold voltage Vth of all driving transistors in the display panel is 0, the difference in compensation effect under different gray levels is avoided, and the uniformity of display brightness of the display panel is improved.

[0094] In some embodiments, such as Figure 2 As shown, the initialization module 120 may include a first initialization submodule 121 and a second initialization submodule 122;

[0095] The first initialization submodule 121 can be connected to the initialization signal line and the first gate of the driving transistor;

[0096] The second initialization submodule 122 can be connected to the first gate and the first electrode of the driving transistor;

[0097] Preferably, the control terminals of the first initialization submodule and the second initialization submodule can be connected to the same scanning signal.

[0098] The first initialization submodule 121 can connect the initialization signal line and the first gate G of the driving transistor Tdrive. That is, during the initialization phase, the first initialization submodule 121 can write the initialization signal Vini on the initialization signal line into the first gate G of the driving transistor Tdrive.

[0099] The second initialization submodule 122 can be connected to the first gate G and the first terminal S of the driving transistor Tdrive. That is, during the initialization phase, the second initialization submodule 122 can write the voltage of the first gate G of the driving transistor Tdrive to the first terminal S of the driving transistor Tdrive.

[0100] As can be seen from the above, during the initialization phase, the initialization signal Vini can be written into the first gate G and the first electrode S of the driving transistor Tdrive through the first initialization submodule 121 and the second initialization submodule 122. In other words, during the initialization phase, the V of the driving transistor Tdrive can be realized. G =Vs=Vini.

[0101] Specifically, such as Figure 2 As shown, the initialization module 120 may include a first initialization submodule 121 and a second initialization submodule 122. The first initialization submodule 121 may be connected to the initialization signal line and the first gate of the driving transistor; the second initialization submodule 122 may be connected to the first gate and the first electrode of the driving transistor. During the initialization phase, the initialization signal Vini can be written to the first gate G and the first electrode S of the driving transistor Tdrive by controlling the switching transistors in the first initialization submodule 121 and the second initialization submodule 122 to initialize the first gate G and the first electrode S of the driving transistor Tdrive.

[0102] In one embodiment, such as Figure 3 As shown, the control terminals of the first initialization submodule 121 and the second initialization submodule 122 can be connected to the same scan line to receive the scan signal RE. By dividing the initialization module into two, it can be divided into two initialization submodules. The inventors have found that the two initialization submodules function during the initialization and compensation phases, but not during the data writing and light emission phases. Therefore, the timing of the control terminals of the two initialization submodules is the same, and they can use the same scan line, which can reduce the number of wires and improve the resolution of the display panel.

[0103] In some embodiments, such as Figure 4 As shown, the reset module 130 may include a first reset submodule 131 and a second reset submodule 132;

[0104] The first reset submodule 131 is connected to the second gate and the second electrode of the driving transistor;

[0105] The second reset submodule 132 is connected to the reset signal line and the second gate of the drive transistor;

[0106] Preferably, the control terminal of the first reset submodule 131 and the control terminal of the second reset submodule 132 are connected to different scanning signals.

[0107] Specifically, such as Figure 4As shown, the second reset submodule 132 can be connected to the reset signal line and the second gate BG of the drive transistor Tdrive, and can be used to write the reset signal Vref on the reset signal line into the second gate BG of the drive transistor Tdrive during the initialization phase.

[0108] The first reset submodule 131 can be connected to the second gate BG and the second terminal D of the driving transistor Tdrive, and can be used to write the voltage of the second gate BG of the driving transistor Tdrive to the second terminal D of the driving transistor Tdrive during the initialization phase.

[0109] Therefore, the reset signal Vref on the reset signal line can be written into the second gate BG and the second electrode D of the driving transistor Tdrive through the second reset submodule 132 and the first reset submodule 131.

[0110] In one embodiment, the inventors discovered that the first reset submodule 131 can function during the initialization and compensation phases, but not during the data writing and light emission phases; the second reset submodule 132 can function during the initialization phase, but not during the compensation, data writing, and light emission phases. Therefore, the timing of the two reset submodules is different; that is, the control terminals of the first reset submodule 131 and the second reset submodule 132 can be connected to different scan lines, which is beneficial for controlling the two reset submodules to function at different stages.

[0111] In some embodiments, such as Figure 5 As shown, the control terminals of the initialization module and the first reset submodule are both connected to the first scan line;

[0112] The control terminal of the second reset submodule is connected to the second scan line;

[0113] Preferably, such as Figure 6 As shown, the pixel circuit also includes a data writing module 150, which is connected to the data line and the first gate of the driving transistor.

[0114] Preferably, the control terminal of the data writing module is connected to the third scan line;

[0115] Preferably, such as Figure 7 As shown, the pixel circuit also includes a light emission control module 160. The light emission control module is connected to the first power supply line and the first electrode of the driving transistor. The control terminal of the light emission control module is connected to the light emission control signal line. Preferably, the first scan signal on the first scan line is a line-by-line scan signal, which is used to turn on the initialization module and the first reset sub-module line by line in one frame time.

[0116] Preferably, the second scan signal on the second scan line is a line-by-line scan signal, used to turn on the second reset submodule line by line within one frame.

[0117] The data writing module 150 is connected to the data line and the first gate G of the driving transistor 110, and can be used to write the data signal Data on the data line to the first gate G of the driving transistor Tdrive during the data writing stage.

[0118] It should be noted that the first scan line can be called L. RE First scan line L RE The first scan signal transmitted can be called RE; the second scan line can be called L. SNR Second scan line L SNR The second scan signal transmitted can be called the SNR; the third scan line can be called the L. SNW Third scan line L SNW The third scan signal transmitted upwards can be called SNW, and the light emission control signal line can be called L. EM Light emission control signal line L EM The light control signal transmitted from above can be called EM.

[0119] Specifically, see Figure 3 and Figure 5 Through research, the inventors discovered that the first initialization submodule, the second initialization submodule, and the first reset submodule all function during the initialization and compensation phases, but not during the data writing and light emission phases, thus having the same timing. The second reset submodule, however, only functions during the initialization phase. Therefore, the control terminal of the second reset submodule can be connected to the second scan line L. SNR The control terminals of the initialization module and the first reset submodule can both be connected to the same first scan line L. RE This further reduces the number of wires and further improves the resolution of the display panel.

[0120] In one embodiment, such as Figure 6 As shown, the data writing module 150 connects the data line and the first gate of the driving transistor, and the control terminal of the data writing module 150 can be connected to the third scan line L. SNW It can be used to control the switching transistor in the data writing module to turn on during the data writing stage, and write the data signal to the first gate G of the driving transistor Tdrive.

[0121] In another embodiment, such as Figure 7 As shown, the control terminal of the light-emitting control module 160 can be connected to the light-emitting control signal line L. EMIt can be used to control the switching transistor in the light-emitting control module to turn on during the light-emitting stage, and write the voltage VDD on the first power signal line into the first terminal S of the driving transistor Tdrive so as to drive the driving transistor Tdrive to generate a driving current to drive the light-emitting module to emit light.

[0122] In another embodiment, the first scan signal RE on the first scan line is a line-by-line scanning signal, used to sequentially activate the initialization module and the first reset submodule within one frame. The second scan signal SNR on the second scan line is a line-by-line scanning signal, used to sequentially activate the second reset submodule within one frame. Within one frame, the pixel circuits of all lines can be initialized and threshold compensation performed first through line-by-line scanning of the first scan signal RE and the second scan signal SNR, and then data is written line by line. This separates the compensation stage from the data writing stage, allowing the compensation process to proceed without being limited by the data writing time, resulting in more thorough compensation.

[0123] In some embodiments, the driving transistor may include a P-type transistor;

[0124] Preferably, the driving transistor includes a P-type low-temperature polysilicon transistor;

[0125] Preferably, the voltage value of the initialization signal is greater than the voltage value of the reset signal;

[0126] Preferably, the voltage value of the reset signal is less than 0;

[0127] Preferably, the initialization signal is greater than the minimum value of the data signal and less than the maximum value of the data signal;

[0128] Preferably, the difference between the minimum value of the initialization signal and the minimum value of the data signal is greater than or equal to a preset value, and the difference between the maximum value of the data signal and the initialization signal is greater than or equal to a preset value.

[0129] Preferably, the preset value is half the difference between the maximum value and the minimum value of the data signal;

[0130] Preferably, the initialization module and the reset module are used to adjust the threshold voltage of the driving transistor to a predetermined value;

[0131] Preferably, the predetermined value includes 0;

[0132] Preferably, the thickness of the second gate of the driving transistor is greater than or equal to the thickness of its first gate.

[0133] Specifically, the driving transistor Tdrive can include a P-type transistor. For example, when the driving transistor is a dual-gate P-type transistor, the threshold voltage Vth of the driving transistor Tdrive is related to the bottom-gate-source voltage difference Vbs. When the bottom-gate-source voltage difference Vbs is large, Vth > 0. When the bottom-gate-source voltage difference Vbs gradually decreases, Vth will be negatively biased. During the process of the bottom-gate-source voltage difference Vbs decreasing, Vth will be negatively biased to 0.

[0134] The initialization module can be used to keep the voltage of the first gate G and the first electrode S of the driving transistor Tdrive equal and constant. The initialization module, the reset module and the first storage module are configured to gradually raise the voltage of the second gate BG and the second electrode D of the driving transistor Tdrive after it is turned on.

[0135] In one embodiment, the voltage value of the initialization signal Vini is greater than the voltage value of the reset signal Vref, and the voltage value of the reset signal Vref can be less than 0, i.e., Vref < 0 and Vref < Vini. Since Vini has already been written to the first gate G and first electrode S of the driving transistor Tdrive during the initialization phase, and Vref has already been written to the second gate BG and second electrode D of the driving transistor Tdrive, i.e., V... G =V s =Vini, Vbs = Vref - Vini, Vbs is larger, Vth > 0. During the compensation phase, because V... G -V s =0 < Vth, which satisfies the conduction condition of the driving transistor Tdrive. After the driving transistor Tdrive is turned on, the voltage of the second terminal D and the second gate BG of the driving transistor Tdrive is raised, and the voltage difference Vbs between Vb and Vs will gradually decrease. The threshold voltage Vth of the driving transistor drifts to 0 and remains unchanged. Since the threshold voltage Vth of all driving transistors in the display panel is 0, the difference in compensation effect under different gray levels is avoided, and the uniformity of display brightness of the display panel is improved.

[0136] In another embodiment, the minimum value of the data signal Vdata, Vdatamin, is less than the initialization signal, Vini, and the maximum value of the data signal Vdata, Vdatamax, i.e., it falls within the range of the data signal Vdata. The initialization signal, Vini, falls within the range of the data signal Vdata. For example, if the minimum value of the data signal Vdata, Vdatamin, is 0.5V and the maximum value of the data signal Vdata, Vdatamax, is 7V, then 0.5V is less than the initialization signal, Vini, and 7V.

[0137] In one example, (initialization signal Vini) - (minimum value of data signal Vdata, Vdatamin) ≥ preset value, (maximum value of data signal Vdata, Vdatamax) - (initialization signal Vini) ≥ preset value, that is, (Vdatamin + preset value) ≤ Vini ≤ (Vdatamax - preset value). This preset value can be a value that limits the initialization signal Vini to a certain part of the data signal Vdata range. For example, if the minimum value of data signal Vdata, Vdatamin = 0.5V, and the maximum value of data signal Vdata, Vdatamax = 7V, and the preset value can be 2V, then the value range of the initialization signal Vini can be 2.5V to 5V. Alternatively, the preset value can also be 3V, then the value range of the initialization signal Vini can be 3.5V to 4V. A preset value of 3V corresponds to lower power consumption during capacitor charging and discharging compared to a preset value of 2V.

[0138] It should be noted that, according to the inventors' research, the value of the initialization signal Vini needs to be considered from multiple aspects. First, as long as Vini > Vref, the Tdrive can be turned on; the existence of a voltage difference allows for conduction, thus fulfilling the function of the compensation stage. Furthermore, the larger the voltage difference, the larger the current flowing through the Tdrive, resulting in faster compensation and a higher compensation rate. Therefore, the initialization signal Vini needs to have a relatively large voltage value. Second, however, the initialization signal Vini cannot be infinitely large; it needs to match the output supply value of the IC chip. For example, if the IC's voltage supply range is 0.2V to 7V, then the initialization signal Vini cannot be greater than 7V. Third, given the above, if the initialization signal Vini is 7V, it will cause the storage capacitor, such as capacitor C2 in the second storage module, to store the voltage Vini at the end of the compensation stage. In the subsequent data writing stage, Vdata needs to be written, increasing the difference between Vini and Vdata. For example, when Vdata = 0.5V at low grayscale, the voltage difference between Vini and Vdata is 6.5V, increasing the power consumption of capacitor C2 during charging and discharging. Therefore, the initialization signal Vini cannot be the maximum value of 7V. To balance these three points, it is necessary to ensure the conduction of Tdrive during the compensation phase, guarantee the compensation speed, and improve the compensation rate. It is also necessary to match the output supply value of the IC chip and reduce the power consumption of capacitor charging and discharging, that is, to reduce the power consumption of capacitor charging and discharging in each pixel circuit, which is the power consumption of the entire display panel. Therefore, the initialization signal Vini can take the voltage value between Vdatamin and Vdatamax. This can not only improve the compensation speed and compensation rate, but also match the output supply value of the IC chip, and reduce the power consumption of capacitor charging and discharging. This improves the uniformity of the display panel while reducing power consumption.

[0139] For example, the preset value can be half the difference between the maximum and minimum values ​​of the data signal, i.e., the preset value can be 1 / 2 × (7V - 0.5V) = 3.25. At this time, the initialization signal Vini - 0.5V ≥ 3.25 and the initialization signal 7V - Vini ≥ 3.25, i.e., Vini = 3.75. That is, Vini is the middle value of the range of the data signal Vdata. Therefore, when Vdata takes a value between 0.5V and 7V, the voltage difference between Vdata and Vini changes less, reducing the power consumption of capacitor charging and discharging.

[0140] In another embodiment, the initialization module and the reset module are used to adjust the threshold voltage of the driving transistor to a predetermined value. This predetermined value refers to the threshold voltage Vth of the driving transistor Tdrive at the end of the compensation phase. For example, the predetermined value can be 0, meaning that the threshold voltage Vth of the driving transistor Tdrive is 0 at the end of the compensation phase. By making the threshold voltage Vth of all driving transistors of the display panel drift to 0 and remain unchanged, the difference in compensation effect at different gray levels can be avoided, and the uniformity of display brightness of the display panel can be improved.

[0141] In another embodiment, the thickness of the second gate BG of the driving transistor Tdrive can be greater than or equal to the thickness of its first gate G. The inventors have discovered that, since the embodiments of this application change the bottom gate voltage V by fixing the source voltage... BG To adjust Vth, therefore the bottom gate voltage V BG The rate of change of the threshold voltage Vth, ΔV1, affects the rate of change of the threshold voltage Vth, ΔV2, of the driving transistor Tdrive. When the bottom gate thickness (BG) is less than the top gate thickness (G), the rate of change of the threshold voltage Vth, ΔV2, is greater than that of the bottom gate voltage Vth. BG The rate of change of the threshold voltage Vth ΔV1 must be faster, meaning the control capability of the bottom gate is too strong, and the row scan time is very short. Therefore, excessive control capability of the bottom gate will produce a large error during compensation. For example, if the bottom gate thickness is 1000μm and the top gate thickness is 2000μm, then (the rate of change of the threshold voltage Vth ΔV2) = 2 × (the rate of change of the bottom gate voltage Vth). BG If the rate of change of the threshold voltage Vth is too fast (ΔV1), it indicates that the control capability of the bottom gate is too strong, the rate of change of the threshold voltage Vth is too fast, and the row scan time is very short, which will produce a large compensation error. In the embodiments of this application, the thickness of the second gate BG of the driving transistor Tdrive is greater than or equal to the thickness of its first gate G, that is, the bottom gate thickness is greater than or equal to the top gate thickness. This can reduce the error caused by the excessively fast change of Vth during compensation, further improve the compensation rate, and achieve a high degree of compensation and good compensation effect.

[0142] In one example, the bottom gate thickness of the driving transistor Tdrive can be equal to the top gate thickness, then the bottom gate voltage V BGThe rate of change of the threshold voltage Vth, ΔV1, is equal to the rate of change of the threshold voltage Vth, ΔV2, of the driving transistor Tdrive. This avoids compensation errors caused by excessively strong control of the bottom gate, and also avoids insufficient compensation caused by insufficient control of the bottom gate. It can improve the compensation rate while increasing the compensation speed, resulting in good compensation effect. For example, if the bottom gate thickness is 1000μm and the top gate thickness is 1000μm, then the rate of change of the threshold voltage Vth, ΔV2, is equal to the rate of change of the bottom gate voltage Vth. BG If the rate of change of the voltage at the bottom gate is ΔV1, it means that the rate of change of the voltage at the bottom gate is the same as the rate of change of the voltage at the bottom gate. This allows for better control of the compensation process, improving both the compensation speed and the compensation effect.

[0143] In some embodiments, such as Figure 8 As shown, the pixel circuit 100 may further include a first storage module 170 and a second storage module 180:

[0144] The first storage module 170 is connected to the second gate of the driving transistor and the first power supply line;

[0145] The second storage module 180 is connected to the first gate and the first electrode of the driving transistor;

[0146] Preferably, the first storage module 170 is used to store a voltage signal that maintains the threshold voltage of the driving transistor at a predetermined value;

[0147] Preferably, the second storage module 180 is used to store the data signals transmitted by the data line.

[0148] Specifically, the second storage module 180 can be connected to the first gate and the first electrode S of the driving transistor Tdrive, and the second storage module 180 can store the data signal transmitted by the data line.

[0149] The first storage module 170 can be used to store a voltage signal that maintains the threshold voltage of the driving transistor at a predetermined value. For example, the predetermined value can be 0, i.e., storing the second gate voltage V of the driving transistor at the end of the compensation phase. BG This ensures that Vth remains constant after drifting to 0, making the threshold voltage Vth of all driving transistors in the display panel 0, avoiding differences in compensation effects under different gray levels Vdata, and improving the uniformity of display brightness of the display panel.

[0150] In some embodiments, such as Figure 9As shown, the initialization module includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the initialization signal line, the second terminal of the first transistor is connected to the first gate of the driving transistor, and the gate of the first transistor is connected to the first scan line. The first terminal of the second transistor is connected to the first gate of the driving transistor, the second terminal of the second transistor is connected to the first terminal of the driving transistor, and the gate of the second transistor is connected to the first scan line.

[0151] The reset module includes a third transistor and a fourth transistor. The first terminal of the third transistor is connected to the second terminal of the driving transistor, the second terminal of the third transistor is connected to the second gate of the driving transistor, and the gate of the third transistor is connected to the first scan line. The first terminal of the fourth transistor is connected to the reset signal line, the second terminal of the fourth transistor is connected to the second gate of the driving transistor, and the gate of the fourth transistor is connected to the second scan line.

[0152] Specifically, such as Figure 9 As shown,

[0153] Initialization module 120 may include a first transistor T1 and a second transistor T2. The first terminal of the first transistor T1 is connected to the initialization signal line, the second terminal of the first transistor T1 is connected to the first gate of the driving transistor, and the gate of the first transistor T1 is connected to the first scan line L. RE Then, the first transistor T1 can be used to control the writing of the Vini signal to the first gate of the driving transistor; the first terminal of the second transistor T2 is connected to the first gate of the driving transistor, the second terminal of the second transistor T2 is connected to the first terminal of the driving transistor, and the gate of the second transistor T2 is connected to the first scan line L. RE Then, the first transistor T1 and the second transistor T2 can jointly control the Vini signal to be written to the first terminal S of the driving transistor;

[0154] The reset module 130 may include a third transistor T3 and a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the reset signal line, the second terminal of the fourth transistor T4 is connected to the second gate BG of the driving transistor, and the gate of the fourth transistor T4 is connected to the first scan line L. RE Then, the fourth transistor T4 can control Vref to be written to the second gate BG of the driving transistor; the first terminal of the third transistor T3 is connected to the second terminal D of the driving transistor, the second terminal of the third transistor T3 is connected to the second gate BG of the driving transistor, and the gate of the third transistor T3 is connected to the first scan line L. RE Then, the third transistor T3 and the fourth transistor T4 can jointly control Vref to be written to the second electrode D of the driving transistor.

[0155] In one example, such as Figure 10As shown, the pixel circuit can include 7 transistors and 2 capacitors, i.e., a 7T2C structure, wherein the driving transistor Tdrive is a dual-gate P-type transistor.

[0156] Specifically, the pixel circuit 100 may include a driving transistor 110, an initialization module 120, a reset module 130, a light-emitting module 140, a data writing module 150, a light-emitting control module 160, a first storage module 170, and a second storage module 180.

[0157] The initialization module 120 may include a first initialization submodule 121 and a second initialization submodule 122, and the reset module 130 may include a first reset submodule 131 and a second reset submodule 132. The light emission control module 160 may include a sixth transistor T6, with its first terminal connected to the first power line VDD and its second terminal connected to the first terminal S of the driving transistor. Therefore, the sixth transistor T6 can be used to control the pixel circuit to enter the light emission stage.

[0158] The data writing module 150 may include a fifth transistor T5, the first terminal of the fifth transistor T5 is connected to the data line, the second terminal of the fifth transistor T5 is connected to the first gate G of the driving transistor, and the gate of the fifth transistor T5 is connected to the third scan line L. SNW Then the fifth transistor T5 passes through the third scan line L SNW The third scan signal SNW is turned on, and the control data signal is directly written into the first gate G of the driving transistor;

[0159] The first storage module 170 includes a first capacitor C1, and the first terminal of the first capacitor C1 is connected to a first power line L. Vdd The second terminal of the first capacitor C1 is connected to the second gate BG of the driving transistor C1.

[0160] The light-emitting control module 160 may include a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to the first power supply line VDD, the second terminal of the sixth transistor T6 is connected to the first terminal S of the driving transistor, and the gate of the sixth transistor T6 is connected to the light-emitting control line L. EM If connected, the sixth transistor T6 can be used to control the pixel circuit to enter the light-emitting stage.

[0161] Based on the same inventive concept, this application also provides a pixel circuit driving method, which can be used to drive the pixel circuit described in any of the above embodiments.

[0162] like Figure 11 As shown, the pixel circuit driving method also provided in this application embodiment may include the first stage S210 to the fourth stage S240 executed sequentially:

[0163] In the first stage S210, the initialization module transmits the initialization signal on the initialization signal line to the first gate and first electrode of the driving transistor, and the reset module transmits the reset signal on the reset signal line to the second gate and second electrode of the driving transistor.

[0164] In the second stage S220, the initialization module and the reset module respond to the initialization signal to turn on the driving transistor, and the first storage module stores the voltage of the second gate when the driving transistor is turned off, with the threshold voltage of the driving transistor fixed as a predetermined value.

[0165] In the third stage S230, the data writing module transmits the data signal on the data line to the first gate of the driving transistor.

[0166] In the fourth stage S240, the light-emitting control module is turned on, and the driving transistor generates a driving current according to the data signal to drive the light-emitting module to emit light.

[0167] The first stage S210 can be understood as the initialization stage; the second stage S220 can be understood as the compensation stage; the third stage S230 can be understood as the data writing stage; and the fourth stage S240 can be understood as the light emission stage.

[0168] Specifically, in the first stage S210, the initialization module 120 can be turned on by the scan signal. After the initialization module 120 is turned on, it can transmit the initialization signal Vini on the initialization signal line Lini to the first gate G and the first terminal S of the driving transistor Tdrive, and the reset module 130 can transmit the reset signal Vref on the reset signal line Lref to the second gate BG and the second terminal D of the driving transistor Tdrive. The initialization module can initialize the potential voltage of the first gate G and the first terminal S of the driving transistor Tdrive to Vini, that is, V G =V S =Vini.

[0169] The reset module resets the potential voltage of the second gate BG and the second terminal D of the driving transistor Tdrive to Vref, i.e., V BG =V D =Vref, where Vref can be less than 0, Vini > Vref, the driving transistor Tdrive is a dual-gate P-type transistor, and since the voltage difference Vbs between the bottom gate and the first electrode S is large, the threshold voltage Vth of the driving transistor Tdrive is greater than 0. At the same time, the anode of the light-emitting module 140 is reset by the reset module to avoid image retention.

[0170] At the beginning of the second stage S220, the driving transistor Tdrive satisfies "V G =V S=Vini,V GS =V G —V S =0, Vth>0, therefore V GS When Vth < Vth, the driving transistor Tdrive is turned on. After Tdrive is turned on, the potential voltage at its second terminal (D) is raised, which in turn raises the potential voltage at its second gate (BG). As the potential voltage at the second gate (BG) rises, Vbs gradually decreases, and the threshold voltage Vth of the driving transistor Tdrive drifts from a positive value to 0. When the threshold voltage Vth = 0, V... GS =V G —V S =0=Vth, the driving transistor Tdrive is turned off. After the driving transistor Tdrive is turned off, the value of V at this time can be stored through capacitor C1 in the first storage module. BG V S The voltage remains fixed through the second storage module 180, maintaining Vth = 0. The voltage difference stored in the second storage module is V. G -V S =Vini-Vini=0V.

[0171] In the third stage S230, Vth = 0, the driving transistor Tdrive is off, and the data writing module is on. The data writing module can write the data signal Vdata transmitted on the data signal line into the first gate G of the driving transistor. Since the light-emitting control module is off, the second storage module has no conducting loop, i.e., one end is floating. Therefore, according to the coupling effect of the second storage module, V... S Will follow V G The voltage changes abruptly because the voltage difference stored in the second storage module is 0V, therefore V G =V S .

[0172] Next, the light-emitting control module 160 changes from the off state to the on state, and transmits the first power signal VDD to the second electrode S. Since the data writing module is still on at this time, the two ends of the second storage module are connected to the voltage source signals VDD and Vdata respectively. They are not in a floating state and there is no coupling effect. That is, the voltage at one end will not change with the voltage jump at the other end. Therefore, Vs = VDD, V G =Vdata. At the same time, since the reset module 130 is turned off, the setting of the first storage module 170 and the voltage at the connection terminal of the second gate BG change, maintaining the previous state Vth = 0.

[0173] It should be noted that: 1) When both ends of the capacitor are connected to a voltage source, there is no coupling effect, that is, the voltage at one end of the capacitor will not change with the voltage jump at the other end; 2) When one end of the capacitor is connected to a voltage source and the other end is floating, there is a coupling effect, which means that the voltage difference is stored, that is, the voltage at one end will change with the voltage jump at the other end.

[0174] In the fourth stage S240, the light-emitting control module is turned on, the fifth transistor T5 of the data writing module is turned off, and the capacitor C2 in the second storage module can store the voltage difference ΔU across its terminals. C2 =Vdata - VDD remains constant. According to the current formula "i = k(V GS -Vth) 2 "where k is a constant", which can be interpreted as "Vth=0, V GS Substituting "=Vdata-VDD" into the current formula, we can see that the current i is only related to Vdata-VDD and has nothing to do with the Vth of the driving transistor Tdrive. Therefore, by separating the compensation stage from the data writing stage, we can not only keep the Vth of all driving transistors unchanged at 0 to improve the uniformity of display brightness, but also achieve Vth compensation, which further improves the display effect.

[0175] In this embodiment, the data writing module is directly connected to the data line and the first gate of the driving transistor. During the data writing stage, the data signal does not need to flow through any module to be directly written to the first gate of the driving transistor. Therefore, the data writing stage and the compensation stage can be separated, so that the compensation process is not limited by the data writing time and the compensation is more complete. At the same time, during the compensation process, the initialization module and the reset module can use the initialization signal on the initialization signal line and the reset signal on the reset signal line to adjust the voltage of the second gate of the driving transistor to adjust the threshold voltage of the driving transistor. For example, if the top gate and source voltages of the driving transistor remain unchanged and the bottom gate voltage changes, the threshold voltage Vth of the driving transistor can be made to drift to 0 and remain unchanged. Since the threshold voltage Vth of all driving transistors in the display panel is 0, the difference in compensation effect under different gray levels is avoided, and the uniformity of display brightness of the display panel is improved. Furthermore, during the light-emitting stage, the current i flowing through the OLED is only related to Vdata-VDD and is independent of the threshold voltage Vth of the driving transistor. Therefore, by separating the compensation stage from the data writing stage, not only can the Vth of all driving transistors be kept constant at 0 to improve the uniformity of display brightness, but VDD compensation can also be achieved, further improving the display effect.

[0176] In one embodiment, such as Figure 12 As shown, Figure 12 This is a signal timing diagram used to drive the pixel circuit described in any of the above embodiments.

[0177] The signal timing diagram can include two types of signals: a scan signal, i.e. a switching signal, used to control the transistor to turn on and off, and a data signal Vdata, i.e. a grayscale signal, used to write Vdata to the first gate G of the driving transistor Tdrive during the data writing stage, so as to control the light-emitting diode OLED to emit light.

[0178] The scan signal may include: a first scan line L RE The first scan signal "RE" and the second scan line L transmitted on the upper part SNR The second scan signal "SNR" and the third scan line L transmitted upwards. SNW The third scan signal "SNW" transmitted from the upper line, and the light emission control signal line L EM The light emission control signal "EM" is transmitted from the source.

[0179] The data signal Vdata is generated by the third scan line L. SNW The third scan signal “SNW” transmitted up selectively allows the data signal Vdata to be written to the first gate G of the Tdrive.

[0180] It should be noted that the specific connection methods of the scan signals RE, SNR, SNW, EM and the data signal Vdata with the various components in the drive circuit can be found in [reference needed]. Figure 10 Since VDD, VSS, Vini, and Vref are fixed voltage signals, they do not need to be drawn in the timing diagram.

[0181] It should also be noted that the scan signal can be active low, for example, controlling a P-type transistor, or active high, for example, controlling an N-type transistor. Specifically, an active high scan signal means that the transistor is turned on when the scan signal is high, and an active low scan signal means that the transistor is turned on when the scan signal is low.

[0182] In this embodiment, a P-type transistor controlled by the scan signal is used as an example for illustration, meaning that the transistor can be turned on when the scan signal is low. Specifically, as shown... Figure 11 As shown, the pixel-driven process can be divided into four stages: initialization stage ①, compensation stage ②, data writing stage ③, and emission stage ④, which means that one frame of time is divided into four stages executed sequentially.

[0183] 1) During the initialization phase①, among the scan signals RE, SNR, SNW, and EM, only RE and SNR are low. For example, ... Figure 10As shown, a low RE level controls the conduction of transistors T1, T2, and T3; the initialization signal Vini can be written to the gate (G) and source (S) terminals of the Tdrive; a low SNR level controls the conduction of transistor T4; and the reset signal Vref can be written to the drain (D) and gate (BG) terminals of the Tdrive. For example, if Vref = -3V and Vini = 3.7V, then the bottom gate voltage V of the Tdrive... BG =Vref=-3V,V G -V S =Vini-Vini=0V. In addition to initializing the G, S, D and BG terminals of Tdrive, the initialization stage can also assign an initial value to the voltage across capacitor C2 to prevent capacitor C2 from being floating, and can also assign an initial value to the voltage across capacitor C1 to prevent capacitor C1 from being floating. In addition, the anode of the light-emitting transistor can be reset.

[0184] 2) At the end of initialization phase ①, which is the beginning of compensation phase ②, the state of the pixel circuit is: Since Tdrive is a dual-gate P-type transistor, the bottom gate voltage V at this time is... BG =Vref=-3V<0, threshold voltage Vth>0, V G -V S =Vini-Vini=0V<Vth, then Tdrive is in the on state.

[0185] 3) In compensation phase ②, among the scan signals RE, SNR, SNW, and EM, only RE is low. Compared to the initialization phase, SNR has no effect. This means the reset signal Vref will no longer be continuously supplied to the D and BG terminals, and the voltages at the D and BG terminals may change from their original Vref values. For example, ... Figure 10 As shown, a low level RE can control T1, T2, and T3 to conduct. At this time, Tdrive is also in a conducting state. Therefore, a conducting loop is formed along T1, T2, Tdrive, and T3. Vini can be injected from the source to the drain and then into the gate, thereby raising the voltage of the drain and gate.

[0186] It should be noted that, according to the inventors' research, it is also possible to control only T3 to be turned on during the compensation stage, while T1 and T2 are not turned on. Although this scheme can also write the S-terminal voltage to the D-terminal and then to the BG-terminal, the S-terminal voltage will drop as a result, which may lead to insufficient compensation rate. Therefore, in this embodiment of the application, by controlling T1 and T2 to be turned on during the compensation stage ②, the initialization signal Vini on the initialization signal line can continuously supply power to the S-terminal of Tdrive, thereby improving the compensation rate.

[0187] After the gate-gate voltage (BG) of the Tdrive is raised, the threshold voltage (Vth) will shift from its original positive value to a negative bias until Vth = 0, at which point the Tdrive transitions from the on state to the off state. When the Tdrive is off, the path between the source (S) and drain (D) terminals is broken, and the voltage between the drain (D) and gate-gate voltage (BG) remains constant. At this time, capacitor C1 can maintain the voltage Vth when the threshold voltage Vth = 0. BG Store it.

[0188] It should be noted that the compensation process is not limited by the data writing time, such as Figure 12 As shown, the compensation period is longer, and the compensation is more comprehensive.

[0189] It should also be noted that, within one frame, since the compensation phase and the data writing phase can be independent of each other, the threshold voltage Vth of Tdrive in all pixel circuits can be compensated first, making the threshold voltage Vth of Tdrive in all pixel circuits on the display panel 0, and then data writing can be performed. Therefore, the data writing phase and the compensation phase can be separated, so that the compensation process is not limited by the data writing time, and the compensation is more thorough. At the same time, during the compensation process, the initialization module and the reset module can use the initialization signal on the initialization signal line and the reset signal on the reset signal line to adjust the voltage of the second gate of the driving transistor, thereby adjusting the threshold voltage of the driving transistor. For example, if the top gate and source voltages of the driving transistor remain unchanged, and the bottom gate voltage changes, the threshold voltage Vth of the driving transistor can be made to drift to 0 and remain unchanged. Since the threshold voltage Vth of all driving transistors on the display panel is 0, the difference in compensation effect at different gray levels is avoided, and the uniformity of display brightness of the display panel is improved.

[0190] 4) At the end of compensation phase ②, which is the beginning of data writing phase ③, the state of the pixel circuit is: Tdrive is off, and capacitor C1 stores the Vth that maintains the threshold voltage Vth = 0. BG Capacitor C2 stores the voltage difference V. G -V S =0V.

[0191] 5) In the early stage of data writing phase ③, among the scan signals RE, SNR, SNW, and EM, only SNW is low. For example, ... Figure 10 As shown, a low SNW level can control T5 to conduct, and the data signal Vdata can be written to the first gate G of the driving transistor Tdrive. Since the light-emitting control module is in the off state, capacitor C2 has no conducting loop, meaning one end is floating. Therefore, based on the coupling effect of capacitor C2, V... S Will follow V G The voltage changes abruptly because the voltage difference stored in capacitor C2 is 0V, therefore V G=V S .

[0192] Then, EM transitions from high to low, and the light-emitting control module 160 changes from off to on. The light-emitting control module 160 transmits the first power signal VDD to the second electrode S. Since the data writing module is still on at this time, the two ends of capacitor C2 are connected to the VDD and Vdata signals respectively, and are not in a floating state. Therefore, there is no coupling effect; that is, the voltage at one end will not change with the voltage change at the other end. Thus, Vs = VDD, V... G =Vdata. At the same time, since the reset module 130 is turned off, the setting of the first storage module 170 and the voltage at the connection terminal of the second gate BG change, maintaining the previous state Vth = 0.

[0193] 6) At the end of data writing stage ③, which is the beginning of light emission stage ④, the state of the pixel circuit is: capacitor C2 stores the voltage difference V. G —V S =Vdata—VDD, capacitor C1 stores the V data that maintains the threshold voltage Vth = 0. BG .

[0194] 7) During the light-emitting stage ④, among the scanning signals RE, SNR, SNW, and EM, only EM is at a low level. For example, ... Figure 10 As shown, EM is still low, T6 is on and T5 is off. The first power supply signal VDD can be written to the source of Tdrive through T6. At this time, Vs = VDD remains unchanged, and capacitor C2 stores the voltage difference V. G —V S =Vdata - VDD remains unchanged, then V G =Vdata remains unchanged. At this time, in the conduction loop formed by VDD, T6, Tdrive, OLED, and VSS, a driving current can be generated to drive the OLED to emit light. The formula for the current controlling the OLED's light emission is "i = k(V GS -Vth) 2 "where k is a constant", which can be interpreted as "Vth=0, V GS Substituting "=Vdata-VDD" into the current formula, we find that the current i is only related to Vdata-VDD and not to Vth. Therefore, by separating the compensation stage from the data writing stage, we can not only keep the Vth of all driving transistors constant at 0, improving the uniformity of display brightness, but also achieve Vth compensation, further improving the display effect.

[0195] See Figure 13 , Figure 13This is a schematic diagram of a display device provided in this application. The display device may include a display panel and may be at least one of wearable devices, cameras, mobile phones, tablets, displays, televisions, and vehicle-mounted display terminals.

[0196] The display panel includes the pixel circuit provided in any of the above embodiments, and the display device includes the display panel. Therefore, the display device and the display panel have all the beneficial effects of the above-described display panel.

[0197] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0198] It should be understood that in the embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0199] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized in that, Includes driving transistors, initialization module, reset module, and light-emitting module; The driving transistor includes a first gate, a second gate, a first electrode, and a second electrode; The first terminal of the driving transistor is connected to the first power supply line; The initialization module is connected to the initialization signal line, the first gate and the first electrode of the driving transistor; The reset module is connected to the reset signal line, the second gate and the second electrode of the driving transistor; The light-emitting module is connected to the second electrode of the driving transistor and the second power supply line; The initialization module and the reset module are used to adjust the threshold voltage of the driving transistor using the initialization signal on the initialization signal line and the reset signal on the reset signal line. The initialization module includes a first initialization submodule and a second initialization submodule; The first initialization submodule is connected to the initialization signal line and the first gate of the driving transistor; The second initialization submodule is connected to the first gate and the first electrode of the driving transistor; The reset module includes a first reset submodule and a second reset module; the first reset module is connected to the second gate and the second electrode of the driving transistor; the second reset module is connected to the reset signal line and the second gate of the driving transistor. The control terminal of the initialization module and the control terminal of the first reset submodule are both connected to the first scan line; the control terminal of the second reset submodule is connected to the second scan line; the first scan signal on the first scan line is a line-by-line scan signal, used to turn on the initialization module and the first reset submodule line by line in one frame time; the second scan signal on the second scan line is a line-by-line scan signal, used to turn on the second reset submodule line by line in one frame time. The pixel circuit further includes: a first storage module, connected to the second gate of the driving transistor and the first power supply line; the first storage module is used to store a voltage signal that maintains the threshold voltage of the driving transistor at a predetermined value.

2. The pixel circuit according to claim 1, characterized in that, The control terminals of the first initialization submodule and the second initialization submodule are connected to the same scanning signal.

3. The pixel circuit according to claim 1 or 2, characterized in that, The control terminals of the first reset submodule and the second reset submodule are connected to different scan signals.

4. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes a data writing module, which is connected to the data line and the first gate of the driving transistor.

5. The pixel circuit according to claim 4, characterized in that, The control terminal of the data writing module is connected to the third scan line.

6. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes a light-emitting control module, which is connected to the first power line and the first electrode of the driving transistor, and the control terminal of the light-emitting control module is connected to the light-emitting control signal line.

7. The pixel circuit according to claim 1, characterized in that, The driving transistor includes a P-type transistor.

8. The pixel circuit according to claim 7, characterized in that, The driving transistor includes a P-type low-temperature polycrystalline silicon transistor.

9. The pixel circuit according to claim 8, characterized in that, The voltage of the initialization signal is greater than the voltage of the reset signal.

10. The pixel circuit according to claim 9, characterized in that, The voltage of the reset signal is less than 0.

11. The pixel circuit according to claim 9, characterized in that, The initialization signal is greater than the minimum value of the data signal and less than the maximum value of the data signal.

12. The pixel circuit according to claim 11, characterized in that, The difference between the minimum value of the initialization signal and the minimum value of the data signal is greater than or equal to a preset value, and the difference between the maximum value of the data signal and the initialization signal is greater than or equal to the preset value.

13. The pixel circuit according to claim 12, characterized in that, The preset value is half the difference between the maximum value and the minimum value of the data signal.

14. The pixel circuit according to claim 12, characterized in that, The initialization module and the reset module are used to adjust the threshold voltage of the driving transistor to a predetermined value.

15. The pixel circuit according to claim 14, characterized in that, The predetermined value includes 0.

16. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: The second storage module is connected to the first gate and the first electrode of the driving transistor.

17. The pixel circuit according to claim 16, characterized in that, The second storage module is used to store the data signals transmitted via the data line.

18. The pixel circuit according to claim 1, characterized in that, The initialization module includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the initialization signal line, and the second terminal of the first transistor is connected to the first gate of the driving transistor. The gate of the first transistor is connected to the first scan line. The first terminal of the second transistor is connected to the first gate of the driving transistor, and the second terminal of the second transistor is connected to the first terminal of the driving transistor. The gate of the second transistor is connected to the first scan line. The reset module includes a third transistor and a fourth transistor. The first terminal of the third transistor is connected to the second terminal of the driving transistor, the second terminal of the third transistor is connected to the second gate of the driving transistor, and the gate of the third transistor is connected to the first scan line. The first terminal of the fourth transistor is connected to the reset signal line, the second terminal of the fourth transistor is connected to the second gate of the driving transistor, and the gate of the fourth transistor is connected to the second scan line.

19. A driving method for a pixel circuit, characterized in that, Applied to a pixel circuit as described in any one of claims 1 to 18, the method comprises: In the first stage, the initialization module transmits the initialization signal on the initialization signal line to the first gate and first electrode of the driving transistor, and the reset module transmits the reset signal on the reset signal line to the second gate and second electrode of the driving transistor. In the second stage, the initialization module and the reset module respond to the initialization signal to turn on the driving transistor, and the first storage module stores the voltage of the second gate of the driving transistor when it is in the off state, so as to fix the threshold voltage of the driving transistor as a predetermined value. In the third stage, the data writing module transmits the data signal on the data line to the first gate of the driving transistor; In the fourth stage, the light-emitting control module is turned on, and the driving transistor generates a driving current according to the data signal to drive the light-emitting module to emit light.

20. A display panel, characterized in that, The display panel includes the pixel circuitry as described in any one of claims 1 to 18.

21. A display device, characterized in that, The display device includes the display panel as described in claim 20.

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