A gate drive circuit

Abstract

The application discloses a gate driving circuit, which comprises a plurality of cascaded GOA units, an nth-stage GOA unit comprises a pull-up module and a random detection module, the random detection module and the pull-up module are connected with a first node, the pull-up module is used for outputting a plurality of row write control signals, the random detection module comprises an electric energy storage unit, the random detection module is used for charging the electric energy storage unit when a preset signal is received in a driving period, the potential of the first node is raised to make the selected mth-row write control signal stable, and the nth-stage GOA unit can normally output the mth-row write control signal, so that the display panel can be normally displayed.

Description

Technical Field

[0001] This application relates to the field of display panel driving technology, and more specifically to a gate driving circuit. Background Technology

[0002] Gate Driver On Array (GOA) is a method that uses existing thin-film transistor liquid crystal display array manufacturing processes to fabricate the gate row scanning drive signal circuit on the array substrate, thereby achieving a row-by-row scanning drive method for the gate. This eliminates the need for the gate drive circuit in the panel, which has the advantages of reducing panel production costs and enabling narrow bezel designs, and is used in a variety of displays.

[0003] Therefore, in order to perform external compensation for pixels, the GOA circuit needs to provide a stable write control signal WR[n]. Currently, in order to minimize the number of thin-film transistors and achieve a narrow bezel design for the panel, the GOA circuit usually adopts a single Q-point control method. In order to ensure the high potential of the first node Q in the display stage, the capacitance value of capacitor C1 connected to the output terminal of the nth stage transmission signal Cout[n] is much larger than the capacitance value of capacitor C2 connected to the signal output terminal. Thus, in the random detection stage, due to the voltage division effect of capacitor C1, the Q point cannot be coupled to a higher level, resulting in a low peak voltage of the write control signal (WR[n]) output by the signal output terminal, which cannot complete the normal detection process. Summary of the Invention

[0004] To solve or improve the above problems, embodiments of this application provide a gate driving circuit.

[0005] This application provides a gate drive circuit including multiple cascaded GOA units, wherein the nth GOA unit includes a pull-up module and a random detection module;

[0006] The pull-up module is connected to the first node and is used to output multi-line write control signals;

[0007] The random detection module includes a power storage unit and is connected to the first node. When the random detection module receives a preset signal during the drive cycle, it charges the power storage unit to increase the potential of the first node so that the selected m-th row write control signal remains stable; where m and n are positive integers.

[0008] In some embodiments, the energy storage unit includes a first capacitor connected to the first node, a first input terminal of the random detection module connected to a first power supply high voltage, and a first control terminal of the random detection module connected to a reset signal.

[0009] The random detection module is used to charge the first capacitor to the high voltage of the first power supply when it receives the reset signal during the random detection phase of the driving cycle, thereby increasing the potential of the first node so that the m-th row write control signal remains stable.

[0010] In some embodiments, the energy storage unit further includes a second capacitor, the output terminal of the random detection module is connected to a second node, the second input terminal of the random detection module is connected to a second power supply high voltage, the second power supply high voltage is lower than the first power supply high voltage, and the third input terminal of the random detection module is connected to a pull-up control signal.

[0011] The random detection module is also used to charge the second capacitor to the high voltage of the second power supply through the second node when the pull-up control signal is received during the row selection phase of the driving cycle, thereby increasing the potential of the first node so that the m-th row write control signal remains stable.

[0012] In some embodiments, the random detection module further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0013] The gates of the first transistor, the fourth transistor, and the sixth transistor are all the first control terminals of the random detection module;

[0014] The drain of the first transistor is connected to the third node QB, the source of the first transistor is connected to the drain of the second transistor, and the source of the second transistor is connected to the third power supply high voltage.

[0015] The drain of the third transistor is connected to one end of the second capacitor, and the other end of the second capacitor and the gate of the third transistor are connected to the second node.

[0016] The source of the third transistor and the drain of the fourth transistor are both connected to the gate of the fifth transistor, and the source of the fourth transistor is connected to the first node.

[0017] The drain of the fifth transistor is the first input terminal of the random detection module, the source of the fifth transistor is connected to the drain of the sixth transistor, the source of the sixth transistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the first node.

[0018] In some embodiments, the random detection module further includes a seventh transistor, an eighth transistor, and a ninth transistor;

[0019] The seventh transistor and the eighth transistor share a common gate. The drain of the seventh transistor is the third input terminal of the random detection module. The source of the seventh transistor and the drain of the eighth transistor are both connected to the source of the ninth transistor. The source of the eighth transistor is connected to the second node.

[0020] One end of the second capacitor is connected to the second node and the gate of the third transistor, respectively. The drain of the ninth transistor is the second input terminal of the random detection module, and the other end of the second capacitor is connected to the drain of the ninth transistor.

[0021] In some embodiments, the second control terminal of the random detection module is connected to the random detection row selection and reset signal. The random detection module is used to discharge the second node and the first capacitor simultaneously when the random detection row selection and reset signal received during the random detection phase is at a high level.

[0022] In some embodiments, the random detection module further includes a tenth transistor, which reuses the gate of the seventh transistor and the gate of the eighth transistor as the second control terminal of the random detection module. The source of the tenth transistor is connected to a first low-voltage power supply, the gate of the tenth transistor is connected to a global reset signal, and the drain of the tenth transistor is connected to the source of the sixth transistor.

[0023] In some embodiments, the pull-up module includes a third capacitor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor;

[0024] One end of the third capacitor, the gate of the eleventh transistor, the gate of the twelfth transistor, the gate of the thirteenth transistor, the gate of the fourteenth transistor, and the gate of the fifteenth transistor are all connected to the first node.

[0025] The drain of the eleventh transistor is connected to the first clock signal, and the other end of the third capacitor is connected to the source of the eleventh transistor. The source of the eleventh transistor is used to output the nth stage transmission signal.

[0026] The drain of the twelfth transistor is connected to the second clock signal, and the source of the twelfth transistor is used to output the m-th row write control signal.

[0027] The drain of the thirteenth transistor is connected to the third clock signal, and the source of the thirteenth transistor is used to output the (m+1)th row write control signal.

[0028] The drain of the fourteenth transistor is connected to the fourth clock signal, and the fourteenth transistor is used to output the write control signal for the (m+2)th row.

[0029] The drain of the fifteenth transistor is connected to the fifth clock signal, and the source of the fifteenth transistor is used to output the write control signal for the (m+3)th row.

[0030] In some embodiments, the nth-level GOA unit further includes a pull-up control module, which is connected to the output terminal of the random detection module and is used to pull up the potential of the output terminal of the random detection module.

[0031] In some embodiments, the pull-up control module includes a sixteenth transistor and a seventeenth transistor;

[0032] The drain of the sixteenth transistor is connected to the high voltage of the second power supply. The gates of the sixteenth transistor and the seventeenth transistor are both connected to the pull-up control signal. The source of the sixteenth transistor is connected to the drain of the seventeenth transistor, and the source of the seventeenth transistor is connected to the first node.

[0033] The gate drive circuit provided in this application embodiment includes multiple cascaded GOA units. The nth GOA unit includes a pull-up module and a random detection module. Both the random detection module and the pull-up module are connected to the first node. The pull-up module is used to output multi-line write control signals. The random detection module includes a power storage unit. When the random detection module receives a preset signal during the drive cycle, it charges the power storage unit. The potential of the first node is increased through the power storage unit to keep the selected mth line write control signal stable, so that the nth GOA unit can output the mth line write control signal normally, thereby ensuring that the display panel displays normally. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the gate driving circuit provided in an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of the cascaded structure of the gate drive circuit provided in the embodiments of this application;

[0037] Figure 3 This is a circuit diagram of the gate driving circuit provided in an embodiment of this application;

[0038] Figure 4This is a timing diagram provided in the embodiments of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0040] In the description of this application, it should be understood that the terms "one end," "the other end," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, a link, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0042] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed. In the above embodiments, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0043] The display panel in this application embodiment can be used in mobile phones, tablets, desktop computers, laptops, e-readers, handheld computers, electronic display screens, laptops, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) / virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0044] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0045] Please see Figure 1 , Figure 1 This is a schematic diagram of the gate driving circuit provided in this application. A gate driving circuit includes multiple cascaded GOA units, wherein the nth GOA unit includes a pull-up module 10 and a random detection module 20.

[0046] The pull-up module 10 is connected to the first node Q and is used to output multi-line write control signals;

[0047] The random detection module 20 includes a power storage unit 21. The random detection module 20 is connected to the first node Q. When the random detection module 20 receives a preset signal during the drive cycle, it charges the power storage unit 21 to increase the potential of the first node Q so that the selected m-th row write control signal WR[m] remains stable; where m and n are positive integers.

[0048] Specifically, such as Figure 1 As shown, the pull-up module is connected to the first node Q and is used to output multiple rows of write control signals, such as the first row write control signal WR1, the second row write control signal WR2, the third row write control signal WR3, the fourth row write control signal WR4, etc. The random detection module 20 is connected to the first node Q and includes a power storage unit 21. When the random detection module 20 receives a preset signal during the drive cycle, it charges the power storage unit 21, raising the potential of the first node Q so that the selected m-th row write control signal WR[m] remains stable.

[0049] In some embodiments of this application, the energy storage unit 21 includes a first capacitor C4, the first capacitor C4 is connected to the first node Q, the first input terminal of the random detection module 20 is connected to the first power supply high voltage VGH2, and the first control terminal of the random detection module 20 is connected to the reset signal RESET.

[0050] The random detection module 20 is used to charge the first capacitor C4 to the first power supply high voltage VGH2 when the reset signal RESET is received during the random detection phase of the driving cycle, thereby increasing the potential of the first node Q so that the m-th row write control signal WR[m] remains stable.

[0051] Specifically, such as Figure 2 As shown, the energy storage unit 21 includes a first capacitor C4, one end of which is connected to the first node Q. The first input terminal of the random detection module 20 is connected to the first power supply high voltage VGH2, and the first control terminal of the random detection module 20 is connected to the reset signal RESET. When the first control terminal of the random detection module 20 receives the reset signal RESET during the random detection phase of the driving cycle, it charges the first capacitor C4 through the first power supply high voltage VGH2 connected to the first input terminal of the random detection module 20. Since one end of the first capacitor C4 is connected to the first node Q, charging the first capacitor C4 can increase the potential of the first node Q, so that the m-th row write control signal WR[m] remains stable.

[0052] In some embodiments of this application, the energy storage unit 21 further includes a second capacitor C3, the output terminal of the random detection module 20 is connected to the second node M, the second input terminal of the random detection module 20 is connected to the second power supply high voltage VGH, the second power supply high voltage VGH is less than the first power supply high voltage VGH2, and the third input terminal of the random detection module 20 is connected to the pull-up control signal Cout-PU.

[0053] The random detection module 20 is further configured to charge the second capacitor C3 to the second power supply high voltage VGH through the second node M when the pull-up control signal Cout-PU is received during the row selection phase of the driving cycle, thereby increasing the potential of the first node Q so that the m-th row write control signal WR[m] remains stable.

[0054] Specifically, the energy storage unit 21 also includes a second capacitor C3. The output terminal of the random detection module 20 is connected to the second node M. The second input terminal of the random detection module 20 is connected to the second power supply high voltage VGH. The second input terminal of the random detection module 20 is connected to one end of the second capacitor C3, and the other end of the second capacitor C3 is connected to the second node M. The third input terminal of the random detection module 20 is connected to the pull-up control signal Cout-PU. Thus, when the third input terminal of the random detection module 20 receives the pull-up control signal Cout-PU during the row selection phase of the driving cycle, it pulls up the potential of the second node M, and the potential of the second node M is pulled up to the second power supply high voltage VGH. Since the second capacitor C3 is connected to the second node M, it can be charged to the second power supply high voltage VGH, where the second power supply high voltage VGH is less than the first power supply high voltage VGH2. This raises the potential of the first node Q so that the m-th row write control signal WR[m] remains stable. It should be noted that the row selection phase precedes the random detection phase.

[0055] In some embodiments of this application, the random detection module 20 further includes a first transistor T67, a second transistor T66, a third transistor T64, a fourth transistor T65, a fifth transistor T68, and a sixth transistor T69;

[0056] The gates of the first transistor T67, the fourth transistor T65, and the sixth transistor T69 are all the first control terminals of the random detection module 20.

[0057] The drain of the first transistor T67 is connected to the third node QB, the source of the first transistor T67 is connected to the drain of the second transistor T66, and the source of the second transistor T66 is connected to the third power supply high voltage VGH1.

[0058] The drain of the third transistor T64 is connected to one end of the second capacitor C3, and the other end of the second capacitor C3 and the gate of the third transistor T64 are connected to the second node M.

[0059] The source of the third transistor T64 and the drain of the fourth transistor T65 are both connected to the gate of the fifth transistor T68, and the source of the fourth transistor T65 is connected to the first node Q.

[0060] The drain of the fifth transistor T68 is the first input terminal of the random detection module 20. The source of the fifth transistor T68 is connected to the drain of the sixth transistor T69. The source of the sixth transistor T69 is connected to one end of the first capacitor C4. The other end of the first capacitor C4 is connected to the first node Q.

[0061] In some embodiments of this application, the random detection module 20 further includes a seventh transistor T61, an eighth transistor T62, and a ninth transistor T63;

[0062] The seventh transistor T61 and the eighth transistor T62 share a common gate. The drain of the seventh transistor T61 is the third input terminal of the random detection module 20. The source of the seventh transistor T61 and the drain of the eighth transistor T62 are both connected to the source of the ninth transistor T63. The source of the eighth transistor T62 is connected to the second node M.

[0063] One end of the second capacitor C3 is connected to the gate of the second node M and the third transistor T64, respectively. The drain of the ninth transistor T63 is the second input terminal of the random detection module 20, and the other end of the second capacitor C3 is connected to the drain of the ninth transistor T63.

[0064] In some embodiments of this application, the second control terminal of the random detection module 20 is connected to the random detection row selection and reset signal LSP. The random detection module 20 is used to discharge the second node M and the first capacitor C4 simultaneously when the random detection row selection and reset signal LSP received during the random detection phase is at a high level.

[0065] In some embodiments of this application, the random detection module 20 further includes a tenth transistor T69-1, which reuses the gate of the seventh transistor T61 and the gate of the eighth transistor T62 as the second control terminal of the random detection module 20. The source of the tenth transistor T69-1 is connected to the first power supply low voltage VGL, the gate of the tenth transistor T69-1 is connected to the global reset signal VST, and the drain of the tenth transistor T69-1 is connected to the source of the sixth transistor T69.

[0066] In some embodiments of this application, the pull-up module 10 includes a third capacitor C1, an eleventh transistor T21, a twelfth transistor T22A, a thirteenth transistor T22B, a fourteenth transistor T22C, and a fifteenth transistor T22D;

[0067] One end of the third capacitor C1, the gate of the eleventh transistor T21, the gate of the twelfth transistor T22A, the gate of the thirteenth transistor T22B, the gate of the fourteenth transistor T22C, and the gate of the fifteenth transistor T22D are all connected to the first node Q.

[0068] The drain of the eleventh transistor T21 is connected to the first clock signal CKa, and the other end of the third capacitor C1 is connected to the source of the eleventh transistor T21. The source of the eleventh transistor T21 is used to output the nth stage transmission signal Cout[n].

[0069] The drain of the twelfth transistor T22A is connected to the second clock signal CKb1, and the source of the twelfth transistor T22A is used to output the m-th row write control signal WR1.

[0070] The drain of the thirteenth transistor T22B is connected to the third clock signal CKb2, and the source of the thirteenth transistor T22B is used to output the m+1th row write control signal WR2.

[0071] The drain of the fourteenth transistor T22C is connected to the fourth clock signal CKb3, and the fourteenth transistor T22C is used to output the m+2th row write control signal WR3;

[0072] The drain of the fifteenth transistor T22D is connected to the fifth clock signal CKb4, and the source of the fifteenth transistor T22D is used to output the m+4th row write control signal WR4.

[0073] In some embodiments of this application, the nth level GOA unit further includes a pull-up control module 30, which is connected to the output terminal of the random detection module 20 and is used to pull up the potential of the output terminal of the random detection module 20.

[0074] In some embodiments of this application, the pull-up control module 30 includes a sixteenth transistor T11 and a seventeenth transistor T12;

[0075] The drain of the sixteenth transistor T11 is connected to the second power supply high voltage VGH. The gates of the sixteenth transistor T11 and the seventeenth transistor T12 are both connected to the pull-up control signal Cout-PU. The source of the sixteenth transistor T11 is connected to the drain of the seventeenth transistor T12. The source of the seventeenth transistor T12 is connected to the first node QB.

[0076] Specifically, such as Figure 3 and Figure 4 As shown, in the row selection stage, the second-stage signal terminal Cout-PU is connected to a high level, and the row selection and reset signal LSP is randomly detected to be high level. In this way, the seventh transistor T61, the eighth transistor T62 and the ninth transistor T63 are turned on, thereby inputting the second power supply high voltage VGH connected to the drain of the ninth transistor T63 to point M and storing it through the second capacitor C3.

[0077] At the start of the random detection phase, the reset signal Reset is high, and the high voltage of the first power supply VGH2 (greater than the high voltage of the second power supply VGH) is written to the upper plate of the first capacitor C4, effectively coupling and boosting the potential of the first node Q. During the latter half of the random detection phase, when the random detection row selection and reset signal LSP are high, the second node M is discharged. Simultaneously, the global reset phase VST completes the discharge of the upper plate of the first capacitor C4. This enhances the coupling potential at the mid-Q point during the random detection process, ensuring more efficient output.

[0078] This application proposes a novel multi-line share GOA circuit, such as... Figure 3 The diagram shows a 4-share GOA circuit, where the write control signals required for the four rows of pixels, such as WR1 to WR4, come from the first-stage GOA circuit. This application can increase the coupling potential of the first node Q in the random detection process, ensuring a more complete output.

[0079] In the gate drive circuit, for the first k GOA units, the nk-th stage transfer signal Cout[nk] does not exist. Therefore, in the first k GOA units, a start signal can be set to replace the nk-th stage transfer signal Cout[nk], which will not be described in detail here. Similarly, for the last k GOA units, the (n+k)-th stage transfer signal Cout[n+k] does not exist. Therefore, in the last k GOA units, a start signal or another signal can be set to replace the (n+k)-th stage transfer signal Cout[n+k]. It should be noted that, apart from the above differences, the circuit structure and signal connections of the first k GOA units and the last k GOA units are the same as those of other GOA units, which will not be repeated here. k is a positive integer, and the value of k can be 1, 2, 3, 4, 5, 6 or even more.

[0080] For example, Figure 2Taking the cascaded (n-1)th, nth, and (n+1)th level GOA units as an example. When the (n-1)th level GOA unit outputs the (n-1)th level transmission signal Cout[n-1], this signal is at a high potential and is used to control the operation of the nth level GOA unit. When the nth level GOA unit starts working, it outputs the nth level transmission signal Cout[n], which is at a high potential. This signal turns on the transistor switch of each pixel in a row of the display panel and charges the pixel electrode in each pixel through a data signal. The nth level transmission signal Cout[n] is then used to control the operation of the (n+1)th level GOA unit. When the (n+1)th level GOA unit is working, the (n+1)th level transmission signal Cout[n+1] output by the (n+1)th level GOA unit is at a high potential, and at the same time, the (n+1)th level transmission signal Cout[n+1] is used to pull down the potential of the (n)th level transmission signal Cout[n].

[0081] In some embodiments, the gate drive circuit further includes an inverter 40, which includes a 30th transistor T51A, a 31st transistor T51B, a 32nd transistor T52, a 33rd transistor T53, a 34th transistor T54, and a 35th transistor T56. The gate and drain of the 30th transistor T51A, the gate of the 31st transistor T51B, and the drain of the 33rd transistor T53 are connected to a low-frequency clock signal LC. The source of the 30th transistor T51A is connected to the drain of the 31st transistor T51B, and the source of the 31st transistor T51B is connected to the drain of the 32nd transistor T52 and the gate of the 33rd transistor T53. The gates of the thirty-second transistor T52 and the thirty-fourth transistor T54 are connected to the first node Q. The source of the thirty-second transistor T52 is connected to the third low-potential signal terminal VGL3. The source of the thirty-third transistor T53 is connected to the third node QB. The drain of the thirty-fourth transistor T54 is connected to the third node QB. The drain of the thirty-fifth transistor T56 is connected to the third node QB. The source of the thirty-fourth transistor T54 is connected to the second low-voltage power supply VGL1. The source of the thirty-fifth transistor T56 is connected to the second low-voltage power supply VGL1. The gate of the thirty-fifth transistor T56 is connected to the second stage signal transmission terminal Cout-PU. By setting an inverter 40, the potentials of the first node Q and the third node QB are reversed, allowing the circuit to operate normally.

[0082] In some embodiments, the gate drive circuit further includes a leakage protection module 50, which is used to prevent leakage current from the pull-down module 70 and the pull-down sustaining module 60 in the following embodiments. The leakage protection module 50 includes:

[0083] The eighteenth transistor T7_1 and the nineteenth transistor T7_2, the gate of the eighteenth transistor T7_1 and the gate of the nineteenth transistor T7_2 are connected to the first node Q;

[0084] The source of the eighteenth transistor T7_1 is connected to the first control signal N[n], the drain of the eighteenth transistor T7_1 is connected to the source of the nineteenth transistor T7_2, and the drain of the nineteenth transistor T7_2 is connected to the second power supply high voltage VGH.

[0085] In some embodiments, the gate drive circuit further includes a pull-down sustaining module 60, which includes a twentieth transistor T31, a twenty-first transistor T32A, a twenty-second transistor T32B, a twenty-third transistor T32C, and a twenty-fourth transistor T32D. The gates of the twentieth transistor T31, the twentieth transistor T32A, the twentieth transistor T32B, the twentieth transistor T32C, and the twenty-fourth transistor T32D are connected to the third node QB. The drain of the twentieth transistor T31 is connected to a stage transmission signal terminal, which is used to output the nth stage transmission signal Cout[n]. The source of the twentieth transistor T31 is connected to a second low-voltage power supply VGL1. The drain of the twentieth transistor T32A is connected to a first output signal terminal, which is used to output the mth row write control signal WR1. The source of the twentieth transistor T32A is connected to a third low-voltage power supply VGL2. The drain of the 22nd transistor T32B is connected to the second output signal terminal, which is used to output the (m+1)th row write control signal WR2. The source of the 22nd transistor T32B is connected to the third power supply low voltage VGL2. The drain of the 23rd transistor T32C is connected to the third output signal terminal, which is used to output the (m+2)th row write control signal WR3. The source of the 23rd transistor T32C is connected to the third power supply low voltage VGL2. The drain of the 24th transistor T32D is connected to the fourth output signal terminal, which is used to output the (m+3)th row write control signal WR4. The source of the 24th transistor T32D is connected to the third power supply low voltage VGL2. By setting the pull-down sustaining module 60, the potentials of the cascade signal terminal and the first to fourth output signal terminals can be maintained at a low potential.

[0086] In some embodiments, the pull-down sustaining module 60 further includes a 25th transistor T43A and a 26th transistor T44B. The gate of the 25th transistor T43A and the gate of the 26th transistor T44B are connected to the third node QB. The drain of the 25th transistor T43A is connected to the first node Q. The source of the 25th transistor T43A and the drain of the 26th transistor T44B are connected, and the drain of the 26th transistor T44B is connected to the first control signal N[n]. The source of the 26th transistor T44B is connected to the second low power supply voltage VGL1. By connecting the drain of the 26th transistor T44B to the first control signal N[n], the problem of leakage current in the third node QB caused by the negative bias of the threshold voltages of the 25th transistor T43A and the 26th transistor T44B can be avoided, allowing the gate drive circuit to output signals normally and enabling the display panel to display normally.

[0087] In some embodiments, the gate drive circuit further includes a pull-down module 70 connected to the first node for pulling the potential of the first node low; wherein the pull-down module 70 includes: a twenty-seventh transistor T41 and a twenty-eighth transistor T42;

[0088] The gates of the 27th transistor T41 and the 28th transistor T42 are connected to the pull-down control signal Cout-PD;

[0089] One of the drains of the 27th transistor T41 is connected to the first node Q, and the source of the 27th transistor T41 is connected to the drain of the 28th transistor T42.

[0090] The source of the 28th transistor T42 is connected to the second power supply low voltage VGL1.

[0091] In some embodiments, the gate drive circuit further includes a reset module 80, which is connected to the first node Q, and the reset module 80 includes a twenty-ninth transistor T45 and a thirtieth transistor T46.

[0092] The gates of the 29th transistor T45 and the 30th transistor T46 are both connected to the global reset signal terminal VST.

[0093] The drain of the 29th transistor T45 is connected to the first node Q, and the source of the 29th transistor T45 is connected to the drain of the 30th transistor T46.

[0094] The source of the thirtieth transistor T46 is connected to the second power supply low voltage VGL1.

[0095] In some implementations, after a frame ends, the reset module can turn on the 29th transistor T45 and the 30th transistor T46 by outputting a high potential at the global reset signal terminal VST, thereby pulling the first node Q of the GOA circuit low.

[0096] It should be noted that the channel material of these transistors is low-temperature polycrystalline silicon, which not only improves the dynamic performance of the gate drive circuit but also simplifies the fabrication process, structure, and cost. While low-temperature polycrystalline silicon thin-film transistors are a preferred option, they are not the only option. At least one of the aforementioned transistors may also be an indium gallium zinc oxide thin-film transistor.

[0097] The above provides a detailed description of a gate driving circuit provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A gate drive circuit characterized by comprising: It includes multiple cascaded GOA units, wherein the nth level GOA unit includes a pull-up module and a random detection module; The pull-up module is connected to the first node and is used to output multi-line write control signals; The random detection module includes a power storage unit and is connected to the first node. The random detection module is used to charge the power storage unit when a preset signal is received during the drive cycle, thereby increasing the potential of the first node so that the selected m-th row write control signal remains stable; where m and n are positive integers. The energy storage unit includes a first capacitor and a second capacitor. The first capacitor is connected to the first node. The first input terminal of the random detection module is connected to the first high voltage power supply. The first control terminal of the random detection module is connected to the reset signal. The output terminal of the random detection module is connected to the second node. The second input terminal of the random detection module is connected to the second high voltage power supply, which is lower than the first high voltage power supply. The third input terminal of the random detection module is connected to the pull-up control signal. The random detection module is used to charge the first capacitor to the high voltage of the first power supply when the reset signal is received during the random detection phase of the driving cycle, thereby increasing the potential of the first node so that the m-th row write control signal remains stable. The random detection module is also used to charge the second capacitor to the high voltage of the second power supply through the second node when the pull-up control signal is received during the row selection phase of the driving cycle, thereby increasing the potential of the first node so that the m-th row write control signal remains stable.

2. The gate drive circuit according to claim 1, characterized by The random detection module further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The gates of the first transistor, the fourth transistor, and the sixth transistor are all the first control terminals of the random detection module; The drain of the first transistor is connected to the third node, the source of the first transistor is connected to the drain of the second transistor, and the source of the second transistor is connected to the third power supply high voltage. The drain of the third transistor is connected to one end of the second capacitor, and the other end of the second capacitor and the gate of the third transistor are connected to the second node. The source of the third transistor and the drain of the fourth transistor are both connected to the gate of the fifth transistor, and the source of the fourth transistor is connected to the first node. The drain of the fifth transistor is the first input terminal of the random detection module, the source of the fifth transistor is connected to the drain of the sixth transistor, the source of the sixth transistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the first node.

3. The gate drive circuit according to claim 2, characterized by The random detection module also includes a seventh transistor, an eighth transistor, and a ninth transistor; The seventh transistor and the eighth transistor share a common gate. The drain of the seventh transistor is the third input terminal of the random detection module. The source of the seventh transistor and the drain of the eighth transistor are both connected to the source of the ninth transistor. The source of the eighth transistor is connected to the second node. One end of the second capacitor is connected to the second node and the gate of the third transistor, respectively. The drain of the ninth transistor is the second input terminal of the random detection module, and the other end of the second capacitor is connected to the drain of the ninth transistor.

4. The gate drive circuit according to claim 3, characterized by The second control terminal of the random detection module is connected to the random detection row selection and reset signal. The random detection module is used to discharge the second node and the first capacitor simultaneously when the random detection row selection and reset signal received during the random detection phase is at a high level.

5. The gate drive circuit according to claim 4, characterized in that The random detection module further includes a tenth transistor, which reuses the gate of the seventh transistor and the gate of the eighth transistor as the second control terminal of the random detection module. The source of the tenth transistor is connected to the first power supply at a low voltage, the gate of the tenth transistor is connected to the global reset signal, and the drain of the tenth transistor is connected to the source of the sixth transistor.

6. The gate drive circuit according to claim 5, characterized by The pull-up module includes a third capacitor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; One end of the third capacitor, the gate of the eleventh transistor, the gate of the twelfth transistor, the gate of the thirteenth transistor, the gate of the fourteenth transistor, and the gate of the fifteenth transistor are all connected to the first node. The drain of the eleventh transistor is connected to the first clock signal, and the other end of the third capacitor is connected to the source of the eleventh transistor. The source of the eleventh transistor is used to output the nth stage transmission signal. The drain of the twelfth transistor is connected to the second clock signal, and the source of the twelfth transistor is used to output the m-th row write control signal. The drain of the thirteenth transistor is connected to the third clock signal, and the source of the thirteenth transistor is used to output the (m+1)th row write control signal. The drain of the fourteenth transistor is connected to the fourth clock signal, and the fourteenth transistor is used to output the write control signal for the (m+2)th row. The drain of the fifteenth transistor is connected to the fifth clock signal, and the source of the fifteenth transistor is used to output the write control signal for the (m+4)th row.

7. The gate driving circuit according to claim 6, characterized in that, The nth level GOA unit also includes a pull-up control module, which is connected to the output terminal of the random detection module and is used to pull up the potential of the output terminal of the random detection module.

8. The gate driving circuit according to claim 7, characterized in that, The pull-up control module includes a sixteenth transistor and a seventeenth transistor; The drain of the sixteenth transistor is connected to the high voltage of the second power supply. The gates of the sixteenth transistor and the seventeenth transistor are both connected to the pull-up control signal. The source of the sixteenth transistor is connected to the drain of the seventeenth transistor, and the source of the seventeenth transistor is connected to the first node.

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