Compensator and circuit compensation method

Abstract

The present invention relates to circuit compensation technology, and discloses a compensator and a circuit compensation method, wherein the compensator comprises an error calculation unit, a parameter selection unit, and a calculation unit: the error calculation unit is used to obtain the current sampling value of the sampling circuit, and calculate the current error value according to the current sampling value and the preconfigured system expected value; the parameter selection unit is used to determine the zero-pole parameter group according to the comparison result between the current error value and the preset threshold value, and reduce the parameters in the zero-pole parameter group to obtain configurable parameters; the calculation unit is used to obtain the latch parameters of the sampling circuit, and perform multiplication and accumulation calculation according to the latch parameters and the configurable parameters to obtain the compensation result. The present invention can ensure the accuracy of the compensation circuit when performing compensation calculation while reducing the waste of computing resources.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit compensation, and in particular to a compensator and a circuit compensation method. Background Art

[0002] In the field of motor or power closed-loop control, compensation circuits are often required to complete closed-loop control of voltage or current. Using dedicated integrated circuits can efficiently complete the calculation of compensation values ​​for specific transmission systems. In the prior art, most of them support multi-zero and multi-pole compensation circuit structures, but this method consumes a large number of multiplier computing units, which increases the hardware resource cost of the compensator. Summary of the invention

[0003] The present invention provides a compensator and a circuit compensation method, the main purpose of which is to solve the problem of excessive resource consumption when performing compensation calculation in the existing compensation circuit.

[0004] To achieve the above object, the present invention provides a compensator, which includes an error calculation unit, a parameter selection unit, and a calculation unit:

[0005] The error calculation unit is used to obtain a current sampling value of the sampling circuit, and calculate a current error value according to the current sampling value and a preconfigured system expected value;

[0006] The parameter selection unit is used to determine a zero-pole parameter group according to a comparison result between the current error value and a preset threshold value, and to reduce parameters in the zero-pole parameter group to obtain configurable parameters;

[0007] The calculation unit is used to obtain the latch parameters of the sampling circuit, and perform multiplication and accumulation calculation according to the latch parameters and the configurable parameters to obtain a compensation result.

[0008] In one embodiment of the present invention, the error calculation unit calculates the current error value corresponding to the current sampling value and the system expected value by using the following error calculation formula:

[0009] e(n)=command(n)-sample(n)

[0010] Among them, e(n) represents the current error value corresponding to the current sampling value, command(n) represents the system expected value, and sample(n) represents the current sampling value input by the sampling circuit.

[0011] In one embodiment of the present invention, when the parameter selection unit determines the zero-pole parameter group according to the comparison result between the current error value and the preset threshold value, the following steps are included:

[0012] Compare the error value with the threshold value one by one, and obtain the threshold value interval corresponding to the error value according to the comparison result;

[0013] The zero-pole parameter group corresponding to the threshold value interval is determined according to a preset threshold value parameter configuration rule.

[0014] In one embodiment of the present invention, the parameter selection unit reduces the parameters in the zero-pole parameter group respectively by the following formula to obtain the configurable parameters:

[0015]

[0016] k=ceiling(log2(absmax{b0, b1, b2, a0, a1}))

[0017] Among them, A0, A1, B0, B1, B2, A2, B3, and k are configurable parameters, a0, a1, a2, b0, b1, b2, and b3 are parameters in the zero-pole parameter group, absmax means taking the maximum absolute value, ceiling means rounding up, 2 k Expressed as reduction coefficient.

[0018] In an embodiment of the present invention, the parameter selection unit is further used to determine the input parameters calculated by the calculation processing unit according to the latch parameters and the configurable parameters.

[0019] In one embodiment of the present invention, the computing unit includes an input control unit, a computing processing unit, and an output control unit:

[0020] The input control unit is used to receive input parameters and send them to the calculation processing unit;

[0021] The calculation processing unit is used to perform a first calculation on the input parameter to obtain a calculation result;

[0022] The calculation output control unit is used to store the calculation result and perform a second calculation to obtain an output result, and generate a compensation result according to the output result.

[0023] In one embodiment of the present invention, the calculation processing unit includes a multiplier, which is used to perform multiplication calculation on the input parameter to obtain a calculation result;

[0024] The calculation output control unit includes an accumulator, which is used to accumulate the calculation results to obtain output results.

[0025] In one embodiment of the present invention, when the parameter selection unit determines the input parameter calculated by the calculation processing unit according to the latch parameter and the configurable parameter, the steps include:

[0026] Generating a first latch parameter set and a second latch parameter set according to the latch parameter, and generating a first configurable parameter set and a second configurable parameter set according to the configurable parameter;

[0027] A plurality of first input parameter groups are generated according to the combination of the first latch parameter set and the first configurable parameter, and a plurality of second input parameter groups are generated according to the combination of the second latch parameter set and the second configurable parameter.

[0028] In one embodiment of the present invention, the calculation unit comprises the following steps when generating the output result:

[0029] The multiplier performs multiplication calculation on the first input parameters one by one to obtain a first calculation result;

[0030] The accumulator performs accumulation calculation on the first calculation result to obtain an initial first output value;

[0031] The calculation output control unit determines the current first output value according to the comparison result between the initial first output value and the preset first limit value, and uses the current first output value as the second input parameter;

[0032] The multiplier performs a multiplication calculation according to the second input parameter to obtain a second calculation result;

[0033] The accumulator performs accumulation calculation on the second calculation result to obtain an initial second output value;

[0034] The calculation output control unit determines a current second output value according to a comparison result between the initial second output value and a preset second limit value, and uses the second output value as an output result.

[0035] In one embodiment of the present invention, the current first output value is expressed by the following formula:

[0036] y(n)=2 k ·

[0037] (B0·e(n)+B1·e(n-1)+B2·e(n-2)+A0·y(n-1)+A1·y(n-2))

[0038] Wherein, y(n) represents the current first output value, 2 kis represented as the reduction coefficient, A0 is represented as the first configurable parameter in the first input parameter, A1 is represented as the second configurable parameter in the first input parameter, B0 is represented as the fourth configurable parameter in the first input parameter, B1 is represented as the fifth configurable parameter in the first input parameter, B2 is represented as the sixth configurable parameter in the first input parameter, e(n) is represented as the current error value in the first input parameter, e(n-1) is represented as the error value of the previous state in the first input parameter, e(n-2) is represented as the error value of the previous state in the first input parameter, y(n-1) is represented as the first output value of the previous state in the first input parameter, and y(n-2) is represented as the first output value of the previous state in the first input parameter;

[0039] The current second output value is expressed by the following formula:

[0040] u(n)=y(n)+B3·y(n-1)+A2·u(n-1)

[0041] Among them, u(n) represents the current second output value, y(n) represents the current first output value, A2 represents the third configurable parameter in the second input parameter, B3 represents the seventh configurable parameter in the second input parameter, y(n-1) represents the first output value of the previous state in the second input parameter, and u(n-1) represents the second output value of the previous state in the second input parameter.

[0042] In one embodiment of the present invention, the calculation unit comprises the following steps when generating the compensation result:

[0043] The calculation output control unit determines whether the compensator is in an independent compensation mode or a D / Q cross-coupling mode;

[0044] If it is an independent compensation mode, the output value is used as the compensation result;

[0045] If it is a D / Q cross-coupling mode, the input control unit obtains coupling parameters of the D channel and the Q channel;

[0046] The multiplier performs multiplication calculation on the coupling parameter to obtain a third calculation result;

[0047] The calculation output control unit performs addition calculation according to the third calculation result and a preset magnetic flux component to obtain a fourth calculation result;

[0048] The multiplier performs multiplication calculation according to the fourth calculation result and the preset current speed to obtain a fifth calculation result;

[0049] The adder performs cumulative calculation according to the fifth calculation result and the output result to obtain compensation results corresponding to the D channel and the Q channel.

[0050] In one embodiment of the present invention, the compensation results corresponding to the D channel and the Q channel are expressed by the following formula:

[0051] c d (n) = u d (n)+(sample q (n)*L q +Ke q )*speed

[0052] c q (n) = u q (n)+(sample d (n)*L d +Ke d )*speed

[0053] Among them, c d (n) represents the compensation result corresponding to the D channel, c q (n) is the compensation result corresponding to the Q channel, u d (n) represents the output result corresponding to the D channel, u q (n) represents the output result corresponding to the Q channel, sample q (n) represents the current sample value of the Q channel, sample d (n) represents the current sampling value of the D channel, L q is the Q-axis inductance, L d is the D-axis inductance, Ke q Expressed as the Q-axis flux component, Ke d It is expressed as the D-axis magnetic flux component, and speed is expressed as the current speed.

[0054] In order to solve the above problem, the present invention further provides a circuit compensation method, the method comprising:

[0055] Obtaining a current sampling value of the sampling circuit, and calculating a current error value according to the current sampling value and a preconfigured system expected value;

[0056] Determine a zero-pole parameter group according to a comparison result between the current error value and a preset threshold value, and perform reduction according to parameters in the zero-pole parameter group to obtain configurable parameters;

[0057] The latch parameters of the sampling circuit are acquired, and a multiplication and accumulation calculation is performed according to the latch parameters and the configurable parameters to obtain a compensation result.

[0058] In one embodiment of the present invention, performing a multiplication and accumulation calculation according to the latch parameter and the configurable parameter to obtain a compensation result includes:

[0059] Determine an input parameter according to the latch parameter and the configurable parameter;

[0060] Perform multiplication and accumulation calculations according to the input parameters to obtain an output result;

[0061] A compensation result is generated according to the output result.

[0062] In one embodiment of the present invention, the step of determining the input parameter according to the latch parameter and the configurable parameter includes:

[0063] Generating a first latch parameter set and a second latch parameter set according to the latch parameter, and generating a first configurable parameter set and a second configurable parameter set according to the configurable parameter;

[0064] A plurality of first input parameter groups are generated according to the combination of the first latch parameter set and the first configurable parameter, and a plurality of second input parameter groups are generated according to the combination of the second latch parameter set and the second configurable parameter.

[0065] In one embodiment of the present invention, performing multiplication and accumulation calculations according to the input parameters to obtain an output result includes:

[0066] Performing multiplication calculation on the first input parameters one by one to obtain a first calculation result;

[0067] Performing cumulative calculation on the first calculation results to obtain an initial first output value;

[0068] Determine a current first output value according to a comparison result between the initial first output value and the preset first amplitude limit value, and use the current first output value as a second input parameter;

[0069] Perform a multiplication calculation according to the second input parameter to obtain a second calculation result;

[0070] Performing cumulative calculation on the second calculation results to obtain an initial second output value;

[0071] The current second output value is determined according to a comparison result between the initial second output value and the preset second limit value, and the second output value is used as an output result.

[0072] In one embodiment of the present invention, generating a compensation result according to the output result includes:

[0073] Determine whether the compensator is in independent compensation mode or D / Q cross-coupling mode;

[0074] If it is an independent compensation mode, the output value is used as the compensation result;

[0075] If it is D / Q cross coupling mode, the coupling parameters of D channel and Q channel are obtained;

[0076] Performing multiplication calculation on the coupling parameter to obtain a third calculation result;

[0077] Performing an addition calculation based on the third calculation result and a preset magnetic flux component to obtain a fourth calculation result;

[0078] Performing multiplication calculation according to the fourth calculation result and the preset current speed to obtain a fifth calculation result;

[0079] Accumulated calculation is performed according to the fifth calculation result and the output result to obtain compensation results corresponding to the D channel and the Q channel.

[0080] The present invention can share the multiplier circuit in the calculation unit through parameter reduction, saving the hardware resources required for the calculation process; complete the independent compensation calculation or the compensation calculation of the D / Q axis coupling through a certain clock cycle, ensuring the calculation efficiency; realize the cross decoupling in the motor control through the two parallel compensation units set by the D channel and the Q channel; through the zero-pole configuration and selection of the compensator, it can realize the configuration of up to three zero points and three poles, improving the circuit compensation efficiency. Therefore, the compensator and circuit compensation method proposed by the present invention can solve the problem of excessive resource consumption when the existing compensation circuit performs compensation calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figure 1 A functional module diagram of a compensator provided by an embodiment of the present invention when it is in an independent compensation mode;

[0082] Figure 2 A functional module diagram of a compensator provided by an embodiment of the present invention when it is in a D / Q cross-coupling mode;

[0083] Figure 3 A functional module diagram of a computing unit provided by an embodiment of the present invention;

[0084] Figure 4 A schematic diagram of a flow chart of a circuit compensation method provided by an embodiment of the present invention.

[0085] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0086] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0087] like Figure 1 , Figure 2, which is a functional module diagram of a compensator 100 provided by an embodiment of the present invention. According to the functions to be implemented, the compensator 100 may include an error calculation unit 101, a parameter selection unit 102, and a calculation unit 103. The module of the present invention may also be referred to as a unit, which refers to a series of computer program segments that can be executed by the processor of the compensator 100 and can complete fixed functions, which can be stored in a storage chip corresponding to the compensator.

[0088] The error calculation unit 101 is used to obtain a current sampling value of the sampling circuit, and calculate a current error value according to the current sampling value and a preconfigured system expected value.

[0089] In the embodiment of the present invention, the current sampling value includes a current voltage value, a current current value, etc. acquired by a sampling circuit.

[0090] Specifically, in the embodiment of the present invention, the current error value corresponding to the current sampling value and the system expected value may be calculated by the following error calculation formula:

[0091] e(n)=command(n)-sample(n)

[0092] Among them, e(n) represents the current error value corresponding to the current sampling value, command(n) represents the system expected value, and sample(n) represents the current sampling value input by the sampling circuit.

[0093] The system expected value is a value configured by the central processing unit through the system bus.

[0094] In an embodiment of the present invention, the compensator latches the current error value, the error value of the previous state, and the error value of the previous state. After the error value is calculated based on the current sampling value and the system expected value, the error value is updated to the current error value of the compensator, the original latched current error value is updated to the error value of the previous state, and the original latched error value of the previous state is updated to the error value of the previous state.

[0095] At this time, the compensator contains e(n), e(n-1) and e(n-2), where e(n) represents the current error value corresponding to the current sampling value, e(n-1) represents the error value obtained by the last sampling, and e(n-2) represents the error value obtained by the last sampling.

[0096] Furthermore, *(n) represents the current value, *(n-1) represents the value obtained by the last sampling, *(n-2) represents the value obtained by the last sampling, and * can be e (error value), y (two-zero-two-pole output value, hereinafter referred to as the first output value), u (three-zero-three-pole output value, referred to as the second output value), etc.

[0097] The parameter selection unit 102 is used to determine a zero-pole parameter group according to a comparison result between the current error value and a preset threshold value, and perform reduction according to parameters in the zero-pole parameter group to obtain configurable parameters.

[0098] In an embodiment of the present invention, the zero-pole parameter group is composed of multiple pairs of zeros and poles, specifically, it can include three groups of zeros and poles, and the parameter selection of each group of zeros and poles is different; the zero-pole parameter group is selected according to the error value, so that the transmission gain brought by matching different zero-pole parameter groups with different error sizes can be achieved, thereby achieving flexible configuration.

[0099] For example, the zero-pole parameter group may include parameter groups obtained from three groups of parameter configurations: HI_POINT group, MID_POINT group, and LO_POINT, wherein the transmission gain corresponding to the zero-pole of the HI_POINT group is relatively high, the transmission gain corresponding to the zero-pole of the MID_POINT group is medium, and the transmission gain corresponding to the zero-pole of the LO_POINT group is relatively low.

[0100] The present invention does not specifically limit the number and configuration of zero-pole parameter groups. The zero-pole parameter groups may be four groups, five groups, six groups, etc., which may be specifically determined according to the transmission gain to be selected according to different error sizes.

[0101] In an embodiment of the present invention, when the parameter selection unit determines the zero-pole parameter group according to the comparison result between the current error value and the preset threshold value, the following steps are included:

[0102] Compare the error value with the threshold value one by one, and obtain the threshold value interval corresponding to the error value according to the comparison result;

[0103] The zero-pole parameter group corresponding to the threshold value interval is determined according to a preset threshold value parameter configuration rule.

[0104] Specifically, the threshold value is a value corresponding to a pre-configured threshold register. Before the compensator works, the central processing unit can configure the threshold register through the system bus.

[0105] The threshold parameter configuration rule is that when the error value is in different threshold value intervals, different zero-pole parameter groups are selected accordingly; the present invention does not limit the number of threshold registers and the threshold value, and 3 threshold registers, 4 threshold registers, 5 threshold registers, etc. can be set.

[0106] Taking the configuration of four threshold registers HI / MIDHI / MIDLO / LO on the system bus as an example, these four threshold registers need to satisfy: HI>=MIDHI>=MIDLO>=LO. The parameter selection unit can determine the zero-pole parameter group according to the size relationship between e(n) and the four threshold registers; specifically, the error value is compared with the threshold value one by one, that is, the error value e(n) is compared with HI, MIDHI, MIDLO, and LO one by one. When e(n) is greater than or equal to HI or less than or equal to LO, the parameter selection is the HI_POINT group; when e(n) is greater than MIDHI and less than HI, or less than MIDLO and greater than LO, the parameter selection is the MID_POINT group; when e(n) is greater than or equal to MIDLO and less than or equal to MIDHI, the parameter selection is the LO_POINT group.

[0107] In the embodiment of the present invention, the parameters in the zero-pole parameter group can be reduced by the following formula to obtain the configurable parameters:

[0108]

[0109] k = ceiling(log z (absmax{b0, b1, b2, a0, a1}))

[0110] Among them, A0, A1, B0, B1, B2, A2, B3, and k are configurable parameters, a0, a1, a2, b0, b1, b2, and b3 are parameters in the zero-pole parameter group, absmax means taking the maximum absolute value, ceiling means rounding up, 2 k Expressed as reduction coefficient.

[0111] Specifically, 2 k To reduce the coefficients, the multiplication operation in the computing unit can be reduced to a multiplier structure by performing parameter reduction: a decimal with an absolute value less than 1 (other parameters in the input computing unit except the configurable parameters) is multiplied by a signed integer (the reduced parameter).

[0112] For example, it can be a structure of Q31*Int32(n*Int n), where Q31 is a 32-bit signed fixed-point number, in which the highest bit is the sign bit and the remaining bits are decimal bits; and Int32 is a signed integer, in which the highest bit is the sign bit.

[0113] The compensator in the present invention supports a three-zero-three-pole (3P3Z) mode, and can also configure b3 and a2 to be 0 to become a two-zero-two-pole (2P2Z) mode.

[0114] In the embodiment of the present invention, the multiplier circuits in the computing unit can be shared through parameter reduction, thereby saving the hardware resources required for the computing process.

[0115] The calculation unit 103 is used to obtain the latch parameters of the sampling circuit, and perform multiplication and accumulation calculation according to the latch parameters and the configurable parameters to obtain a compensation result.

[0116] See also Figure 3 As shown, in the embodiment of the present invention, the calculation unit 103 includes an input control unit 1031, a calculation processing unit 1032, and an output control unit 1033:

[0117] In the embodiment of the present invention, the parameter selection unit 102 is further configured to determine the input parameters calculated by the calculation processing unit according to the latch parameters and the configurable parameters.

[0118] In the calculation unit 103:

[0119] The input control unit 1031 is used to receive input parameters and send them to the calculation processing unit;

[0120] The calculation processing unit 1032 is used to perform a first calculation on the input parameter to obtain a calculation result;

[0121] The calculation output control unit 1033 is used to store the calculation result and perform a second calculation to obtain an output result, and generate a compensation result according to the output result.

[0122] Further, the calculation processing unit includes a multiplier for performing multiplication calculation on the input parameter to obtain a calculation result;

[0123] The calculation output control unit includes an accumulator, which is used to accumulate the calculation results to obtain output results.

[0124] In an embodiment of the present invention, the computing unit performs a multiplication calculation in each clock cycle; within one clock cycle, it includes: performing a multiplication calculation according to the input parameters determined by the previous clock, and sending the result of the multiplication calculation to the accumulator, and the parameter selection unit determines the input parameters of the next clock cycle and sends them to the calculation input control unit; but in the first clock cycle, it is necessary to calculate the error value, and update the error value to the current error value of the compensator, the parameter selection unit selects a configurable parameter according to the relationship between the current error value and the threshold register, and the parameter selection unit determines the input parameters of the next clock cycle and sends them to the calculation input control unit.

[0125] In an embodiment of the present invention, when the parameter selection unit determines the input parameter calculated by the calculation processing unit according to the latch parameter and the configurable parameter, the steps include:

[0126] Generating a first latch parameter set and a second latch parameter set according to the latch parameter, and generating a first configurable parameter set and a second configurable parameter set according to the configurable parameter;

[0127] A plurality of first input parameter groups are generated according to the combination of the first latch parameter set and the first configurable parameter, and a plurality of second input parameter groups are generated according to the combination of the second latch parameter set and the second configurable parameter.

[0128] In the embodiment of the present invention, the latch parameters include a current error value e(n), an error value e(n-1) of a previous state, an error value e(n-2) of a previous previous state, a current first output value y(n), a previous state first output value y(n-1), a previous previous state first output value y(n-2), and a previous state second output value u(n-1); the configurable parameters include a first configurable parameter A0, a second configurable parameter A1, a third configurable parameter A2, a fourth configurable parameter B0, a fifth configurable parameter B1, a sixth configurable parameter B2, a seventh configurable parameter B3, and an eighth configurable parameter k;

[0129] The first latch parameter set includes: the current error value e(n), the error value e(n-1) of the previous state, the error value e(n-2) of the previous state, the first output value y(n-1) of the previous state, and the first output value y(n-2) of the previous state; the second latch parameter set includes the current first output value y(n), the first output value y(n-1) of the previous state, and the second output value u(n-1) of the previous state;

[0130] The first configurable parameter set includes: a first configurable parameter A0, a second configurable parameter A1, a fourth configurable parameter B0, a fifth configurable parameter B1, and a sixth configurable parameter B2; the second configurable parameter set includes: a third configurable parameter A2, a seventh configurable parameter B3, and an eighth configurable parameter k.

[0131] Further, the first input parameter includes: {fourth configurable parameter B0, current error value e(n)}, {fifth configurable parameter B1, error value e(n-1) of the previous state}, {sixth configurable parameter B2, error value e(n-2) of the previous state}, {first configurable parameter A0, first output value y(n-1) of the previous state}, {second configurable parameter A1, first output value y(n-2) of the previous state};

[0132] The second input parameters include {current first output value y(n)}, {seventh configurable parameter B3, previous state first output value y(n-1)}, {third configurable parameter A2, previous state second output value u(n-1)},

[0133] It should be noted that the current first output value y(n) is calculated by using multiple sets of first input parameters. After the current first output value y(n) is obtained, it is used as the second input parameter for calculation to obtain the current second output value u(n).

[0134] In one embodiment of the present invention, the configurable parameters obtained by parameter reduction are the configurable parameters in the first configurable parameter set, and parameter reduction is not performed on the configurable parameters in the second configurable parameter set; that is, only the parameters used in the first calculation result are reduced.

[0135] In the embodiment of the present invention, the calculation unit comprises the following steps when generating the output result:

[0136] The multiplier in the calculation processing unit performs multiplication calculation on the first input parameters one by one to obtain a first calculation result;

[0137] The accumulator in the calculation output control unit performs accumulation calculation on the first calculation result to obtain an initial first output value;

[0138] The calculation output control unit determines the current first output value according to the comparison result between the initial first output value and the preset first limit value, and uses the current first output value as the second input parameter;

[0139] The multiplier performs a multiplication calculation according to the second input parameter to obtain a second calculation result;

[0140] The accumulator performs accumulation calculation on the second calculation result to obtain an initial second output value;

[0141] The calculation output control unit determines a current second output value according to a comparison result between the initial second output value and a preset second limit value, and uses the second output value as an output result.

[0142] Specifically, the current first output value can be expressed by the following formula:

[0143] y(n)=2 k ·

[0144] (B0·e(n)+B1·e(n-1)+B2·e(n-2)+A0·y(n-1)+A1·y(n-2))

[0145] Wherein, y(n) represents the current first output value, 2 kis represented as the reduction coefficient, A0 is represented as the first configurable parameter in the first input parameter, A1 is represented as the second configurable parameter in the first input parameter, B0 is represented as the fourth configurable parameter in the first input parameter, B1 is represented as the fifth configurable parameter in the first input parameter, B2 is represented as the sixth configurable parameter in the first input parameter, e(n) is represented as the current error value in the first input parameter, e(n-1) is represented as the error value of the previous state in the first input parameter, e(n-2) is represented as the error value of the previous state in the first input parameter, y(n-1) is represented as the first output value of the previous state in the first input parameter, and y(n-2) is represented as the first output value of the previous state in the first input parameter;

[0146] The current second output value can be expressed by the following formula:

[0147] u(n)=y(n)+B3·y(n-1)+A2·u(n-1)

[0148] Among them, u(n) represents the current second output value, y(n) represents the current first output value, A2 represents the third configurable parameter in the second input parameter, B3 represents the seventh configurable parameter in the second input parameter, y(n-1) represents the first output value of the previous state in the second input parameter, and u(n-1) represents the second output value of the previous state in the second input parameter.

[0149] See also Figure 1 , Figure 2 As shown, further, the calculation unit includes the following steps when generating the compensation result:

[0150] The calculation output control unit determines whether the compensator is in an independent compensation mode or a D / Q cross-coupling mode;

[0151] If it is an independent compensation mode, the output value is used as the compensation result;

[0152] If it is a D / Q cross-coupling mode, the input control unit obtains coupling parameters of the D channel and the Q channel;

[0153] The multiplier in the calculation processing unit performs multiplication calculation on the coupling parameter to obtain a third calculation result;

[0154] The calculation output control unit performs addition calculation according to the third calculation result and a preset magnetic flux component to obtain a fourth calculation result;

[0155] The multiplier performs multiplication calculation according to the fourth calculation result and the preset current speed to obtain a fifth calculation result;

[0156] The adder performs cumulative calculation according to the fifth calculation result and the output result to obtain compensation results corresponding to the D channel and the Q channel.

[0157] The coupling parameters include current sampling values ​​of the D channel and the Q channel, the Q-axis inductance, and the D-axis inductance.

[0158] In the embodiment of the present invention, the compensation results corresponding to the D channel and the Q channel can be expressed by the following formula:

[0159] c d (n) = u d (n)+(sample q (n)*L q +Ke q )*speed

[0160] c q (n) = u q (n)+(sample d (n)*L d +Ke d )*speed

[0161] Among them, c d (n) represents the compensation result corresponding to the D channel, c q (n) is the compensation result corresponding to the Q channel, u d (n) represents the output result corresponding to the D channel, u q (n) represents the output result corresponding to the Q channel, sample q (n) represents the current sample value of the Q channel, sample d (n) represents the current sampling value of the D channel, L q is the Q-axis inductance, L d is the D-axis inductance, Ke q Expressed as the Q-axis flux component, Ke d It is expressed as the D-axis magnetic flux component, and speed is expressed as the current speed.

[0162] Specifically, the first limiting value is a value corresponding to a preconfigured yn limiting register. Before the compensator works, the central processing unit can configure the yn limiting register through the system bus; the second limiting value is a value corresponding to a preconfigured un limiting register. Before the compensator works, the central processing unit can configure the un limiting register through the system bus; wherein, the comparison process between the initial first output value and the first limiting value and the comparison process between the initial second output value and the second limiting value are similar to the above-mentioned comparison process between the current error value and the threshold value, and will not be elaborated here.

[0163] The present invention does not limit the number of settings and threshold values of the yn clipping register and the un clipping register, and 2 yn clipping registers / un clipping registers, 3 yn clipping registers / un clipping registers, etc. can be set.

[0164] Taking the system bus configuration of 2 yn clipping registers YN_LO and YN_HI as an example, the calculation output control unit can determine the first output value according to the size relationship between the calculated initial first output value pre_y(n) and the 2 yn clipping registers; specifically, compare the initial first output value with the first clipping value one by one, that is, compare pre_y(n) with YN_LO and YN_HI one by one. If YN_LO <= pre_y(n) <= YN_HI, then y(n) = pre_y(n); if pre_y(n) > YN_HI, then y(n) = YN_HI; if pre_y(n) < YN_LO, then y(n) = YN_LO.

[0165] Taking the system bus configuration of 2 un clipping registers UN_LO and UN_HI as an example, the calculation output control unit can determine the second output value (output result) according to the size relationship between the calculated initial second output value pre_u(n) and the 2 un clipping registers; specifically, compare the initial second output value with the second clipping value one by one, that is, compare pre_u(n) with UN_LO and UN_HI one by one. If UN_LO <= pre_u(n) <= UN_HI, then u(n) = pre_u(n); if pre_u(n) > UN_HI, then u(n) = UN_HI; if pre_u(n) < UN_LO, then u(n) = UN_LO.

[0166] In the embodiment of the present invention, the processing flow of the compensator during compensation is as follows:

[0167] First, the control state machine waits for sampling in the idle mode. After the current sampling signal is triggered (that is, after the sampling circuit acquires the current sampling value), the control state machine enters step one in the next clock cycle;

[0168] Step one: The error calculation unit calculates the current error value e(n) according to the current sampling value. The parameter selection unit determines the configurable parameters according to the relationship between the current error value e(n) and the threshold register, and takes B0 and e(n) in the configurable parameters as the first input parameters and sends them to the input control unit. The control state machine enters step two in the next clock cycle;

[0169] Step 2: The calculation processing unit performs multiplication calculation on the first input parameter transmitted by the input control unit to obtain B0*e(n) and sends it to the calculation output control unit, and the result of the accumulator in the calculation output control unit is B0*e(n). The parameter selection unit updates the first input parameter to B1 and e(n-1), and the control state machine enters step 3 in the next clock cycle;

[0170] Step 3: The calculation processing unit performs multiplication calculation on the first input parameter transmitted by the input control unit to obtain B1*e(n-1) and sends it to the calculation output control unit, and the result of the accumulator in the calculation output control unit is B0*e(n)+B1*e(n-1). The parameter selection unit updates the first input parameter to B2 and e(n-2), and the control state machine enters step 4 in the next clock cycle;

[0171] Step 4: The calculation processing unit performs multiplication calculation on the first input parameter transmitted by the input control unit to obtain B2*e(n-2) and sends it to the calculation output control unit, and the result of the accumulator in the calculation output control unit is B0*e(n)+B1*e(n-1)+B2*e(n-2). The parameter selection unit updates the first input parameter to A0 and y(n-1), and the control state machine enters step 5 in the next clock cycle;

[0172] Step 5: The calculation processing unit performs multiplication calculation on the first input parameter transmitted by the input control unit to obtain A0*y(n-1) and sends it to the calculation output control unit, and the result of the accumulator in the calculation output control unit is B0*e(n)+B1*e(n-1)+B2*e(n-2)+A0*y(n-1). The parameter selection unit updates the first input parameter to A1 and y(n-2), and the control state machine enters step 6 in the next clock cycle;

[0173] Step 6: The calculation processing unit performs multiplication calculation on the first input parameter transmitted by the input control unit to obtain A1*y(n-2) and sends it to the calculation output control unit, and the result of the accumulator in the calculation output control unit is B0*e(n)+B1*e(n-1)+B2*e(n-2)+A0*y(n-1)+A1*y(n-2). k Parameter reduction is performed, so the accumulator result needs to be shifted left by k bits (left shift k bits is equivalent to multiplying by 2 k ), the result of the accumulator is (B0*e(n)+B1*e(n-1)+B2*e(n-2)+A0*y(n-1)+A1*y(n-2))*2 k , the result of the accumulator at this time is used as the initial first output value pre_y(n);

[0174] Compare the initial first output value with the yn limit registers YN_LO and YN_HI (pre-configured by the central processing unit). If YN_LO <= pre_y(n) <= YN_HI, then y(n) = pre_y(n); if pre_y(n) > YN_HI, then y(n) = YN_HI; if pre_y(n) < YN_LO, then y(n) = YN_LO. Latch the result after the clipping calculation as the result y(n) of the accumulator.

[0175] The parameter selection unit updates the second input parameter to B3 and y(n - 1), and controls the state machine to enter step seven in the next clock cycle;

[0176] Step seven: The calculation processing unit performs a multiplication calculation on the second input parameter transmitted by the input control unit to obtain B3 * y(n - 1) and sends it to the calculation output control unit. The result of the accumulator in the calculation output control unit is y(n) + B3 * y(n - 1). The parameter selection unit updates the second input parameter to A2 and u(n - 1), and controls the state machine to enter step eight in the next clock cycle;

[0177] Step eight: The calculation processing unit performs a multiplication calculation on the second input parameter transmitted by the input control unit to obtain A2 * u(n - 1) and sends it to the calculation output control unit. The result of the accumulator in the calculation output control unit is y(n) + B3 * y(n - 1) + A2 * u(n - 1). Use the result of the accumulator at this time as the initial second output value pre_u(n);

[0178] Compare the initial second output value with the un limit registers UN_LO and UN_HI (pre-configured by the central processing unit). If UN_LO <= pre_u(n) <= UN_HI, then u(n) = pre_u(n); if pre_u(n) > UN_HI, then u(n) = UN_HI; if pre_u(n) < UN_LO, then u(n) = UN_LO. Latch the result after the clipping calculation as the result u(n) of the accumulator.

[0179] Determine whether the compensator is in the independent compensation mode or the D / Q cross-coupling mode. If the compensator is currently configured in the independent compensation mode, the compensator outputs the current u(n) as the final output c(n) of the compensator, and controls the state machine to jump to the idle mode in the next clock cycle; if the compensator is currently configured in the D / Q cross-coupling mode, then transmit the coupling parameters sample(n) and L to the input control unit, and control the state machine to enter step nine in the next clock cycle; where the D channel uses sample q (n) and L of the Q channel q , and the Q channel uses sample of the D channel d(n) and L d ;

[0180] Step 9: The calculation processing unit multiplies the coupling parameters transmitted by the input control unit to obtain sample(n)*L and sends it to the calculation output control unit. The calculation output control unit adds the result to the magnetic flux component Ke to obtain sample(n)*L+Ke, and keeps the result of the accumulator unchanged. The parameter selection unit updates the coupling parameters to sample(n)*L+Ke and speed, and the control state machine enters step 10 in the next clock cycle; among them, the D channel adopts the Q-axis magnetic flux component Ke of the Q channel q , the Q channel uses the D-axis magnetic flux component Ke of the D channel d ;

[0181] Step 10: The calculation processing unit multiplies the coupling parameters transmitted by the input control unit to obtain (sample(n)*L+Ke)*speed, and sends it to the calculation output control unit, and obtains the result of the accumulator in the calculation output control unit as u(n)+(sample(n)*L+Ke)*speed, and uses the result of the accumulator as the compensation result after cross-coupling, and controls the state machine to jump to the idle mode in the next clock cycle; wherein, the compensation result after D channel cross-coupling is u d (n)+(sample q (n)*L q +Ke q )*speed, the compensation result after Q channel cross coupling is u q (n)+(sample d (n)*L d +Ke d )*speed.

[0182] Among them, the process of obtaining the first output value y(n) and the second output value u(n) goes through 7 multiplication operations and 6 addition operations. The multiplication operations consume a lot of resources. Through the parameter reduction and shared multiplier structure of the present invention, the resource consumption can be effectively reduced.

[0183] In the embodiment of the present invention, an independent compensation calculation can be completed once every 8 clock cycles or a compensation calculation taking into account the D / Q axis coupling can be completed once every 10 clock cycles, which not only ensures the calculation efficiency but also greatly saves hardware resources by sharing the calculation unit.

[0184] The embodiment of the present application provides a circuit compensation method. The circuit compensation method can be executed by software or hardware installed in a terminal device or a server device. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc. The server can be an independent server or a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, etc.

[0185] Reference Figure 4 FIG. 1 is a flow chart of a circuit compensation method provided by an embodiment of the present invention. In this embodiment, the circuit compensation method includes:

[0186] S1, obtaining a current sampling value of a sampling circuit, and calculating a current error value according to the current sampling value and a preconfigured system expected value;

[0187] S2, determining a zero-pole parameter group according to a comparison result between the current error value and a preset threshold value, and reducing parameters in the zero-pole parameter group to obtain configurable parameters;

[0188] S3. Obtain latch parameters of the sampling circuit, and perform multiplication and accumulation calculations according to the latch parameters and the configurable parameters to obtain compensation results.

[0189] In the embodiment of the present invention, performing a multiplication and accumulation calculation according to the latch parameter and the configurable parameter to obtain a compensation result includes:

[0190] Determine an input parameter according to the latch parameter and the configurable parameter;

[0191] Perform multiplication and accumulation calculations according to the input parameters to obtain an output result.

[0192] A compensation result is generated according to the output result.

[0193] Further, the determining the input parameter according to the latch parameter and the configurable parameter comprises:

[0194] Generating a first latch parameter set and a second latch parameter set according to the latch parameter, and generating a first configurable parameter set and a second configurable parameter set according to the configurable parameter;

[0195] A plurality of first input parameter groups are generated according to the combination of the first latch parameter set and the first configurable parameter, and a plurality of second input parameter groups are generated according to the combination of the second latch parameter set and the second configurable parameter.

[0196] In the embodiment of the present invention, the latch parameters include a current error value e(n), an error value e(n-1) of a previous state, an error value e(n-2) of a previous previous state, a current first output value y(n), a previous state first output value y(n-1), a previous previous state first output value y(n-2), and a previous state second output value u(n-1); the configurable parameters include a first configurable parameter A0, a second configurable parameter A1, a third configurable parameter A2, a fourth configurable parameter B0, a fifth configurable parameter B1, a sixth configurable parameter B2, a seventh configurable parameter B3, and an eighth configurable parameter k;

[0197] The first latch parameter set includes: the current error value e(n), the error value e(n-1) of the previous state, the error value e(n-2) of the previous state, the first output value y(n-1) of the previous state, and the first output value y(n-2) of the previous state; the second latch parameter set includes the current first output value y(n), the first output value y(n-1) of the previous state, and the second output value u(n-1) of the previous state;

[0198] The first configurable parameter set includes: a first configurable parameter A0, a second configurable parameter A1, a fourth configurable parameter B0, a fifth configurable parameter B1, and a sixth configurable parameter B2; the second configurable parameter set includes: a third configurable parameter A2, a seventh configurable parameter B3, and an eighth configurable parameter k.

[0199] Further, the first input parameter includes: {fourth configurable parameter B0, current error value e(n)}, {fifth configurable parameter B1, error value e(n-1) of the previous state}, {sixth configurable parameter B2, error value e(n-2) of the previous state}, {first configurable parameter A0, first output value y(n-1) of the previous state}, {second configurable parameter A1, first output value y(n-2) of the previous state};

[0200] The second input parameters include {current first output value y(n)}, {seventh configurable parameter B3, previous state first output value y(n-1)}, {third configurable parameter A2, previous state second output value u(n-1)},

[0201] It should be noted that the current first output value y(n) is calculated by using multiple sets of first input parameters. After the current first output value y(n) is obtained, it is used as the second input parameter for calculation to obtain the current second output value u(n).

[0202] In detail, performing multiplication and accumulation calculations according to the input parameters to obtain output results includes:

[0203] Performing multiplication calculation on the first input parameters one by one to obtain a first calculation result;

[0204] Performing cumulative calculation on the first calculation results to obtain an initial first output value;

[0205] Determine a current first output value according to a comparison result between the initial first output value and the preset first amplitude limit value, and use the current first output value as a second input parameter;

[0206] Perform a multiplication calculation according to the second input parameter to obtain a second calculation result;

[0207] Performing cumulative calculation on the second calculation results to obtain an initial second output value;

[0208] The current second output value is determined according to a comparison result between the initial second output value and the preset second limit value, and the second output value is used as an output result.

[0209] Specifically, the current first output value can be expressed by the following formula:

[0210] y(n)=2 k ·

[0211] (B0·e(n)+B1·e(n-1)+B2·e(n-2)+A0·y(n-1)+A1·y(n-2))

[0212] Wherein, y(n) represents the current first output value, 2 k is represented as the reduction coefficient, A0 is represented as the first configurable parameter in the first input parameter, A1 is represented as the second configurable parameter in the first input parameter, B0 is represented as the fourth configurable parameter in the first input parameter, B1 is represented as the fifth configurable parameter in the first input parameter, B2 is represented as the sixth configurable parameter in the first input parameter, e(n) is represented as the current error value in the first input parameter, e(n-1) is represented as the error value of the previous state in the first input parameter, e(n-2) is represented as the error value of the previous state in the first input parameter, y(n-1) is represented as the first output value of the previous state in the first input parameter, and y(n-2) is represented as the first output value of the previous state in the first input parameter;

[0213] The current second output value can be expressed by the following formula:

[0214] u(n)=y(n)+B3·y(n-1)+A2·u(n-1)

[0215] Among them, u(n) represents the current second output value, y(n) represents the current first output value, A2 represents the third configurable parameter in the second input parameter, B3 represents the seventh configurable parameter in the second input parameter, y(n-1) represents the first output value of the previous state in the second input parameter, and u(n-1) represents the second output value of the previous state in the second input parameter.

[0216] Further, generating a compensation result according to the output result includes:

[0217] Determine whether the compensator is in independent compensation mode or D / Q cross-coupling mode;

[0218] If it is an independent compensation mode, the output value is used as the compensation result;

[0219] If it is D / Q cross coupling mode, the coupling parameters of D channel and Q channel are obtained;

[0220] Performing multiplication calculation on the coupling parameter to obtain a third calculation result;

[0221] Performing an addition calculation based on the third calculation result and a preset magnetic flux component to obtain a fourth calculation result;

[0222] Performing multiplication calculation according to the fourth calculation result and the preset current speed to obtain a fifth calculation result;

[0223] Accumulated calculation is performed according to the fifth calculation result and the output result to obtain compensation results corresponding to the D channel and the Q channel.

[0224] The coupling parameters include current sampling values ​​of the D channel and the Q channel, the Q-axis inductance, and the D-axis inductance.

[0225] In the embodiment of the present invention, the compensation results corresponding to the D channel and the Q channel can be expressed by the following formula:

[0226] c d (n) = u d (n)+(sample q (n)*L q +Ke q )*speed

[0227] c q (n) = u q (n)+(sample d (n)*L d +Ke d )*speed

[0228] Among them, c d(n) represents the compensation result corresponding to the D channel, c q (n) represents the compensation result corresponding to the Q channel, sample q (n) represents the current sampling value of the Q channel, sample d (n) represents the current sampling value of the D channel, L q is the Q-axis inductor, L d is the D-axis inductor, Ke q represents the Q-axis flux linkage component, Ke d represents the D-axis flux linkage component, and speed represents the current rotational speed.

[0229] Specifically, the first limit value is the value corresponding to the pre-configured yn limit register. Before the compensator works, the central processing unit can configure the yn limit register through the system bus; the second limit value is the value corresponding to the pre-configured un limit register. Before the compensator works, the central processing unit can configure the un limit register through the system bus; among them, the comparison process of the initial first output value and the first limit value and the comparison process of the initial second output value and the second limit value are similar to the comparison process of the current error value and the threshold value described above, and will not be elaborated here.

[0230] The present invention does not limit the number of settings of the yn limit register and the un limit register and the threshold value. It is possible to set 2 yn limit registers / un limit registers, 3 yn limit registers / un limit registers, etc.

[0231] Taking the system bus to configure 2 yn limit registers YN_LO and YN_HI as an example, the calculation and output control unit can determine the first output value according to the magnitude relationship between the calculated initial first output value pre_y(n) and the 2 yn limit registers; specifically, compare the initial first output value with the first limit value one by one, that is, compare pre_y(n) with YN_LO and YN_HI one by one. If YN_LO <= pre_y(n) <= YN_HI, then y(n) = pre_y(n); if pre_y(n) > YN_HI, then y(n) = YN_HI; if pre_y(n) < YN_LO, then y(n) = YN_LO.

[0232] Taking the example of configuring 2 unlimited amplitude registers UN_LO and UN_HI with the system bus, the calculation output control unit can determine the second output value (output result) according to the calculated initial second output value pre_u(n) and the size relationship of the 2 unlimited amplitude registers; specifically, compare the initial second output value with the second limit value one by one, that is, compare pre_u(n) with UN_LO and UN_HI one by one. If UN_LO <= pre_u(n) <= UN_HI, then u(n) = pre_u(n); if pre_u(n) > UN_HI, then u(n) = UN_HI; if pre_u(n) < UN_LO, then u(n) = UN_LO.

[0233] In the embodiments of the present invention, the process of calculating compensation in the current compensation method is the same as the processing flow when the above compensator performs compensation, and will not be elaborated here.

[0234] In several embodiments provided by the present invention, it should be understood that the disclosed compensator and method can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation.

[0235] The unit described as a separated component may or may not be physically separated, and the component shown as a module may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0236] In addition, in each embodiment of the present invention, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware, or in the form of hardware plus software function modules.

[0237] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention.

[0238] Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to cover all changes falling within the meaning and scope of the equivalent elements of the claims in the present invention. Any associated drawing marks in the claims should not be regarded as limiting the claimed rights.

[0239] In addition, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or systems stated in a system claim can also be implemented by one unit or system through software or hardware. The words first, second, etc. are used to indicate names, and do not indicate any particular order.

[0240] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A compensator, characterized in that: The compensator includes an error calculation unit, a parameter selection unit, and a calculation unit: The error calculation unit is used to obtain a current sampling value of the sampling circuit, and calculate a current error value according to the current sampling value and a preconfigured system expected value; The parameter selection unit is used to determine the zero-pole parameter group according to the comparison result between the current error value and the preset threshold value, and reduce the parameters in the zero-pole parameter group to obtain the configurable parameters, wherein the parameter selection unit reduces the parameters in the zero-pole parameter group respectively according to the following formula to obtain the configurable parameters: ； ； ； ； ； ； ； ； Among them, A0, A1, B0, B1, B2, A2, B3, and k are configurable parameters. , , , , , , They represent the parameters in the zero-pole parameter group, absmax represents the maximum absolute value, and ceiling represents rounding up. Expressed as reduction coefficient; The calculation unit is used to obtain the latch parameters of the sampling circuit, and perform multiplication and accumulation calculation according to the latch parameters and the configurable parameters to obtain a compensation result.

2. The compensator according to claim 1, characterized in that The calculation unit includes a calculation processing unit, and the parameter selection unit is further used to determine the input parameters calculated by the calculation processing unit according to the latch parameters and the configurable parameters.

3. The compensator according to claim 2, characterized in that: The calculation unit includes an input control unit, a calculation processing unit, and a calculation output control unit: The input control unit is used to receive input parameters and send them to the calculation processing unit; The calculation processing unit is used to perform a first calculation on the input parameter to obtain a calculation result; The calculation output control unit is used to store the calculation result and perform a second calculation to obtain an output result, and generate a compensation result according to the output result.

4. The compensator according to claim 3, characterized in that: The calculation processing unit includes a multiplier, which is used to perform multiplication calculation on the input parameter to obtain a calculation result; The calculation output control unit includes an accumulator, which is used to accumulate the calculation results to obtain output results.

5. The compensator according to claim 4, characterized in that When the parameter selection unit determines the input parameter calculated by the calculation processing unit according to the latch parameter and the configurable parameter, the parameter selection unit includes the following steps: Generating a first latch parameter set and a second latch parameter set according to the latch parameter, and generating a first configurable parameter set and a second configurable parameter set according to the configurable parameter; A plurality of first input parameter groups are generated according to the combination of the first latch parameter set and the first configurable parameter, and a plurality of second input parameter groups are generated according to the combination of the second latch parameter set and the second configurable parameter.

6. The compensator according to claim 5, characterized in that The computing unit comprises the following steps when generating an output result: The multiplier performs multiplication calculation on the first input parameters one by one to obtain a first calculation result; The accumulator performs accumulation calculation on the first calculation result to obtain an initial first output value; The calculation output control unit determines the current first output value according to the comparison result between the initial first output value and the preset first limit value, and uses the current first output value as the second input parameter; The multiplier performs a multiplication calculation according to the second input parameter to obtain a second calculation result; The accumulator performs accumulation calculation on the second calculation result to obtain an initial second output value; The calculation output control unit determines a current second output value according to a comparison result between the initial second output value and a preset second limit value, and uses the second output value as an output result.

7. The compensator according to claim 6, characterized in that The current first output value is expressed by the following formula: ； Wherein, y(n) represents the current first output value, is represented as the reduction coefficient, A0 is represented as the first configurable parameter in the first input parameter, A1 is represented as the second configurable parameter in the first input parameter, B0 is represented as the fourth configurable parameter in the first input parameter, B1 is represented as the fifth configurable parameter in the first input parameter, B2 is represented as the sixth configurable parameter in the first input parameter, e(n) is represented as the current error value in the first input parameter, e(n-1) is represented as the error value of the previous state in the first input parameter, e(n-2) is represented as the error value of the previous state in the first input parameter, y(n-1) is represented as the first output value of the previous state in the first input parameter, and y(n-2) is represented as the first output value of the previous state in the first input parameter; The current second output value is expressed by the following formula: ； Among them, u(n) represents the current second output value, y(n) represents the current first output value, A2 represents the third configurable parameter in the second input parameter, B3 represents the seventh configurable parameter in the second input parameter, y(n-1) represents the first output value of the previous state in the second input parameter, and u(n-1) represents the second output value of the previous state in the second input parameter.

8. The compensator according to claim 4, characterized in that The calculation unit comprises the following steps when generating the compensation result: The calculation output control unit determines whether the compensator is in an independent compensation mode or a D / Q cross-coupling mode; If it is an independent compensation mode, the output result is used as the compensation result; If it is a D / Q cross-coupling mode, the input control unit obtains coupling parameters of the D channel and the Q channel; The multiplier performs multiplication calculation on the coupling parameter to obtain a third calculation result; The calculation output control unit performs addition calculation according to the third calculation result and a preset magnetic flux component to obtain a fourth calculation result; The multiplier performs multiplication calculation according to the fourth calculation result and the preset current speed to obtain a fifth calculation result; The accumulator performs accumulation calculation according to the fifth calculation result and the output result to obtain compensation results corresponding to the D channel and the Q channel.

9. The compensator according to claim 8, characterized in that The compensation results corresponding to the D channel and the Q channel are expressed by the following formula: ； ； in, It is expressed as the compensation result corresponding to the D channel, Expressed as the compensation result corresponding to the Q channel, It is represented as the output result corresponding to the D channel. Expressed as the output result corresponding to the Q channel, Represents the current sampling value of the Q channel, Represents the current sampling value of the D channel. is the Q-axis inductance, is the D-axis inductance, Expressed as the Q-axis flux component, It is expressed as the D-axis magnetic flux component, and speed is expressed as the current speed.

10. A circuit compensation method, characterized in that: The method comprises: Obtaining a current sampling value of the sampling circuit, and calculating a current error value according to the current sampling value and a preconfigured system expected value; A zero-pole parameter group is determined according to a comparison result between the current error value and the preset threshold value, and the parameters in the zero-pole parameter group are reduced to obtain configurable parameters, wherein the parameter selection unit reduces the parameters in the zero-pole parameter group respectively by the following formula to obtain the configurable parameters: ； ； ； ； ； ； ； ； Among them, A0, A1, B0, B1, B2, A2, B3, and k are configurable parameters. , , , , , , They represent the parameters in the zero-pole parameter group, absmax represents the maximum absolute value, and ceiling represents rounding up. Expressed as reduction coefficient; The latch parameters of the sampling circuit are acquired, and a multiplication and accumulation calculation is performed according to the latch parameters and the configurable parameters to obtain a compensation result.

11. The circuit compensation method according to claim 10, characterized in that: The performing a multiplication and accumulation calculation according to the latch parameter and the configurable parameter to obtain a compensation result includes: Determine an input parameter according to the latch parameter and the configurable parameter; Perform multiplication and accumulation calculations according to the input parameters to obtain an output result; A compensation result is generated according to the output result.

12. The circuit compensation method according to claim 11, characterized in that: The step of determining the input parameter according to the latch parameter and the configurable parameter comprises: Generating a first latch parameter set and a second latch parameter set according to the latch parameter, and generating a first configurable parameter set and a second configurable parameter set according to the configurable parameter; A plurality of first input parameter groups are generated according to the combination of the first latch parameter set and the first configurable parameter, and a plurality of second input parameter groups are generated according to the combination of the second latch parameter set and the second configurable parameter.

13. The circuit compensation method according to claim 12, characterized in that: The multiplication and accumulation calculations are performed according to the input parameters to obtain output results, including: Performing multiplication calculation on the first input parameters one by one to obtain a first calculation result; Performing cumulative calculation on the first calculation results to obtain an initial first output value; Determine a current first output value according to a comparison result between the initial first output value and the preset first amplitude limit value, and use the current first output value as a second input parameter; Perform a multiplication calculation according to the second input parameter to obtain a second calculation result; Performing cumulative calculation on the second calculation results to obtain an initial second output value; The current second output value is determined according to a comparison result between the initial second output value and the preset second limit value, and the second output value is used as an output result.

14. The circuit compensation method according to claim 12, characterized in that: Generating a compensation result according to the output result includes: Determine whether the compensator is in independent compensation mode or D / Q cross-coupling mode; If it is an independent compensation mode, the output result is used as the compensation result; If it is D / Q cross coupling mode, the coupling parameters of D channel and Q channel are obtained; Performing multiplication calculation on the coupling parameter to obtain a third calculation result; Performing an addition calculation based on the third calculation result and a preset magnetic flux component to obtain a fourth calculation result; Performing multiplication calculation according to the fourth calculation result and the preset current speed to obtain a fifth calculation result; Accumulated calculation is performed according to the fifth calculation result and the output result to obtain compensation results corresponding to the D channel and the Q channel.

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