Data pre-fetching method and device, processor and computer-readable storage medium

Abstract

Embodiments of the present disclosure provide a data prefetching method and device, a processor, and a computer-readable storage medium. The data prefetching method includes: obtaining thread information of multiple threads processed in a processor; according to the thread information of the multiple threads, in response to at least a first thread and a second thread in the multiple threads sharing code, the threads sharing the code share the same shared data prefetcher to perform data prefetching processing. The method can improve the overall performance of the processor and reduce the power consumption generated by prefetcher training.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data pre-fetching method, a data pre-fetching device, a processor, and a computer-readable storage medium. Background Art

[0002] A modern multi-issue high-performance CPU (Central Processing Unit) includes at least one processor core, and each processor core includes multiple execution units to execute instructions. For example, the pipeline process of instruction execution includes five stages: instruction fetch (IF), decoding (ID), execution (EX), memory access (MEM), and write back (WB, Write Back, updating the result of instruction execution to the register).

[0003] For an application, a thread can be the smallest scheduling unit for the operation and execution of a process (a process is an entity's running process of a program, and is an independent unit for the system to allocate and deploy resources). When the processor core executes the instructions of a single thread, the multiple execution units and hardware resources inside the processor core cannot be fully utilized most of the time. In particular, when the single thread is paused for some reason (such as L2 cache flushing), the execution unit can only idle, resulting in a waste of hardware resources and a reduction in the performance-power-consumption ratio.

[0004] If multiple threads are running simultaneously in a process to complete different tasks, the design is called multithreading. Simultaneous multithreading (SMT) is a hardware multithreading technology that can execute instructions from multiple threads in one operation cycle. This technology uses the multi-issue and out-of-order execution mechanisms of high-performance processor cores, and uses multiple execution units to execute instructions from multiple threads simultaneously. When a thread stops running for some reason, other threads can still run, or the excess resources of one thread can be used by another thread, thereby improving the multi-threaded throughput of the processor core, the overall CPU performance and performance-to-power ratio, and the utilization of hardware resources. Summary of the invention

[0005] At least one embodiment of the present disclosure provides a data prefetching method, comprising: acquiring thread information of multiple threads being processed in a processor; and based on the thread information of the multiple threads, in response to at least a first thread and a second thread among the multiple threads sharing code, allowing the threads sharing the code to share a same shared data prefetcher to perform data prefetching processing.

[0006] In the data prefetching method provided by at least one embodiment of the present disclosure, the threads that share code share the same shared data prefetcher to perform data prefetching processing, including: using the request issued by the first thread to perform data prefetching training on the shared data prefetcher.

[0007] In the data prefetching method provided by at least one embodiment of the present disclosure, the use of the request issued by the first thread to perform data prefetching training on the shared data prefetcher includes: blocking or filtering requests issued by threads of shared code other than the first thread, so as to avoid the requests issued by threads of shared code other than the first thread being used for data prefetching training of the shared data prefetcher.

[0008] In the data prefetching method provided by at least one embodiment of the present disclosure, the threads sharing the shared code share the same shared data prefetcher to perform data prefetching processing, and also include: using the shared data prefetcher to respond to the request of the first thread and the request of the second thread respectively.

[0009] The data prefetching method provided by at least one embodiment of the present disclosure also includes: determining that the first thread and the second thread share code based on thread information of the multiple threads, wherein the first thread uses a first data prefetcher to perform the data prefetching process, and the second thread uses a second data prefetcher to perform the data prefetching process; wherein, allowing the threads that share the code to share the same shared data prefetcher to perform data prefetching processing includes: merging the first data prefetcher and the second data prefetcher to obtain the shared data prefetcher.

[0010] In the data prefetching method provided by at least one embodiment of the present disclosure, merging the first data prefetcher and the second data prefetcher to obtain the shared data prefetcher includes: using the first data prefetcher as the shared data prefetcher.

[0011] In the data prefetching method provided by at least one embodiment of the present disclosure, the merging of the first data prefetcher and the second data prefetcher to obtain the shared data prefetcher includes: merging at least a portion of the hardware resources of the first data prefetcher and at least a portion of the hardware resources of the second data prefetcher for use in the shared data prefetcher.

[0012] The data prefetching method provided in at least one embodiment of the present disclosure further includes: setting a shared state flag in the table entry trained by the shared data prefetcher to record that the shared data prefetcher is shared by the thread of the shared code.

[0013] The data prefetching method provided in at least one embodiment of the present disclosure also includes: based on thread information of the multiple threads, in response to the first thread and the second thread among the multiple threads no longer sharing code, obtaining a first data prefetcher and a second data prefetcher from the shared data prefetcher to be used for the first thread and the second thread to perform the data prefetching processing respectively.

[0014] In the data prefetching method provided by at least one embodiment of the present disclosure, the first data prefetcher and the second data prefetcher are obtained by the shared data prefetcher to be used for the first thread and the second thread to perform the data prefetching processing respectively, including: making the first data prefetcher retain at least a first part of the table entries of the shared data prefetcher, and making the second data prefetcher retain at least a second part of the table entries of the shared data prefetcher, or making the second data prefetcher empty.

[0015] In the data prefetching method provided by at least one embodiment of the present disclosure, the first portion of table entries retained by the first data prefetcher and the second portion of table entries retained by the second data prefetcher are at least partially identical to each other.

[0016] In the data prefetching method provided by at least one embodiment of the present disclosure, after the first data prefetcher and the second data prefetcher are obtained by the shared data prefetcher, in response to the second data prefetcher being empty, the request issued by the second thread is used for data prefetching training of the second data prefetcher.

[0017] At least one embodiment of the present disclosure also provides a data prefetching device, including: a thread information acquisition module, configured to acquire thread information of multiple threads processed in a processor; and a data prefetching processing module, configured to, based on the thread information of the multiple threads and in response to at least a first thread and a second thread among the multiple threads sharing code, allow the threads sharing the code to share the same shared data prefetcher for data prefetching processing.

[0018] In the data prefetch device provided by at least one embodiment of the present disclosure, the data prefetch processing module includes: a prefetch training module, configured to use the request issued by the first thread to perform data prefetch training on the shared data prefetcher; and a request response module, configured to use the shared data prefetcher to respond to the requests issued by the threads of the shared code respectively.

[0019] In the data prefetch device provided by at least one embodiment of the present disclosure, the data prefetch processing module also includes: a shared state determination module, configured to determine that the first thread and the second thread share code based on thread information of the multiple threads, wherein the first thread uses a first data prefetcher to perform the data prefetch processing, and the second thread uses a second data prefetcher to perform the data prefetch processing; a resource allocation module, configured to: in response to the first thread and the second thread sharing code, merge the first data prefetcher and the second data prefetcher to obtain the shared data prefetcher, or, in response to the first thread and the second thread no longer sharing code, obtain the first data prefetcher and the second data prefetcher from the shared data prefetcher to be used for the first thread and the second thread to perform the data prefetch processing respectively.

[0020] The data prefetching device provided by at least one embodiment of the present disclosure further includes: an identification setting module, configured to set a shared state identification in the table entry trained by the shared data prefetcher to record that the shared data prefetcher is shared by the thread of the shared code.

[0021] At least one embodiment of the present disclosure also provides a data prefetching device, comprising a processing unit and a memory communicatively connected to the processing unit; wherein the memory stores computer-readable instructions; the processing unit executes the computer-readable instructions stored in the memory to implement the data prefetching method provided by any embodiment of the present disclosure.

[0022] At least one embodiment of the present disclosure further provides a processor, comprising the data pre-fetching device provided by any embodiment of the present disclosure.

[0023] At least one embodiment of the present disclosure further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions, and when a processor executes the computer-readable instructions, the data prefetching method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0025] Figure 1A A flow chart of training and pre-fetching of a data pre-fetcher is shown;

[0026] Figure 1B A schematic diagram showing a flow chart of a data pre-fetching method provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 2AA schematic diagram showing a data pre-fetching training process when a first thread and a second thread are in a shared code state provided by at least one embodiment of the present disclosure;

[0028] Figure 2B A schematic diagram showing a data prefetching operation when a first thread and a second thread are in a shared code state provided by at least one embodiment of the present disclosure is shown;

[0029] Figure 3 A schematic diagram showing a data prefetching operation when a first thread and a second thread are in a non-shared code state provided by at least one embodiment of the present disclosure;

[0030] Figure 4 A schematic diagram of the structure of a data pre-fetching device provided by at least one embodiment of the present disclosure is shown;

[0031] Figure 5 A schematic diagram showing the structure of another data pre-fetching device provided by at least one embodiment of the present disclosure is shown;

[0032] Figure 6 A schematic diagram of a computer-readable storage medium provided for at least one embodiment of the present disclosure;

[0033] Figure 7 A schematic block diagram of an electronic device provided according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] A computer usually includes one or more processor cores (CPU cores) and multiple levels of cache. In the multi-level cache architecture, the first-level (L1) cache memory has the fastest access speed but the smallest capacity and is usually set in the processor core; the last-level (LLC, generally the third level) cache memory has the largest capacity but the slowest access speed and is usually shared by multiple processor cores; the second-level (L2) cache memory has an access speed and capacity between the L1 cache memory and the LLC cache memory and is also usually set in the processor core.

[0037] Explanations of terms that may be involved in at least one embodiment of the present disclosure are as follows.

[0038] Data Prefetch: In the CPU architecture, program instructions and data can be stored in the dynamic random access memory (DRAM). The operating frequency of the processor core is much higher than the operating frequency of the DRAM memory. Therefore, it takes hundreds of processor core clock cycles to obtain data and instructions from the memory, causing the processor core to idle while waiting for related instructions and data, resulting in performance loss. Therefore, modern high-performance processor cores all contain a multi-level cache architecture to save recently accessed data, and use a prefetcher to discover the CPU's data access pattern to pre-fetch the data and instructions that will be accessed into the cache in advance.

[0039] Prefetcher: A prefetcher used to prefetch instructions is called an instruction prefetcher; a prefetcher used to prefetch data is called a data prefetcher. For example, a data prefetcher can be divided into a first-level data prefetcher (i.e., a data prefetcher that prefetches target data into a first-level cache memory), a second-level data prefetcher (i.e., a data prefetcher that prefetches target data into a second-level cache memory), a last-level data prefetcher (i.e., a data prefetcher that prefetches target data into a last-level cache memory), etc.

[0040] Prefetch Pattern: In data prefetching, different prefetchers learn different prefetch patterns by identifying the access history of memory addresses. The prefetchers initiate new data prefetching based on the learned prefetch patterns and fetch data blocks into the cache before memory access arrives. When memory access arrives, it directly hits the cache, thereby hiding the memory access latency.

[0041] In the case of SMT, prefetchers are provided for multiple threads respectively, and the training of prefetchers is based on the memory address access history of multiple threads; since the hardware resources are generally limited, the hardware resources of each prefetcher are allocated according to the number of threads, and each thread trains the corresponding prefetching mode according to the request of the thread. Therefore, in the case of multi-threading, the resources occupied by each thread in the prefetcher are further limited, and it may not be guaranteed that the prefetcher can learn the prefetching mode of each thread.

[0042] Figure 1A A flow chart of training and pre-fetching of a data pre-fetcher is shown. Figure 1A The prefetcher shown is a first-level data prefetcher, that is, a data prefetcher that prefetches target data into a first-level cache memory. The prefetcher uses a virtual address to train the data prefetcher.

[0043] For example, Figure 1A As shown, the data prefetcher performs data prefetch training and data prefetch operations (also referred to as "training" and "prefetching") through the following steps S012 to S017.

[0044] Step S012: The data prefetcher receives virtual addresses and other attributes of all (or part) of the access requests (e.g., historical access requests), uses the virtual addresses of the above access requests (e.g., historical access requests) for training to obtain the data access rules of the processor core, outputs data prefetch requests based on the above data access rules, and performs data prefetching based on the above data prefetch requests.

[0045] Step S013: Use the address translator to translate the virtual address of the target data of the data prefetch request into a physical address, and then check (for example, the processor core uses the physical address of the target data of the data prefetch request to check) whether the target data of the data prefetch request is in the first-level cache memory.

[0046] For example, if the target data of the data pre-fetch request is in the first-level cache memory, the data pre-fetch request is discarded. Correspondingly, for the data pre-fetch request, there is no need to perform the following steps S014 to S017.

[0047] Step S014: If the target data of the data pre-fetch request is not in the primary cache memory, a storage item is requested from the Missing Address Buffer (MAB) 112, and the storage item is allocated to the data pre-fetch request.

[0048] Step S015: the miss address buffer memory 112 requests the target data from the next level of buffer memory (eg, the secondary cache memory).

[0049] Step S016: The next level buffer memory obtains the target data and returns the target data to the miss address buffer memory.

[0050] For example, Figure 1A As shown, in the case where the target data of the data prefetch request is stored in the secondary cache memory, the secondary cache memory obtains the target data of the data prefetch request from the secondary cache memory. For example, in the case where the target data of the data prefetch request is not stored in the secondary cache memory, the secondary cache memory obtains the target data of the data prefetch request from a storage device located at the next level of the secondary cache memory.

[0051] Step S017: the miss address buffer memory writes the target data into the first-level cache memory.

[0052] It should be noted that while the data prefetcher is training and prefetching, the processor core reads data to perform related operations. Correspondingly, for the convenience of description, Figure 1A Part of the process of the processor core reading data is also shown. For example, the process of the processor core reading data includes the following step S011.

[0053] Step S011: The processor core outputs the virtual address of the target data of the access request to the address translator (e.g., address translation pipeline) 111, the address translator translates the above virtual address into a physical address, and then the processor core checks whether the target data of the access request is in the first-level cache memory.

[0054] If the target data of the access request is in the first-level cache memory, the processor core retrieves the target data of the access request from the first-level cache memory. If the target data of the access request is not in the first-level cache memory, the miss address buffer memory 112 obtains the target data of the access request and writes the target data of the access request into the first-level cache memory, and then the processor core retrieves the target data of the access request from the first-level cache memory.

[0055] For example, only the address pairs of the load access requests (eg, historical load access requests) may be used. Figure 1A The data prefetcher shown is trained. In this case, the access rule obtained by the data prefetcher is only the rule of the load access request. Correspondingly, the data prefetcher can only perform load access prefetching, that is, the data prefetcher can only prefetch the target data of the load access request. However, since the data prefetcher cannot prefetch the target data of the storage access request, when the data of the target data of the storage access request is not located in the buffer memory (e.g., the first and second buffer memories), it is necessary to obtain data from the memory (DRAM), which will have an adverse effect on the CPU performance.

[0056] For example, in order for the data prefetcher to prefetch target data of a storage access request, the address of a load access request (eg, a historical load access request) and the address of a storage access request (eg, a historical storage access request) may be used simultaneously. Figure 1A The data prefetcher (single data prefetcher) shown is trained so that the access requests output by the data prefetcher include load access requests and store access requests.

[0057] The inventors of the present disclosure noticed that in a simultaneous multi-threaded processor, for multi-threaded applications that share code, for example, two threads among multiple threads at least partially execute the same instruction sequence, and the data access rules of the two threads are basically consistent, that is, each thread has the same prefetch mode, resulting in repeated training of the same prefetch mode in the data prefetcher, causing a certain amount of resource waste.

[0058] In view of the above shortcomings, one or more embodiments of the present disclosure provide a data pre-fetching method, a data pre-fetching device, a processor and a computer-readable storage medium.

[0059] The data prefetching method includes: obtaining thread information of multiple threads processed in a processor; and according to the thread information of the multiple threads, in response to at least a first thread and a second thread sharing a code among the multiple threads, allowing the threads sharing the code to share the same shared data prefetcher to perform data prefetching processing. The method enables the threads sharing the code to share the same shared data prefetcher, that is, the shared data prefetcher can only learn the prefetching mode of any one thread (for example, the first thread or the second thread) among the threads sharing the code, and the prefetching mode can be simultaneously applied to requests issued by all threads sharing the code, thereby improving the utilization rate of the prefetcher hardware resources, and in at least one embodiment, the processor has sufficient resources to fully learn the prefetching mode and thus improve the hit rate of the prefetcher.

[0060] The processor is, for example, a simultaneous multi-threading (SMT) processor.

[0061] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0062] Figure 1B A schematic flow chart of a data pre-fetching method provided by at least one embodiment of the present disclosure is shown. The data pre-fetching method includes steps S10 and S20.

[0063] Step S10: Obtain thread information of multiple threads processed in the processor.

[0064] Step S20: according to the thread information of the plurality of threads, in response to at least a first thread and a second thread among the plurality of threads sharing a code, the threads sharing the code share a same shared data prefetcher to perform data prefetching processing.

[0065] For example, the thread information may be information about instruction sequences executed by multiple threads, including shared code information, i.e., which threads among the multiple threads currently share code or do not share code. For example, whether code information is shared may be recorded through a register. For example, for an SMT4 (i.e., simultaneous 4 threads) processor, a 4-bit register may be used to record which threads among the multiple threads currently share code. For example, bits 0 to 3 of the register correspond to threads T0, T1, T2, and T3, respectively. When two threads share code, the corresponding positions of the two threads in the register are set to 1, otherwise to 0, so "0101" indicates that threads T0 and T2 share code.

[0066] For example, the first thread and the second thread share code, that is, the first thread and the second thread execute the same instruction sequence. Therefore, the first thread and the second thread can share the same shared data prefetcher and perform data prefetch processing according to the same prefetch mode. The data prefetch processing includes data prefetch training or data prefetch operation, and the data prefetch operation is performed using the prefetcher obtained through data prefetch training.

[0067] For example, for an SMT4 processor including 4 threads, 3 threads can share code and use the same data prefetcher to perform data prefetch processing; or all threads (4 threads) can share code and use the same data prefetcher to perform data prefetch processing, and the present disclosure does not impose any restrictions on this.

[0068] For example, step S20 may include step S210 or step S220; there is no restriction on the execution order of step S210 and step S220, for example, the two may be executed successively or in parallel, so the pre-fetch training and pre-fetch operations are dynamic.

[0069] Step S210: using the request sent by the first thread to perform data prefetching training on the shared data prefetcher.

[0070] Step S220: using the shared data prefetcher to respond to the requests of the threads of the shared code respectively.

[0071] In step S210, since the prefetch modes of the threads sharing the code are the same, and the threads sharing the code include at least a first thread and a second thread, a request sent by any thread in the threads sharing the code can be selected to perform data prefetch training on the shared data prefetcher. The first thread is selected here, and of course the second thread or other threads in the threads sharing the code can also be selected.

[0072] When the first thread is used for data prefetch training, requests (data prefetch requests) issued by threads of shared code other than the first thread are blocked or filtered to avoid requests issued by threads of shared code other than the first thread being used for data prefetch training of the shared data prefetcher, thereby reducing a training process, improving the performance of the processor, and reducing the power consumption of the processor. For example, data prefetch requests issued by threads of shared code other than the first thread are prevented from entering the shared data prefetcher or being processed by the shared data prefetcher, thereby blocking or filtering requests issued by threads of shared code other than the first thread.

[0073] It should be noted that the embodiments of the present disclosure are not limited to using the first thread to perform data prefetch training and preventing threads of shared code other than the first thread from being trained. Rather, during the data prefetch training process, it is only necessary to use a request issued by any thread in the threads of the shared code to train the shared data prefetcher, and prevent threads other than the selected thread from participating in the data prefetch training, thereby avoiding repeated training.

[0074] As described above, the thread information itself can be modified in near real time as the application executes to reflect the current status of multiple threads in the processor, so that the processor uses a shared data prefetcher for a period of time and does not use the shared data prefetcher for another period of time and reverts to each thread having its own data prefetcher, or vice versa.

[0075] For example, before the above step S20, the data pre-fetching method may further include the following step S30.

[0076] Step S30: determining, based on thread information of the plurality of threads, that a first thread and a second thread share code, wherein the first thread uses a first data prefetcher to perform data prefetch processing, and the second thread uses a second data prefetcher to perform data prefetch processing.

[0077] That is, before the first thread and the second thread share the same shared data prefetcher for data prefetch processing, after determining that the first thread and the second thread share code, the data prefetch mode is switched from the first thread using the first data prefetcher for data prefetch processing and the second thread using the second data prefetcher for data prefetch processing to the first thread and the second thread sharing the same shared data prefetcher for data prefetch processing.

[0078] For example, the code injection technology may be used to determine whether the first thread and the second thread in the plurality of threads share code; for example, some specific instructions or tags may be inserted into the code to identify the shared code portion, thereby determining the threads that share the code.

[0079] For another example, thread information may come from statistical data of instructions within a predetermined time period before the current time (e.g., 100 milliseconds), or from records of a compiler after compiling a multi-threaded application; the thread information itself may be modified in near real time as the application is executed to reflect the current status of multiple threads in the processor, and the embodiments of the present disclosure are not limited to this.

[0080] Step S30 can also detect thread information of whether different threads share code by introducing additional metadata information in I-Cache (instruction cache), such as storing the most recently accessed thread ID and the type of code.

[0081] As described above, before determining that the first thread and the second thread share code, the first thread uses the first data prefetcher to perform data prefetch processing, and the second thread uses the second data prefetcher to perform data prefetch processing; correspondingly, for example, after determining that the first thread and the second thread share code, the first thread and the second thread share the same shared data prefetcher to perform data prefetch processing, including: merging the first data prefetcher and the second data prefetcher to obtain a shared data prefetcher.

[0082] For example, the first data prefetcher can be directly used as a shared data prefetcher to perform subsequent data prefetching training and data prefetching operations. In this case, the data of the shared data prefetcher at the beginning is a copy of the data of the first data prefetcher. At this time, for example, the resources occupied by the second data prefetcher can be reallocated after the second data prefetcher is cleared; or, at least part of the hardware resources of the first data prefetcher and at least part of the hardware resources of the second data prefetcher can be merged for the shared data prefetcher. In this case, the shared data prefetcher is the sum of the first data prefetcher and the second data prefetcher, and the data at the beginning is the sum of the data of the first data prefetcher and the second data prefetcher. For example, repeated parts of the data can also be removed.

[0083] For example, the hardware resources of the prefetcher include the prefetch table, prefetch buffer, address prediction unit, state machine and controller, etc. The prefetch table includes multiple entries, which are used to record and track the memory access mode and the address information of the prefetched data or instructions; the prefetch buffer is used to temporarily store the prefetched data waiting for the use of the processor core; the address prediction unit is used to generate the prediction of the future memory address according to the prefetch mode; the state machine and controller are used to manage and schedule the prefetch operation, such as deciding when to initiate the prefetch operation and how to update the prefetch table entries.

[0084] In the prefetch table of the prefetcher, the relevant information of each predicted or executed prefetch operation is recorded as an entry (also called "entry"). For example, each entry contains the thread number, predicted memory address, prefetch status and related metadata, such as timestamp and hit rate statistics.

[0085] For example, Figure 2A A schematic diagram of a data prefetch training process when a first thread and a second thread are in a shared code state provided by at least one embodiment of the present disclosure is shown.

[0086] This embodiment takes a 4-thread simultaneous multithreading (SMT4) processor as an example. Figure 2AAs shown, the SMT4 processor has four threads (i.e., a first thread T1, a second thread T2, a third thread T3, and a fourth thread T4) running therein, and the first thread T1, the second thread T2, the third thread T3, and the fourth thread T4 respectively issue requests R1-R4. Before determining that there are threads with shared code in threads T1-T4, threads T1-T4 respectively have their own corresponding data prefetchers; the hardware resources 200 for data prefetchers in the processor can be allocated to the four data prefetchers corresponding to threads T1-T4 according to a certain pattern. For example, the hardware resources 200 include 16 table entries, and the data prefetcher corresponding to each thread can be allocated four table entries in an evenly distributed pattern. For the convenience of description, the hardware resources allocated to threads T1-T4 are respectively described as first data prefetchers (not marked in the figure, see below). Figure 3 ), the second data pre-fetcher (not shown in the figure, see below Figure 3 ), a third data prefetcher 223 and a fourth data prefetcher 224; these data prefetchers may, for example, share a processing logic portion when implemented, but operate different hardware resources (portions).

[0087] like Figure 2A As shown, during the operation of the processor, after determining that the first thread T1 and the second thread T2 are shared codes, the first data prefetcher corresponding to the first thread T1 can be used as the shared data prefetcher 220 to perform data prefetch training and subsequent data prefetch operations; or, at least part of the hardware resources of the first data prefetcher corresponding to the first thread T1 and at least part of the hardware resources of the second data prefetcher corresponding to the second thread T2 can be combined to be used for the shared data prefetcher 220. The third threads T3 and T4 still use the previously corresponding data prefetchers 223 and 224 respectively to perform data prefetch processing.

[0088] For example, the 4 table entries originally occupied by the first data prefetcher and the 4 table entries originally occupied by the second data prefetcher can be used for the shared data prefetcher 220, so the shared data prefetcher 220 has 8 table entries, corresponding to the 4 table entries still occupied by the third data prefetcher 223 and the 4 table entries still occupied by the fourth data prefetcher 224. In this way, the shared data prefetcher 220 is significantly improved in prefetch processing capability compared with the previous first data prefetcher and the second data prefetcher.

[0089] Alternatively, the hardware resources 200 are reallocated, for example, so that the shared data prefetcher 220 occupies 6 entries (for example, 4 entries originally occupied by the first data prefetcher and 2 entries from the original second data prefetcher), the third data prefetcher 223 occupies 5 entries (the original 4 entries and 1 entry from the original second data prefetcher), and the fourth data prefetcher 224 still occupies 5 entries (the original 4 entries and 1 entry from the original second data prefetcher). Compared with the original hardware resource allocation method, the shared data prefetcher 220, the third data prefetcher 223, and the fourth data prefetcher 224 after the hardware resources are reallocated are improved in terms of processing capabilities.

[0090] Since the first thread T1 and the second thread T2 share code, and the prefetch modes of the first thread T1 and the second thread T2 are the same, the request of any thread among the threads sharing the code can be selected for training to train the shared data prefetcher 220, for example, the request R1 of the first thread T1 or the request R2 of the second thread T2, and the request R3 of the third thread T3 can be used to train the third data prefetcher 223 and the request R4 of the fourth thread T4 can be used to train the fourth data prefetcher 224. For example, when the request R1 of the first thread T1 trains the shared data prefetcher 220, the filter 210 can be used to block or filter the request R2 issued by the second thread T2 according to the thread number in the request, so as to avoid the request R2 issued by the second thread T2 being used for data prefetching training of the shared data prefetcher 220, thereby avoiding the training operation for the request R2 issued by the second thread T2 and reducing power consumption.

[0091] Figure 2B A schematic diagram of a data prefetching operation when a first thread and a second thread are in a shared code state provided by at least one embodiment of the present disclosure is shown.

[0092] like Figure 2B As shown, since the first thread T1 and the second thread T2 are determined as shared code, the first thread T1 and the second thread T2 share the same shared data prefetcher 220, and the requests R1 and R2 issued by the first thread T1 and the second thread T2 respectively can trigger the shared data prefetcher 220 to perform corresponding data prefetch operations, and the prefetched data is stored in the corresponding cache. The third thread T3 does not belong to the thread of the shared code, and only the request R3 issued by the third thread T3 can trigger the prefetch operation of the third data prefetcher 223. The fourth thread T4 is similar to the third thread T3, and will not be repeated here.

[0093] It should be noted that Figure 2A-2BThe multithreading shown includes 4 threads, among which the first thread T1 and the second thread T2 share code, but the embodiments of the present disclosure are not limited thereto. For example, the multiple threads may also include threads other than thread T5 and thread T6. For example, in addition to the first thread T1 and the second thread T2 sharing code, thread T5 and thread T6 may also share code. For example, among the multiple threads, threads T0, T1, and T2 may share code, or all threads T0-T4 may share code.

[0094] For example, the data prefetching method provided by at least one embodiment of the present disclosure may further include: setting a shared state flag in the table entry trained by the shared data prefetcher to record that the shared data prefetcher is shared by threads of the shared code.

[0095] In one example of the present disclosure, the multiple threads in the processor include 4 threads, namely the above-mentioned threads T1-T4. When the CPU starts working, the threads that share the code are determined according to the thread information of threads T1-T4, and the shared state flag can be set in the table entry trained by the data prefetcher using, for example, an additional 4 bits. For example, when the shared state flag is 0001, it indicates that the resources of the data prefetcher corresponding to the table entry are used solely by the first thread T1. When the shared state flag is 0101, it indicates that the first thread T1 and the third thread T3 share the code and the resources of the data prefetcher corresponding to the table entry are used jointly by the first thread T1 and the third thread T3. In addition, the shared state flag can be set using, but is not limited to, 4 bits. Other representations that can indicate that the resources of the data prefetcher are exclusively used by a certain thread or shared by multiple threads can also be used as a shared state flag.

[0096] The data prefetching method provided by at least one embodiment of the present disclosure may further include: based on thread information of multiple threads, in response to the first thread and the second thread no longer sharing code, obtaining the first data prefetcher and the second data prefetcher from the shared data prefetcher to perform data prefetch processing on the first thread and the second thread respectively.

[0097] For example, when the first thread and the second thread no longer share codes, the first data prefetcher and the second data prefetcher are used for the first thread and the second thread to perform data prefetching processing respectively.

[0098] Figure 3 A schematic diagram of a data prefetching operation when a first thread and a second thread are in a non-shared code state provided by at least one embodiment of the present disclosure is shown.

[0099] Reference Figure 3As shown, the first thread T1 and the second thread T2 are changed to use the first data prefetcher 221 and the second data prefetcher 222 to perform data prefetch processing respectively; the third data prefetcher and the fourth data prefetcher are still used for the third thread T3 and the fourth thread T4 to perform data prefetch processing respectively, which will not be repeated here.

[0100] For example, when the first data prefetcher and the second data prefetcher are obtained from the shared data prefetcher, the data inside the shared data prefetcher is maintained unchanged, and the first data prefetcher and the second data prefetcher are obtained only by reallocating the hardware resources of the shared data prefetcher.

[0101] For example, when the first data prefetcher and the second data prefetcher are obtained from the shared data prefetcher, the first data prefetcher can be made to retain at least a first portion of table entries of the shared data prefetcher, and the second data prefetcher can be made to retain at least a second portion of table entries of the shared data prefetcher, wherein the first portion of table entries retained by the first data prefetcher and the second portion of table entries retained by the second data prefetcher are at least partially identical to each other. For example, the first portion of table entries and the second portion of table entries can be table entries with higher confidence in the shared data prefetcher.

[0102] For example, when the first data prefetcher and the second data prefetcher are obtained by the shared data prefetcher, the second data prefetcher may be made empty, even if the second data prefetcher does not retain the entry of the shared data prefetcher.

[0103] For example, in response to the second data prefetcher being empty, the request issued by the second thread T2 can be used for data prefetching training of the second data prefetcher to obtain the prefetching mode of the second thread T2, that is, the second data prefetcher is retrained from scratch and used for data prefetching processing of the second thread T2.

[0104] The data prefetching method provided in the above embodiment is not only applicable to a data prefetcher, but also applicable to an instruction prefetcher, and the embodiment of the present disclosure does not limit this.

[0105] Figure 4 A schematic structural diagram of a data pre-fetching device according to at least one embodiment of the present disclosure is shown.

[0106] like Figure 4 As shown, the data prefetching device 400 includes a thread information acquisition module 410 and a data prefetching processing module 420. The thread information acquisition module 410 is configured to acquire thread information of multiple threads processed in the processor. The data prefetching processing module 420 is configured to, based on the thread information of the multiple threads, in response to the existence of threads sharing code among the multiple threads, share the same shared data prefetcher for data prefetching processing by the threads sharing code, wherein the threads sharing code include at least a first thread and a second thread.

[0107] For example, the data prefetch processing module of the above embodiment includes a prefetch training module and a request response module. The prefetch training module is configured to perform data prefetch training on the shared data prefetcher using the request issued by the first thread, and is also configured to block or filter the request issued by the second thread to avoid the request issued by the second thread being used for data prefetch training of the shared data prefetcher. The request response module is configured to use the shared data prefetcher to respond to the requests issued by the threads of the shared code respectively.

[0108] The data prefetching device of the above embodiment also includes a sharing state determination module and a resource allocation module. The sharing state determination module is configured to determine that the first thread and the second thread share code according to the thread information of the plurality of threads, wherein the first thread uses the first data prefetcher to perform data prefetching processing, and the second thread uses the second data prefetcher to perform data prefetching processing.

[0109] The resource allocation module is configured to, in response to the first thread and the second thread sharing code, merge the first data prefetcher and the second data prefetcher to obtain a shared data prefetcher, at which time the first thread and the second thread share the same shared data prefetcher to perform data prefetching processing. Merging the first data prefetcher and the second data prefetcher to obtain the shared data prefetcher includes: using the first data prefetcher as the shared data prefetcher; or merging at least part of the hardware resources of the first data prefetcher and at least part of the hardware resources of the second data prefetcher for the shared data prefetcher.

[0110] The resource allocation module is configured to, in response to the first thread and the second thread among the multiple threads no longer sharing code, obtain the first data prefetcher and the second data prefetcher from the shared data prefetcher to respectively use for the first thread and the second thread to perform the data prefetching process.

[0111] For example, the resource allocation module enables the first data prefetcher to retain at least a first portion of table entries of the shared data prefetcher, enables the second data prefetcher to retain at least a second portion of table entries of the shared data prefetcher, or enables the second data prefetcher to be empty. For example, the first portion of table entries retained by the first data prefetcher and the second portion of table entries retained by the second data prefetcher are at least partially identical to each other.

[0112] The data prefetching device of the above embodiment further includes a flag setting module, which is configured to set a shared state flag in the table entry trained by the shared data prefetcher to record that the shared data prefetcher is shared by threads of the shared code.

[0113] The data pre-fetching device or the modules therein of the above-mentioned embodiments of the present disclosure may be implemented, for example, by hardware, software, firmware or any combination thereof, and the embodiments of the present disclosure are not limited in this regard.

[0114] Figure 5 A schematic structural diagram of another data pre-fetching device provided by at least one embodiment of the present disclosure is shown.

[0115] like Figure 5 As shown, the data pre-fetching device 500 includes a processing unit 520 and a memory 510 in communication with the processing unit 520. Computer-readable instructions are stored in the memory 510. The processing unit 520 executes the computer-readable instructions stored in the memory 510 to implement the data pre-fetching method provided by any embodiment of the present disclosure.

[0116] For example, the memory 510 and the processing unit 520 may communicate with each other directly or indirectly. Figure 5 As shown, the data pre-fetching device 500 may further include a system bus 530, and the memory 510 and the processing unit 520 may communicate with each other through the system bus 530. For example, the processing unit 520 may access the memory 510 through the system bus 530. For example, in other examples, the memory 510 and the processing unit 520 and other components may communicate through a network on chip (NOC) connection.

[0117] For example, the processing unit 520 can control other components in the data pre-fetching device to perform the desired functions. The processing unit 520 can be a device with data processing capabilities and / or program execution capabilities, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU), and can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0118] For example, the memory 510 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc.

[0119] For example, one or more computer-readable instructions may be stored on the memory 510, and the processing unit 520 may execute the computer-readable instructions to implement various functions. Various applications and various data may also be stored in the computer-readable storage medium, such as instruction processing codes and various data used and / or generated by the application.

[0120] For example, some computer instructions stored in the memory 510 may be executed by the processing unit 520 to perform one or more steps in the data pre-fetching method described above.

[0121] For example, Figure 5 As shown, the data pre-fetching device 500 may also include an input interface 540 that allows an external device to communicate with the data pre-fetching device 500. For example, the input interface 540 may be used to receive instructions from an external computer device, from a user, etc. The data pre-fetching device 500 may also include an output interface 550 that interconnects the data pre-fetching device 500 and one or more external devices. For example, the data pre-fetching device 500 may be output through the output interface 550, etc.

[0122] It should be noted that the data pre-fetching device provided in the embodiments of the present disclosure is exemplary rather than restrictive. According to actual application requirements, the data pre-fetching device may also include other conventional components or structures. For example, in order to realize the necessary functions of the data pre-fetching device, those skilled in the art may set other conventional components or structures according to the specific application scenarios, and the embodiments of the present disclosure are not limited to this.

[0123] At least one embodiment of the present disclosure further provides a processor, such as an SMT processor, which includes a data prefetching device provided by any embodiment of the present disclosure. The maximum number of threads that can be supported by the SMT processor can be, for example, 2, 4, 8, etc., and can be a single-core or multi-core processor. For example, the processor core can adopt a micro-architecture such as X86, ARM, RISC-V, etc., and can include a first-level or multi-level cache, which is not limited by the embodiments of the present disclosure.

[0124] At least one embodiment of the present disclosure also provides a computer-readable storage medium.

[0125] Figure 6 A schematic diagram of a computer-readable storage medium provided for at least one embodiment of the present disclosure.

[0126] For example, Figure 6 As shown, the computer-readable storage medium 600 stores computer-readable instructions 610. When the computer-readable instructions 610 are executed by a computer (including a processor), the data pre-fetching method provided by any embodiment of the present disclosure can be implemented.

[0127] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 600. Some of the computer-readable instructions stored on the computer-readable storage medium 600 may be, for example, instructions for implementing one or more steps in the above-mentioned data pre-fetching method.

[0128] For example, the computer-readable storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above computer-readable storage media, or other applicable storage media. For example, the computer-readable storage medium 600 may include the memory 510 in the aforementioned data pre-fetching device 500.

[0129] The technical effects of the computer-readable storage medium provided by the embodiments of the present disclosure can be referred to the corresponding description of the data pre-fetching method in the above embodiments, which will not be repeated here.

[0130] At least some embodiments of the present disclosure further provide an electronic device, which includes the processor of any of the above embodiments. Figure 7 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0131] The electronic device in the embodiments of the present disclosure can be implemented as but not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc.

[0132] Figure 7 The electronic device 700 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0133] For example, Figure 7 As shown, in some examples, the electronic device 700 includes a processor 701, which may include a processor of any of the above-mentioned embodiments, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device 708 to a random access memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the computer system are also stored. The processor 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0134] For example, the following components may be connected to the I / O interface 705: an input device 706 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 708 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 709 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 709 may allow the electronic device 700 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as needed. Removable media 711, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 710 as needed, so that the computer programs read therefrom are installed into the storage device 708 as needed. Although Figure 7 The electronic device 700 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0135] For example, the electronic device 700 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 709 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0136] In addition to the above exemplary descriptions, there are a few points that need to be explained:

[0137] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0138] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0139] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A data pre-fetching method, comprising: Obtain thread information of multiple threads processed in the processor; as well as In response to at least a first thread and a second thread among the plurality of threads sharing a code, the threads sharing the code share a same shared data prefetcher to perform data prefetch processing; The step of making the threads sharing the shared code share the same shared data prefetcher to perform data prefetching includes: Using the request issued by the first thread to perform data prefetching training on the shared data prefetcher, Block or filter requests issued by threads sharing the code other than the first thread to prevent the requests issued by threads sharing the code other than the first thread from being used for data prefetching training of the shared data prefetcher.

2. The data pre-fetching method according to claim 1, wherein: The method of allowing the threads sharing the shared code to share the same shared data prefetcher to perform data prefetching processing also includes: The shared data prefetcher is used to respond to requests of the threads of the shared code respectively.

3. The data pre-fetching method according to claim 1, further comprising: Determining, according to thread information of the plurality of threads, that the first thread and the second thread share code, Wherein, the first thread uses a first data prefetcher to perform the data prefetching process, and the second thread uses a second data prefetcher to perform the data prefetching process; The step of using the first thread and the second thread to share the same shared data prefetcher to perform data prefetching includes: The first data prefetcher and the second data prefetcher are merged to obtain the shared data prefetcher.

4. The data pre-fetching method according to claim 3, wherein: The step of merging the first data prefetcher and the second data prefetcher to obtain the shared data prefetcher comprises: The first data prefetcher is used as the shared data prefetcher.

5. The data pre-fetching method according to claim 3, wherein: The step of merging the first data prefetcher and the second data prefetcher to obtain the shared data prefetcher comprises: At least a portion of the hardware resources of the first data prefetcher and at least a portion of the hardware resources of the second data prefetcher are combined for use in the shared data prefetcher.

6. The data pre-fetching method according to claim 1, further comprising: A shared state flag is set in the table entry trained by the shared data prefetcher to record that the shared data prefetcher is shared by the threads of the shared code.

7. The data pre-fetching method according to claim 1, further comprising: In response to the first thread and the second thread among the multiple threads no longer sharing code, the shared data prefetcher obtains a first data prefetcher and a second data prefetcher to be used for the first thread and the second thread to perform the data prefetching process respectively.

8. The data pre-fetching method according to claim 7, wherein: The step of obtaining a first data prefetcher and a second data prefetcher from the shared data prefetcher to respectively use the first thread and the second thread to perform the data prefetching process comprises: enabling the first data prefetcher to retain at least a first portion of table entries of the shared data prefetcher, and The second data prefetcher is made to at least retain a second part of the table entries of the shared data prefetcher, or the second data prefetcher is made empty.

9. The data pre-fetching method according to claim 8, wherein: The first portion of table entries retained by the first data prefetcher and the second portion of table entries retained by the second data prefetcher are at least partially identical to each other.

10. The data pre-fetching method according to claim 8, wherein: After the shared data prefetcher obtains the first data prefetcher and the second data prefetcher, in response to the second data prefetcher being empty, the request issued by the second thread is used for data prefetching training of the second data prefetcher.

11. A data pre-fetching device, comprising: A thread information acquisition module, configured to acquire thread information of a plurality of threads processed in the processor; as well as a data prefetch processing module, configured to, in response to at least a first thread and a second thread among the plurality of threads sharing a code, allow the threads sharing the code to share a same shared data prefetcher to perform data prefetch processing; Wherein, the data pre-fetch processing module includes a pre-fetch training module, and the pre-fetch training module is configured as follows: Using the request issued by the first thread to perform data prefetching training on the shared data prefetcher, Block or filter requests issued by threads sharing the code other than the first thread to prevent the requests issued by threads sharing the code other than the first thread from being used for data prefetching training of the shared data prefetcher.

12. The data pre-fetching device according to claim 11, wherein: The data pre-fetch processing module comprises: The request response module is configured to use the shared data prefetcher to respond to the requests issued by the threads of the shared code respectively.

13. The data pre-fetching device according to claim 11, further comprising: a sharing state determination module, configured to determine, based on thread information of the plurality of threads, that the first thread and the second thread share code, wherein the first thread uses a first data prefetcher to perform the data prefetching process, and the second thread uses a second data prefetcher to perform the data prefetching process; Resource allocation module, configured as: In response to the first thread and the second thread sharing code, merging the first data prefetcher and the second data prefetcher to obtain the shared data prefetcher, or, In response to the first thread and the second thread no longer sharing code, the first data prefetcher and the second data prefetcher are obtained by the shared data prefetcher to be used for the first thread and the second thread to perform the data prefetching process respectively.

14. The data pre-fetching device according to claim 11, further comprising: The identification setting module is configured to set a shared state identification in the table entry trained by the shared data prefetcher to record that the shared data prefetcher is shared by the thread of the shared code.

15. A data pre-fetching device, comprising a processing unit and a memory connected to the processing unit in communication; wherein: The memory stores computer readable instructions; The processing unit executes the computer-readable instructions stored in the memory to implement the data pre-fetching method according to any one of claims 1 to 10.

16. A processor comprising the data pre-fetching device according to any one of claims 11 to 15.

17. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer-readable instructions. When the processor executes the computer-readable instructions, the data pre-fetching method according to any one of claims 1 to 10 is implemented.

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