A display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising a pixel circuit and a light emitting element; the pixel circuit comprising a driving module, a reset module and a bootstrap module; the driving module being configured to selectively provide a driving current to the light emitting element; the driving module comprising a driving transistor; the reset module comprising a first reset transistor; the bootstrap module comprising a first bootstrap capacitor; a first electrode of the first reset transistor receiving a first fixed signal; a second electrode of the first reset transistor being electrically connected with a first plate of the first bootstrap capacitor; a second plate of the first bootstrap capacitor being electrically connected with a gate of the driving transistor at a first node; a working process of the pixel circuit comprising a reset stage; in the reset stage, the first reset transistor is turned on, and the first bootstrap capacitor lowers or raises a potential of the first node according to the first fixed signal. The above technical solution is conducive to reducing power consumption and improving display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Display panels are widely used in electronic devices such as smartphones, tablets, and car navigation systems, becoming indispensable in people's lives and work. With the development of display technology, people's requirements for the display quality of display panels are becoming increasingly higher.

[0003] Display panels typically have a reset module in their pixel circuitry to reset the nodes, improving the accuracy of node potentials and thus enhancing the display panel's performance. However, this reset process generates a significant current, resulting in substantial power consumption. Summary of the Invention

[0004] The present invention provides a display panel and a display device to reduce power consumption during the reset process.

[0005] According to one aspect of the present invention, a display panel is provided, comprising: pixel circuitry and light-emitting elements;

[0006] The pixel circuit includes a driving module, a reset module, and a bootstrap module;

[0007] The driving module is used to selectively provide driving current to the light-emitting element;

[0008] The driving module includes a driving transistor; the reset module includes a first reset transistor; the bootstrap module includes a first bootstrap capacitor; the first terminal of the first reset transistor receives a first fixed signal; the second terminal of the first reset transistor is electrically connected to the first plate of the first bootstrap capacitor; the second plate of the first bootstrap capacitor is electrically connected to the gate of the driving transistor at a first node.

[0009] The operation of the pixel circuit includes a reset phase; during the reset phase, the first reset transistor is turned on, and the first bootstrap capacitor pulls down or raises the potential of the first node according to the first fixed signal.

[0010] According to another aspect of the present invention, a display device is provided, the display device including the above-described display panel.

[0011] The technical solution of this invention, by setting a first bootstrap capacitor of the bootstrap module between the first reset transistor and the first node, allows the bootstrap effect of the first bootstrap capacitor to rapidly change the potential of the first node during the reset phase, reducing the voltage difference between the first node and the first fixed signal, thereby reducing the current flowing through the first reset transistor. This allows the first node to be quickly charged without requiring a large current, enabling it to quickly reset to the required potential, which helps reduce power consumption. Furthermore, by utilizing the capacitive characteristics of the first bootstrap capacitor, current can be isolated after the first node is reset, further contributing to low power consumption. Moreover, the potential of the first node can be maintained without requiring continuous current to charge it, thereby improving the reliability of the pixel circuit. Consequently, when this pixel circuit is applied to a display panel, the display effect of the display panel can be improved.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the circuit structure of a pixel circuit in the prior art;

[0015] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0021] Figure 8 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0022] Figure 9 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0023] Figure 10 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0024] Figure 11 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0025] Figure 12 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0026] Figure 13 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0027] Figure 14 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0028] Figure 15 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0029] Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] Figure 1 This is a schematic diagram of the circuit structure of a pixel circuit in the prior art, for reference. Figure 1 The pixel circuit 01 is electrically connected to the light-emitting element LED, and includes a first light-emitting control transistor M1, a first reset transistor M4, a compensation transistor M5, a second light-emitting control transistor M6, a second reset transistor M7, a write transistor M2, a drive transistor M3, and a storage capacitor Cst. The first terminal of the first reset transistor M4 receives a first reset signal Vref1, and the second terminal of the first reset transistor M4 is electrically connected to the gate of the drive transistor M3 at a first node N1, enabling the first reset transistor M4 to reset the first node N1. The first terminal of the second reset transistor M7 receives a second reset signal Vref2, and the second terminal of the second reset transistor M7 is electrically connected to the anode of the light-emitting element LED at a fourth node N4, enabling the second reset transistor M7 to reset the fourth node N4.

[0033] When the first scan signal Scan1 controls the first reset transistor M4 to turn on, the first reset transistor M4 can reset the first node N1. During this reset phase, the voltage difference between the first and second terminals of the first reset transistor M4 causes a current to flow between them, resulting in power consumption. Furthermore, the time required to reset the potential of the first reset signal Vref1 to the first node N1 is relatively long, leading to significant power consumption, which is detrimental to the low power consumption of the display panel. Similarly, when the first scan signal Scan1 or the second scan signal Scan2 controls the second reset transistor M7 to turn on, the second reset transistor M7 can reset the fourth node N4. During this reset phase, the voltage difference between the first and second terminals of the second reset transistor M7 causes a current to flow between them, resulting in power consumption. Furthermore, the time required to reset the potential of the second reset signal Vref2 to the fourth node N4 is relatively long, leading to significant power consumption, which is also detrimental to the low power consumption of the display panel.

[0034] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, comprising: a pixel circuit and a light-emitting element; the pixel circuit includes a driving module, a reset module, and a bootstrap module; the driving module is used to selectively provide driving current to the light-emitting element; the driving module includes a driving transistor; the reset module includes a first reset transistor; the bootstrap module includes a first bootstrap capacitor; the first electrode of the first reset transistor receives a first fixed signal; the second electrode of the first reset transistor is electrically connected to the first plate of the first bootstrap capacitor; the second plate of the first bootstrap capacitor is electrically connected to the gate of the driving transistor at a first node; the operation of the pixel circuit includes a reset phase; in the reset phase, the first reset transistor is turned on, and the first bootstrap capacitor pulls down or raises the potential of the first node according to the first fixed signal.

[0035] By employing the above technical solution, by setting a first bootstrap capacitor of the bootstrap module between the first reset transistor and the first node, the bootstrap effect of the first bootstrap capacitor can be used during the reset phase to rapidly change the potential of the first node, reducing the voltage difference between the first node and the first fixed signal, thereby reducing the current flowing through the first reset transistor. This allows for rapid charging of the first node without requiring a large current, enabling the first node to quickly reset to the required potential, which helps reduce power consumption. Furthermore, by utilizing the capacitive characteristics of the first bootstrap capacitor, current can be isolated after the first node is reset, contributing to low power consumption. Moreover, the potential of the first node can be maintained without requiring continuous current charging, thereby improving the reliability of the pixel circuit. Consequently, when this pixel circuit is applied to a display panel, the display effect of the display panel can be improved.

[0036] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0037] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 2 The display panel 02 includes multiple pixel units P located in the display area AA. Each pixel unit P includes a pixel circuit 10 and a light-emitting element LED. The pixel circuit 10 is used to convert data signals into driving current and to provide driving current to the light-emitting element LED during the light-emitting phase of the LED.

[0038] Figure 3 This is a schematic diagram of a pixel circuit structure provided in an embodiment of the present invention, for reference. Figure 3The pixel circuit 10 includes a driving module 101, a reset module 102, and a bootstrap module 103. The driving module 101 selectively provides driving current to the light-emitting element LED. The driving module 101 includes a driving transistor M3, the reset module 102 includes a first reset transistor M4, and the bootstrap module 103 includes a first bootstrap capacitor C1. The first terminal of the first reset transistor M4 receives a first fixed signal V1, and the second terminal of the first reset transistor M4 is electrically connected to the first plate of the first bootstrap capacitor C1. The second plate of the first bootstrap capacitor C1 is electrically connected to the gate of the driving transistor M3 at the first node N1. The operation of the pixel circuit 10 includes a reset phase t1. During the reset phase t1, the first reset transistor M4 is turned on, and the first bootstrap capacitor C1 pulls down or raises the potential of the first node N1 according to the first fixed signal V1.

[0039] Specifically, the first reset transistor M4 is electrically connected to the first node N1 through the first bootstrap capacitor C1. During the reset phase t1, the first reset transistor M4 can be turned on under the control of the first scan signal Scan1 received at its gate. The potential of the first fixed signal V1 is transmitted from the first reset transistor M4 to the first plate of the first bootstrap capacitor C1. The potential of the first plate of the first bootstrap capacitor C1 changes. Taking advantage of the characteristic that the potential across the first bootstrap capacitor C1 cannot change abruptly, the potential of its second plate changes, causing the potential of the first node N1 to tend towards the potential of the first fixed signal V1, changing rapidly.

[0040] By setting the first bootstrap capacitor C1 of the bootstrap module 103 between the first reset transistor M4 and the first node N1, on the one hand, the reset of the first node N1 can be accelerated, the voltage difference between the first node N1 and the first fixed signal V1 can be reduced, thereby reducing the current flowing through the first reset transistor M4. On the other hand, the time to reset the first node N1 to the required potential can be shortened, which is beneficial to reducing the power consumption during the reset process.

[0041] On the other hand, by setting the first bootstrap capacitor C1 of the bootstrap module 103 between the first reset transistor M4 and the first node N1, the current between the first reset transistor M4 and the first node N1 can be isolated after the first node N1 is reset, so that the channel current of the first reset transistor M4 is almost zero, which is beneficial to further reduce power consumption. At the same time, the potential of the first node N1 can be stored by using the first bootstrap capacitor C1, and the potential of the first node N1 can still be maintained stably without continuous current charging of the first node N1, thereby ensuring the reliability of the pixel circuit 10 and improving the display effect of the display panel 02.

[0042] In an alternative embodiment, reference continues. Figure 3The pixel circuit 10 also includes a writing module 104. The writing module 104 includes a writing transistor M2, whose first terminal receives a data signal Data, and whose second terminal is electrically connected to a first node N1. The potential of the first fixed signal V1 is the de-enabled potential of the driving transistor M3.

[0043] For details, please refer to Figure 3 The operation of the pixel circuit 10 includes a reset phase t1 and a write phase t2. In the reset phase t1, the first reset transistor M4 is turned on, and the first node N1 can be quickly reset through the first bootstrap capacitor C1 of the bootstrap module 103, causing the driving transistor M3 to turn off and clearing the data signal Data written to the first node N1 in the previous driving cycle. In the write phase t2, the write transistor M2 is turned on, and the data signal Data of the current driving cycle can be written to the first node N1, thereby controlling the magnitude of the driving current provided by the driving transistor M3 to the light-emitting element LED, and realizing the brightness adjustment of the light-emitting element LED.

[0044] In another alternative embodiment, Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, for reference. Figure 4 The pixel circuit 10 also includes a writing module 104 and a compensation module 15. The writing module 104 includes a writing transistor M2, and the compensation module 15 includes a compensation transistor M5. The first terminal of the writing transistor M2 receives a data signal Data, and the second terminal of the writing transistor M2 is electrically connected to the first terminal of the driving transistor M3 at a second node N2. The first terminal of the compensation transistor M5 is electrically connected to the second terminal of the driving transistor M3 at a third node N3, and the second terminal of the compensation transistor M5 is electrically connected to a first node N1. The potential of the first fixed signal V1 is the enable potential of the driving transistor M3.

[0045] For details, please refer to Figure 4 The operation of the pixel circuit 10 includes a reset phase t1 and a write phase t2. In the reset phase t1, the first reset transistor M4 is turned on, and the first node N1 can be quickly reset through the first bootstrap capacitor C1 of the bootstrap module 103, causing the driving transistor M3 to be fully turned on. This clears the residual data signal Data written to the first node N1 in the previous driving cycle, and prepares for the subsequent write phase, where the data signal Data is written to the first node. In the write phase t2, the write transistor M2 and the compensation transistor M5 are turned on. Through the write transistor M2, the driving transistor M3, and the compensation transistor M5, the first node N1 is charged until the driving transistor M3 is turned off, thereby writing the compensated data signal Data to the first node N1. This controls the magnitude of the driving current provided by the driving transistor M3 to the light-emitting element LED, thereby achieving brightness adjustment of the light-emitting element LED.

[0046] Thus, regardless of how the write transistor M2 of the write module 104 is connected, the first reset transistor M4 can be electrically connected to the first node N1 through the first bootstrap capacitor C1 to achieve a fast reset of the first node N1. This allows the gate of the drive transistor M3 to clear the data signal Data written and remaining in the previous drive cycle before writing the data signal Data. At the same time, during the reset phase t1, this can help reduce the power consumption of the pixel circuit 10 during the reset process, thereby helping to reduce the power consumption of the display panel 02 when the pixel circuit 10 is applied to the display panel 02.

[0047] It should be noted that the effective pulses of the first scan signal Scan1 and the second scan signal Scan2 can control the transistors in the pixel circuit 10 to turn on. The effective pulses can be high-level or low-level pulse signals. For P-type transistors, the enable potential is low and the disable potential is high, so the effective pulse can be a low-level pulse signal. For N-type transistors, the enable potential is high and the disable potential is low, so the effective pulse can be a high-level pulse signal. For ease of description, unless otherwise specified, the embodiments of the present invention use P-type transistors and low-level pulse signals as examples to illustrate the technical solutions of the embodiments of the present invention.

[0048] Optional, see reference Figure 3 and Figure 4 The pixel circuit 10 also includes a storage module 106. The storage module 106 includes a storage capacitor Cst, the first plate of which receives a first power signal PVDD, and the second plate of which is electrically connected to a first node N1; wherein, the capacitance of the first bootstrap capacitor C1 is greater than the capacitance of the storage capacitor Cst.

[0049] Specifically, after the data signal Data is written to the first node N1, the storage capacitor Cst stores charge and maintains the potential stability of the first node N1. By setting a relatively large value for the first bootstrap capacitor C1, when the first reset transistor M4 is turned on, the first bootstrap capacitor C1 can overcome the potential maintenance effect of the storage capacitor Cst on the first node N1, thereby achieving a rapid reset of the first node N1. In this way, power consumption can be effectively reduced.

[0050] Optional, Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 5 and Figure 6The bootstrap module 103 also includes a first bootstrap transistor M8. The first terminal of the first bootstrap transistor M8 receives a second fixed signal V2, and the second terminal of the first bootstrap transistor M8 is electrically connected to the first plate of the first bootstrap capacitor C1. The operation of the pixel circuit 10 also includes a writing stage t2. In the writing stage t2, the writing transistor M2 is turned on, and the data signal Data is written to the first node N1. In the writing stage t2, the first bootstrap transistor M8 is also turned on, and the first bootstrap capacitor C1 raises or lowers the potential of the first node N1 according to the second fixed signal V2. The potential of the first fixed signal V1 is the de-enabled potential of the driving transistor M3, and the potential of the second fixed signal V2 is the enabled potential of the driving transistor M3; or, the potential of the first fixed signal V1 is the enabled potential of the driving transistor M3, and the potential of the second fixed signal V2 is the de-enabled potential of the driving transistor M3.

[0051] For example, refer to Figure 5 The pixel circuit 10 includes a write transistor M2. The first terminal of the write transistor M2 receives the data signal Data, and the second terminal of the write transistor M2 is electrically connected to the first node N1. At this time, the potential of the first fixed signal V1 is the de-enabled potential of the driving transistor M3, and the potential of the second fixed signal V2 is the enabled potential of the driving transistor M3. During the write phase t2, the write transistor M2 and the first bootstrap transistor M8 are turned on. While the write transistor M2 writes the data signal Data to the first node N1, the first bootstrap transistor M8 writes the second fixed signal V2 to the first plate of the first bootstrap capacitor C1. Utilizing the characteristic that the potential across the first bootstrap capacitor C1 cannot change abruptly, the potential of its second plate changes, causing the potential of the first node N1 to tend towards the potential of the second fixed signal V2. This rapid change can accelerate the transition of the first node N1 towards the data signal Data, reduce the current flowing through the write transistor M2 and the charging time of the first node N1 during the write phase t2, and help reduce power consumption.

[0052] Similarly, refer to Figure 6The pixel circuit 10 includes a write transistor M2 and a compensation transistor M5. At this time, the potential of the first fixed signal V1 is the enable potential of the drive transistor M3, and the potential of the second fixed signal V2 is the disable potential of the drive transistor M3. During the write phase t2, the write transistor M2, the compensation transistor M5, and the first bootstrap transistor M8 are turned on. While the write transistor M2 writes the data signal Data to the first node N1, the first bootstrap transistor M8 writes the second fixed signal V2 to the first plate of the first bootstrap capacitor C1. Utilizing the characteristic that the potential across the first bootstrap capacitor C1 cannot change abruptly, the potential of its second plate changes, causing the potential of the first node N1 to tend towards the potential of the second fixed signal V2. This rapid change can accelerate the transition of the first node N1 towards the data signal Data, reducing the current flowing through the write transistor M2 and the charging time of the first node N1 during the write phase t2, which is beneficial for reducing power consumption.

[0053] Optionally, when the potential of the second fixed signal V2 is the enable potential of the driving transistor M3, the channel type of the first bootstrap transistor M8 is the same as the channel type of the driving transistor M3, such as... Figure 5 As shown; or, when the potential of the second fixed signal V2 is the non-enable potential of the driving transistor M3, the channel type of the first bootstrap transistor M8 is different from the channel type of the driving transistor M3, such as... Figure 7 As shown.

[0054] For example, taking a P-type transistor as the driving transistor M3, the enable potential of the driving transistor M3 is low, and the disable potential of the driving transistor M3 is high. (Reference) Figure 5 When the second terminal of the write transistor M2 is electrically connected to the gate of the drive transistor M3 at the first node N1, the potential of the first fixed signal V1 is high, and the potential of the second fixed signal V2 is low. At this time, the first bootstrap transistor M8 is a P-type transistor, and the enable potential of the first bootstrap transistor M8 is also low. During the write phase t2, the first node N1 is pulled low. During this phase, the third scan signal ScanP received by the gate of the first bootstrap transistor M8 is low. The parasitic capacitance of the first bootstrap transistor M8 can affect the potential of the second terminal of the first bootstrap transistor M8 to be lower, that is, affect the first plate of the first bootstrap capacitor C1 to be lower. Due to the characteristics of the first bootstrap capacitor C1, the potential of the second plate of the first bootstrap capacitor C1 can be pulled low, which is beneficial to accelerate the potential change of the first node N1 and reduce power consumption. This avoids the parasitic capacitance of the first bootstrap transistor M8 causing the potential of the first node N1 to be higher, delaying the potential change of the first node N1 and increasing power consumption.

[0055] refer to Figure 7When the second terminal of the write transistor M2 and the first terminal of the drive transistor M3 are electrically connected to the second node N2, the potential of the first fixed signal V1 is low, and the potential of the second fixed signal V2 is high. At this time, the first bootstrap transistor M8 is an N-type transistor, and the enable potential of the first bootstrap transistor M8 is high. During the write phase t2, the first node N1 is raised. During this phase, the third scan signal ScanP received by the gate of the first bootstrap transistor M8 is high. The parasitic capacitance of the first bootstrap transistor M8 can affect the potential of the second terminal of the first bootstrap transistor M8 to be higher, that is, affect the first plate of the first bootstrap capacitor C1 to be higher. Due to the characteristics of the first bootstrap capacitor C1, the potential of the second plate of the first bootstrap capacitor C1 can be raised, which is beneficial to accelerate the potential change of the first node N1 and reduce power consumption. This avoids the parasitic capacitance of the first bootstrap transistor M8 causing the potential of the first node N1 to be lower, delaying the potential change of the first node N1 and increasing power consumption.

[0056] In an optional embodiment, when the second terminal of the write transistor M2 is electrically connected to the gate of the drive transistor M3 at the first node N1, the channel type of the write transistor M2 is the same as the channel type of the drive transistor M3, such as... Figure 5 As shown; or, when the second terminal of the write transistor M2 and the first terminal of the drive transistor M3 are electrically connected to the second node N2, the channel type of the write transistor M2 is different from the channel type of the drive transistor M3, such as... Figure 8 As shown.

[0057] For example, taking a P-type transistor as the driving transistor M3, the enable potential of the driving transistor M3 is low, and the disable potential of the driving transistor M3 is high. (Reference) Figure 5 When the second terminal of the write transistor M2 is electrically connected to the gate of the drive transistor M3 at the first node N1, the write transistor M2 is a P-type transistor, and its enable potential is also low. During the write phase t2, the first node N1 is pulled low. During this phase, the second scan signal Scan2 received by the gate of the write transistor M2 is low. The parasitic capacitance of the write transistor M2 can affect the low potential of its second terminal, thus affecting the low potential of the first node N1. Under the action of the first bootstrap capacitor C1, this helps to accelerate the potential change of the first node N1 and reduce power consumption. This avoids the parasitic capacitance of the write transistor M2 causing the potential of the first node N1 to be too high, thus delaying the potential change of the first node N1 and increasing power consumption.

[0058] refer to Figure 8When the second terminal of the write transistor M2 is electrically connected to the first terminal of the drive transistor M3 at the second node N2, the write transistor M2 is an N-type transistor, and its enable potential is high. During the write phase t2, the first node N1 is raised. During this phase, the second scan signal Scan2 received by the gate of the write transistor M2 is high. The parasitic capacitance of the write transistor M2 can affect the high potential of its second terminal, which in turn affects the high potential of the first node N1. Under the action of the first bootstrap capacitor C1, this helps to accelerate the potential change of the first node N1 and reduce power consumption, thus avoiding the parasitic capacitance of the write transistor M2 causing the potential of the first node N1 to be low, delaying the potential change of the first node N1, and increasing power consumption.

[0059] Optional, see reference Figure 9 and Figure 10 The pixel circuit 10 also includes a light-emitting control module 107, which controls the driving transistor M3 to provide driving current to the light-emitting element LED when it is turned on. The pixel circuit 10 also includes a light-emitting stage t3, in which the light-emitting control module 107 is turned on and the first bootstrap transistor M8 is also turned on.

[0060] For example, the light-emitting control module 107 includes a first light-emitting control transistor M1 and a second light-emitting control transistor M6. The first terminal of the first light-emitting control transistor M1 receives a first power signal PVDD. The second terminal of the first light-emitting control transistor M1 is electrically connected to the first terminal of the driving transistor M3. The first terminal of the second light-emitting control transistor M6 is electrically connected to the second terminal of the driving transistor M3. The second terminal of the second light-emitting control transistor M6 is electrically connected to the anode of the light-emitting element LED. The cathode of the light-emitting element LED receives a second power signal PVEE.

[0061] Specifically, during the light-emitting stage t3, the first light-emitting control transistor M1, the driving transistor M3, and the second light-emitting control transistor M6 are all turned on. The driving transistor M3 provides a driving current to the light-emitting element LED. The magnitude of the driving current is related to the potential of the first node N1. The first bootstrap capacitor C1 can also store charge. By setting the first bootstrap transistor M8 to be turned on during the light-emitting stage t3, the first plate of the first bootstrap capacitor C1 can receive the first fixed signal V1, which helps to maintain the potential stability of the first node N1 and improve the display effect.

[0062] Optional, Figure 11 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention, for reference. Figure 9 , Figure 10 and Figure 11The gate of the first reset transistor M4 receives the first scan signal Scan1, the gate of the write transistor M2 receives the second scan signal Scan2, and the gate of the first bootstrap transistor M8 receives the third scan signal ScanP. In one drive cycle F0 of the pixel circuit 10, the first scan signal Scan1 includes a first valid pulse S1, the second scan signal Scan2 includes a second valid pulse S2, and the third scan signal ScanP includes a third valid pulse S3. The effective time of the third valid pulse S3 does not overlap with the effective time of the first valid pulse S1, but the effective time of the third valid pulse S3 overlaps with the effective time of the second valid pulse S2.

[0063] For example, taking the pixel circuit 10 as a P-type transistor, the effective pulse is a low-level pulse signal. The first effective pulse S1 is located in the reset phase t1. In this phase, the first reset transistor M4 is turned on, the write transistor M2 and the first bootstrap transistor M8 are both turned off, and the first node N1 is reset. The second effective pulse S2 is located in the write phase t2. In this phase, the first reset transistor M4 is turned off, the write transistor M2 and the first bootstrap transistor M8 are both turned on, and the first node N1 writes the data signal Data. The effective time of the third effective pulse S3 overlaps with the effective time of the second effective pulse S2, which can ensure that when the write transistor M2 writes the data signal Data to the first node N1, the first bootstrap transistor M8 can be turned on. On the one hand, the first bootstrap capacitor C1 can accelerate the potential change of the first node N1 and reduce power consumption in the early stage of writing the data signal Data. On the other hand, the first bootstrap capacitor C1 can store charge after the data signal Data is written to the first node N1, which is beneficial to maintaining the potential stability of the first node N1.

[0064] Furthermore, the effective time of the third effective pulse S3 overlaps with the start time of the second effective pulse S2 to ensure that the first bootstrap capacitor C1 can accelerate the potential change of the first node N1 and reduce power consumption.

[0065] Based on the above embodiments, Figure 12 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 9 , Figure 10 and Figure 12The pixel circuit 10 also includes a light-emitting control module 107, which controls the driving transistor M3 to provide driving current to the light-emitting element LED when it is turned on. The light-emitting control module 107 includes light-emitting control transistors (M1, M6), whose gates receive a light-emitting control signal Emit. In one driving cycle F0 of the pixel circuit, the light-emitting control signal Emit includes a fourth valid pulse S4. The effective time of the third valid pulse S3 overlaps with the effective time of the fourth valid pulse S4.

[0066] For example, taking the pixel circuit 10 as an example where all transistors are P-type transistors, the effective pulse is a low-level pulse signal. The fourth effective pulse S4 is located in the light-emitting stage t3. In this stage, the first node N1 has been written with the data signal Data, and both the light-emitting control transistors (M1, M6) and the driving transistor M3 are turned on. The driving transistor M3 provides driving current to the light-emitting element LED, and the potential of the first node N1 can control the magnitude of the driving current. By setting the effective time of the third effective pulse S3 to overlap with the effective time of the fourth effective pulse S4, when the driving transistor M3 provides driving current to the light-emitting element LED, the first bootstrap transistor M8 is turned on, so that the first plate of the first bootstrap capacitor C1 can receive the first fixed signal V1, which helps to maintain the potential stability of the first node N1 and improve the display effect.

[0067] Furthermore, the effective time of the third effective pulse S3 covers the termination time of the second effective pulse S2 and the start time of the fourth effective pulse S4. Thus, before the data signal Data of the first node N1 is written to completion and before the light-emitting control transistors (M1, M6) are turned on, the first bootstrap transistor M8 can be controlled to turn on. After the first bootstrap transistor M8 causes a potential fluctuation in the first node N1, the write transistor M2 can rewrite the data signal Data to the first node N1 after the potential fluctuation, which is beneficial to the potential accuracy of the first node N1 and improves the display effect.

[0068] Optional, Figure 13 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 13 The pixel circuit 10 and the light-emitting element LED are electrically connected to the fourth node N4. The reset module 102 also includes a second reset transistor M7, and the bootstrap module 103 also includes a second bootstrap capacitor C2. The first terminal of the second reset transistor M7 receives a third fixed signal V3, the second terminal of the second reset transistor M7 is electrically connected to the first plate of the second bootstrap capacitor C2, and the second plate of the second bootstrap capacitor C2 is electrically connected to the fourth node N4. During the reset phase t1, the second reset transistor M7 is turned on, and the second bootstrap capacitor C2 pulls down the potential of the fourth node N4 according to the third fixed signal V3.

[0069] Specifically, the second reset transistor M7 is electrically connected to the fourth node N4 through the second bootstrap capacitor C2. During the reset phase t1, the second reset transistor M7 is turned on, and the potential of the third fixed signal V3 is transmitted from the second reset transistor M7 to the first plate of the second bootstrap capacitor C2. The potential of the first plate of the second bootstrap capacitor C2 changes. Taking advantage of the characteristic that the potential across the second bootstrap capacitor C2 cannot change abruptly, the potential of its second plate changes, causing the potential of the fourth node N4 to tend towards the potential of the third fixed signal V3, changing rapidly. On the one hand, it can speed up the reset of the fourth node N4, reduce the voltage difference between the fourth node N4 and the third fixed signal V3, thereby reducing the current flowing through the second reset transistor M7. At the same time, it can also shorten the time to reset the fourth node N4 to the required potential, which is beneficial to reduce the power consumption during the reset process. On the other hand, the first bootstrap capacitor C1 can isolate the current between the second reset transistor M7 and the fourth node N4 after the fourth node N4 is reset, so that the channel current of the second reset transistor M7 is almost zero, which is beneficial to further reduce power consumption. At the same time, the first bootstrap capacitor C1 can store the potential of the first node N1, without the need for continuous current to charge the fourth node N4, and can still maintain the potential stability of the fourth node N4, thereby ensuring the reliability of the pixel circuit 10 and improving the display effect of the display panel 02.

[0070] For example, taking the anode of the light-emitting element LED and the pixel circuit 10 electrically connected to the fourth node N4, the potential of the third fixed signal V3 is low, for example, it can be negative. When the second reset transistor M7 is turned on, the potential of the first plate of the first bootstrap capacitor C1 is negative, which drives the second plate of the first bootstrap capacitor C1 to pull down, causing the potential of the fourth node N4 to drop rapidly.

[0071] It should be noted that, Figure 13 This is merely an example illustrating the case where the second terminal of the write transistor M2 is electrically connected to the first terminal of the drive transistor M3 at the second node N2. However, it is not limited to this. In other embodiments, the second terminal of the write transistor M2 may also be electrically connected to the gate of the drive transistor M3 at the first node N1.

[0072] In other feasible implementations, the second reset transistor M7 can be turned on during the write phase t2. For example, the second reset transistor M7 can be turned on simultaneously with the write transistor M2. When the channel types of the two are the same, the gate of the second reset transistor M7 and the gate of the write transistor M2 can receive the same scan signal.

[0073] In other feasible implementations, the cathode of the light-emitting element LED is electrically connected to the pixel circuit 10 at the fourth node N4 (not shown in the figure). When the second reset transistor M7 is turned on, the second bootstrap capacitor C2 rapidly raises the potential of the fourth node N4 according to the third fixed signal V3.

[0074] Based on the above embodiments, Figure 14 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 14 The bootstrap module 103 also includes a second bootstrap transistor M9. The first terminal of the second bootstrap transistor M9 receives a fourth fixed signal V4, and the second terminal of the second bootstrap transistor M9 is electrically connected to the first plate of the second bootstrap capacitor C2. The operation of the pixel circuit 10 also includes a light-emitting stage t3. In the light-emitting stage t3, the driving transistor M3 provides a driving current to the light-emitting element LED, the second bootstrap transistor M9 is turned on, and the second bootstrap capacitor C2 raises the potential of the fourth node N4 according to the fourth fixed signal V4. The potential of the fourth fixed signal V4 is higher than the potential of the third fixed signal V3.

[0075] For example, taking the anode of the light-emitting element LED and the pixel circuit 10 electrically connected to the fourth node N4, the potential of the third fixed signal V3 is low, and the potential of the fourth fixed signal V4 is high. During the light-emitting stage t3, when the second bootstrap transistor M9 is turned on, the second bootstrap transistor M9 writes the fourth fixed signal V4 to the first plate of the second bootstrap capacitor C2. Utilizing the characteristic that the potential across the second bootstrap capacitor C2 cannot change abruptly, it drives a change in the potential of its second plate, causing the potential of the fourth node N2 to rise rapidly, which helps to reduce power consumption.

[0076] In other feasible embodiments, the cathode of the light-emitting element LED is electrically connected to the pixel circuit 10 at the fourth node N4 (not shown in the figure). When the second bootstrap transistor M9 is turned on, the second bootstrap capacitor C2 quickly pulls down the potential of the fourth node N4 according to the fourth fixed signal V4. At this time, the potential of the fourth fixed signal V4 is lower than the potential of the third fixed signal V3.

[0077] Further reference Figure 14 The channel type of the second bootstrap transistor M9 is N-type.

[0078] For example, consider the anode of the light-emitting element LED being electrically connected to the pixel circuit 10 at the fourth node N4. During the light-emitting stage t3, the fourth node N4 is raised. During this stage, the sixth scan signal ScanP' received by the gate of the second bootstrap transistor M9 is at a high level. The parasitic capacitance of the second bootstrap transistor M9 can affect the potential of the second terminal of the second bootstrap transistor M9 to be higher. Under the action of the second bootstrap capacitor C2, it is beneficial to accelerate the potential change of the fourth node N4 and reduce power consumption, so as to avoid the parasitic capacitance of the second bootstrap transistor M9 affecting the fourth node N4 to fluctuate in the opposite direction, delaying the potential change of the fourth node N4 and increasing power consumption.

[0079] Further reference Figure 14 The channel type of the second reset transistor M7 is P-type.

[0080] For example, consider the anode of the light-emitting element LED being electrically connected to the pixel circuit 10 at the fourth node N4. When the second reset transistor M7 is turned on, the fourth node N4 is pulled low. During this stage, the fifth scan signal received at the gate of the second reset transistor M7 is at a low level. The parasitic capacitance of the second reset transistor M7 can affect the low potential of the second terminal of the second reset transistor M7. Under the action of the second bootstrap capacitor C2, this helps to accelerate the potential change of the fourth node N4 and reduce power consumption, so as to avoid the parasitic capacitance of the second reset transistor M7 affecting the fourth node N4 to fluctuate in the opposite direction, delaying the potential change of the fourth node N4 and increasing power consumption.

[0081] In an optional implementation, the fifth scan signal may be multiplexed from the first scan signal Scan1 and / or the second scan signal Scan2.

[0082] Based on the above embodiments, Figure 15 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention, for reference. Figure 14 and Figure 15The pixel circuit 10 also includes a light-emitting control module 107, which controls the driving transistor M3 to provide driving current to the light-emitting element LED when it is turned on. The light-emitting control module 107 includes light-emitting control transistors (M1, M6). The gates of the light-emitting control transistors (M1, M6) receive the light-emitting control signal Emit, the gate of the second reset transistor M7 receives the fifth scan signal, and the gate of the second bootstrap transistor M9 receives the sixth scan signal ScanP'. In one driving cycle F0 of the pixel circuit, the light-emitting control signal Emit includes a fourth valid pulse S4, the fifth scan signal includes a fifth valid pulse S5, and the sixth scan signal ScanP' includes a sixth valid pulse S6. The effective time of the sixth valid pulse S6 overlaps with the effective time of the fourth valid pulse S4, but does not overlap with the effective time of the fifth valid pulse S5.

[0083] For example, the fifth scan signal multiplexes the first scan signal Scan1 and / or the second scan signal Scan2. Taking the example that all transistors in the pixel circuit 10 are P-type transistors, the effective pulse is a low-level pulse signal. The fourth effective pulse S4 is located in the light-emitting stage t3. In this stage, the fourth node N4 has been reset. The sixth effective pulse S6 of the sixth scan signal ScanP' controls the second bootstrap transistor M9 to turn on, so that the second bootstrap transistor M9 writes the fourth fixed signal V4 into the first plate of the second bootstrap capacitor C2. Taking advantage of the characteristic that the potential at both ends of the second bootstrap capacitor C2 cannot change abruptly, it drives the potential of its second plate to change, so that the potential of the fourth node N2 rises rapidly, which helps to reduce power consumption.

[0084] Furthermore, the effective time of the sixth effective pulse S6 covers the start time of the fourth effective pulse S4. Thus, the second bootstrap transistor M9 can be turned on before the light-emitting control transistors (M1, M6) are turned on, ensuring that when the light-emitting control transistors (M1, M6) are turned on, the bootstrap module can effectively accelerate the potential rise of the fourth node N4, which helps reduce power consumption.

[0085] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 16 The display device 03 includes the display panel 02 provided in any embodiment of the present invention. The display device 03 provided in the embodiments of the present invention can be... Figure 16 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0086] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module, a reset module, and a bootstrap module; The driving module is used to selectively provide driving current to the light-emitting element; The driving module includes a driving transistor; the reset module includes a first reset transistor; the bootstrap module includes a first bootstrap capacitor; the first terminal of the first reset transistor receives a first fixed signal; the second terminal of the first reset transistor is electrically connected to the first plate of the first bootstrap capacitor; the second plate of the first bootstrap capacitor is electrically connected to the gate of the driving transistor at a first node. The operation of the pixel circuit includes a reset phase; in the reset phase, the first reset transistor is turned on, and the first bootstrap capacitor pulls down or raises the potential of the first node according to the first fixed signal. The bootstrap module further includes a first bootstrap transistor; the first terminal of the first bootstrap transistor receives a second fixed signal; the second terminal of the first bootstrap transistor is electrically connected to the first plate of the first bootstrap capacitor. The pixel circuit further includes a writing module; the writing module includes a writing transistor; the first terminal of the writing transistor receives a data signal; the second terminal of the writing transistor is coupled to the first node; The operation of the pixel circuit also includes a writing phase; during the writing phase, the writing transistor is turned on, and the data signal is written to the first node. During the writing phase, the first bootstrap transistor is also turned on, and the first bootstrap capacitor raises or lowers the potential of the first node according to the second fixed signal. Wherein, the potential of the first fixed signal is the de-enabled potential of the driving transistor, and the potential of the second fixed signal is the enabled potential of the driving transistor; Alternatively, the potential of the first fixed signal is the enable potential of the driving transistor, and the potential of the second fixed signal is the disable potential of the driving transistor.

2. The display panel according to claim 1, characterized in that, The second terminal of the write transistor is electrically connected to the first node; Wherein, the potential of the first fixed signal is the non-enable potential of the driving transistor.

3. The display panel according to claim 1, characterized in that, The pixel circuit further includes a compensation module; the compensation module includes a compensation transistor; The second terminal of the write transistor is electrically connected to the first terminal of the drive transistor at the second node; the first terminal of the compensation transistor is electrically connected to the second terminal of the drive transistor at the third node; the second terminal of the compensation transistor is electrically connected to the first node. Wherein, the potential of the first fixed signal is the enable potential of the driving transistor.

4. The display panel according to claim 1, characterized in that, When the potential of the second fixed signal is the enable potential of the driving transistor, the channel type of the first bootstrap transistor is the same as the channel type of the driving transistor. Alternatively, when the potential of the second fixed signal is the non-enable potential of the driving transistor, the channel type of the first bootstrap transistor is different from the channel type of the driving transistor.

5. The display panel according to claim 1, characterized in that, The pixel circuit further includes a light-emitting control module; the light-emitting control module is used to control the driving transistor to provide driving current to the light-emitting element when it is turned on; The pixel circuit further includes a light-emitting stage; during the light-emitting stage, the light-emitting control module is turned on, and the first bootstrap transistor is also turned on.

6. The display panel according to claim 1, characterized in that, The gate of the first reset transistor receives a first scan signal; the gate of the write transistor receives a second scan signal; and the gate of the first bootstrap transistor receives a third scan signal. In one driving cycle of the pixel circuit, the first scan signal includes a first valid pulse, the second scan signal includes a second valid pulse, and the third scan signal includes a third valid pulse; Wherein, the effective time of the third effective pulse does not overlap with the effective time of the first effective pulse; however, the effective time of the third effective pulse overlaps with the effective time of the second effective pulse.

7. The display panel according to claim 6, characterized in that, The pixel circuit further includes a light-emitting control module; the light-emitting control module is used to control the driving transistor to provide driving current to the light-emitting element when it is turned on; The light-emitting control module includes a light-emitting control transistor, the gate of which receives a light-emitting control signal; In one driving cycle of the pixel circuit, the light emission control signal includes a fourth valid pulse; The effective time of the third effective pulse overlaps with the effective time of the fourth effective pulse.

8. The display panel according to claim 1, characterized in that, The pixel circuit is electrically connected to the light-emitting element at the fourth node; The reset module further includes a second reset transistor; the bootstrap module further includes a second bootstrap capacitor; the first terminal of the second reset transistor receives a third fixed signal; the second terminal of the second reset transistor is electrically connected to the first plate of the second bootstrap capacitor; the second plate of the second bootstrap capacitor is electrically connected to the fourth node; During the reset phase, the second reset transistor is turned on, and the second bootstrap capacitor pulls down the potential of the fourth node according to the third fixed signal.

9. The display panel according to claim 8, characterized in that, The bootstrap module further includes a second bootstrap transistor; The first terminal of the second bootstrap transistor receives a fourth fixed signal; the second terminal of the second bootstrap transistor is electrically connected to the first plate of the second bootstrap capacitor. The operation of the pixel circuit also includes a light-emitting stage; During the light-emitting phase, the driving transistor provides a driving current to the light-emitting element, the second bootstrap transistor is turned on, and the second bootstrap capacitor raises the potential of the fourth node according to the fourth fixed signal. The potential of the fourth fixed signal is higher than that of the third fixed signal.

10. The display panel according to claim 9, characterized in that, The second bootstrap transistor has an N-type channel.

11. The display panel according to claim 9, characterized in that, The pixel circuit further includes a light-emitting control module; the light-emitting control module is used to control the driving transistor to provide driving current to the light-emitting element when it is turned on; The light-emitting control module includes a light-emitting control transistor, the gate of which receives a light-emitting control signal; the gate of the second reset transistor receives a fifth scan signal; and the gate of the second bootstrap transistor receives a sixth scan signal. In one driving cycle of the pixel circuit, the light emission control signal includes a fourth valid pulse, the fifth scan signal includes a fifth valid pulse, and the sixth scan signal includes a sixth valid pulse; The effective time of the sixth effective pulse overlaps with the effective time of the fourth effective pulse. The effective time of the sixth effective pulse does not overlap with the effective time of the fifth effective pulse.

12. The display panel according to claim 1, characterized in that, The pixel circuit also includes a storage module; The storage module includes a storage capacitor; the first plate of the storage capacitor receives a first power signal, and the second plate of the storage capacitor is electrically connected to the first node. The capacitance of the first bootstrap capacitor is greater than the capacitance of the storage capacitor.

13. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1-12.

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