Scanning driving circuit, scanning driving method, display panel and display device

Abstract

The present invention discloses a scanning driving circuit, a scanning driving method, a display panel and a display device, and relates to the field of display technology. The circuit includes a plurality of cascaded gate scanning driving circuits, the gate scanning driving circuit includes an input module, a pull-down module, an output module and a pull-up control node, the input module, the output module and the pull-down module are respectively connected to the pull-up control node; when the potential of the pull-up control node is the first potential, the pull-down module adjusts the off-state leakage current to the minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal to maintain the first potential of the pull-up control node; when the potential of the pull-up control node is the first potential, the output module outputs a scanning signal and a level transmission signal according to the clock signal and the first control signal. In the above manner, the TFT off-state voltage is adjusted, the off-state leakage current is controlled to the minimum value in the high potential stage of the Q point, the high potential of the Q point is maintained, and high temperature abnormality is avoided.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a scan driving circuit, a scan driving method, a display panel and a display device. Background Art

[0002] As liquid crystal display technology continues to mature, liquid crystal displays (LCD) have been widely used in various fields. At present, LCD generally adopts gate driver less (GDL) technology, and the gate scanning drive circuit (ie, GDL circuit) of LCD is manufactured on the array substrate.

[0003] In the GDL circuit, if the Q point (pull-up control node) is in a high potential period, the QB point (pull-down control node) potential is always at a low potential, and the related TFT (Thin Film Transistor) is in a closed state, but its leakage current is high (nA order of magnitude), the non-leakage current is minimum (pA order of magnitude), and the leakage current is large, resulting in the inability to maintain the high potential of the Q point, and the Gout output waveform is distorted, especially under high temperature conditions, the leakage current increases, and high temperature image abnormalities are prone to occur, affecting the display effect. Summary of the invention

[0004] The main purpose of the present invention is to provide a scan drive circuit, a scan drive method, a display panel and a display device, aiming to solve the technical problem in the prior art that high temperature image distortion is caused by TFT leakage, which affects the display effect.

[0005] To achieve the above object, the present invention provides a scan driving circuit, the scan driving circuit includes a plurality of cascaded gate scanning driving circuits, the gate scanning driving circuit includes an input module, a pull-down module, an output module and a pull-up control node, the input module, the output module and the pull-down module are respectively connected to the pull-up control node, the input module is connected to a first control signal, the output module is connected to a clock signal, and the pull-down module is connected to a first low level signal and a second low level signal;

[0006] The input module is used to pull up the potential of the pull-up control node to a first potential according to the first control signal;

[0007] The pull-down module is used for adjusting the off-state leakage current to a minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal when the potential of the pull-up control node is the first potential, so as to maintain the first potential of the pull-up control node;

[0008] The output module is used to output a scan signal and a level transfer signal according to the clock signal and the first control signal when the potential of the pull-up control node is a first potential.

[0009] Optionally, the gate scanning drive circuit further includes an output pull-down module, a reverse control module and a pull-down control node, the pull-down module, the output pull-down module and the reverse control module are respectively connected to the pull-down control node, the pull-down module and the reverse control module are respectively connected to the pull-up control node, the output pull-down module is connected to the second control signal, the reverse control module is connected to the power supply voltage, and the pull-down module is connected to the second control signal;

[0010] The pull-down module is further used to pull down the potential of the pull-up control node to a second potential according to the second control signal;

[0011] The reverse control module is further used to pull up the potential of the pull-down control node to the first potential and pull down the potential of the output end in the output module when the potential of the pull-up control node is the second potential;

[0012] The pull-down module is further used to maintain the first potential of the pull-down control node;

[0013] The output pull-down module is used to pull down the potential of the output terminal in the output module according to the second control signal when the potential of the pull-down control node is the first potential;

[0014] The output module is also used to stop outputting the scanning signal and the level transmission signal after the potential of the output terminal is pulled down.

[0015] Optionally, the pull-down module includes a first pull-down unit and a pull-down control unit, the first pull-down unit is connected to the second low-level signal, and the pull-down control unit is connected to the second control signal;

[0016] The first pull-down unit is used to adjust the off-state leakage current to a minimum value according to the target off-state voltage;

[0017] The pull-down control unit is used to pull down the potential of the pull-up control node to a second potential according to the second control signal.

[0018] Optionally, the first pull-down unit includes a first transistor, a second transistor and a third transistor, the first transistor is connected in series with the second transistor, the first end of the first transistor is connected to the second end of the second transistor, the control end of the first transistor and the control end of the second transistor are both connected to the pull-down control node, the pull-up control node is respectively connected to the first end of the second transistor and the control end of the third transistor, the second end of the first transistor is connected to the first low-level signal, the first end of the third transistor is connected to the second low-level signal, and the second end of the third transistor is connected to the second end of the second transistor;

[0019] The pull-down control unit includes a fourth transistor, a control terminal of the fourth transistor is connected to the second control signal, a first terminal of the fourth transistor is connected to the pull-down control node, and a second terminal of the fourth transistor is connected to the first low level signal.

[0020] Optionally, the pull-down module also includes a second pull-down unit, the second pull-down unit includes a fifth transistor, a sixth transistor and a seventh transistor, the fifth transistor is connected in series with the sixth transistor, the first end of the fifth transistor is connected to the second end of the sixth transistor, the second end of the fifth transistor is connected to the second end of the first transistor, the control end of the sixth transistor is respectively connected to the second end of the fourth transistor, the control end of the seventh transistor and the control end of the fifth transistor, the first end of the seventh transistor is connected to the second end of the sixth transistor, and the second end of the seventh transistor is connected to the second low-level signal.

[0021] Optionally, the input module includes an eighth transistor and a ninth transistor, the control end and the first end of the eighth transistor are respectively connected to the first control signal, the second end of the eighth transistor is connected to the first end of the ninth transistor, and the control end of the ninth transistor is connected to the second control signal.

[0022] Optionally, the output module includes a tenth transistor, an eleventh transistor and a capacitor, the output end includes a first output end and a second output end, the first output end outputs a stage transmission signal, the second output end outputs a scan signal, the control end of the tenth transistor is connected to the pull-up control node, the second end of the tenth transistor is connected to the first output end, the first end of the tenth transistor is connected to the clock signal, the control end of the eleventh transistor is respectively connected to the pull-up control node and the first end of the capacitor, the second end of the eleventh transistor is respectively connected to the second end of the capacitor and the second output end, and the first end of the eleventh transistor is connected to the clock signal.

[0023] To achieve the above object, the present invention further provides a scanning driving method, the scanning driving method comprising:

[0024] According to the first control signal, the potential of the pull-up control node is pulled up to the first potential;

[0025] When the potential of the pull-up control node is a first potential, adjusting the off-state leakage current to a minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal to maintain the first potential of the pull-up control node;

[0026] When the potential of the pull-up control node is a first potential, a scan signal and a level transfer signal are output according to a clock signal and the first control signal.

[0027] To achieve the above object, the present invention further proposes a display panel, including a display area and a non-display area, wherein the non-display area is provided with a scanning driving circuit as described above, and the scanning driving circuit is used to provide a row scanning signal for the display area.

[0028] To achieve the above object, the present invention further proposes a display device, comprising a backlight module and a display panel as described above, wherein the backlight module is arranged corresponding to the display panel, and the backlight module is used to provide a backlight source to the display panel.

[0029] In the present invention, the scan drive circuit includes a plurality of cascaded gate scan drive circuits, the gate scan drive circuit includes an input module, a pull-down module, an output module and a pull-up control node, the input module, the output module and the pull-down module are respectively connected to the pull-up control node, the input module is connected to a first control signal, the output module is connected to a clock signal, the pull-down module is connected to a first low-level signal and a second low-level signal, the input module is used to pull up the potential of the pull-up control node to a first potential according to the first control signal, the pull-down module is used to adjust the off-state leakage current to a minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal when the potential of the pull-up control node is the first potential, so as to maintain the first potential of the pull-up control node, and the output module is used to output a scan signal and a stage transmission signal according to the clock signal and the first control signal when the potential of the pull-up control node is the first potential. Compared with the high-temperature image distortion caused by the large TFT leakage in the traditional GDL circuit, the present invention adjusts the TFT off-state voltage in the pull-down module to control the off-state leakage current to the minimum value in the high-potential stage of the Q point, thereby maintaining the high potential of the Q point, avoiding high-temperature image distortion, and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0031] Figure 1 It is a structural schematic diagram of a first embodiment of a scan driving circuit of the present invention;

[0032] Figure 2 It is a structural schematic diagram of a second embodiment of the scan driving circuit of the present invention;

[0033] Figure 3 It is a structural schematic diagram of a third embodiment of the scan driving circuit of the present invention;

[0034] Figure 4 It is a structural schematic diagram of a fourth embodiment of the scan driving circuit of the present invention;

[0035] Figure 5 A schematic diagram of a conventional GDL circuit structure of an embodiment of a scan driving circuit of the present invention;

[0036] Figure 6 A schematic diagram of an IV characteristic curve of an embodiment of a scan drive circuit of the present invention;

[0037] Figure 7 It is a detailed structural schematic diagram of a second embodiment of the scan driving circuit of the present invention;

[0038] Figure 8 It is a schematic diagram of the overall structure of a first embodiment of a scan driving circuit of the present invention;

[0039] Fig. 9 A schematic diagram of a flow chart of a first embodiment of a scanning driving method of the present invention;

[0040] Fig.10 It is a schematic structural diagram of an embodiment of a display device of the present invention.

[0041] Description of Figure Numbers:

[0042]

[0043] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0044] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0047] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0048] Embodiment 1

[0049] Reference Figure 1 , Figure 1 The present invention provides a first embodiment of a scan driving circuit.

[0050] In this embodiment, the scan drive circuit includes a plurality of cascaded gate scan drive circuits, wherein the gate scan drive circuit includes an input module 10, a pull-down module 20, an output module 30 and a pull-up control node Q(n), wherein the input module 10, the output module 30 and the pull-down module 20 are respectively connected to the pull-up control node Q(n), the input module 10 is connected to the first control signal Carry(n-1), the output module is connected to the clock signal CLK(n), and the pull-down module 10 is connected to the first low level signal VGL1 and the second low level signal VGL2.

[0051] It should be noted that the gate scanning drive circuit is a GDL circuit, and the scanning drive circuit includes a plurality of cascaded gate scanning drive circuits. It can be considered that there are N cascaded GDL circuits (N>1), and each GDL circuit has the same structure. Each GDL circuit can receive a clock signal that is in a step-like shape in the rising phase, and output a scanning signal according to the clock signal to drive the corresponding row of pixels in the display area. The phases of the clock signals received by any two adjacent GDL circuits can be different, so as to output two scanning signals separated by a period of time, so that the pixels can be scanned row by row. This embodiment is described by taking the nth level GDL circuit as an example (1≤n≤N).

[0052] It can be understood that the pull-up control node Q(n) is the Q point in the n-th level GDL circuit, and the clock signal CLK(n) is the clock signal received by the n-th level GDL circuit, which can be set according to actual needs. The first control signal Carry(n-1) can be a level transfer signal of the previous level GDL circuit (the n-1-th level GDL circuit), or a start signal, which is not limited in this embodiment. The first low-level signal VGL1 and the second low-level signal VGL2 are signals output by the low-level end, wherein the second low-level signal VGL2 outputs a DC low voltage, which can be dynamically adjusted according to needs.

[0053] It should be understood that the input module 10 is used to pull up the potential of the pull-up control node Q(n) to the first potential according to the first control signal Carry(n-1); the pull-down module 20 is used to adjust the off-state leakage current to the minimum value according to the target off-state voltage provided by the first low-level signal VGL1 and the second low-level signal VGL2 when the potential of the pull-up control node Q(n) is the first potential, so as to maintain the first potential of the pull-up control node Q(n); the output module 30 is used to output the scan signal Gout(n) and the level transfer signal Carry(n) according to the clock signal CLK(n) and the first control signal Carry(n-1) when the potential of the pull-up control node Q(n) is the first potential.

[0054] It should be noted that, in this embodiment, the first potential is a high potential and the second potential is a low potential. The target off-state voltage refers to the voltage corresponding to the minimum off-state leakage current. The off-state voltage is usually VGL1-VGL2. The corresponding target off-state voltage can be achieved by adjusting the second low-level signal VGL2 to minimize the off-state leakage current, and at this time, the high potential of Q(n) can be maintained.

[0055] It can be understood that the scanning signal Gout(n) and the level transfer signal Carry(n) are output separately, usually using two different output terminals. The output scanning signal Gout(n) can be used to drive the nth row of pixels in the display area, and the output level transfer signal Carry(n) can be used to start the next level GDL circuit (n+1th level GDL circuit).

[0056] It should be understood that the input module 10 can also be connected to a reset signal Reset, and in this case the potential of the pull-up control node Q(n) can be pulled down according to the reset signal Reset.

[0057] In this embodiment, the scan drive circuit includes a plurality of cascaded gate scan drive circuits, the gate scan drive circuit includes an input module 10, a pull-down module 20, an output module 30 and a pull-up control node Q(n), the input module 10, the output module 30 and the pull-down module 20 are respectively connected to the pull-up control node Q(n), the input module 10 is connected to the first control signal Carry(n-1), the output module 30 is connected to the clock signal CLK(n), the pull-down module is connected to the first low level signal VGL1 and the second low level signal VGL2, the input module 10 is used to control the first control signal Carry(n-1) according to the first control signal Carry(n -1), pull up the potential of the pull-up control node Q(n) to the first potential, the pull-down module 20, when the potential of the pull-up control node Q(n) is the first potential, according to the target off-state voltage provided by the first low-level signal VGL1 and the second low-level signal VGL2, adjust the off-state leakage current to the minimum value to maintain the first potential of the pull-up control node Q(n), the output module 30, when the potential of the pull-up control node Q(n) is the first potential, according to the clock signal CLK(n) and the first control signal Carry(n-1), output the scanning signal Gout(n) and the level transfer signal Carry(n). Compared with the high-temperature image difference caused by the large TFT leakage in the traditional GDL circuit, the present embodiment controls the off-state leakage current to the minimum value in the high-potential stage of the Q point by adjusting the off-state voltage in the pull-down module 20, so as to maintain the high potential of the Q point, avoid the high-temperature image difference, and improve the display effect.

[0058] Embodiment 2

[0059] Reference Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a structure of a second embodiment of a scan driving circuit of the present invention. Based on the above first embodiment, the present invention proposes a second embodiment of a scan driving circuit.

[0060] In this embodiment, the gate scan drive circuit also includes an output pull-down module 40, a reverse control module 50 and a pull-down control node QB(n). The pull-down module 20, the output pull-down module 40 and the reverse control module 50 are respectively connected to the pull-down control node QB(n), the pull-down module 20 and the reverse control module 50 are respectively connected to the pull-up control node Q(n), the output pull-down module 40 is connected to the second control signal Carry(n+1), the reverse control module 50 is connected to the power supply voltage VDD, and the pull-down module 20 is connected to the second control signal Carry(n+1).

[0061] It should be noted that the pull-down control node QB(n), i.e., the QB point in the nth level GDL circuit, is usually connected to the pull-down module 20 and the output pull-down module. The second control signal Carry(n+1) may be a level transfer signal output by the next level GDL circuit, which is not limited in this embodiment.

[0062] It can be understood that the pull-down module 20 is also used to pull down the potential of the pull-up control node Q(n) to the second potential according to the second control signal Carry(n+1); the reverse control module 50 is also used to pull up the potential of the pull-down control node QB(n) to the first potential when the potential of the pull-up control node Q(n) is the second potential, and pull down the potential of the output end in the output module 30; the pull-down module 20 is also used to maintain the first potential of the pull-down control node QB(n); the output pull-down module 40 is used to pull down the potential of the output end in the output module 30 according to the second control signal Carry(n+1) when the potential of the pull-down control node QB(n) is the first potential; the output module 30 is also used to stop outputting the scan signal Gout(n) and the level transfer signal Carry(n) after the potential of the output end is pulled down.

[0063] It should be understood that after the output of the current level (the output of the scanning signal of the current level and the output of the level transmission signal of the current level) is completed, the pull-down module 20 pulls down the potential of the pull-up control node Q(n) to a low potential, and at this time, the reverse control module 50 pulls up the potential of the pull-down control node QB(n) to a high potential, and can pull down the potential of the output end in the output module 30. At the same time, the output pull-down module 40 also pulls down the potential of the output end in the output module 30. In this process, the pull-down module 20 maintains the high potential of the pull-down control node QB(n). By pulling down the potential of the output end in the output module 30 through the reverse control module 50 and the output pull-down module 40, the level of the level transmission signal Carry(n) of the n-th level GDL circuit drops rapidly, thereby stopping the output of the n-th level transmission signal Carry(n) and the n-th level scanning signal Gout(n) in time.

[0064] It should be noted that the output terminals that can pull down the potential of the reverse control module 50 and the output pull-down module 40 are different. The reverse control module 50 can pull down the output terminal corresponding to the level transmission signal Carry(n), and the output pull-down module 40 can pull down the output terminal corresponding to the level transmission signal Carry(n) and the output terminal corresponding to the scanning signal Gout(n). The output pull-down module 40 is usually connected to the third low-level signal VGL3, which is a signal output by the low-level terminal and can be dynamically adjusted according to demand.

[0065] It can be understood that since the reverse control module 50 and the output pull-down module 40 can both pull down the potential of the output end of the output module 30, the potential of the stage transfer signal Carry(n) and the scan signal Gout(n) can be pulled down faster, the potential of the pull-up control node Q(n) of the GDL circuit also rises faster due to the capacitive coupling effect, and the impedance of the output module 30 of the GDL circuit also decreases faster. When the clock signal CLK(n) is converted from a low potential to a high potential, the scan signal Gout(n) output by the GDL circuit output module 30 can rise to the corresponding high potential more quickly, and the rise time of the scan signal output by the GDL circuit can also be shortened, thereby improving the stability of the GDL circuit.

[0066] In this embodiment, the gate scan drive circuit further includes an output pull-down module 40, a reverse control module 50 and a pull-down control node QB(n), the pull-down module 20, the output pull-down module 40 and the reverse control module 50 are respectively connected to the pull-down control node QB(n), the pull-down module 20 and the reverse control module 50 are respectively connected to the pull-up control node Q(n), the output pull-down module 40 is connected to the second control signal Carry(n+1), the reverse control module 50 is connected to the power supply voltage VDD, the pull-down module 20 is connected to the second control signal Carry(n+1), and the pull-down module 20 is also used to pull the pull-up control node Q(n) according to the second control signal Carry(n+1). n) is pulled down to a second potential; the reverse control module 50 is further used for pulling up the potential of the pull-down control node QB(n) to the first potential and pulling down the potential of the output end in the output module 30 when the potential of the pull-up control node Q(n) is the second potential; the pull-down module 20 is further used for maintaining the first potential of the pull-down control node QB(n); the output pull-down module 40 is used for pulling down the potential of the output end in the output module 30 according to the second control signal Carry(n+1) when the potential of the pull-down control node QB(n) is the first potential; the output module 30 is further used for stopping outputting the scan signal Gout(n) and the stage transfer signal Carry(n) after the potential of the output end is pulled down. This embodiment adjusts the off-state voltage in the pull-down module 20 to control the off-state leakage current to a minimum value during the high potential stage of the Q point, thereby maintaining the high potential of the Q point, avoiding high-temperature image distortion, and improving the display effect. In addition, when the Q point is at a low potential, the potential of the Q point will be pulled down to a low potential, and the output of the scanning signal and the level transfer signal will be stopped in time.

[0067] Embodiment 3

[0068] Reference Figure 3 , Figure 3 FIG. 1 is a schematic diagram of a structure of a third embodiment of a scan driving circuit of the present invention. Based on the above embodiments, the present invention proposes a third embodiment of a scan driving circuit.

[0069] In this embodiment, the pull-down module 20 includes a first pull-down unit 201 and a pull-down control unit 202 . The first pull-down unit 201 is connected to the second low level signal VGL2 , and the pull-down control unit 202 is connected to the second control signal Carry(n+1).

[0070] Furthermore, the pull-down module 20 further includes a second pull-down unit 203 , which is connected to the first pull-down unit 201 and the pull-down control unit 202 , respectively, and the second pull-down unit 203 is connected to the second low level signal VGL2 .

[0071] It should be noted that the first pull-down unit 201 is used to adjust the off-state leakage current to the minimum value according to the target off-state voltage; the pull-down control unit 202 is used to pull down the potential of the pull-up control node Q(n) to the second potential according to the second control signal Carry(n+1).

[0072] It can be understood that the pull-down module 20 is composed of three parts: a first pull-down unit 201, a pull-down control unit 202 and a second pull-down unit 203. The first pull-down unit 201 is usually connected to the pull-up control node Q(n) and the pull-down control node QB(n). It can be considered that the first pull-down unit 201 needs to adjust the off-state leakage current to the minimum value. By adjusting the target off-state voltage connected to the first pull-down unit, the off-state voltage of the first pull-down unit 201 is adjusted to the target off-state voltage, so that the off-state leakage current of the first pull-down unit 201 is minimized.

[0073] It should be understood that the pull-down control unit 202 can pull down the potential of the pull-up control node Q(n) to a low potential according to the received second control signal Carry(n+1).

[0074] In this embodiment, the pull-down module 20 includes a first pull-down unit 201 and a pull-down control unit 202. The first pull-down unit 201 is connected to the second low-level signal VGL2, and the pull-down control unit 202 is connected to the second control signal Carry(n+1). The first pull-down unit 201 is used to adjust the off-state leakage current to a minimum value according to the target off-state voltage, and the pull-down control unit 202 is used to pull down the potential of the pull-up control node Q(n) to a second potential according to the second control signal Carry(n+1). In this embodiment, by adjusting the off-state voltage in the pull-down module 20, the off-state leakage current is controlled to a minimum value in the high potential stage of the Q point, so as to maintain the high potential of the Q point, avoid high temperature image abnormality, and improve the display effect.

[0075] Embodiment 4

[0076] Reference Figure 4 , Figure 4 FIG. 5 is a schematic diagram of the structure of a fourth embodiment of a scan driving circuit of the present invention. Based on the above embodiments, the present invention proposes a fifth embodiment of a scan driving circuit.

[0077] In this embodiment, the first pull-down unit 201 includes a first transistor T1, a second transistor T2 and a third transistor T3. The first transistor T1 is connected in series with the second transistor T2. The first end of the first transistor T1 is connected to the second end of the second transistor T2. The control end of the first transistor T1 and the control end of the second transistor T2 are both connected to the pull-down control node QB(n). The pull-up control node Q(n) is respectively connected to the first end of the second transistor T2 and the control end of the third transistor T3. The second end of the first transistor T1 is connected to the first low-level signal VGL1, the first end of the third transistor T3 is connected to the second low-level signal VGL2, and the second end of the third transistor T3 is connected to the second end of the second transistor T2.

[0078] It should be noted that the target off-state voltage is the target off-state voltage of the second transistor T2, and adjusting the off-state leakage current to the minimum value means adjusting the off-state leakage current of the second transistor T2 to the minimum value. When the potential of the pull-up control node Q(n) is a high potential and the potential of the pull-down control node QB(n) is a low potential, the second transistor T2 is turned off and the third transistor is turned on. When the potential of the pull-up control node Q(n) is a low potential and the potential of the pull-down control node QB(n) is a high potential, the second transistor T2 is turned on. The target off-state voltage can be determined based on transistor characteristic data, wherein the transistor characteristic data refers to a characteristic curve of a transistor, such as an IV characteristic curve.

[0079] Furthermore, the pull-down control unit 202 includes a fourth transistor T4, a control end of the fourth transistor T4 is connected to the second control signal Carry(n+1), a first end of the fourth transistor T4 is connected to the pull-down control node QB(n), and a second end of the fourth transistor T4 is connected to the first low level signal VGL1.

[0080] Further, the second pull-down unit 203 includes a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, the fifth transistor T5 is connected in series with the sixth transistor T6, the first end of the fifth transistor T5 is connected to the second end of the sixth transistor T6, the second end of the fifth transistor T5 is connected to the second end of the first transistor T1, the control end of the sixth transistor T6 is respectively connected to the second end of the fourth transistor T4, the control end of the seventh transistor T7 and the control end of the fifth transistor T5, the first end of the seventh transistor T7 is connected to the second end of the sixth transistor T6, and the second end of the seventh transistor T7 is connected to the second low level signal VGL2.

[0081] It is understandable that if Figure 5As shown, in the traditional GDL circuit, the Q point is in the high potential period, T1' is turned on, the QB point potential is always at the low point (VGL2), the T2'&T3' gate voltage is the low voltage VGL1, T2'&T3' is turned off, at this time, the gate Vg voltage is equal to VGL1, the source Vs voltage is also VGL1, the drain Vd point is at the high point, for T2' or T3', Vgs (gate-source voltage difference) is equal to 0V, from the IV characteristics of the transistor, as shown Figure 6 As shown, when Vgs=0V, the leakage current is high, and when the non-leakage current is the minimum point, the off-state leakage of T2' causes the high potential of the Q point to be unable to be maintained. In particular, high temperature will increase the leakage current, and high temperature abnormalities are prone to occur. Figure 4 In this embodiment, the pull-down module is optimized on the basis of the traditional GDL circuit. When the Q point is at a high potential, T3 is turned on, the drain voltage of T3 is VGL2, the QB potential is at a low potential, T2 is in a closed state, the gate voltage of T2 Vg=VGL2, and the source voltage of T2 Vs=VGL3. After the optimization, the off-state voltage Vgs of T2 in the closed state is VGL2-VGL3≠0. At this time, the VGL2 DC voltage can be dynamically adjusted to make the off-state voltage Vgs of T2 at the minimum leakage current state. In this way, it can be ensured that the high potential of the Q point is not pulled down due to the leakage current, and the off-state current can be adjusted at any time according to the IV characteristic curve to keep the off-state leakage current at a minimum in the high potential stage of the Q point, thereby avoiding high temperature abnormality.

[0082] Furthermore, if Figure 7 As shown, the input module 10 includes an eighth transistor T8 and a ninth transistor T9, the control end and the first end of the eighth transistor T8 are respectively connected to the first control signal Carry(n-1), the second end of the eighth transistor T8 is connected to the first end of the ninth transistor T9, and the control end of the ninth transistor T9 is connected to the second control signal Carry(n+1). The output module 30 includes a tenth transistor T10, an eleventh transistor T11 and a capacitor C, the output end includes a first output end and a second output end, the first output end outputs the stage transmission signal Carry(n), and the second output end outputs the scanning signal Gout(n), the control end of the tenth transistor T10 is connected to the pull-up control node Q(n), the second end of the tenth transistor T10 is connected to the first output end, the first end of the tenth transistor T10 is connected to the clock signal CLK(N), the control end of the eleventh transistor T11 is respectively connected to the pull-up control node Q(n) and the first end of the capacitor C, the second end of the eleventh transistor T11 is respectively connected to the second end of the capacitor C and the second output end, and the first end of the eleventh transistor T11 is connected to the clock signal CLK(N).

[0083] It should be understood that if the pull-up control node Q(n) is at a low potential and the pull-down control node QB(n) is at a high potential, T2 is turned on, the potential of the pull-up control node Q(n) is pulled down to VGL2, at which time T11 is turned off and the current stage output ends.

[0084] It can be understood that, in this embodiment, the first terminal of the transistor is the source terminal, the second terminal of the transistor is the drain terminal, and the control terminal of the transistor is the gate terminal.

[0085] It should be noted that, in this embodiment, the voltage output by the second low-level signal VGL2 can be adjusted according to the display state, thereby adjusting the low potential of the pull-up control node Q(n).

[0086] Furthermore, if Figure 8 As shown, the output pull-down module 40 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16, the gate terminal of the twelfth transistor T12 is connected to the second control signal Carry(n+1), the drain terminal of the thirteenth transistor T13 is respectively connected to the drain terminal of the twelfth transistor T12 and the drain terminal of the fourteenth transistor T14, the gate terminal of the thirteenth transistor T13 is connected to the pull-down control node QB(n), the source terminal of the thirteenth transistor T13 is connected to the source terminal of the fourteenth transistor T14 and the first output terminal, the gate terminal of the thirteenth transistor T13 is connected to the gate terminal of the fifteenth transistor T15, the source terminal of the fifteenth transistor T15 is connected to the source terminal of the sixteenth transistor T16 and the second output terminal, the drain terminal of the fifteenth transistor T15 is connected to the drain terminal of the sixteenth transistor T16, and the drain terminal of the fifteenth transistor T15 is connected to the third low level signal VGL3.

[0087] Further, refer to Figure 8The reverse control module includes a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23 and a twenty-fourth transistor T24, the source terminal and the gate terminal of the seventeenth transistor T17 are connected to the power supply voltage, the seventeenth transistor T17 is respectively connected to the gate terminal of the eighteenth transistor T18 and the source terminal of the nineteenth transistor T19, the source terminal of the eighteenth transistor T18 is connected to the source terminal of the seventeenth transistor T17, the gate terminal of the nineteenth transistor T19, the gate terminal of the twentieth transistor T20, the gate terminal of the twenty-first transistor T21 and the twenty-second transistor T24 are connected to the power supply voltage. 2 is connected to the pull-up control node Q(n), the drain terminal of the nineteenth transistor T19 is connected to the drain terminal of the twentieth transistor T20, the source terminal of the eighteenth transistor T18 is connected to the source terminal of the twenty-first transistor T21, the drain terminal of the twenty-first transistor T21 is connected to the drain terminal of the twenty-second transistor T22, the drain terminal of the twenty-third transistor T23 is respectively connected to the source terminal of the twentieth transistor T20 and the gate terminal of the twenty-fourth transistor T24, the source terminal of the twenty-fourth transistor T24, the source terminal of the twenty-third transistor T23 and the gate terminal of the twenty-third transistor T23 are connected to the power supply voltage, and the drain terminal of the twenty-fourth transistor T24 is connected to the source terminal of the twenty-second transistor T22.

[0088] It can be understood that the transistors T1 to T24 in this embodiment can be TFTs, and this embodiment does not limit this.

[0089] In this embodiment, the first pull-down unit 201 includes a first transistor T1, a second transistor T2 and a third transistor T3, the first transistor T1 and the second transistor T2 are connected in series, the first end of the first transistor T1 is connected to the second end of the second transistor T2, the control end of the first transistor T1 and the control end of the second transistor T2 are both connected to the pull-down control node QB(n), the pull-up control node Q(n) is respectively connected to the first end of the second transistor T2 and the control end of the third transistor T3, the second end of the first transistor T1 is connected to the first low-level signal VGL1, the first end of the third transistor T3 is connected to the second low-level signal VGL2, and the second end of the third transistor T3 is connected to the second end of the second transistor T2. In this embodiment, by adjusting the off-state voltage in the pull-down module 20, the off-state leakage current is controlled to the minimum value in the high-potential stage of the Q point, the high potential of the Q point can be maintained, the high temperature image difference can be avoided, and the display effect can be improved. In addition, when the Q point is at a low potential, the potential of the Q point will be pulled down to a low potential, and the output of the scanning signal and the level transfer signal will be stopped in time.

[0090] Embodiment 5

[0091] Reference Fig. 9, Fig. 9 FIG. 5 is a flow chart of a fifth embodiment of a scanning driving method of the present invention. Based on the above embodiments, the present invention proposes a fifth embodiment of a scanning driving method.

[0092] In this embodiment, the scanning driving method includes the following steps:

[0093] Step S10: Pull up the potential of the pull-up control node to a first potential according to a first control signal.

[0094] It should be noted that the execution subject of this embodiment is a scan drive circuit, which includes a plurality of cascaded gate scan drive circuits, each of which includes an input module, a pull-down module, an output module, and a pull-up control node. The specific structure can be referred to Figures 1 to 8 .

[0095] It can be understood that the pull-up control node is the Q point in the gate scan drive circuit (GDL circuit). The first control signal is usually a signal used to control the pull-up of the Q point potential. It can be a level transfer signal output by the previous level GDL circuit or a start signal. This embodiment does not impose any restrictions on this.

[0096] It should be understood that in this embodiment, the first potential is a high potential, the second potential is a low potential, and the potential of the Q point is pulled up to a high potential according to the received first control signal.

[0097] Step S20: When the potential of the pull-up control node is the first potential, adjusting the off-state leakage current to a minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal to maintain the first potential of the pull-up control node.

[0098] It should be noted that the target off-state voltage refers to the voltage corresponding to the minimum value of the off-state leakage current. The first low-level signal and the second low-level signal are signals output by the low-level end, wherein the second low-level signal outputs a DC low voltage, which can be dynamically adjusted according to demand so that the off-state voltage reaches the target off-state voltage, thereby adjusting the off-state leakage current to the minimum value. At this time, the high potential of the Q point can be maintained.

[0099] Step S30: when the potential of the pull-up control node is a first potential, outputting a scan signal and a level transfer signal according to a clock signal and the first control signal.

[0100] It should be understood that the clock signal is a clock signal received in a step-shaped manner in the rising phase, and the phases of the clock signals received by any two adjacent GDL circuits can be different, so as to output two scanning signals separated by a period of time, so that the pixels can be scanned row by row. The output scanning signal is used to drive the corresponding row of pixels in the display area, and the output level transfer signal can be used to start the next level of GDL circuit.

[0101] Furthermore, the scanning driving method also includes pulling down the potential of the pull-up control node to a second potential according to a second control signal, pulling up the potential of the pull-down control node to the first potential when the potential of the pull-up control node is the second potential, and pulling down the potential of the output end to maintain the first potential of the pull-down control node, and pulling down the potential of the output end in the output module according to the second control signal when the potential of the pull-down control node is the first potential, and stopping outputting the scanning signal and the level transfer signal after the potential of the output end is pulled down.

[0102] It should be noted that the pull-down control node is the QB point in the GDL circuit, and the second control signal may be a stage transmission signal output by the next stage GDL circuit, which is not limited in this embodiment.

[0103] It can be understood that after the output of the current level (the output of the scanning signal of the current level and the output of the level transfer signal of the current level) is completed, the potential of the Q point is pulled down to a low potential, the potential of the QB point is pulled up to a high potential, and the potential of the output end is pulled down, and in this process, the high potential of the QB point is maintained. The level of the level transfer signal of the GDL circuit can drop rapidly, thereby stopping the output of the level transfer signal and the scanning signal in time.

[0104] In this embodiment, according to the first control signal, the potential of the pull-up control node is pulled up to the first potential. When the potential of the pull-up control node is the first potential, the off-state leakage current is adjusted to the minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal to maintain the first potential of the pull-up control node. When the potential of the pull-up control node is the first potential, the scanning signal and the level transfer signal are output according to the clock signal and the first control signal. Compared with the high-temperature image difference caused by the large TFT leakage in the traditional GDL circuit, this embodiment adjusts the off-state voltage to control the off-state leakage current to the minimum value in the high-potential stage of the Q point, so as to maintain the high potential of the Q point, avoid the high-temperature image difference, and improve the display effect.

[0105] To achieve the above object, the present invention further proposes a display panel, comprising a display area and a non-display area, wherein the non-display area is provided with a scanning drive circuit as described above, and the scanning drive circuit is used to provide a row scanning signal for the display area. The specific structure of the scanning drive circuit refers to the above embodiment, and since the present display panel can adopt the technical solutions of all the above embodiments, it has at least the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0106] Reference Fig.10 , Fig.10 Schematic diagram of the structure of an embodiment of a display device of the present invention. To achieve the above purpose, the present invention further provides a display device, the display device includes a backlight module 60 and a display panel 70 as described above, the backlight module 60 is arranged corresponding to the display panel 70, and the backlight module 60 is used to provide a backlight source to the display panel 70. The specific structure of the display panel 70 refers to the above embodiment. Since the present display device can adopt the technical solutions of all the above embodiments, it has at least the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here one by one.

[0107] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A scanning driving circuit, characterized in that: The scanning driving circuit comprises a plurality of cascaded gate scanning driving circuits, the gate scanning driving circuit comprises an input module, a pull-down module, an output module and a pull-up control node, the input module, the output module and the pull-down module are respectively connected to the pull-up control node, the input module is connected to a first control signal, the output module is connected to a clock signal, and the pull-down module is connected to a first low-level signal and a second low-level signal; The input module is used to pull up the potential of the pull-up control node to a first potential according to the first control signal; The pull-down module is used for adjusting the off-state leakage current to a minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal when the potential of the pull-up control node is the first potential, so as to maintain the first potential of the pull-up control node; The output module is used to output a scanning signal and a level transmission signal according to the clock signal and the first control signal when the potential of the pull-up control node is the first potential; The gate scanning driving circuit further comprises an output pull-down module, a reverse control module and a pull-down control node, wherein the pull-down module, the output pull-down module and the reverse control module are respectively connected to the pull-down control node, the pull-down module and the reverse control module are respectively connected to the pull-up control node, the output pull-down module is connected to a second control signal, the reverse control module is connected to a power supply voltage, and the pull-down module is connected to the second control signal; The pull-down module is further used to pull down the potential of the pull-up control node to a second potential according to the second control signal; The reverse control module is further used to pull up the potential of the pull-down control node to the first potential and pull down the potential of the output end in the output module when the potential of the pull-up control node is the second potential; The pull-down module is further used to maintain the first potential of the pull-down control node; The output pull-down module is used to pull down the potential of the output terminal in the output module according to the second control signal when the potential of the pull-down control node is the first potential; The output module is further used to stop outputting the scanning signal and the level transmission signal after the potential of the output terminal is pulled down; The pull-down module includes a first pull-down unit and a pull-down control unit, the first pull-down unit is connected to the second low-level signal, and the pull-down control unit is connected to the second control signal; The first pull-down unit is used to adjust the off-state leakage current to a minimum value according to the target off-state voltage; The pull-down control unit is used to pull down the potential of the pull-up control node to a second potential according to the second control signal; The first pull-down unit includes a first transistor, a second transistor and a third transistor, the first transistor is connected in series with the second transistor, the first end of the first transistor is connected to the second end of the second transistor, the control end of the first transistor and the control end of the second transistor are both connected to the pull-down control node, the pull-up control node is respectively connected to the first end of the second transistor and the control end of the third transistor, the second end of the first transistor is connected to the first low-level signal, the first end of the third transistor is connected to the second low-level signal, and the second end of the third transistor is connected to the second end of the second transistor; The pull-down control unit includes a fourth transistor, a control terminal of the fourth transistor is connected to the second control signal, a first terminal of the fourth transistor is connected to the pull-down control node, and a second terminal of the fourth transistor is connected to the first low level signal.

2. The scanning driving circuit according to claim 1, characterized in that: The pull-down module also includes a second pull-down unit, which includes a fifth transistor, a sixth transistor and a seventh transistor, the fifth transistor and the sixth transistor are connected in series, the first end of the fifth transistor is connected to the second end of the sixth transistor, the second end of the fifth transistor is connected to the second end of the first transistor, the control end of the sixth transistor is respectively connected to the second end of the fourth transistor, the control end of the seventh transistor and the control end of the fifth transistor, the first end of the seventh transistor is connected to the second end of the sixth transistor, and the second end of the seventh transistor is connected to the second low-level signal.

3. The scanning driving circuit according to claim 1, characterized in that: The input module includes an eighth transistor and a ninth transistor, the control end and the first end of the eighth transistor are respectively connected to the first control signal, the second end of the eighth transistor is connected to the first end of the ninth transistor, and the control end of the ninth transistor is connected to the second control signal.

4. The scan driving circuit according to any one of claims 1 to 3, characterized in that: The output module includes a tenth transistor, an eleventh transistor and a capacitor, the output end includes a first output end and a second output end, the first output end outputs a stage transmission signal, the second output end outputs a scan signal, the control end of the tenth transistor is connected to the pull-up control node, the first end of the tenth transistor is connected to the clock signal, the second end of the tenth transistor is connected to the first output end, the control end of the eleventh transistor is respectively connected to the pull-up control node and the first end of the capacitor, the first end of the eleventh transistor is connected to the clock signal, and the second end of the eleventh transistor is respectively connected to the second end of the capacitor and the second output end.

5. A scanning driving method, characterized in that: Applied to the scan driving circuit according to any one of claims 1 to 4, the scan driving method comprises: According to the first control signal, the potential of the pull-up control node is pulled up to the first potential; When the potential of the pull-up control node is a first potential, adjusting the off-state leakage current to a minimum value according to the target off-state voltage provided by the first low-level signal and the second low-level signal to maintain the first potential of the pull-up control node; When the potential of the pull-up control node is a first potential, a scan signal and a level transfer signal are output according to a clock signal and the first control signal.

6. A display panel, comprising a display area and a non-display area, characterized in that: The non-display area is provided with a scan driving circuit as claimed in any one of claims 1 to 4, and the scan driving circuit is used to provide a row scan signal for the display area.

7. A display device, characterized in that: The display device comprises a backlight module and the display panel as claimed in claim 6, wherein the backlight module is arranged corresponding to the display panel, and the backlight module is used to provide a backlight source for the display panel.

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