Memory

Abstract

The present disclosure provides a memory device, comprising a first-stage amplifier circuit connected to a bit line and a complementary bit line for amplifying a voltage difference between the bit line and the complementary bit line; a second-stage amplifier circuit connected to a local data line and a complementary local data line, and also connected to a global data line and a complementary global data line. Upon connection between the local data line and the bit line, and between the complementary local data line and the complementary bit line, the amplifier circuit amplifies the voltage difference between the local data line and the complementary local data line, and generates a voltage difference between the global data line and the complementary global data line; and a driver circuit connected to the local data line and the complementary local data line for amplifying the voltage difference between the local data line and the complementary local data line. This arrangement compensates for the effect of coupling capacitance on the voltage of the local data line, shortens the time it takes to amplify the voltage difference between the local data line and the complementary local data line, and improves the timing parameter performance of the memory device.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a memory. Background Art

[0002] With the popularization of electronic devices such as mobile phones, tablets, and personal computers, semiconductor memory technology has also developed rapidly.

[0003] Dynamic random access memory (DRAM) has a multi-stage amplifier circuit that amplifies voltage differences to read or write data from memory cells. Improvements to this multi-stage amplifier circuit can improve memory performance. Summary of the Invention

[0004] The present disclosure provides a memory, comprising:

[0005] a first-stage amplifier circuit connected to the bit line and the complementary bit line, for amplifying the voltage difference between the bit line and the complementary bit line;

[0006] a secondary amplifier circuit connected to the local data line and the complementary local data line, and also connected to the global data line and the complementary global data line, and after the local data line and the bit line are connected, and the complementary local data line and the complementary bit line are connected, amplifying the voltage difference between the local data line and the complementary local data line, and generating a voltage difference between the global data line and the complementary global data line;

[0007] The driving circuit is connected to the local data line and the complementary local data line, and amplifies the voltage difference between the local data line and the complementary local data line.

[0008] In some embodiments, the memory further comprises:

[0009] an equalization circuit connected to the local data line and the complementary local data line, and charging the voltage of the local data line and the complementary local data line to a precharge voltage before the local data line is connected to the bit line and before the complementary local data line is connected to the complementary bit line;

[0010] The driving circuit is used for amplifying the voltage difference between the local data line and the complementary local data line after the voltages of the local data line and the complementary local data line are charged to a pre-charge voltage.

[0011] In some embodiments, the driving circuit starts amplifying the voltage difference between the local data line and the complementary local data line earlier than the secondary amplifying circuit starts amplifying the voltage difference between the local data line and the complementary local data line.

[0012] In some embodiments, when the first time interval is within a first time range, the first starting time is within a first value range;

[0013] When the first time interval is within the second time range, the first starting time is within the second value range;

[0014] The first time interval is the time interval between adjacent row addressing and column addressing of the memory, and the first starting moment is the starting moment when the driving circuit starts to amplify the voltage difference between the local data line and the complementary local data line;

[0015] The upper limit of the first time range is less than or equal to the lower limit of the second time range, and the upper limit of the first numerical range is greater than or equal to the lower limit of the second numerical range.

[0016] In some embodiments, the driver circuit is configured to:

[0017] Amplifying the voltage difference between the local data line and the complementary local data line by driving up the voltage of the local data line and / or the voltage of the complementary local data line;

[0018] The driving capability of driving the local data line upward is negatively correlated with the voltage on the complementary local data line, and the driving capability of driving the complementary local data line upward is negatively correlated with the voltage on the local data line.

[0019] In some embodiments, the driving circuit includes:

[0020] a switch unit connected to the first drive unit and the second drive unit, controlling the first drive unit to be connected to or disconnected from the first power supply terminal under the control of a first control signal, and controlling the second drive unit to be connected to or disconnected from the first power supply terminal under the control of the first control signal; the first power supply terminal provides a power supply voltage;

[0021] a first driving unit connected to the local data line and the complementary local data line, and driving the voltage of the local data line upward according to the voltage of the complementary local data line when the first driving unit is connected to the first power terminal;

[0022] The second driving unit is connected to the local data line and the complementary local data line, and drives the voltage of the complementary local data line upward according to the voltage of the local data line when the second driving unit is connected to the first power terminal.

[0023] In some embodiments, the driving capability of the first driving unit to drive the local data line is negatively correlated with the voltage of the complementary local data line;

[0024] The driving capability of the second driving unit to drive the complementary local data line is negatively correlated with the voltage of the local data line.

[0025] In some embodiments, the first driving unit includes:

[0026] a first P-type transistor, having a source connected to the switch unit, a drain connected to the local data line, and a gate connected to the complementary local data line;

[0027] The second drive unit includes:

[0028] The second P-type transistor has a source connected to the switch unit, a drain connected to the complementary local data line, and a gate connected to the local data line.

[0029] In some embodiments, the switch unit includes:

[0030] The third P-type transistor has a source connected to the first power supply terminal, a drain connected to the source of the first P-type transistor, and a drain further connected to the source of the second P-type transistor, and a gate receiving the first control signal.

[0031] In some embodiments, the driving circuit further comprises:

[0032] a first control circuit, wherein the first output end is connected to the control end of the switch unit, and the second output end is connected to the control end of the secondary amplification circuit; the first input end receives a mode signal, and the second input end receives a reference signal, and is configured to generate a first control signal according to the mode signal and the reference signal, and generate a second control signal according to the reference signal;

[0033] The first control signal starts being valid earlier than the second control signal, and the second control signal controls the secondary amplifier circuit to amplify the voltage difference between the local data line and the complementary local data line.

[0034] In some embodiments, the first control signal starts being valid later than the equalization control signal ends being valid. When the equalization control signal is valid, the voltages of the local data line and the complementary local data line are charged to a precharge voltage.

[0035] In some embodiments, the control circuit is configured to:

[0036] determining a time step between the reference signal and the first control signal according to the mode signal;

[0037] The reference signal is processed according to the time step to generate a first control signal.

[0038] In some embodiments, the mode signal is determined by any one or more parameters of the first time interval, the process corner of the memory, the temperature of the memory, and the operating voltage of the memory;

[0039] The first time interval is the time interval between adjacent row addressing and column addressing of the memory.

[0040] In some embodiments, the reference signal is a column selection signal, which is used to control the connection or disconnection between the bit line and the local data line, and also to control the connection or disconnection between the complementary bit line and the complementary local data line.

[0041] In some embodiments, the memory further comprises:

[0042] The second control circuit is connected to the bit line and the complementary bit line, and is also connected to the local data line and the complementary local data line, and is used to receive a column selection signal, and control the connection or disconnection between the bit line and the local data line under the control of the column selection signal, and control the connection or disconnection between the complementary bit line and the complementary local data line under the control of the column selection signal.

[0043] In some embodiments, the memory further comprises:

[0044] The three-stage amplifier circuit is connected to the global data line and the complementary global data line and is used to amplify the voltage difference between the global data line and the complementary global data line.

[0045] The memory provided by the present disclosure includes a first-level amplifier circuit, a second-level amplifier circuit, and a driver circuit. The first-level amplifier circuit is connected to a bit line and a complementary bit line, and amplifies the voltage difference between the bit line and the complementary bit line. The driver circuit and the second-level amplifier circuit are both connected to a local data line and a complementary local data line. The second-level amplifier circuit is also connected to a global data line and a complementary global data line. After a voltage difference is generated between the local data line and the complementary local data line, the second-level amplifier circuit amplifies the voltage difference between the local data line and the complementary local data line, and generates a voltage difference between the global data line and the complementary global data line. The driver circuit is also used to amplify the voltage difference between the local data line and the complementary local data line to compensate for the influence of the coupling capacitor on the voltage of the local data line. This can shorten the time for amplifying the voltage difference between the local data line and the complementary local data line, thereby improving the timing parameter performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0047] Figure 1 A circuit diagram of a memory;

[0048] Figure 2 A wiring diagram for a local data line in a memory;

[0049] Figure 3 A schematic diagram showing the effect of a coupling capacitor on a local data line voltage in a memory;

[0050] Figure 4A diagram showing the working principle of a memory device when a coupling capacitor has an effect on the voltage of a local data line;

[0051] Figure 5 A circuit diagram of a memory provided in one embodiment of the present disclosure;

[0052] Figure 6 An operating timing diagram of a memory provided in one embodiment of the present disclosure;

[0053] Figure 7 A diagram illustrating the working principle of a memory provided in one embodiment of the present disclosure.

[0054] Reference numerals:

[0055] 100, first-stage amplifier circuit; 200, second-stage amplifier circuit; 300, third-stage amplifier circuit; 400, second control circuit; 500, equalization circuit; 600, drive circuit; 700, first control circuit; 610, first drive unit; 620, second drive unit; 630, switch unit; BL, bit line; BLB, complementary bit line; LIO, local data line; LIOB, complementary local data line; GIO, global data line; GIOB, complementary global data line; M1, first transistor; M2, second transistor; CSL, column selection signal; VintLP, second power supply terminal; RdEnN, first control signal; RdEn, second control signal; CTRLPin, mode signal; RdEnPre, reference signal; P1, first P-type transistor; P2, second P-type transistor; P3, third P-type transistor; EQLOB, equalization control signal.

[0056] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0057] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0058] like Figure 1As shown, a memory device includes a first-stage amplifier circuit 100, a second-stage amplifier circuit 200, a third-stage amplifier circuit 300, a second control circuit 400, and an equalization circuit 500. The first-stage amplifier circuit 100 is connected to a bit line BL and a complementary bit line BLB, and is used to amplify the voltage difference between the bit line BL and the complementary bit line BLB. The second-stage amplifier circuit 200 is connected to a local data line LIO and a complementary local data line LIOB. The second-stage amplifier circuit 200 is also connected to a global data line GIO and a complementary global data line GIOB, and is used to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby generating a voltage difference between the global data line GIO and the complementary global data line GIOB. The third-stage amplifier circuit 300 is used to amplify the voltage difference between the global data line GIO and the complementary global data line GIOB.

[0059] The second control circuit 400 is connected to the bit line BL and the complementary bit line BLB. The second control circuit 400 is also connected to the local data line LIO and the complementary local data line LIOB. The second control circuit 400 is used to control the connection or disconnection between the bit line BL and the local data line LIO. The second control circuit 400 is also used to control the connection or disconnection between the complementary bit line BLB and the complementary local data line LIOB.

[0060] The equalizer circuit 500 is connected to the local data line LIO and the complementary local data line LIOB. The equalizer circuit 500 is used to charge the local data line LIO and the complementary local data line LIOB to the precharge voltage VCC before the connection between the bit line BL and the local data line LIO and before the connection between the complementary bit line BLB and the complementary local data line LIOB.

[0061] Before the bit line BL and the local data line LIO are connected, and before the complementary bit line BLB and the complementary local data line LIOB are connected, charge sharing is performed between the memory cell and the bit line BL, resulting in a small voltage difference between the bit line BL and the complementary bit line BLB. The first-stage amplifier circuit 100 amplifies the small voltage difference between the bit line BL and the complementary bit line BLB.

[0062] After the bit line BL and the local data line LIO are connected, and the complementary bit line BLB and the complementary local data line LIOB are connected, the bit line BL and the complementary bit line BLB generate a voltage difference on the local data line LIO and the complementary local data line LIOB, and the secondary amplifier circuit 200 then amplifies the voltage difference on the local data line LIO and the complementary local data line LIOB, thereby realizing data transmission from the bit line BL and the complementary bit line BLB to the local data line LIO and the complementary local data line LIOB.

[0063] Figure 2This is a wiring diagram of some local data lines LIO in the memory. Multiple local data lines LIO are arranged in sequence. There is a coupling capacitor between two local data lines LIO. When a voltage jump occurs on the coupling capacitor, it will affect the voltage on the local data line LIO.

[0064] For example: Figure 2 The four local data lines LIO are marked as local data lines LIO from top to bottom. <2> , local data line LIO <0> , local data line LIO <3> and local data line LIO <1> Local data line LIO <2> and local data line LIO <3> There is a coupling capacitor between them.

[0065] like Figure 3 , when the local data line LIO <2> and local data line LIO <3> Since the data “0” is transmitted, the voltage drops from the precharge voltage VCC to the voltage corresponding to the data “0”, and the local data line LIO <0> When transmitting data "1", the voltage is still close to the pre-charge voltage VCC. <2> and local data line LIO <3> There is a voltage jump on the local data line LIO <2> and local data line LIO <3> The coupling capacitance between the two will pull down the local data line LIO <0> On voltage.

[0066] like Figure 4 As shown, the local data line LIO is amplified in the secondary amplifier circuit <0> and complementary local data line LIOB <0> When the voltage difference is high, the voltage difference △LIO1 is relatively small, and the secondary amplifier circuit 200 turns the local data line LIO <0> and complementary local data line LIOB <0> The time it takes to amplify the voltage difference between the two lines to a preset value is longer. The memory timing parameter tCCD refers to the time interval between the previous column address strobe pulse and the next column address strobe pulse. When the secondary amplifier circuit 200 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB, the memory timing parameter tCCD deteriorates.

[0067] like Figure 5 As shown, an embodiment of the present disclosure provides a memory including a first-stage amplifier circuit 100 , a second-stage amplifier circuit 200 and a driving circuit 600 .

[0068] The first-stage amplifier circuit 100 connects the bit line BL and the complementary bit line BLB, the second-stage amplifier circuit 200 connects the local data line LIO and the complementary local data line LIOB, and the second-stage amplifier circuit 200 also connects the global data line GIO and the complementary global data line GIOB. The driver circuit 600 connects the local data line LIO and the complementary local data line LIOB.

[0069] The local data line LIO is disconnected from the bit line BL, and the complementary local data line LIOB is disconnected from the complementary bit line BLB. The memory cell shares charge with the bit line BL, generating a small voltage difference between the bit line BL and the complementary bit line BLB. The first-stage amplifier circuit 100 is used to amplify the small voltage difference between the bit line BL and the complementary bit line BLB.

[0070] After local data line LIO and bit line BL are connected, and after complementary local data line LIOB and complementary bit line BLB are connected, bit line BL drives local data line LIO, and complementary bit line BLB drives complementary local data line LIOB, generating a voltage difference between local data line LIO and complementary local data line LIOB. Secondary amplifier circuit 200 amplifies the voltage difference between local data line LIO and complementary local data line LIOB, and generates a voltage difference between global data line GIO and complementary global data line GIOB. After the voltage difference between local data line LIO and complementary local data line LIOB is generated, driver circuit 600 also amplifies the voltage difference between local data line LIO and complementary local data line LIOB.

[0071] In the above technical solution, a driving circuit 600 is provided to connect the local data line LIO and the complementary local data line LIOB. After a voltage difference is generated between the local data line LIO and the complementary local data line LIOB, the secondary amplification circuit 200 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB. The driving circuit 600 is also used to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB to compensate for the influence of the coupling capacitor on the voltage of the local data line LIO. This can shorten the time for amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby improving the timing parameter tCCD of the memory.

[0072] In some embodiments, continue to refer to Figure 5 The memory further includes an equalizer circuit 500 connected to the local data line LIO and the complementary local data line LIOB. Before the local data line LIO is connected to the bit line BL, and before the complementary local data line LIOB is connected to the complementary bit line BLB, the equalizer circuit 500 charges the voltages of the local data line LIO and the complementary local data line LIOB to a precharge voltage.

[0073] After the equalization circuit 500 charges the voltage of the local data line LIO and the complementary local data line LIOB to the pre-charge voltage, the control bit line BL is connected to the local data line LIO, and the control complementary bit line BLB is connected to the complementary local data line LIOB. The bit line BL and the complementary bit line BLB generate a voltage difference between the local data line LIO and the complementary local data line LIOB. The driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB, and the secondary amplification circuit 200 also amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0074] In some embodiments, continue to refer to Figure 5 The equalization circuit 500 is connected to the second power supply terminal. The voltage VintLP of the second power supply terminal is adjustable, so that the pre-charge voltage is also adjustable. The voltage VintLP provided by the second power supply terminal can be adjusted according to the timing parameters of the memory to adjust the pre-charge voltage on the local data line LIO and the complementary local data line LIOB.

[0075] In some embodiments, after the local data line LIO and the complementary local data line LIOB are charged to the pre-charge voltage, before the bit line BL and the local data line LIO are connected, and before the complementary bit line BLB and the complementary local data line LIOB are connected, the driving circuit 600 is turned on and is in a waiting state. After the bit line BL and the local data line LIO are connected, and after the complementary bit line BLB and the complementary local data line LIOB are connected, the bit line BL and the complementary bit line BLB generate a voltage difference between the local data line LIO and the complementary local data line LIOB, and the driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0076] In some embodiments, after the bit line BL and the local data line LIO are connected, and after the complementary bit line BLB and the complementary local data line LIOB are connected, the driving circuit 600 is turned on, and the driving circuit 600 directly amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB without entering a waiting state.

[0077] In the above technical solution, after the voltages of the local data line LIO and the complementary local data line LIOB are charged to the pre-charge voltage, the control driving circuit 600 and the secondary amplification circuit 200 amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby achieving accurate data transmission between the bit line BL and the local data line LIO, and between the complementary bit line BLB and the complementary local data line LIOB.

[0078] In some embodiments, continue to refer to Figure 5The memory also includes a second control circuit 400, which is connected to the bit line BL and the complementary bit line BLB. The second control circuit 400 is also connected to the local data line LIO and the complementary local data line LIOB. The second control circuit 400 is used to receive a column selection signal CSL. Under the control of the column selection signal CSL, the second control circuit 400 controls the connection or disconnection between the bit line BL and the local data line LIO, and controls the connection or disconnection between the complementary bit line BLB and the complementary local data line LIOB under the control of the column selection signal CSL.

[0079] In some embodiments, continue to refer to Figure 5 The second control circuit 400 includes a first transistor M1 and a second transistor M2. The source or drain of the first transistor M1 is connected to the bit line BL, the drain or source of the first transistor M1 is connected to the local data line LIO, and the gate of the first transistor M1 is connected to the column select line and receives the column select signal CSL. The source or drain of the second transistor M2 is connected to the complementary bit line BLB, the drain or source of the second transistor M2 is connected to the complementary local data line LIOB, and the gate of the second transistor M2 is connected to the column select line and receives the column select signal CSL.

[0080] The first transistor M1 and the second transistor M2 are turned on or off under the control of the column select signal CSL to connect or disconnect the control bit line BL and the local data line LIO, and to connect or disconnect the complementary bit line BLB and the complementary local data line LIOB.

[0081] In some embodiments, the first transistor M1 and the second transistor M2 are N-type transistors, and the first transistor M1 and the second transistor M2 are turned on when the column selection signal CSL is at a high level.

[0082] In some embodiments, continue to refer to Figure 5 The memory further includes a three-stage amplifier circuit 300, which is connected to the global data line GIO and the complementary global data line GIOB. The three-stage amplifier circuit 300 is used to amplify the voltage difference between the global data line GIO and the complementary global data line GIOB.

[0083] In some embodiments, the driver circuit 600 starts amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB earlier than the secondary amplifier circuit 200 starts amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB. With this configuration, after the bit line BL and the complementary bit line BLB generate a voltage difference between the local data line LIO and the complementary local data line LIOB, the driver circuit 600 first amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB to compensate for the effect of the coupling capacitor on the voltage of the local data line LIO. The secondary amplifier circuit 200 and the driver circuit 600 then jointly amplify the voltage difference between the local data line LIO and the complementary local data line LIOB and generate a voltage difference between the global data line GIO and the complementary global data line GIOB. This shortens the time it takes the secondary amplifier circuit 200 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby improving the performance of the memory device's timing parameter tCCD.

[0084] In some embodiments, the first time interval is the time interval tRCD between adjacent row addressing and column addressing of the memory, that is, the time interval between adjacent activation commands and read commands, or the time interval between adjacent activation commands and write commands, that is, the time interval from turning on a word line to turning on a column select line.

[0085] The first starting time is the starting time when the driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0086] When the first time interval is within the first time range, the first starting time is within the first numerical range. When the first time interval is within the second time range, the first starting time is within the second numerical range. The upper limit of the first time range is less than or equal to the lower limit of the second time range, and the upper limit of the first numerical range is greater than or equal to the lower limit of the second numerical range.

[0087] The shorter the first time interval, the later the driver circuit 600 begins amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB. If the first time interval is relatively short, the voltage difference between the bit line BL and the complementary bit line BLB decreases during conduction between the bit line BL and the local data line LIO, and between the complementary bit line BLB and the complementary local data line BLB. This increases the likelihood that the local data line LIO and the complementary local data line LIOB will introduce noise into the bit line BL and the complementary bit line BLB. By delaying the start time of driver circuit 600 amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB, the impact of the local data line LIO and the complementary local data line LIOB on the bit line BL and the complementary bit line BLB can be reduced, thereby reducing noise introduction.

[0088] In some embodiments, the first starting time can also be adjusted based on any one or more parameters of the memory's process angle, memory temperature, and memory operating voltage to reduce noise introduced on the bit line BL and the complementary bit line BLB. The relationship between the memory's process angle, memory temperature, memory operating voltage, and the first starting time can be determined by performing multiple tests on the memory.

[0089] In some embodiments, the driving circuit 600 is configured to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB by driving the voltage of the local data line LIO upward and / or driving the voltage of the complementary local data line LIOB upward. The driving capability of driving the local data line LIO or the complementary local data line LIOB upward refers to the ability to increase the voltage of the local data line LIO or the complementary local data line LIOB, which can be measured by the rate of voltage change. The driving capability of driving the local data line LIO upward is negatively correlated with the voltage of the complementary local data line LIOB. The driving capability of driving the complementary local data line LIOB upward is negatively correlated with the voltage of the local data line LIO.

[0090] After a voltage difference is generated between the local data line LIO and the complementary local data line LIOB, for example, the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB, that is, the voltage on the local data line LIO is relatively large, while the voltage on the complementary local data line LIOB is relatively small. When the voltage on the local data line LIO is relatively large, the driving capability of the driver circuit 600 to drive the complementary local data line LIOB upward is relatively weak. When the voltage on the complementary local data line LIOB is relatively small, the driving capability of the driver circuit 600 to drive the local data line LIO upward is relatively strong. If the driving capability of the driver circuit 600 to drive the complementary local data line LIOB upward is relatively weak, while the driving capability of the driver circuit 600 to drive the local data line LIO upward is relatively strong, the voltage on the local data line LIO continues to be greater than the voltage on the complementary local data line LIOB, thereby amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0091] The above example illustrates the principle of the driving circuit 600 amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB, where the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB. The principle is similar when the voltage on the local data line LIO is less than the voltage on the complementary local data line LIOB, and is not further described here.

[0092] In some embodiments, the driving circuit 600 includes a switch unit 630, a first driving unit 610, and a second driving unit 620. The switch unit 630 is connected to the first driving unit 610, and the switch unit 630 is connected to the second driving unit 620. The first driving unit 610 is connected to the local data line LIO and the complementary local data line LIOB, and the second driving unit 620 is connected to the local data line LIO and the complementary local data line LIOB.

[0093] The switch unit 630 controls the first driving unit 610 to be connected or disconnected with the first power supply terminal under the control of the first control signal RdEnN. The switch unit 630 also controls the second driving unit 620 to be connected or disconnected with the first power supply terminal under the control of the first control signal RdEnN. The voltage provided by the first power supply terminal is the power supply voltage VCC.

[0094] The first driving unit 610 drives the voltage of the local data line LIO upward according to the voltage of the complementary local data line LIOB when the first driving unit 610 is connected to the first power terminal, and the second driving unit 620 drives the voltage of the complementary local data line LIOB upward according to the voltage of the local data line LIO when the second driving unit 620 is connected to the first power terminal.

[0095] The driving capability of the first driving unit 610 for driving the local data line LIO is negatively correlated with the voltage of the complementary local data line LIOB, and the driving capability of the second driving unit 620 for driving the complementary local data line LIOB is negatively correlated with the voltage of the local data line LIO.

[0096] The first driver unit 610 and the second driver unit 620 are used to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB. After a voltage difference is generated between the local data line LIO and the complementary local data line LIOB, for example, the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB, that is, the voltage on the local data line LIO is relatively large while the voltage on the complementary local data line LIOB is relatively small. Since the voltage on the complementary local data line LIOB is relatively small, the first driver unit 610 and the driving circuit 600 have a stronger driving capability to drive the local data line LIO upward. When the voltage on the local data line LIO is relatively large, the second driver unit 620 has a weaker driving capability to drive the complementary local data line LIOB upward. If the first driver unit 610 has a stronger driving capability to drive the local data line LIO upward while the second driver unit 620 has a weaker driving capability to drive the complementary local data line LIOB upward, the voltage on the local data line LIO continues to be greater than the voltage on the complementary local data line LIOB, thereby amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0097] The above example uses the case where the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB to illustrate the principle of the first driving unit 610 and the second driving unit 620 amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB. The principle is similar when the voltage on the local data line LIO is less than the voltage on the complementary local data line LIOB, and will not be repeated here.

[0098] The switch unit 630 is used to control whether the first driving unit 610 and the second driving unit 620 can amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0099] When the switch unit 630 controls the first power terminal to be connected to the first driving unit 610 and controls the first power terminal to be connected to the second driving unit 620, the first driving unit 610 and the second driving unit 620 can amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0100] When the switch unit 630 controls the first power terminal to be disconnected from the first driving unit 610 and the second driving unit 620, the first driving unit 610 and the second driving unit 620 cannot amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0101] In some embodiments, after the local data line LIO and the complementary local data line LIOB are charged to the pre-charge voltage, the switch unit 630 controls the first driving unit 610 to be connected to the first power supply terminal, and controls the second driving unit 620 to be connected to the first power supply terminal, so as to avoid the equalization circuit 500 being unable to charge the local data line LIO and the complementary local data line LIOB to the pre-charge voltage due to the first driving unit 610 and the second driving unit 620 being connected to the first power supply terminal all the time.

[0102] In the above technical solution, the switch unit 630 is provided to control whether the first driving unit 610 and the second driving unit 620 can be connected to the first power supply terminal, thereby achieving isolation between the first power supply terminal and the second power supply terminal. This prevents the first driving unit 610 and the second driving unit 620 from continuously amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby preventing the equalization circuit 500 from being able to charge the voltages of the local data line LIO and the complementary local data line LIOB to the pre-charge voltage, thereby preventing data from being accurately transmitted from the bit line BL to the local data line LIO.

[0103] In some embodiments, the first driving unit 610 includes a first P-type transistor P1, a source of the first P-type transistor P1 is connected to the switching unit 630, a drain of the first P-type transistor P1 is connected to the local data line LIO, and a gate of the first P-type transistor P1 is connected to the complementary local data line LIOB.

[0104] The second driving unit 620 includes a second P-type transistor P2, a source of which is connected to the switch unit 630, a drain of which is connected to the complementary local data line LIOB, and a gate of which is connected to the local data line LIO.

[0105] The switching unit 630 includes a third P-type transistor P3, the source of the third P-type transistor P3 is connected to the first power supply terminal, the drain of the third P-type transistor P3 is connected to the source of the first P-type transistor P1, the drain of the third P-type transistor P3 is also connected to the source of the second P-type transistor P2, and the gate of the third P-type transistor P3 receives the first control signal RdEnN.

[0106] The lower the gate voltage of the P-type transistor, the greater the on-current of the P-type transistor, and the stronger the voltage-pulling capability of the P-type transistor.

[0107] The third P-type transistor P3 is turned on, controlling the source of the first P-type transistor P1 to connect to the first power supply terminal, and the source of the second P-type transistor P2 to connect to the first power supply terminal. After a voltage difference is generated between the local data line LIO and the complementary local data line LIOB, for example, the voltage on the local data line LIO is greater than the voltage on the complementary local data line LIOB, that is, the voltage on the local data line LIO is relatively large, while the voltage on the complementary local data line LIOB is relatively small. Because the voltage on the complementary local data line LIOB is relatively small, the first P-type transistor P1 has a stronger driving capability to drive the local data line LIO upward. When the voltage on the local data line LIO is relatively large, the second P-type transistor P2 has a weaker driving capability to drive the complementary local data line LIOB upward. When the first P-type transistor P1 has a stronger driving capability to drive the local data line LIO upward, while the second P-type transistor P2 has a weaker driving capability to drive the complementary local data line LIOB upward, the voltage on the local data line LIO continues to be greater than the voltage on the complementary local data line LIOB, thereby amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0108] The above uses the example of the voltage on the local data line LIO being greater than the voltage on the complementary local data line LIOB to illustrate the principle of the first P-type transistor P1 and the second P-type transistor P2 amplifying the voltage difference between the local data line LIO and the complementary local data line LIOB. The principle is similar when the voltage on the local data line LIO is less than the voltage on the complementary local data line LIOB, and will not be repeated here.

[0109] In some embodiments, continue to refer to Figure 5The driving circuit 600 further includes a first control circuit 700. A first output terminal of the first control circuit 700 is connected to the control terminal of the switch unit 630, and a second output terminal of the first control circuit 700 is connected to the control terminal of the secondary amplifier circuit 200. A first input terminal of the first control circuit 700 receives the mode signal CTRLPin, and a second input terminal of the first control circuit 700 receives the reference signal RdEnPre. The first control circuit 700 is configured to generate a first control signal RdEnN based on the mode signal CTRLPin and the reference signal RdEnPre, and to generate a second control signal RdEn based on the reference signal RdEnPre.

[0110] The first control signal RdEnN controls the driving circuit 600 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB. The second control signal RdEn controls the secondary amplifying circuit 200 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0111] In some embodiments, the first control signal RdEnN is active low, and the second control signal RdEn is active high. When the first control signal RdEnN is low, the driver circuit 600 is controlled to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB. When the second control signal RdEn is high, the secondary amplifier circuit 200 is controlled to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0112] In some embodiments, as Figure 6 As shown, the first control signal RdEnN starts to be active at time t2 earlier than the second control signal RdEn starts to be active at time t3. The control driving circuit 600 first amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB, and the secondary amplification circuit 200 then amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB. With this configuration, the driving circuit 600 first amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB to compensate for the effect of the coupling capacitor on the voltage of the local data line LIO. The secondary amplification circuit 200 and the driving circuit 600 then jointly amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, generating a voltage difference between the global data line GIO and the complementary global data line GIOB. This shortens the time it takes the secondary amplification circuit 200 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby improving the performance of the memory's timing parameter tCCD.

[0113] In some embodiments, as Figure 6As shown, the start time t2 when the first control signal RdEnN is in the valid state is later than the end time t0 when the equalization control signal EQLOB is in the valid state. When the equalization control signal EQLOB is in the valid state, the voltages of the local data line LIO and the complementary local data line LIOB are charged to the precharge voltage.

[0114] In some embodiments, the equalization control signal EQLOB is an active low signal, that is, when the equalization control signal EQLOB is at a low level, the voltages of the local data line LIO and the complementary local data line LIOB are charged to a precharge voltage.

[0115] Through such a configuration, after the voltages of the local data line LIO and the complementary local data line LIOB are charged to the pre-charge voltage, the control driving circuit 600 and the secondary amplification circuit 200 amplify the voltage difference between the local data line LIO and the complementary local data line LIOB, thereby achieving accurate data transmission between the bit line BL and the local data line LIO, and between the complementary bit line BLB and the complementary local data line LIOB.

[0116] In some embodiments, the mode signal CTRLPin is used to adjust the start time t2 when the first control signal RdEnN is in the valid state, that is, to adjust the start time when the driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0117] In some embodiments, the minimum value t2min of the starting time when the first control signal RdEnN is in the valid state is the end time when the equalization control signal EQLOB is in the valid state, and the maximum value t2max of the starting time when the first control signal RdEnN is in the valid state is the starting time when the second control signal RdEn is in the valid state.

[0118] In some embodiments, the first control circuit 700 is configured to determine a time step between the reference signal RdEnPre and the first control signal RdEnN according to the mode signal CTRLPin, and process the reference signal RdEnPre according to the time step to generate the first control signal RdEnN.

[0119] The time step can be a positive time step, denoted by Δτ. It can also be a negative time step, denoted by -Δτ. A positive time step means that the first control signal RdEnN starts to be active at time t2 later than the reference signal RdEnPre starts to be active at time t1, and the difference between t1 and t2 is Δτ. A negative time step means that the first control signal RdEnN starts to be active at time t2 earlier than the reference signal RdEnPre starts to be active at time t1, and the difference between t1 and t2 is Δτ.

[0120] The mode signal CTRLPin is determined by any one or more parameters of a first time interval, a process corner of the memory, a temperature of the memory, and an operating voltage of the memory. The first time interval is the time interval between adjacent row addressing and column addressing of the memory.

[0121] In some embodiments, the mode signal CTRLPin is determined by a first time interval. The shorter the first time interval, the larger the time step corresponding to the mode signal CTRLPin, so that the starting time when the first control signal RdEnN is in the valid state is later.

[0122] Among them, when the time step is a negative time step -△τ, the smaller the absolute value of the negative time step -△τ, the larger the negative time step. When the time step is a positive time step △τ, the larger the absolute value of the positive time step △τ, the larger the positive time step.

[0123] In some embodiments, the mode signal CTRLPin is determined by any one or more parameters of the memory's process angle, memory temperature, and memory operating voltage. Multiple tests of the memory can be performed to determine the relationship between the memory's process angle, memory temperature, memory operating voltage, and the time at which the first control signal RdEnN becomes active, thereby reducing noise introduced into the bit line BL and the complementary bit line BLB.

[0124] By such a configuration, when the timing parameters of the memory are poor, the start time at which the driving circuit 600 amplifies the voltage difference between the local data line LIO and the complementary local data line LIOB is adjusted, thereby reducing the noise introduced by the local data line LIO and the complementary local data line LIOB into the bit line BL and the complementary bit line BLB, thereby achieving accurate data transmission.

[0125] In some embodiments, the reference signal RdEnPre is the column selection signal CSL. Under the control of the column selection signal CSL, the second control circuit 400 controls the connection or disconnection between the bit line BL and the local data line LIO, and is also used to control the connection or disconnection between the complementary bit line BLB and the complementary local data line LIOB.

[0126] In some embodiments, the reference signal RdEnPre is not limited to the column selection signal CSL, but may be any other signal as long as the first control signal RdEnN satisfies the above timing relationship, which is not limited here.

[0127] The following combination Figure 7 The working principle of the memory described in the embodiment of the present disclosure is described below:

[0128] During phase T1, column select signal CSL is low, disconnecting bit line BL from local data line LIO, and disconnecting complementary bit line BLB from complementary local data line LIOB. Data "1" is stored in the memory cell, and charge is shared between the memory cell and bit line BL, generating a small voltage difference ΔBL1 between bit line BL and complementary bit line BLB. First-stage amplifier circuit 100 amplifies this small voltage difference ΔBL1 between bit line BL and complementary bit line BLB during phase T1, for example, to a voltage difference ΔBL2.

[0129] In the T2 phase, the column select signal CSL is at a high level, the bit line BL is connected to the local data line LIO, the complementary bit line BLB is connected to the complementary local data line LIOB, and the data on the bit line BL and the complementary bit line BLB are transferred to the local data line LIO and the complementary local data line LIOB. At this time, if the local data lines LIO on both sides are connected <2> and LIO <3> Due to the voltage jump when transmitting data "0", the local data line LIO in the middle <1> The data "1" is transmitted on the local data line LIO, that is, the voltage of the local data line LIO in the middle is close to the pre-charge voltage VintLP, then the local data lines LIO on both sides are <2> and LIO <3> The coupling capacitor will cause the local data line LIO in the middle <0> The voltage on the

[0130] Starting from the T3 phase, the first control signal RdEnN is at a low level, the third P-type transistor P3 is turned on, the first P-type transistor P1 drives the voltage on the local data line LIO upward, and the second P-type transistor P2 drives the voltage on the complementary local data line LIOB upward. The driving capability of the first P-type transistor P1 to pull the local data line LIO upward is greater than the driving capability of the second P-type transistor P2 to pull the complementary local data line LIOB upward, compensating the local data lines LIO on both sides. <2> and LIO <3> For the intermediate local data line LIO <0> At this time, the complementary bit line BLB drives the voltage of the complementary local data line LIOB downward to compensate the local data lines LIO on both sides. <2> and LIO <3> For the intermediate local data line LIO <0> The voltage difference between the local data line LIO and the complementary local data line LIOB is amplified by the upper voltage.

[0131] Starting from stage T4, the second control signal RdEn is at a high level, and the secondary amplifier circuit 200 begins to amplify the voltages on the local data line LIO and the complementary local data line LIOB. At this time, since the driving circuit 600 has already amplified the voltage difference between the local data line LIO and the complementary local data line LIOB, the voltage difference ΔLIO2 is already relatively large. The secondary amplifier circuit 200 and the driving circuit 600 amplify the voltage difference between the local data line LIO and the complementary local data line LIOB together, which can shorten the time it takes for the secondary amplifier circuit 200 to amplify the voltage difference between the local data line LIO and the complementary local data line LIOB.

[0132] Figure 7 The case where data "1" is stored in a storage unit is taken as an example. The case where data "0" is stored in a storage unit is similar to the case where data "1" is stored, and will not be described in detail here.

[0133] Continue to refer Figure 7 The starting time when the first control signal RdEnN is in the valid state can be adjusted at the starting time indicated by RdEnN1 and the starting time indicated by RdEnN2, so as to adjust the magnitude of the noise introduced by the local data line LIO and the complementary local data line LIOB to the bit line BL and the complementary bit line BLB.

[0134] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0135] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A memory, characterized in that: include: a first-stage amplifier circuit connected to the bit line and the complementary bit line, and configured to amplify a voltage difference between the bit line and the complementary bit line; a secondary amplifier circuit connected to a local data line and a complementary local data line, and also connected to a global data line and a complementary global data line, and amplifying a voltage difference between the local data line and the complementary local data line after connection between the local data line and the bit line, and connection between the complementary local data line and the complementary bit line, and generating a voltage difference between the global data line and the complementary global data line; The driving circuit is connected to the local data line and the complementary local data line, and amplifies the voltage difference between the local data line and the complementary local data line.

2. The memory according to claim 1, wherein The memory further comprises: an equalization circuit connected to the local data line and the complementary local data line, charging the voltages of the local data line and the complementary local data line to a precharge voltage before the local data line is connected to the bit line and before the complementary local data line is connected to the complementary bit line; The driving circuit is used for amplifying the voltage difference between the local data line and the complementary local data line after the voltages of the local data line and the complementary local data line are charged to a pre-charge voltage.

3. The memory according to claim 1 or 2, characterized in that The driving circuit starts amplifying the voltage difference between the local data line and the complementary local data line earlier than the secondary amplifying circuit starts amplifying the voltage difference between the local data line and the complementary local data line.

4. The memory according to claim 1 or 2, characterized in that When the first time interval is within the first time range, the first starting time is within the first value range; When the first time interval is within the second time range, the first starting time is within the second value range; The first time interval is the time interval between adjacent row addressing and column addressing of the memory, and the first starting time is the starting time when the driving circuit amplifies the voltage difference between the local data line and the complementary local data line; The upper limit of the first time range is less than or equal to the lower limit of the second time range, and the upper limit of the first numerical range is greater than or equal to the lower limit of the second numerical range.

5. The memory according to claim 1, wherein: The driving circuit is used for: amplifying a voltage difference between the local data line and the complementary local data line by driving up a voltage of the local data line and / or a voltage of the complementary local data line; The driving capability of driving the local data line upward is negatively correlated with the voltage on the complementary local data line, and the driving capability of driving the complementary local data line upward is negatively correlated with the voltage on the local data line.

6. The memory according to claim 5, wherein: The driving circuit includes: a switch unit connected to the first drive unit and the second drive unit, controlling the first drive unit to be connected to or disconnected from the first power supply terminal under the control of a first control signal, and controlling the second drive unit to be connected to or disconnected from the first power supply terminal under the control of the first control signal; the first power supply terminal provides a power supply voltage; The first driving unit is connected to the local data line and the complementary local data line, and drives the voltage of the local data line upward according to the voltage of the complementary local data line when the first driving unit is connected to the first power terminal; the second driving unit being connected to the local data line and the complementary local data line, and driving the voltage of the complementary local data line upward according to the voltage of the local data line when the second driving unit is connected to the first power terminal; The driving capability of the first driving unit to drive the local data line is negatively correlated with the voltage of the complementary local data line; the driving capability of the second driving unit to drive the complementary local data line is negatively correlated with the voltage of the local data line.

7. The memory according to claim 6, wherein: The first driving unit includes: a first P-type transistor, having a source connected to the switch unit, a drain connected to the local data line, and a gate connected to the complementary local data line; The second driving unit includes: A second P-type transistor has a source connected to the switch unit, a drain connected to the complementary local data line, and a gate connected to the local data line.

8. The memory according to claim 7, wherein: The switch unit includes: The third P-type transistor has a source connected to the first power supply terminal, a drain connected to the source of the first P-type transistor, a drain also connected to the source of the second P-type transistor, and a gate receiving the first control signal.

9. The memory according to claim 6, wherein: The driving circuit further includes: a first control circuit, wherein a first output end is connected to the control end of the switch unit, and a second output end is connected to the control end of the secondary amplification circuit; a first input end receives a mode signal, and a second input end receives a reference signal, and is configured to generate a first control signal according to the mode signal and the reference signal, and generate a second control signal according to the reference signal; The first control signal starts being valid earlier than the second control signal starts being valid, and the second control signal controls the secondary amplifier circuit to amplify the voltage difference between the local data line and the complementary local data line.

10. The memory according to claim 9, wherein: The start time of the first control signal being in the valid state is later than the end time of the equalization control signal being in the valid state. When the equalization control signal is in the valid state, the voltages of the local data line and the complementary local data line are charged to a precharge voltage.

11. The memory according to claim 9, wherein: The control circuit is used to: determining a time step between the reference signal and the first control signal according to the mode signal; The reference signal is processed according to the time step to generate the first control signal.

12. The memory according to claim 11, wherein: The mode signal is determined by any one or more parameters of the first time interval, the process angle of the memory, the temperature of the memory, and the operating voltage of the memory; The first time interval is the time interval between adjacent row addressing and column addressing of the memory.

13. The memory according to claim 9, wherein: The reference signal is a column selection signal, and the column selection signal is used to control the connection or disconnection between the bit line and the local data line, and also to control the connection or disconnection between the complementary bit line and the complementary local data line.

14. The memory according to claim 1, wherein: The memory further comprises: A second control circuit is connected to the bit line and the complementary bit line, and is also connected to the local data line and the complementary local data line, and is used to receive a column selection signal, and control the connection or disconnection between the bit line and the local data line under the control of the column selection signal, and control the connection or disconnection between the complementary bit line and the complementary local data line under the control of the column selection signal.

15. The memory according to claim 1, wherein: The memory further comprises: The three-stage amplifier circuit is connected to the global data line and the complementary global data line, and is used to amplify the voltage difference between the global data line and the complementary global data line.

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