Semiconductor structure fabrication methods, semiconductor structures, memory and devices

Abstract

This application provides a method for fabricating a semiconductor structure, a semiconductor structure, a memory, and a device. The method includes: forming a first semiconductor structure on a substrate; forming a first coupling metal structure on a first dielectric layer, wherein the first coupling metal structure connects a second gate metal structure and a second source / drain metal; washing and removing the substrate; forming a shallow trench isolation layer on the first semiconductor structure; forming a second semiconductor structure on the shallow trench isolation layer; forming a second coupling metal structure and a third coupling metal structure in the shallow trench isolation layer; the second coupling metal structure connects the first gate metal structure and a fourth gate metal structure, and the third coupling metal structure connects the second gate metal structure and the third gate metal structure; forming a fourth coupling metal structure on the second dielectric layer, wherein the fourth coupling metal structure connects the fourth gate metal structure and a fourth source / drain metal. This application can improve the integration density of transistors.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a method for preparing a semiconductor structure, a semiconductor structure, a memory, and a device. Background Technology

[0002] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacking transistors, by integrating two or more layers of transistors in a vertical space, further increases transistor integration density and has become one of the important technologies for continuing the miniaturization of integrated circuits.

[0003] Existing Static Random Access Memory (SRAM) cells are all fabricated based on single-layer transistors, and because there are many components in an SRAM cell, the SRAM is relatively large. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, a device, and an apparatus to improve the integration density of transistors.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, the method comprising: forming a first semiconductor structure on a substrate; the first semiconductor structure being a bipolar transistor, the first semiconductor structure including a first transistor having a first polarity and a second transistor having a second polarity, the first transistor including a first gate metal structure and a first source-drain metal structure, the second transistor including a second gate metal structure and a second source-drain metal structure, a first dielectric layer being formed on the first gate metal structure, the first source-drain metal structure, the second gate metal structure and the second source-drain metal structure; forming a first coupling metal structure on the first dielectric layer, the first coupling metal structure connecting the second gate metal structure and the second source-drain metal structure; flipping a wafer and removing the substrate; forming a shallow trench isolation layer on the first semiconductor structure; forming a second semiconductor structure on the shallow trench isolation layer; the first semiconductor structure and the second semiconductor structure being perpendicular to the active region. The second semiconductor structure is a bipolar transistor, comprising a third transistor with a first polarity and a fourth transistor with a second polarity. The third transistor includes a third gate metal structure and a third source / drain metal structure, and the fourth transistor includes a fourth gate metal structure and a fourth source / drain metal structure. A second dielectric layer is formed on the third gate metal structure, the third source / drain metal structure, the fourth gate metal structure, and the fourth source / drain metal structure. A second coupling metal structure and a third coupling metal structure are formed in a shallow trench isolation layer. The second coupling metal structure connects the first gate metal structure and the fourth gate metal structure, and the third coupling metal structure connects the second gate metal structure and the third gate metal structure. The third gate metal structure corresponds to the second gate metal structure, and the fourth gate metal structure corresponds to the first gate metal structure. A fourth coupling metal structure is formed on the second dielectric layer, connecting the fourth gate metal structure and the fourth source / drain metal structure.

[0006] In some possible implementations, forming a first semiconductor structure on a substrate may include: etching the substrate to form an active structure; the active structure includes a first active structure for fabricating the first semiconductor structure, a second active structure for fabricating a second semiconductor structure, and an intermediate dielectric layer located between the first and second active structures; depositing an insulating material on the active structure and the substrate to form a shallow trench isolation structure; the shallow trench isolation structure encapsulating the active structure; removing a portion of the shallow trench isolation structure that encapsulates the first active structure to expose the first active structure; and forming the first semiconductor structure based on the first active structure.

[0007] In some possible implementations, forming a first semiconductor structure based on a first active structure may include: forming a first source / drain structure of the first semiconductor structure based on the first active structure; depositing a first insulating material on the first source / drain structure and the first active structure to form a first interlayer dielectric layer; photolithographically opening a first gate region of the first semiconductor structure and depositing a metal material in the first gate region to form a first gate metal structure and a second gate metal structure; the first source / drain structures being spaced apart on both sides of the first gate metal structure and the second gate metal structure; forming a first source / drain metal structure and a second source / drain metal structure based on the first source / drain structure; and depositing a second insulating material on the first gate metal structure, the second gate metal structure, the first source / drain metal structure, the second source / drain metal structure, and the first interlayer dielectric layer to form a first dielectric layer.

[0008] In some possible implementations, forming a first coupling metal structure on a first dielectric layer may include: etching a portion of the first dielectric layer to form a first via; connecting the first via to a second gate metal structure and a second source / drain metal structure; and depositing metal material in the first via to form the first coupling metal structure.

[0009] In some possible implementations, after forming the first coupling metal structure on the first dielectric layer, the above method may further include: performing a post-processing step on the first interlayer dielectric layer to form a first metal interconnect layer; the first metal interconnect layer includes a first drain metal line (VDD), a first source metal line (VSS), a first word line (WL), and a first bit line (BL).

[0010] In some possible implementations, forming a shallow trench isolation layer on the first semiconductor structure may include: removing a portion of the shallow trench isolation structure that encloses the second active structure to expose the second active structure and forming the shallow trench isolation layer; the shallow trench isolation layer surrounds an intermediate dielectric layer.

[0011] In some possible implementations, forming a second semiconductor structure on a shallow trench isolation layer may include: forming a second source / drain structure of the second semiconductor structure based on a second active structure; depositing a first insulating material on the second source / drain structure and the second active structure to form a second interlayer dielectric layer; photolithographically opening a second gate region of the second semiconductor structure and depositing metal material in the second gate region to form a third gate metal structure and a fourth gate metal structure; the second source / drain structures being spaced apart on both sides of the third gate metal structure and the fourth gate metal structure; forming a third source / drain metal structure and a fourth source / drain metal structure based on the second source / drain structure; and depositing a second insulating material on the third gate metal structure, the fourth gate metal structure, the third source / drain metal structure, the fourth source / drain metal structure, and the second interlayer dielectric layer to form a second dielectric layer.

[0012] In some possible implementations, prior to forming the third gate metal structure and the fourth gate metal structure, the method further includes: photolithographically processing the shallow trench isolation layer to form the second via and the third via; and depositing metal material in the second via and the third via to form the second coupling metal structure and the third coupling metal structure.

[0013] In some possible implementations, forming a fourth coupling metal structure on the second dielectric layer may include: etching a portion of the second dielectric layer to form a fourth via; the fourth via connecting a fourth gate metal structure and a fourth source / drain metal structure; and depositing metal material in the fourth via to form the fourth coupling metal structure.

[0014] In some possible implementations, after forming the fourth coupling metal structure on the second dielectric layer, the above method may further include: performing a post-processing step on the second interlayer dielectric layer to form a second metal interconnect layer; the second metal interconnect layer includes a second VDD, a second VSS, a second WL, and a second BL.

[0015] In some possible implementations, the semiconductor structure is a six-transistor static random access memory (6TSRAM) cell; wherein, the first semiconductor structure includes a first pull-down (PD) transistor, a first passgate (PG) transistor, a first pull-up (PU) transistor, and a first sub-semiconductor structure; the first PG transistor and the first sub-semiconductor structure are arranged side by side in a first direction, the first PD transistor and the first PU transistor are arranged side by side in a first direction, the first PG transistor and the first PD transistor are arranged side by side in a second direction, and the first sub-semiconductor structure and the first PU transistor are arranged side by side in a second direction; the first direction is the length direction of the first gate metal structure, and the second direction is a direction perpendicular to the first direction; the second semiconductor structure includes a second PD transistor, a second PG transistor, a second PU transistor, and a second sub-semiconductor structure; the second PG transistor and the second sub-semiconductor structure are arranged side by side in a first direction, the second PD transistor and the second PU transistor are arranged side by side in a first direction, the second PG transistor and the second PD transistor are arranged side by side in a second direction, and the second sub-semiconductor structure and the second PU transistor are arranged side by side in a second direction.

[0016] In some possible implementations, the first active structure includes a first sub-active structure located within a first sub-semiconductor structure; prior to depositing insulating material on the active structure and the substrate to form a shallow trench isolation structure, the method may further include: coating a photoresist on the first active structure and etching a first portion of the first sub-active structure away from the first PU transistor using the photoresist as a mask; the length of the first portion is half the length of the first sub-semiconductor structure.

[0017] In some possible implementations, the second active structure includes a second sub-active structure located in the second sub-semiconductor structure; after forming a shallow trench isolation layer on the first semiconductor structure, the above method may further include: coating the second active structure with photoresist and etching a second portion of the second sub-active structure that is away from the second PU transistor using the photoresist as a mask; the length of the second portion is half the length of the second sub-semiconductor structure.

[0018] Secondly, embodiments of this application provide a semiconductor structure, comprising: a first semiconductor structure; the first semiconductor structure is a bipolar transistor, the first semiconductor structure including a first transistor having a first polarity and a second transistor having a second polarity, the first transistor including a first gate metal structure and a first source-drain metal structure, the second transistor including a second gate metal structure and a second source-drain metal structure; a second semiconductor structure; the second semiconductor structure is a bipolar transistor, the second semiconductor structure including a third transistor having a first polarity and a fourth transistor having a second polarity, the third transistor including a third gate metal structure and a third source-drain metal structure, the fourth transistor including a fourth gate metal structure and a third source-drain metal structure. A quad-source-drain metal structure; a first semiconductor structure and a second semiconductor structure self-aligned in a direction perpendicular to the active region; a first coupling metal structure; the first coupling metal structure connects the second gate metal structure and the second source-drain metal structure; a second coupling metal structure; the second coupling metal structure is located between the first gate metal structure and the fourth gate metal structure, and connects the first gate metal structure and the fourth gate metal structure; a third coupling metal structure; the third coupling metal structure is located between the second gate metal structure and the third gate metal structure, and connects the second gate metal structure and the third gate metal structure; a fourth coupling metal structure; the fourth coupling metal structure connects the fourth gate metal structure and the fourth source-drain metal structure.

[0019] In some possible implementations, the above-described semiconductor structure is a six-transistor static random access memory (SRAM) cell; wherein, the first semiconductor structure includes a first pull-down PD transistor, a first transmission gate PG transistor, a first pull-up PU transistor, and a first sub-semiconductor structure; the first PG transistor and the first sub-semiconductor structure are arranged side by side in a first direction, the first PD transistor and the first PU transistor are arranged side by side in a first direction, the first PG transistor and the first PD transistor are arranged side by side in a second direction, and the first sub-semiconductor structure and the first PU transistor are arranged side by side in a second direction; the first direction is the length direction of the first gate metal structure, and the second direction is a direction perpendicular to the first direction; the second semiconductor structure includes a second PD transistor, a second PG transistor, a second PU transistor, and a second sub-semiconductor structure; the second PG transistor and the second sub-semiconductor structure are arranged side by side in a first direction, the second PD transistor and the second PU transistor are arranged side by side in a first direction, the second PG transistor and the second PD transistor are arranged side by side in a second direction, and the second sub-semiconductor structure and the second PU transistor are arranged side by side in a second direction.

[0020] In some possible implementations, the above semiconductor structure further includes: a first metal interconnect layer in the first semiconductor structure; the first metal interconnect layer is formed by a back-end process, and the first metal interconnect layer includes a first drain metal line VDD, a first source metal line VSS, a first word line WL, and a first bit line BL; and a second metal interconnect layer in the second semiconductor structure; the second metal interconnect layer is formed by a back-end process, and the second metal interconnect layer includes a second VDD, a second VSS, a second WL, and a second BL.

[0021] Thirdly, embodiments of this application provide a memory, which includes a semiconductor structure as described in the above embodiments.

[0022] Fourthly, embodiments of this application provide an electronic device, which includes: a circuit board and a memory as described in the above embodiments, the memory being disposed on the circuit board.

[0023] In this application, the first coupling metal structure in the semiconductor structure is connected to the second gate metal structure and the second source / drain metal structure, the second coupling metal structure is connected to the first gate metal structure and the fourth gate metal structure, the third coupling metal structure is connected to the second gate metal structure and the third gate metal structure, and the fourth coupling metal structure is connected to the fourth gate metal structure and the fourth source / drain metal structure. In this way, cross-coupling between the first semiconductor structure and the second semiconductor structure can be achieved. Based on this, the design and layout of the above cross-coupling further reduces the size of the semiconductor structure and increases the integration density.

[0024] Furthermore, the semiconductor structure is a six-transistor SRAM cell, and the self-aligned first semiconductor structure and the second semiconductor structure together form a flip-chip stacked transistor (i.e., semiconductor structure). The combination of the flip-chip stacked transistor and the six-transistor SRAM cell can reduce the spacing between adjacent devices, thereby significantly improving the integration density.

[0025] Furthermore, wiring is simultaneously performed in the first metal interconnect layer of the first semiconductor structure and the second metal interconnect layer of the second semiconductor structure, allowing power lines (VDD, VSS) and signal lines (WL, BL) to achieve a wider area, thereby reducing parasitics.

[0026] Furthermore, the semiconductor structure provided in this application can be inspected using analytical instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, the semiconductor structure provided in this application can be inspected by TEM slicing, including the front fin-cut region, the back fin-cut region, the first coupling metal structure, the second coupling metal structure, the third coupling metal structure, the fourth coupling metal structure, the first metal interconnect layer, and the second interconnect layer.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0029] Figure 1 This is a schematic diagram of an implementation process of the semiconductor structure fabrication method in this application.

[0030] Figures 2A to 2C This is a schematic diagram of a semiconductor structure in one embodiment of this application;

[0031] Figures 3A to 3M This is a schematic diagram of a semiconductor structure fabrication process in an embodiment of this application;

[0032] The above images:

[0033] 10. Semiconductor structure; 11. First semiconductor structure; 111. First active structure; 112. First source / drain structure; 113. First / second source / drain metal structure; 114. First gate cutoff structure; 115. First dielectric layer; 116. First interlayer dielectric layer; 117. First metal interconnect layer; 118n. First gate metal structure; 118p. Second gate metal structure; 119. First dummy gate structure; 12. Second semiconductor structure; 121. Second active structure; 122. Second source / drain structure; 123. Third / fourth source / drain metal structure; 124. Second gate cutoff structure; 125. 126. Second interlayer dielectric layer; 127. Second metal interconnect layer; 128n. Third gate metal structure; 128p. Fourth gate metal structure; 13. Shallow trench isolation layer; 14. Insulating layer; 15. Carrier wafer; 21. Substrate; 211. Top substrate; 212. Intermediate dielectric layer; 213. Bottom substrate; 22. Anti-reflection layer; 23. Photoresist; 24. Shallow trench isolation structure; 31. First coupling metal structure; 32. Second coupling metal structure; 33. Third coupling metal structure; 34. Fourth coupling metal structure; 41. First through-layer via; 42. Second through-layer via. Detailed Implementation

[0034] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0035] With Moore's Law continuously evolving, and beyond the technology node of gate-all-around FETs (GAA), further miniaturizing transistor size is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. This technology is considered one of the key technologies for continuing the miniaturization of integrated circuits.

[0036] In one embodiment, there are two methods for fabricating stacked transistors: the first is a monolithic stacking method, and the second is a sequential method.

[0037] Existing SRAM cells are all based on single-layer transistor fabrication, and because there are many components in an SRAM cell, the integration density and size of SRAM are relatively large.

[0038] To address the aforementioned technical problems, this application provides a method for fabricating a semiconductor structure to improve the integration density of transistors.

[0039] In the embodiments of this application, the above-described semiconductor structure can be applied to semiconductor devices such as memory and processors.

[0040] In some embodiments, the semiconductor structure can be a stacked flip-chip transistor, comprising a first semiconductor structure and a second transistor semiconductor structure disposed opposite to each other, the first semiconductor structure and the second semiconductor structure being self-aligned in a direction perpendicular to the active region. Both the first semiconductor structure and the second semiconductor structure are bipolar transistors, wherein the first semiconductor structure includes a first transistor with a first polarity and a second transistor with a second polarity; and the second semiconductor structure includes a third transistor with a first polarity and a fourth transistor with a second polarity.

[0041] It should be noted that, since the first semiconductor structure and the second semiconductor structure are arranged back-to-back and stacked on top of each other, in this embodiment, the first semiconductor structure can also be referred to as a front-side transistor, and the second semiconductor structure can also be referred to as a back-side transistor. Correspondingly, each device in the front-side transistor can also be referred to as a front-side device; for example, the first source-drain metal structure and the second source-drain metal structure in the first semiconductor structure can be referred to as a front-side source-drain metal structure, and similarly, the third source-drain metal structure and the fourth source-drain metal structure in the second semiconductor structure can be referred to as a back-side source-drain metal structure.

[0042] In the embodiments of this application, in the first case, the first polarity is n-type and the second polarity is p-type; in the second case, the first polarity is p-type and the second polarity is n-type; the embodiments of this application do not specifically limit this.

[0043] In some embodiments, based on the complementary characteristics of n-type transistors and p-type transistors, taking an example where the first polarity is n-type and the second polarity is p-type, the first transistor (n-type) of the first semiconductor structure corresponds to the fourth transistor (p-type) of the second semiconductor structure, and the second transistor (p-type) of the first semiconductor structure corresponds to the third transistor (n-type) of the second semiconductor structure.

[0044] In some embodiments, the first active structure of the first semiconductor structure and the second active structure of the second semiconductor structure are formed through the same process, so the active regions of the first semiconductor structure and the second semiconductor structure are self-aligned.

[0045] In the embodiments of this application, the active region is a collective term for the source region, the drain region, and the channel region.

[0046] In the embodiments of this application, the first semiconductor structure and the second semiconductor structure in the semiconductor structure can be transistors of the same type, such as any of the following: fin field-effect transistor, nanosheet field-effect transistor, planar transistor, etc. The embodiments of this application do not specifically limit the type of the first semiconductor structure and the second semiconductor structure, and they can also be other types of transistors.

[0047] Figures 2A to 2C The semiconductor structure is composed of fin field-effect transistors, which will be discussed below. Figures 2A to 2C The semiconductor structure shown illustrates the method for fabricating the semiconductor structure provided in the embodiments of this application.

[0048] Figure 1 This is a schematic diagram illustrating one implementation process of the semiconductor structure fabrication method in this application. See also... Figure 1 As shown, the method for fabricating the above-mentioned semiconductor structure may include:

[0049] S101, a first semiconductor structure is formed on the substrate.

[0050] The first semiconductor structure is a bipolar transistor, which includes a first transistor with a first polarity and a second transistor with a second polarity. The first transistor includes a first gate metal structure and a first source-drain metal structure, and the second transistor includes a second gate metal structure and a second source-drain metal structure. A first dielectric layer is formed on the first gate metal structure, the second gate metal structure, the first source-drain metal structure and the second source-drain metal structure.

[0051] Understandably, in the initial stage of semiconductor structure fabrication, a substrate can be provided first, then an active structure can be formed on the substrate, and finally a first semiconductor structure can be formed based on the active structure. Specifically, when the first and second semiconductor structures in the semiconductor structure are fin field-effect transistors, the active structure is a fin-shaped structure; when the first and second semiconductor structures are nanosheet field-effect transistors, the active structure is a nanosheet structure; and when the first and second semiconductor structures are planar transistors, the active structure is a bulk structure.

[0052] In some possible implementations, S101 may include: etching a substrate to form an active structure; the active structure includes a first active structure for fabricating a first semiconductor structure, a second active structure for fabricating a second semiconductor structure, and an intermediate dielectric layer located between the first and second active structures; depositing an insulating material on the active structure and the substrate to form a shallow trench isolation (STI) structure; the shallow trench isolation structure encapsulating the active structure; removing a portion of the shallow trench isolation structure that encapsulates the first active structure to expose the first active structure; and forming a first semiconductor structure based on the first active structure.

[0053] Understandably, since the active structure comprises three parts—a first active structure, a second active structure, and an intermediate dielectric layer—and these three parts are formed through the same etching process, the substrate can also be configured to comprise three parts: a bottom substrate, an intermediate dielectric layer, and a top substrate. The substrate fabrication process can include: epitaxially depositing an oxide layer on the bottom substrate to form the intermediate dielectric layer; then, epitaxially depositing the same semiconductor material as the bottom substrate above the intermediate dielectric layer to form the top substrate. The substrate formed by the above method comprises a top substrate, an intermediate dielectric layer, and a bottom substrate stacked sequentially. The top substrate is used to fabricate the first active structure, the bottom substrate is used to fabricate the second active structure, and the intermediate dielectric layer is used to isolate the first and second active structures.

[0054] It should be noted that, in the embodiments of this application, besides providing an intermediate dielectric layer, the isolation between the first active structure and the second active structure can also take other forms. For example, ion implantation can be performed between the first active structure and the second active structure to form an electrical isolation layer. When other means are used to achieve isolation between the first active structure and the second active structure, the substrate may also omit the intermediate dielectric layer. Using an intermediate dielectric layer to achieve isolation between the first active structure and the second active structure is merely an example, and the embodiments of this application do not limit how the isolation between the first active structure and the second active structure is specifically achieved.

[0055] In some embodiments, when the first semiconductor structure and the second semiconductor structure in the semiconductor structure are fin field-effect transistors or planar transistors, both the top substrate and the bottom substrate are single-layer structures. For example, the bottom substrate and the top substrate can be single-layer silicon (Si) material.

[0056] In other embodiments, when the first semiconductor structure and the second semiconductor structure in the semiconductor structure are nanosheet field-effect transistors, both the top substrate and the bottom substrate are stacked structures. For example, the top substrate and the bottom substrate can be a stack formed by alternating deposition of silicon and silicon germanium (SiGe).

[0057] In some embodiments, the height of the top substrate can be designed according to actual needs, such as 50 nm, the height of the bottom substrate is greater than that of the top substrate, and the height of the intermediate dielectric layer is less than that of the top substrate.

[0058] In some embodiments, the height of the shallow trench isolation structure is greater than the height of the active structure; after forming the shallow trench isolation structure, the above method may include performing chemical-mechanical planarization (CMP) on the shallow trench isolation structure.

[0059] In the embodiments of this application, the insulating material forming the shallow trench isolation structure can be any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc., and the embodiments of this application do not specifically limit it.

[0060] In this embodiment, chemical mechanical planarization of the shallow trench isolation structure can ensure that the etching depth of different areas of the shallow trench isolation structure is the same during subsequent etching, thereby making the height of the exposed active structure the same.

[0061] It should be noted that the etching process mentioned in the embodiments of this application may include, but is not limited to, any of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal process. The embodiments of this application do not specifically limit this process.

[0062] S102, a first coupling metal structure is formed on the first dielectric layer.

[0063] The first coupling metal structure connects the second gate metal structure and the second source / drain metal structure.

[0064] Understandably, the first dielectric layer is formed after the front-end processing of the first semiconductor structure is completed and before the back-end processing of the first semiconductor structure is performed. Accordingly, the first dielectric layer is located between the device layer and the first metal interconnect layer of the first semiconductor structure.

[0065] In some possible implementations, S102 may include: etching a portion of the first dielectric layer to form a first via; the first via connecting a second gate metal structure and a second source / drain metal structure; and depositing metal material in the first via to form a first coupling metal structure.

[0066] Understandably, a via (i.e., a first via) is etched in the first dielectric layer through photolithography. The surface of the first via near the first active structure is connected to the second gate metal structure, and the surface of the first via near the second source / drain metal structure is connected to the second source / drain metal structure. Metal material is deposited in the first via to form a first coupling metal structure, which is electrically connected to the second gate metal structure and the second source / drain metal structure.

[0067] S103, rewind and remove substrate.

[0068] Understandably, after completing the back-end processes of the first semiconductor structure, it can be flipped so that the bottom substrate faces upwards. The substrate is then removed to expose the surfaces of the shallow trench isolation structure and the second active structure that are far from the first semiconductor structure, facilitating the subsequent fabrication of the second semiconductor structure.

[0069] In some embodiments, prior to S103 above, the method may further include: depositing an insulating material (such as silicon oxide) on a first semiconductor structure to form an insulating layer, and bonding the insulating layer to a carrier wafer.

[0070] In this embodiment, the bonded carrier wafer can provide physical support for the flipped first semiconductor structure after the wafer is flipped, effectively preventing the first semiconductor structure from being broken by external force during the fabrication of the second semiconductor structure.

[0071] S104, a shallow trench isolation layer is formed on the first semiconductor structure.

[0072] In some possible implementations, S104 may include: removing a portion of the shallow trench isolation structure that encloses the second active structure to expose the second active structure and form a shallow trench isolation layer; the shallow trench isolation layer surrounds the intermediate dielectric layer.

[0073] Understandably, after wafer flipping and substrate removal, the shallow trench isolation structure encapsulates the second active structure and the intermediate dielectric layer. By removing a portion of the shallow trench isolation structure that encapsulates the second active structure, while retaining a portion of the shallow trench isolation structure that encapsulates the intermediate dielectric layer (for ease of distinction, this retained portion of the shallow trench isolation structure is called the shallow trench isolation layer), a shallow trench isolation layer can be formed between the first semiconductor structure and the second semiconductor structure. The shallow trench isolation layer is used to isolate the first semiconductor structure and the second semiconductor structure.

[0074] S105, a second semiconductor structure is formed on the shallow trench isolation layer.

[0075] In this configuration, the first semiconductor structure and the second semiconductor structure are self-aligned in a direction perpendicular to the active region. The second semiconductor structure is a bipolar transistor and includes a third transistor with a first polarity and a fourth transistor with a second polarity. The third transistor includes a third gate metal structure and a third source-drain metal structure, and the fourth transistor includes a fourth gate metal structure and a fourth source-drain metal structure. A second dielectric layer is formed on the third gate metal structure, the fourth gate metal structure, the third source-drain metal structure, and the fourth source-drain metal structure. A second coupling metal structure and a third coupling metal structure are formed in the shallow trench isolation layer. The second coupling metal structure connects the first gate metal structure and the fourth gate metal structure, and the third coupling metal structure connects the second gate metal structure and the third gate metal structure. The third gate metal structure corresponds to the second gate metal structure, and the fourth gate metal structure corresponds to the first gate metal structure.

[0076] S106, a fourth coupled metal structure is formed on the second dielectric layer.

[0077] The fourth coupling metal structure connects the fourth gate metal structure and the fourth source / drain metal structure.

[0078] Understandably, the second dielectric layer is formed after the front-end processing of the second semiconductor structure is completed and before the back-end processing of the second semiconductor structure is performed. Accordingly, the second dielectric layer is located between the device layer and the second metal interconnect layer of the second semiconductor structure.

[0079] In some possible implementations, S106 may include: etching a portion of the second dielectric layer to form a fourth via; the fourth via connecting a fourth gate metal structure and a fourth source / drain metal structure; and depositing metal material in the fourth via to form a fourth coupling metal structure.

[0080] Understandably, a via (i.e., a fourth via) is etched in the second dielectric layer through photolithography. The surface of the fourth via near the second active structure is connected to the fourth gate metal structure, and the surface of the fourth via near the fourth source / drain metal structure is connected to the fourth source / drain metal structure. Depositing metal material in the fourth via can form a fourth coupling metal structure, which is electrically connected to the fourth gate metal structure and the fourth source / drain metal structure.

[0081] In some possible implementations, the semiconductor structure is a six-transistor SRAM cell; wherein, the first semiconductor structure includes a first PD transistor, a first PG transistor, a first PU transistor, and a first sub-semiconductor structure; the first PG transistor and the first sub-semiconductor structure are arranged side by side in a first direction, the first PD transistor and the first PU transistor are arranged side by side in a first direction, the first PG transistor and the first PD transistor are arranged side by side in a second direction, and the first sub-semiconductor structure and the first PU transistor are arranged side by side in a second direction; the first direction is the length direction of the first gate metal structure, and the second direction is a direction perpendicular to the first direction; the second semiconductor structure includes a second PD transistor, a second PG transistor, a second PU transistor, and a second sub-semiconductor structure; the second PG transistor and the second sub-semiconductor structure are arranged side by side in a first direction, the second PD transistor and the second PU transistor are arranged side by side in a first direction, the second PG transistor and the second PD transistor are arranged side by side in a second direction, and the second sub-semiconductor structure and the second PU transistor are arranged side by side in a second direction.

[0082] Understandably, the first semiconductor structure includes: a first PG transistor, a first PU transistor, a first PD transistor, and a first sub-semiconductor structure. Since the first semiconductor structure is also a bipolar transistor, it can be further divided into a first transistor and a second transistor. The first transistor consists of a first PD transistor and a first PG transistor, and the second transistor consists of a first PU transistor and a first sub-semiconductor structure. The first PG transistor, first PU transistor, first PD transistor, and first sub-semiconductor structure are arranged in a 2×2 configuration, with the first PG transistor and first PD transistor in the same row, the first sub-semiconductor structure and first PU transistor in the same row, the first PG transistor and first sub-semiconductor structure in the same column, and the first PD transistor and first PU transistor in the same column. Corresponding to the first semiconductor structure, the first active structure can be divided into: a first PG active structure located in the first PG transistor, a first PD active structure located in the first PD transistor, a first PU active structure located in the first PU transistor, and a first sub-active structure located in the first sub-semiconductor structure. Accordingly, the second semiconductor structure includes: a second PG transistor, a second PU transistor, a second PD transistor, and a second sub-semiconductor structure. Since the second semiconductor structure is also a bipolar transistor, it can be further divided into a third transistor and a fourth transistor. The third transistor consists of a second PD transistor and a second PG transistor, and the fourth transistor consists of a second PU transistor and a second field-effect transistor. The second PG transistor, second PU transistor, second PD transistor, and second sub-semiconductor structure are arranged in a 2×2 configuration. The second PG transistor and second PD transistor are in the same row, the second sub-semiconductor structure and second PU transistor are in the same row, the second PG transistor and second sub-semiconductor structure are in the same column, and the second PD transistor and second PU transistor are in the same column. Corresponding to the second semiconductor structure, the second active structure can be divided into: the second PG active structure located in the second PG transistor, the second PD active structure located in the second PD transistor, the second PU active structure located in the second PU transistor, and the second sub-active structure located in the second sub-semiconductor structure.

[0083] In some possible implementations, where the first PG transistor, the first PU transistor, the first PD transistor, and the first sub-semiconductor structure are arranged in the above-described "2×2" configuration, the method may further include, before forming the shallow trench isolation structure, coating the first active structure with photoresist and etching a first portion of the first sub-active structure that is far from the first PU transistor using the photoresist as a mask; the length of the first portion is half the length of the first sub-active structure.

[0084] Understandably, the first sub-active structure can be divided into two parts: one part is the portion of the first sub-active structure that is far from the first PU transistor, and the other part is the portion of the first sub-active structure that is close to the first PU transistor. Through photolithography, the portion of the first sub-active structure that is far from the first PU transistor (i.e., the first part) is removed to facilitate subsequent cross-coupling processing.

[0085] In some possible implementations, after removing the first portion of the first sub-active structure that is distant from the first PU transistor, a first semiconductor structure can be formed based on the first active structure. Forming the first semiconductor structure based on the first active structure may include: forming a first source / drain structure of the first semiconductor structure based on the first active structure; depositing a first insulating material on the first source / drain structure and the first active structure to form a first interlayer dielectric layer; photolithographically opening a first gate region of the first semiconductor structure and depositing metal material in the first gate region to form a first gate metal structure and a second gate metal structure; the first source / drain structures being spaced apart on both sides of the first gate metal structure and the second gate metal structure; forming a first source / drain metal structure and a second source / drain metal structure based on the first source / drain structure; and depositing a second insulating material on the first gate metal structure, the second gate metal structure, the first source / drain metal structure, the second source / drain metal structure, and the first interlayer dielectric layer to form a first dielectric layer.

[0086] In some embodiments, before forming the first source / drain structure, the method may further include: photolithographically opening the first gate region of the first semiconductor structure, depositing semiconductor material in the first gate region to form a first dummy gate structure; and forming a first spacer on both sides of the first dummy gate structure.

[0087] In some embodiments, the first source / drain structure forming the first semiconductor structure based on the first active structure may include: removing a portion of the first active structure by etching to provide a source / drain groove for the first semiconductor structure; using a first spacer wall as a mask, selectively epitaxially growing a strain material such as silicon-germanium or silicon carbide in the source / drain groove of the first semiconductor structure to fill the source / drain groove of the first semiconductor structure; and then forming the first source / drain structure on the strain material by a heavy doping process.

[0088] It should be noted that, for ease of explanation, the first source / drain structure mentioned in the embodiments of this application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. Furthermore, the second source / drain structure, the first source / drain metal structure, the second source / drain metal structure, the source / drain groove, etc., are all similar to the first source / drain structure, where "source / drain" is an abbreviation for "source and / or drain".

[0089] In some embodiments, the deposition of a first insulating material on the first source / drain structure and the first active structure to form a first interlayer dielectric layer may include: depositing an insulating material (such as silicon dioxide (SiO2)) on the first active structure and the first source / drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer may cover the first active structure and the first source / drain structure.

[0090] In some embodiments, the above-mentioned photolithography opens the first gate region of the first semiconductor structure and deposits metal material in the first gate region to form a first gate metal structure and a second gate metal structure, which may include: removing the first dummy gate structure by etching to expose the first gate region, and depositing metal material in the first gate region to form the gate metal structure of the first semiconductor structure (i.e., the first gate metal structure and the second gate metal structure).

[0091] It should be noted that since the first gate metal structure and the second gate metal structure are formed separately, the first dummy gate structure can be etched in two steps. That is, the first dummy gate structure corresponding to the location of the first gate metal structure can be removed first by etching, exposing the gate region corresponding to the first gate metal structure. Metal material is then deposited in the gate region corresponding to the first gate metal structure to form the first gate metal structure. Then, the first dummy gate structure corresponding to the location of the second gate metal structure can be removed by etching, exposing the gate region corresponding to the second gate metal structure. Metal material is then deposited in the gate region corresponding to the second gate metal structure to form the second gate metal structure. The third and fourth gate metal structures are also formed separately, and their formation process is similar to that of the first and second gate metal structures described above. This application does not specifically limit this process.

[0092] In the embodiments of this application, the metal materials of the first gate metal structure and the second gate metal structure may include, but are not limited to: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), and titanium aluminum nitride (TiAlN). The materials of the first gate metal structure and the second gate metal structure may be selected according to the actual situation and are not limited to the metal materials listed above.

[0093] In some embodiments, after forming the gate metal structure of the first semiconductor structure (i.e., the first gate metal structure and the second gate metal structure), the above method may further include: depositing an anti-reflective material on the gate metal structure of the first semiconductor structure to form an anti-reflective layer; coating photoresist on the anti-reflective layer; and performing a gate cut-off process on the gate metal structure of the first semiconductor structure after the photoresist has been developed and a photolithographic pattern has been formed.

[0094] In some embodiments, forming a first source / drain metal structure and a second source / drain metal structure based on the first source / drain structure may include: etching a portion of the first interlayer dielectric layer above the first source / drain structure until the upper surface of the first source / drain structure is exposed, to form a first source / drain metal groove and a second source / drain metal groove. Metal material is deposited in the first source / drain metal groove and the second source / drain metal groove to form the first source / drain metal structure and the second source / drain metal structure.

[0095] In some possible implementations, after forming the first coupled metal structure on the first dielectric layer, the above method may further include: performing a post-processing step on the first interlayer dielectric layer to form a first metal interconnect layer; the first metal interconnect layer includes a first VDD, a first VSS, a first WL, and a first BL.

[0096] Understandably, by performing interconnect dielectric deposition, metal line formation, and lead-out pad formation on the first dielectric layer, a first metal interconnect layer of the first semiconductor structure can be formed. In some possible embodiments, when the second PG transistor, second PU transistor, second PD transistor, and second sub-semiconductor structure are arranged in the above-described "2×2" configuration, after forming a shallow trench isolation layer on the first semiconductor structure, the above method may further include: coating photoresist on the second active structure, and using the photoresist as a mask to etch a second portion of the second sub-active structure that is away from the second PU transistor; the length of the second portion is half the length of the second sub-active structure.

[0097] Understandably, the second sub-active structure can be divided into two parts: one part is the portion of the second sub-active structure that is far from the second PU transistor, and the other part is the portion of the second sub-active structure that is close to the second PU transistor. Through photolithography, the portion of the second sub-active structure that is far from the second PU transistor (i.e., the second part) is removed to facilitate subsequent cross-coupling processing.

[0098] In some possible implementations, after removing the second portion of the second sub-active structure that is away from the second PU transistor, a second semiconductor structure can be formed on the shallow trench isolation layer. The formation of the second semiconductor structure on the shallow trench isolation layer may include: forming a second source / drain structure of the second semiconductor structure based on the second active structure; depositing a first insulating material on the second source / drain structure and the second active structure to form a second interlayer dielectric layer; photolithographically opening the second gate region of the second semiconductor structure and depositing metal material in the second gate region to form a third gate metal structure and a fourth gate metal structure; the second source / drain structures being spaced apart on both sides of the third gate metal structure and the fourth gate metal structure; forming a third source / drain metal structure and a fourth source / drain metal structure based on the second source / drain structure; and depositing a second insulating material on the third gate metal structure, the fourth gate metal structure, the third source / drain metal structure, the fourth source / drain metal structure, and the second interlayer dielectric layer to form a second dielectric layer.

[0099] In some embodiments, before forming the second source / drain structure, the method may further include: photolithographically opening the second gate region of the second semiconductor structure, depositing semiconductor material in the second gate region to form a second pseudo-gate structure; and forming second gap walls on both sides of the second pseudo-gate structure.

[0100] In the embodiments of this application, the semiconductor materials forming the first pseudo-gate structure and the second pseudo-gate structure may include, but are not limited to, amorphous carbon and amorphous silicon, or other semiconductor materials. The embodiments of this application do not specifically limit the use of these materials.

[0101] In some embodiments, the second source / drain structure, which forms the second semiconductor structure based on the second active structure, may include: removing a portion of the second active structure by etching to provide a source / drain trench for the second semiconductor structure; using a second spacer wall as a mask, selectively epitaxially growing a strain material such as silicon-germanium or silicon carbide in the source / drain trench of the second semiconductor structure to fill the trench; and then forming the second source / drain structure on the strain material by a heavy doping process.

[0102] In some embodiments, the deposition of a first insulating material on the second source / drain structure and the second active structure to form a second interlayer dielectric layer may include: depositing an insulating material (such as silicon dioxide) on the second active structure and the second source / drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer may cover the second active structure and the second source / drain structure.

[0103] In some embodiments, the above-described photolithography opens the second gate region of the second semiconductor structure and deposits metal material in the second gate region to form a third gate metal structure and a fourth gate metal structure, which may include: removing the second dummy gate structure by etching to expose the second gate region, and depositing metal material in the second gate region to form the third gate metal structure and the fourth gate metal structure of the second semiconductor structure.

[0104] In some possible implementations, before forming the third gate metal structure and the fourth gate metal structure, the above method may further include: photolithographically processing the shallow trench isolation layer to form the second via and the third via; and depositing metal material in the second via and the third via to form the second coupling metal structure and the third coupling metal structure.

[0105] Understandably, by coating photoresist on the shallow trench isolation layer and then etching the shallow trench isolation layer using the photoresist as a mask after photoresist development, two through-holes (i.e., the second through-hole and the third through-hole) can be formed. Based on the second through-hole and the third through-hole, a second coupling metal structure and a third coupling metal structure can be formed.

[0106] In some embodiments, forming the third and fourth source / drain metal structures based on the second source / drain structure may include: etching a portion of the second interlayer dielectric layer above the second source / drain structure until the upper surface of the second source / drain structure is exposed to form the third and fourth source / drain metal recesses; and depositing metal material in the third and fourth source / drain metal recesses to form the third and fourth source / drain metal structures.

[0107] In some possible implementations, after forming the fourth coupling metal structure on the second dielectric layer, the above method may further include: performing a post-processing step on the second interlayer dielectric layer to form a second metal interconnect layer; the second metal interconnect layer includes a second VDD, a second VSS, a second WL, and a second BL.

[0108] Understandably, by performing processes such as inter-interconnect dielectric deposition, metal line formation, and lead-out pad formation on the second dielectric layer, a second metal interconnect layer of the second semiconductor structure can be formed.

[0109] The semiconductor structures provided in the embodiments of this application will be described below, taking the first semiconductor structure and the second semiconductor structure as fin field-effect transistors as examples. Figures 2A to 2C This is a schematic diagram of a first type of semiconductor structure in an embodiment of this application. Wherein, Figure 2A (a) in the diagram is the design layout of the device layer in the semiconductor structure. For ease of explanation, Figure 2A(a) shows the overall layout of the device layer of the semiconductor structure, the front layout of the device layer of the first semiconductor structure, and the back layout of the device layer of the second semiconductor structure, respectively. Figure 2A (b) in the diagram is a design layout of the metal interconnect layer in the semiconductor structure. For ease of explanation, Figure 2A (b) shows the overall layout of the metal interconnect layer of the semiconductor structure, the front layout of the metal interconnect layer for the first semiconductor structure, and the back layout of the metal interconnect layer for the second semiconductor structure, respectively. Figure 2B (a) in the diagram is a cross-sectional view of the semiconductor structure along the AA' direction in the design layout; Figure 2B (b) in the diagram is a cross-sectional view of the semiconductor structure along the BB' direction in the design layout; Figure 2B (c) in the diagram is a cross-sectional view of the semiconductor structure along the CC' direction in the design layout; Figure 2B In the diagram, (d) is a cross-sectional view of the semiconductor structure along the DD' direction in the design layout; Figure 2C (a) in the diagram is a cross-sectional view of the semiconductor structure along the EE' direction in the design layout; Figure 2C (b) in the diagram is a cross-sectional view of the semiconductor structure along the FF' direction in the design layout; Figure 2C (c) in the diagram is a cross-sectional view of the semiconductor structure along the GG' direction in the design layout.

[0110] See Figures 2A to 2C As shown, the semiconductor structure 10 includes a first semiconductor structure 11 and a second semiconductor structure 12. The active structures in the semiconductor structure 10 are multiple fin-shaped structures. Each fin-shaped structure is divided into upper and lower parts, which are respectively designated as the first active structure 111 and the second active structure 121. An intermediate dielectric layer 212 is disposed between the first active structure 111 and the second active structure 121, and the intermediate dielectric layer 212 is used to isolate the first active structure 111 and the second active structure 121.

[0111] See Figures 2A to 2C As shown, the first semiconductor structure 11 has a conventional arrangement of bipolar transistors. The first semiconductor structure 11 includes a first transistor corresponding to an n-type channel and a second transistor corresponding to a p-type channel (not shown in the figure). The first transistor includes a first gate metal structure 118n and a first source-drain metal structure, and the second transistor includes a second gate metal structure 118p and a second source-drain metal structure. Similarly, the third transistor in the second semiconductor structure 12 includes a third gate metal structure 128n and a third source-drain metal structure, and the fourth transistor includes a fourth gate metal structure 128p and a fourth source-drain metal structure.

[0112] See Figures 2A to 2CAs shown, the semiconductor structure 10 may further include: a first coupling metal structure 31; the first coupling metal structure 31 connects the second gate metal structure 118p and the second source / drain metal structure; a second coupling metal structure 32; the second coupling metal structure 32 is located between the first gate metal structure 118n and the fourth gate metal structure 128p, and the second coupling metal structure 32 connects the first gate metal structure 118n and the fourth gate metal structure 128p; a third coupling metal structure 33; the third coupling metal structure 33 is located between the second gate metal structure 118p and the third gate metal structure 128n, and the third coupling metal structure 33 connects the second gate metal structure 118p and the third gate metal structure 128n; and a fourth coupling metal structure 34; the fourth coupling metal structure 34 connects the fourth gate metal structure 128p and the fourth source / drain metal structure.

[0113] See Figure 2A As shown, semiconductor structure 10 is a six-transistor SRAM cell; wherein, the first semiconductor structure includes a first PD transistor, a first PG transistor, a first PU transistor, and a first sub-semiconductor structure; the first PG transistor and the first sub-semiconductor structure are arranged side by side in a first direction, the first PD transistor and the first PU transistor are arranged side by side in a first direction, the first PG transistor and the first PD transistor are arranged side by side in a second direction, and the first sub-semiconductor structure and the first PU transistor are arranged side by side in a second direction; the first direction is the length direction of the first gate metal structure, and the second direction is the direction perpendicular to the first direction; correspondingly, the second semiconductor structure 12 includes a second PD transistor, a second PG transistor, a second PU transistor, and a second sub-semiconductor structure; the second PG transistor and the second sub-semiconductor structure are arranged side by side in a first direction, the second PD transistor and the second PU transistor are arranged side by side in a first direction, the second PG transistor and the second PD transistor are arranged side by side in a second direction, and the second sub-semiconductor structure and the second PU transistor are arranged side by side in a second direction.

[0114] See Figures 2A to 2C As shown, the semiconductor structure 10 may further include: a first metal interconnect layer 117 in the first semiconductor structure 11; the first metal interconnect layer 117 is formed by a back-end process, and includes VDD, VSS, WL and BL'; a second metal interconnect layer 127 in the second semiconductor structure 12; the second metal interconnect layer 127 is formed by a back-end process, and includes VDD, VSS, WL and BL.

[0115] The following section, in conjunction with the above preparation method, discusses... Figures 2A to 2C The fabrication process of the semiconductor structure 10 shown will be explained. Figures 2A to 2C The semiconductor structure 10 shown can be used to... Figures 3A to 3M The process shown is used for preparation. Figures 3A to 3M This is a schematic diagram of a semiconductor structure fabrication process in an embodiment of this application.

[0116] In one example, taking the first semiconductor structure 11 and the second semiconductor structure 12 as fin field-effect transistors, with the first polarity being n-type and the second polarity being p-type, a fabrication process of the semiconductor structure 10 may include the following steps:

[0117] Step 1: Provide a substrate 21 (see...) Figure 3A ).

[0118] The substrate 21 is composed of a top substrate 211, an intermediate dielectric layer 212, and a bottom substrate 213 stacked sequentially. The top substrate 211 and the bottom substrate 213 are made of silicon, and the intermediate dielectric layer 212 is made of oxide.

[0119] It should be noted that, Figure 3A In diagram (a), the design layout is shown. In diagram (a) of 3A, the front-side fin structure-n-type channel and the front-side fin structure-p-type channel are symmetrically arranged in the design layout, and the front-side gate structure is also symmetrically arranged in the design layout. Accordingly, Figures 3B to 3M The fin structure and gate structure in the design layout are also symmetrically arranged.

[0120] Step 2: Patterning of the active structure on substrate 21, sequentially etching the top substrate 211, the intermediate dielectric layer 212, and the bottom substrate 213 to form a fin-like structure (see...). Figure 3B ).

[0121] The fin structure located above the intermediate dielectric layer 212 serves as the first active structure 111 in the first semiconductor structure 11, and the fin structure located below the intermediate dielectric layer 212 serves as the second active structure 121 in the second semiconductor structure 12. The height of the fin structure is greater than 100 nm.

[0122] It should be noted that in the fabrication process of semiconductor structure 10, each process has its corresponding design layout, and the cross-sectional views of semiconductor structure 10 in different directions correspond to the cross-sectional directions marked in the design layout. For example, in Figure 3B In the diagram, (a) is the design layout of semiconductor structure 10 in the second process step described above; (b) is a cross-sectional view of semiconductor structure 10 along the AA' direction of the design layout; (c) is a cross-sectional view of semiconductor structure 10 along the BB' direction of the design layout; and (d) is a cross-sectional view of semiconductor structure 10 along the CC' direction of the design layout. Since the first semiconductor structure 11 is a bipolar transistor, the fin structures correspondingly correspond to n-type and p-type channels, respectively. Figure 3B(a) shows the fin structure corresponding to the n-type channel and the fin structure corresponding to the p-type channel in the first semiconductor structure 11.

[0123] Step 3: Deposit anti-reflective material on the fin structure and substrate 21 to form an anti-reflective coating 22 (bottom anti-reflective coating, BARC); coat photoresist 23 on the anti-reflective layer and expose and develop the photoresist to form the front fin cut area in the photolithographic pattern (see...). Figure 3C (b) in the middle.

[0124] Step 4: Etch the anti-reflective layer 22 according to the fin cut area until the first active structure 111 under the photolithographic pattern is exposed. Then, selectively etch the first active structure 111 under the photolithographic pattern, stopping the etching at the intermediate dielectric layer 212. Next, remove the anti-reflective layer 22 and photoresist 23 (see...). Figure 3C (c) in the middle.

[0125] Step 5: Deposit insulating material on substrate 21 and active structure to form shallow trench isolation structure 24; remove the portion of the shallow trench isolation structure 24 that encloses the first active structure 111 by etching, exposing the first active structure 111; photolithography opens the first gate region of the first semiconductor structure 11, and deposit polysilicon in the first gate region to form the first dummy gate structure 119 (see...). Figure 3D ).

[0126] After the first pseudo-gate structure 119 is formed, insulating material is deposited on the sidewall of the first pseudo-gate structure 119 according to standard procedures to form a first gap wall (not shown in the figure).

[0127] Step 6: Form the first source / drain structure 112 on the first active structure 111 (see...) Figure 3E ).

[0128] Wherein, since the first semiconductor structure 11 is a bipolar transistor, the first source-drain structure 112 includes an n-type epitaxial layer (epi) and a p-type epi.

[0129] Step 7: Remove the first dummy gate structure 119 to expose the first gate region. Deposit metal material in the first gate region to form the gate metal structure of the first semiconductor structure 11. Deposit insulating material in the regions other than the first gate region to form the first interlayer dielectric layer 116. See also Figure 3F As shown, the gate metal structure of the first semiconductor structure 11 includes a first gate metal structure 118n corresponding to an n-type channel and a second gate metal structure 118p corresponding to a p-type channel (see [reference]). Figure 3F ).

[0130] After removing the first dummy gate structure 119 and before forming the gate metal structure of the first semiconductor structure 11, an insulating material (such as a high K material) can be deposited on the surface of the first active structure 111 to form a first gate dielectric layer (not shown in the figure) according to standard procedures.

[0131] Step 8: Photoresist is coated on the first gate metal structure 118n and the second gate metal structure 118p. After forming the photoresist pattern, gate cutting is performed on the first and second gate metal structures in the front gate cutting area to form a first gate cutting groove (not shown in the figure). After removing the photoresist, an insulating material (such as silicon nitride (SiN)) is filled into the first gate cutting groove to form a groove. Figure 3G The first gate cutoff structure 114 is shown.

[0132] Step 9: Deposit dielectric material on the first gate metal structure 118n, the second gate metal structure 118p, and the first interlayer dielectric layer 116 to form a first dielectric layer 115, which covers the first gate metal structure 118n, the second gate metal structure 118p, and the first interlayer dielectric layer 116; etch a portion of the first dielectric layer 115 and the first interlayer dielectric layer 116 to form a first source / drain metal trench and a second source / drain metal trench; fill the first and second source / drain metal trenches with metallic material to form the first / second source / drain metal structure 113 (see...). Figure 3H ).

[0133] It should be noted that the first / second source / drain metal structure can refer to: a first source / drain metal structure and / or a second source / drain metal structure.

[0134] Step 10: An anti-reflective layer 22 is formed on the first dielectric layer 115. Photoresist 23 is coated on the anti-reflective layer 22. After forming the photolithography pattern, the anti-reflective layer is etched according to the first via etching region until the second source / drain metal structure and the first dielectric layer 115 under the first via etching region are exposed. Then, the first dielectric layer 115 is selectively etched to form a via. Metal material is filled into the via to form the first coupling metal structure 31 (see...). Figure 3I ).

[0135] In this process, after etching the anti-reflection layer according to the photolithography pattern and exposing the second source / drain metal structure and the first dielectric layer 115 under the first via etching area, the etching solvent used in the etching process of the first dielectric layer 115 will not etch the second source / drain metal structure. The second source / drain metal structure is equivalent to a self-aligned layer in the etching process, which can make the sidewall of the finally formed first coupling metal structure 31 fit tightly with the sidewall of the second source / drain metal structure.

[0136] Step 11: Perform subsequent processes on the first dielectric layer 115 to form the first metal interconnect layer 117 (see...) Figure 3J ).

[0137] See Figure 3J As shown, the first metal interconnect layer 117 includes VSS and VDD, and VSS and VDD are respectively connected to the first / second source / drain metal structure 113 via metal lines. The first metal interconnect layer 117 also includes WL and BL', WL is connected to the first gate metal structure 118n via a metal line, and BL' is connected to the first / second source / drain metal structure 113 via a metal line.

[0138] It should be noted that, for ease of distinction, BL' represents the bit line in the first metal interconnect layer, and BL represents the bit line in the second metal interconnect layer.

[0139] Step 12: Deposit an insulating layer 14 on the first metal interconnect layer 117, and bond the carrier wafer 15 to the insulating layer 14; flip the first semiconductor structure 11 after bonding the carrier wafer 15 so that the substrate 21 faces upward; remove the substrate 21 and the shallow trench isolation structure 24 surrounding the second active structure 121 to expose the second active structure 121 and form a shallow trench isolation layer 13. Next, etch the second active structure 121 according to the back fin cut area in the design layout (see...). Figure 3K (b)); then, following standard procedures, the second pseudo-gate structure, the second spacer wall, and the second source / drain structure 122 are formed (see steps five and six for specific processes). Next, the second pseudo-gate structure is removed to form the second gate dielectric layer (not shown in the figure).

[0140] Step 13: An anti-reflective layer 22 is formed on the shallow trench isolation layer 13, and photoresist 23 is coated on the anti-reflective layer 22 to form a photolithographic pattern (not shown in the figure). The anti-reflective layer 22 and the shallow trench isolation layer 13 are etched according to the second via etching region and the third via etching region (i.e., the second / third via etching region in the design layout) to form two through-layer vias (i.e., the first through-layer via 41 and the second through-layer via 42). The first through-layer via 41 is connected to the first gate metal structure 118n, and the second through-layer via 42 is connected to the second gate metal structure 118p (see [reference]). Figure 3K (c) in the middle.

[0141] Step 14: Following standard procedures, deposit metal material in the second gate region, the first through-hole 41, and the second through-hole 42 to form a second coupling metal structure 32, a third coupling metal structure 33, a third gate metal structure 128n, and a fourth gate metal structure 128p; and form a second interlayer dielectric layer 126 and a second gate cutoff structure 124. The third gate metal structure 128n corresponds to an n-type channel, the fourth gate metal structure 128p corresponds to a p-type channel, the second coupling metal structure 32 is connected to the first gate metal structure 118n and the fourth gate metal structure 128p respectively, and the third coupling metal structure 33 is connected to the second gate metal structure 118p and the third gate metal structure 128n respectively (see [reference]). Figure 3L ).

[0142] Step 15: Form the second dielectric layer 125 and the third / fourth source / drain metal structure 123 (see Step 9 for specific process details); Next, form an anti-reflection layer 22 on the second dielectric layer 125, coat photoresist 23 on the anti-reflection layer 22, after forming the photoresist pattern, etch the anti-reflection layer 22 according to the fourth via etching region until the fourth source / drain metal structure and the second dielectric layer 125 under the fourth via etching region are exposed, then selectively etch the second dielectric layer 125 to form a via; fill the via with metal material to form the fourth coupling metal structure 34 (see Step 9 for details). Figure 3M ).

[0143] In this process, after etching the anti-reflection layer according to the photolithography pattern and exposing the fourth source / drain metal structure and the second dielectric layer 125 under the fourth via etching area, the etching solvent used in the etching process of the second dielectric layer 125 will not etch the fourth source / drain metal structure. The fourth source / drain metal structure is equivalent to a self-aligned layer in the etching process, which can make the sidewall of the finally formed fourth coupling metal structure 34 fit tightly with the sidewall of the fourth source / drain metal structure.

[0144] Step sixteen: Following standard procedures, form the second metal interconnect layer 127 (see step eleven for specific process details) (see [reference needed] for the semiconductor structure formed in the assembly). Figure 2B and Figure 2C ).

[0145] See Figure 2B and Figure 2C As shown, the second metal interconnect layer 127 includes VSS and VDD, and VSS and VDD are respectively connected to the third / fourth source / drain metal structure 123 via metal lines. The second metal interconnect layer 127 also includes WL and BL, WL is connected to the third gate metal structure 128n via metal lines, and BL is connected to the third / fourth source / drain metal structure 123 via metal lines.

[0146] Thus, the semiconductor structure 10, in which the first semiconductor structure 11 and the second semiconductor structure 12 are fin field-effect transistors, has been fabricated.

[0147] In this embodiment, the first coupling metal structure in the semiconductor structure is connected to the second gate metal structure and the second source / drain metal structure, the second coupling metal structure is connected to the first gate metal structure and the fourth gate metal structure, the third coupling metal structure is connected to the second gate metal structure and the third gate metal structure, and the fourth coupling metal structure is connected to the fourth gate metal structure and the fourth source / drain metal structure. In this way, cross-coupling between the first semiconductor structure and the second semiconductor structure can be achieved. Based on this, the design and layout of the above cross-coupling further reduces the size of the semiconductor structure and increases the integration density.

[0148] Furthermore, the semiconductor structure is a six-transistor SRAM cell, and the self-aligned first semiconductor structure and the second semiconductor structure together form a flip-chip stacked transistor (i.e., semiconductor structure). The combination of the flip-chip stacked transistor and the six-transistor SRAM cell can reduce the spacing between adjacent devices, thereby significantly improving the integration density.

[0149] Furthermore, wiring is simultaneously performed in the first metal interconnect layer of the first semiconductor structure and the second metal interconnect layer of the second semiconductor structure, allowing power lines (VDD, VSS) and signal lines (WL, BL) to achieve a wider area, thereby reducing parasitics.

[0150] Furthermore, the semiconductor provided in this application embodiment can be detected using detection and analysis instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, the semiconductor structure provided in this application embodiment can be detected by TEM slicing to examine the front fin-cut region, the back fin-cut region, the first coupling metal structure, the second coupling metal structure, the third coupling metal structure, the fourth coupling metal structure, the first metal interconnect layer, and the second interconnect layer.

[0151] This application provides a memory, including a semiconductor structure as described in the above embodiments. Specific limitations of the semiconductor structure can be found above. Figure 2A-2C The semiconductor structure shown will not be described in detail here.

[0152] This application provides an electronic device, including a circuit board and a memory as described in the above embodiments, wherein the memory is disposed on the circuit board. The memory includes the semiconductor structure described above. Specific limitations of the semiconductor structure can be found above. Figure 2A-2C The semiconductor structure shown will not be described in detail here.

[0153] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0154] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A first semiconductor structure is formed on a substrate; the first semiconductor structure is a bipolar transistor, the first semiconductor structure includes a first transistor having a first polarity and a second transistor having a second polarity, the first transistor includes a first gate metal structure and a first source-drain metal structure, the second transistor includes a second gate metal structure and a second source-drain metal structure, and a first dielectric layer is formed on the first gate metal structure, the first source-drain metal structure, the second gate metal structure and the second source-drain metal structure. A first coupling metal structure is formed on the first dielectric layer, and the first coupling metal structure connects the second gate metal structure and the second source / drain metal structure. The wafer is then poured and the substrate is removed. A shallow trench isolation layer is formed on the first semiconductor structure; A second semiconductor structure is formed on the shallow trench isolation layer; the first semiconductor structure and the second semiconductor structure are self-aligned in a direction perpendicular to the active region; the second semiconductor structure is a bipolar transistor, and includes a third transistor having the first polarity and a fourth transistor having the second polarity; the third transistor includes a third gate metal structure and a third source / drain metal structure, and the fourth transistor includes a fourth gate metal structure and a fourth source / drain metal structure; a second dielectric layer is formed on the third gate metal structure, the third source / drain metal structure, the fourth gate metal structure, and the fourth source / drain metal structure; a second coupling metal structure and a third coupling metal structure are formed in the shallow trench isolation layer; the second coupling metal structure connects the first gate metal structure and the fourth gate metal structure, and the third coupling metal structure connects the second gate metal structure and the third gate metal structure; wherein, the third gate metal structure corresponds to the second gate metal structure, and the fourth gate metal structure corresponds to the first gate metal structure; A fourth coupling metal structure is formed on the second dielectric layer, the fourth coupling metal structure connecting the fourth gate metal structure and the fourth source / drain metal.

2. The method according to claim 1, characterized in that, The formation of the first semiconductor structure on the substrate includes: An active structure is formed by etching a substrate; the active structure includes a first active structure for fabricating the first semiconductor structure, a second active structure for fabricating the second semiconductor structure, and an intermediate dielectric layer located between the first active structure and the second active structure; An insulating material is deposited on the active structure and the substrate to form a shallow trench isolation structure; the shallow trench isolation structure encloses the active structure. Remove a portion of the shallow trench isolation structure that encloses the first active structure to expose the first active structure; The first semiconductor structure is formed based on the first active structure.

3. The method according to claim 2, characterized in that, The process of forming the first semiconductor structure based on the first active structure includes: Based on the first active structure, a first source-drain structure of a first semiconductor structure is formed; A first insulating material is deposited on the first source / drain structure and the first active structure to form a first interlayer dielectric layer; Photolithography is used to open the first gate region of the first semiconductor structure, and metal material is deposited in the first gate region to form the first gate metal structure and the second gate metal structure; the first source and drain structures are spaced apart on both sides of the first gate metal structure and the second gate metal structure; Based on the first source / drain structure, a first source / drain metal structure and a second source / drain metal structure are formed; A second insulating material is deposited on the first gate metal structure, the second gate metal structure, the first source / drain metal structure, the second source / drain metal structure, and the first interlayer dielectric layer to form the first dielectric layer.

4. The method according to claim 3, characterized in that, The formation of the first coupled metal structure on the first dielectric layer includes: A portion of the first dielectric layer is etched to form a first via; the first via connects the second gate metal structure and the second source / drain metal structure. Metallic material is deposited in the first through-hole to form the first coupled metallic structure.

5. The method according to claim 3, characterized in that, After forming a first coupled metal structure on the first dielectric layer, the method further includes: A back-end process is performed on the first interlayer dielectric layer to form a first metal interconnect layer; the first metal interconnect layer includes a first drain metal line VDD, a first source metal line VSS, a first word line WL, and a first bit line BL.

6. The method according to claim 2, characterized in that, The step of forming a shallow trench isolation layer on the first semiconductor structure includes: A portion of the shallow trench isolation structure enclosing the second active structure is removed to expose the second active structure and form the shallow trench isolation layer; the shallow trench isolation layer surrounds the intermediate dielectric layer.

7. The method according to claim 2, characterized in that, The formation of the second semiconductor structure on the shallow trench isolation layer includes: Based on the second active structure, a second source / drain structure of the second semiconductor structure is formed; A first insulating material is deposited on the second source / drain structure and the second active structure to form a second interlayer dielectric layer; Photolithography is used to open the second gate region of the second semiconductor structure, and metal material is deposited in the second gate region to form the third gate metal structure and the fourth gate metal structure; the second source-drain structure is spaced apart on both sides of the third gate metal structure and the fourth gate metal structure; Based on the second source-drain structure, the third source-drain metal structure and the fourth source-drain metal structure are formed; A second insulating material is deposited on the third gate metal structure, the fourth gate metal structure, the third source / drain metal structure, the fourth source / drain metal structure, and the second interlayer dielectric layer to form the second dielectric layer.

8. The method according to claim 7, characterized in that, Before forming the third gate metal structure and the fourth gate metal structure, the method further includes: The shallow trench isolation layer is subjected to photolithography to form the second and third through holes; Metallic material is deposited in the second and third through holes to form the second and third coupled metal structures.

9. The method according to claim 7, characterized in that, The formation of the fourth coupled metal structure on the second dielectric layer includes: A portion of the second dielectric layer is etched to form a fourth via; the fourth via connects the fourth gate metal structure and the fourth source / drain metal structure. Metallic material is deposited in the fourth through hole to form the fourth coupled metallic structure.

10. The method according to claim 9, characterized in that, After forming a fourth coupled metal structure on the second dielectric layer, the method further includes: A subsequent process is performed on the second interlayer dielectric layer to form a second metal interconnect layer; the second metal interconnect layer includes a second VDD, a second VSS, a second WL, and a second BL.

11. The method according to claim 2, characterized in that, The semiconductor structure is a six-transistor static random access memory (SRAM) cell. The first semiconductor structure includes a first pull-down transistor, a first transmission gate transistor, a first pull-up transistor, and a first sub-semiconductor structure. The first transmission gate transistor and the first sub-semiconductor structure are arranged side-by-side in a first direction, the first pull-down transistor and the first pull-up transistor are arranged side-by-side in the first direction, the first transmission gate transistor and the first pull-down transistor are arranged side-by-side in a second direction, and the first sub-semiconductor structure and the first pull-up transistor are arranged side-by-side in the second direction. The first direction is the length direction of the first gate metal structure, and the second direction is a direction perpendicular to the first direction. The second semiconductor structure includes a second pull-down transistor, a second transmission gate transistor, a second pull-up transistor, and a second sub-semiconductor structure; the second transmission gate transistor and the second sub-semiconductor structure are arranged side by side in the first direction, the second pull-down transistor and the second pull-up transistor are arranged side by side in the first direction, the second transmission gate transistor and the second pull-down transistor are arranged side by side in the second direction, and the second sub-semiconductor structure and the second pull-up transistor are arranged side by side in the second direction.

12. The method according to claim 11, characterized in that, The first active structure includes a first sub-active structure located in the first sub-semiconductor structure; Before depositing insulating material on the active structure and the substrate to form a shallow trench isolation structure, the method further includes: Photoresist is coated on the first active structure, and the first part of the first sub-active structure away from the first pull-up transistor is etched using the photoresist as a mask. The length of the first portion is half the length of the first sub-semiconductor structure.

13. The method according to claim 11, characterized in that, The second active structure includes a second sub-active structure located in the second sub-semiconductor structure; After forming a shallow trench isolation layer on the first semiconductor structure, the method further includes: Photoresist is coated on the second active structure, and the second portion of the second sub-active structure away from the second pull-up transistor is etched using the photoresist as a mask; The length of the second part is half the length of the second sub-semiconductor structure.

14. A semiconductor structure, characterized in that, The semiconductor structure includes: A first semiconductor structure; the first semiconductor structure is a bipolar transistor, the first semiconductor structure includes a first transistor having a first polarity and a second transistor having a second polarity, the first transistor includes a first gate metal structure and a first source-drain metal structure, and the second transistor includes a second gate metal structure and a second source-drain metal structure; A second semiconductor structure; the second semiconductor structure is a bipolar transistor, the second semiconductor structure includes a third transistor having the first polarity and a fourth transistor having the second polarity, the third transistor includes a third gate metal structure and a third source-drain metal structure, the fourth transistor includes a fourth gate metal structure and a fourth source-drain metal structure; the first semiconductor structure and the second semiconductor structure are self-aligned in a direction perpendicular to the active region; A first coupling metal structure; the first coupling metal structure connects the second gate metal structure and the second source / drain metal structure; A second coupling metal structure; the second coupling metal structure is located between the first gate metal structure and the fourth gate metal structure, and the second coupling metal structure connects the first gate metal structure and the fourth gate metal structure; A third coupling metal structure; the third coupling metal structure is located between the second gate metal structure and the third gate metal structure, and the third coupling metal structure connects the second gate metal structure and the third gate metal structure; A fourth coupling metal structure; the fourth coupling metal structure connects the fourth gate metal structure and the fourth source / drain metal structure.

15. The semiconductor structure according to claim 14, characterized in that, The semiconductor structure is a six-transistor static random access memory (SRAM) cell. The first semiconductor structure includes a first pull-down transistor, a first transmission gate transistor, a first pull-up transistor, and a first sub-semiconductor structure. The first transmission gate transistor and the first sub-semiconductor structure are arranged side-by-side in a first direction, the first pull-down transistor and the first pull-up transistor are arranged side-by-side in the first direction, the first transmission gate transistor and the first pull-down transistor are arranged side-by-side in a second direction, and the first sub-semiconductor structure and the first pull-up transistor are arranged side-by-side in the second direction. The first direction is the length direction of the first gate metal structure, and the second direction is a direction perpendicular to the first direction. The second semiconductor structure includes a second pull-down transistor and a second transmission gate transistor, a second pull-up transistor and a second sub-semiconductor structure; the second transmission gate transistor and the second sub-semiconductor structure are arranged side by side in the first direction, the second pull-down transistor and the second pull-up transistor are arranged side by side in the first direction, the second transmission gate transistor and the second pull-down transistor are arranged side by side in the second direction, and the second sub-semiconductor structure and the second pull-up transistor are arranged side by side in the second direction.

16. The semiconductor structure according to claim 14, characterized in that, The semiconductor structure also includes: The first metal interconnect layer in the first semiconductor structure; the first metal interconnect layer is formed by back-end processing, and the first metal interconnect layer includes a first drain metal line VDD, a first source metal line VSS, a first word line WL and a first bit line BL; The second metal interconnect layer in the second semiconductor structure; the second metal interconnect layer is formed by back-end processing, and the second metal interconnect layer includes a second VDD, a second VSS, a second WL and a second BL.

17. A memory, characterized in that, include: The semiconductor structure as described in claim 14.

18. An electronic device, characterized in that, include: The circuit board and the memory as described in claim 17, wherein the memory is disposed on the circuit board.

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