Memory fault detection method and device, electronic equipment and storage medium

Abstract

Embodiments of the present disclosure provide a memory fault detection method and device, electronic equipment and a storage medium, and relate to the technical field of computers. The method comprises: switching the software and hardware system between the STR state and the STR test wake-up state through UEFI, wherein the operating system is kept in hibernation in the STR test wake-up state; checking the memory data during the last STR state through the test program in the UEFI in the STR test wake-up state; and determining that the memory has a circuit fault in the case that the memory data checking fails. The embodiments of the present disclosure can reduce the difficulty of solving the STR fault for the memory, and improve the efficiency of STR debugging.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a memory failure detection method, device, electronic device, and storage medium. Background Art

[0002] STR (Suspend to RAM) is a low-latency sleep state designed to allow the hardware and software systems to enter a state that allows for rapid wakeup when idle. In STR, the CPU (Central Processing Unit) and peripherals, except for system memory, are powered off, resulting in very low power consumption. When a standby command is issued, the system saves all context information to memory. After entering STR, memory enters a self-refresh state. Upon a wakeup event, data is read from memory and quickly restored to its pre-STR state. In STR, only memory—virtually the only component—receives power. Because the operating system, all applications, and open documents are stored in memory, users can restore their work to the exact state they left it in. That is, the memory contents upon returning from STR are identical to those at the time of entry. Therefore, it is crucial to ensure that valid memory data is not lost during the STR sleep and wakeup process; any loss of memory data will result in a wakeup failure.

[0003] Currently, during STR debugging, memory verification is added after going to sleep and waking up to compare whether the memory data is consistent. If there is inconsistency, it is considered that there is a fault in STR debugging.

[0004] However, existing STR debugging methods cannot accurately locate the type of memory faults, which increases the difficulty of resolving memory STR faults and reduces the efficiency of STR debugging. Summary of the Invention

[0005] In view of the above problems, the embodiments of the present disclosure are proposed to provide a memory fault detection method that overcomes the above problems or at least partially solves the above problems, thereby reducing the difficulty of solving memory STR faults and improving the efficiency of STR debugging.

[0006] In a first aspect, the present disclosure provides a method for detecting a memory failure, the method comprising:

[0007] Switching the hardware and software systems between the STR state and the STR test wake-up state through UEFI, wherein in the STR test wake-up state, UEFI is started and the operating system remains dormant;

[0008] In the STR test wake-up state, the memory data during the last STR state is verified through the test program in UEFI;

[0009] When the memory data verification fails, it is determined that a circuit fault exists in the memory.

[0010] In a second aspect, the present disclosure provides a memory failure detection device, the device comprising:

[0011] A switching module, configured to switch the software and hardware systems between an STR state and an STR test wake-up state through UEFI, wherein in the STR test wake-up state, UEFI is started and the operating system remains dormant;

[0012] The verification module is used to verify the memory data during the last STR state through the test program in UEFI in the STR test wake-up state;

[0013] The fault determination module is used to determine that a circuit fault exists in the memory when the memory data verification fails.

[0014] In a third aspect, the present disclosure provides an electronic device, comprising: a processor;

[0015] UEFI firmware has a computer program stored thereon, and when the computer program is executed by the processor, the processor implements any of the aforementioned memory failure detection methods.

[0016] In a fourth aspect, the present disclosure provides a computer program product comprising instructions, which, when executed by a processor in an electronic device, causes the electronic device to execute any one of the aforementioned memory failure detection methods.

[0017] In a fifth aspect, the present disclosure provides a readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to execute the above-mentioned memory failure detection method.

[0018] The present disclosure includes the following advantages:

[0019] The STR test program and the wake-up program can be set in the UEFI. In the STR test wake-up state, the CPU and the UEFI are started, but the operating system is not woken up but kept in hibernation, so the kernel and the operating system are not entered, peripherals are not involved, and only the memory is involved. The CPU executes the test program in the UEFI to detect whether the memory data is consistent before and after the STR. If the data is inconsistent, it can be determined that the problem occurs in the memory circuit and the memory self-refresh circuit, and then the memory storage circuit and the self-refresh circuit are troubleshooted, so the method is more simple and convenient. Therefore, through the STR fault detection method of the memory provided in the present disclosure, the difficulty of solving the STR fault of the memory can be reduced, the efficiency of solving the STR fault is improved, and then the efficiency of STR debugging is improved. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A step flowchart of an embodiment of a memory fault detection method of the present disclosure is shown.

[0021] Figure 2 A step flowchart of another embodiment of a memory fault detection method of the present disclosure is shown.

[0022] Figure 3 An allocation diagram of a CPU address space of the present disclosure is shown.

[0023] Figure 4 A structure block diagram of an embodiment of a memory fault detection device of the present disclosure is shown.

[0024] Figure 5 A flowchart of an embodiment of a memory fault detection method of the present disclosure is shown.

[0025] Figure 6 A structure diagram of an electronic device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the present disclosure will be further described in detail below with reference to the drawings and specific embodiments.

[0027] The inventors discovered that existing STR debugging methods are unable to accurately pinpoint the type of memory fault, increasing the difficulty of resolving memory STR faults and reducing the efficiency of STR debugging. This is primarily due to the fact that after entering the STR state, the memory enters a self-refresh state. The memory refresh circuit periodically refreshes the memory data to prevent data loss during the STR period, making it impossible to accurately restore the memory to its pre-STR state. In existing STR debugging methods, the test program is stored in memory, and the operating system performs the STR test process to verify whether the memory data has changed. During the STR state, the operating system is put into hibernation; during the STR test state, the operating system is awakened. This process involves sleeping and waking up the operating system, kernel, and external devices, requiring extensive hardware and software coordination. Data loss during STR can be caused by memory circuit design failures, such as refresh circuit errors, refresh failures, or excessively long refresh cycles; or by circuit failures or interference within the memory cells, preventing data from being retained and lost. The operating system can also introduce changes to memory data before and after the STR test. Therefore, if an STR test within the operating system reveals changes in memory data before and after the STR period, it is impossible to determine whether the changes originated from the memory circuitry itself or the operating system.

[0028] In response to the above technical problems, the embodiments of the present disclosure propose a memory detection method that can accurately identify faults in memory circuits and memory self-refresh circuits. This is achieved by shielding the possible impact of the operating system in the detection of memory circuit faults. As an implementation method, the STR test program and the wake-up program can be set in the UEFI. In the STR test wake-up state, the CPU and UEFI are started, but the operating system is not woken up but kept in sleep mode. The CPU executes the test program in the UEFI to detect whether the memory data is consistent before and after STR. If inconsistent, it can be determined that the problem occurs in the memory circuit and the memory self-refresh circuit, and then the storage circuit and self-refresh circuit of the memory are troubleshooted.

[0029] Figure 1 FIG2 shows a flowchart of an exemplary memory failure detection method embodiment of the present disclosure. Figure 1 The memory fault detection method may specifically include the following steps:

[0030] Step 101: Switch the software and hardware systems between the STR state and the STR test wake-up state through UEFI, wherein in the STR test wake-up state, UEFI is started and the operating system remains dormant.

[0031] The hardware and software system refers to the sum of the software and hardware of an electronic device. UEFI (Unified Extensible Firmware Interface) refers to the Unified Extensible Firmware Interface.

[0032] The STR test wake-up state means that UEFI is started and the operating system remains dormant. This STR test does not involve the kernel, operating system, or peripherals. In other words, this STR test does not involve kernel, peripheral, or operating system processes and only involves memory. The impact of the kernel, peripherals, and operating system is shielded.

[0033] The STR state means starting the CPU and UEFI, and also waking up the operating system. This includes sleeping and waking up the operating system, kernel, and external devices. The main difference between the STR state and the STR test wake-up state is that the former requires waking up the operating system, while the latter does not.

[0034] Step 102: In the STR test wake-up state, the memory data during the last STR state is verified through the test program in the UEFI.

[0035] The test program in UEFI refers to a correct test program, which means that when the test program in UEFI is run on a large amount of memory, UEFI startup can be successfully achieved and the operating system remains in a dormant state.

[0036] The memory data during the last STR state here refers to the most recent STR state of the electronic device before the test. During the last STR state, the CPU and UEFI need to be started, and the operating system needs to be woken up, which includes the sleep and wake-up of the operating system, kernel, and external devices.

[0037] In the STR test wake-up state, the memory data during the last STR state is verified through the test program in UEFI. Since the kernel and operating system will not be entered in this STR test wake-up state, and peripherals are not involved, new data will not be saved to the memory to be tested in this STR test wake-up state. Therefore, in this STR test wake-up state, the memory data during the last STR state is the memory data of the memory to be tested. If the memory data has not changed, the memory data verification has passed. If the memory data of the memory to be tested is different before and after the STR test wake-up state, the memory data verification has failed.

[0038] For memory, failures during the STR test wake-up state are categorized as test program failures and memory circuit failures. The test program in UEFI refers to the correct test program instructions, and there are no failures in the UEFI test program. Under UEFI firmware, the UEFI test program verifies the memory data during the last STR state. This verification shields the influence of the kernel, peripherals, and operating system, and simply verifies whether there is a circuit failure in the memory. In this case, if there is no circuit failure in the memory, the memory data verification during the last STR state can be guaranteed to pass. If there is a circuit failure in the memory, the memory data verification during the last STR state will fail.

[0039] Step 103: If the memory data verification fails, it is determined that a circuit fault exists in the memory.

[0040] The memory has a circuit fault, and the memory data verification during the last STR state fails. Therefore, if the memory data verification during the last STR state fails, it is determined that the memory has a circuit fault, and whether the memory has a circuit fault is conveniently and quickly tested.

[0041] For example, if the UEFI test program can successfully boot the UEFI memory on a large number of computers or motherboards while the operating system remains in a dormant state, the UEFI test program is considered correct. For a new motherboard or computer, such as a newly manufactured motherboard or computer, if the UEFI test program is correct, the UEFI test program verifies the memory data from the last STR state during the STR test wake-up state. During the STR test wake-up state, the operating system remains dormant, shielding the kernel, peripherals, and operating system from any influence. The test simply verifies whether the memory has a circuit fault. In this case, if the memory of the newly manufactured motherboard or computer has no circuit fault, the memory data verification is guaranteed to pass. If the memory of the newly manufactured motherboard or computer has a circuit fault, the memory data verification will fail. Therefore, for a newly manufactured motherboard or computer, no operating system support is required, requiring only the motherboard, memory, and power supply to quickly and easily detect whether the memory has a circuit fault. It should be noted that to further improve the stability of the STR function of the memory of the newly manufactured motherboard or computer, the memory fault test can be performed multiple times. For example, the memory fault test can be performed 1000 times on the memory of a newly manufactured motherboard or computer. For the same batch of motherboards or computer memories, a certain number of memories may be randomly selected, and each memory may be subjected to multiple memory fault tests.

[0042] Optionally, the method can further include: in the case that the memory data of the memory passes the verification in the foregoing step 102, determining that the memory does not have a circuit fault. The influence of the kernel, the peripheral device and the operating system is shielded, and only the memory is simply verified for the circuit fault. In the foregoing case, the memory does not have a circuit fault, and it is ensured that the memory data of the memory passes the verification. The memory has a circuit fault, and the memory data of the memory does not pass the verification. Therefore, after the influence of the kernel, the peripheral device and the operating system is shielded, the memory whether has a circuit fault can be conveniently and quickly detected.

[0043] Optionally, the memory has a circuit fault, which can basically indicate that the storage circuit of the memory and the self-refreshing circuit of the memory have faults. Therefore, after the foregoing step 103, the method can further include: troubleshooting the storage circuit of the memory and the self-refreshing circuit of the memory, for example, troubleshooting the power-on timing of the memory, and then solving the circuit fault of the memory as soon as possible in a targeted manner.

[0044] Here, a detection method of a memory fault is further explained in an embodiment, which can include the following processes.

[0045] First, the system is switched between the STR state and the STR test wake-up state by UEFI, wherein in the STR test wake-up state, the CPU and the UEFI are started and the operating system is kept in hibernation. The test program, the hibernation program and the wake-up program are stored in the UEFI, and the above processes are implemented by the programs in the UEFI. In the STR test wake-up state, the memory data during the last STR state is verified by the test program in the UEFI, and it is determined whether the memory data in the STR test wake-up state is consistent with the memory data before the last time entering the STR state. Since the influence of the operating system is excluded, in the case that the memory data of the memory does not pass the verification, it can be determined that the memory has a circuit fault in the STR, for example, a circuit design defect causes part of the memory cells to be invalid due to interference, or the memory refreshing circuit is invalid.

[0046] In the embodiment, the system sets the register of ACPI (Advanced Configuration and Power Management Interface) according to the hibernation program and the wake-up program in the UEFI, so that the system enters the STR state or enters the STR test wake-up state from the STR state, and before entering the STR state or the STR test wake-up state, the memory is set to enter the self-refreshing by the UEFI.

[0047] Figure 2 A step flowchart of another embodiment of the detection method of the memory fault of the present disclosure is shown. Referring to Figure 2 The detection method of the memory fault can specifically include the following steps:

[0048] Step 201: Determine the target memory space to be verified in the memory.

[0049] In the related art, when performing STR testing under the operating system, after the operating system starts, the UEFI firmware will basically not work, and will release at least part of the memory space it occupies. The operating system may store data in this released part of the memory space. Therefore, when performing STR testing under the operating system, the memory space to be tested needs to include at least part of the memory space occupied by the UEFI firmware. However, the memory data during the last STR state is verified by the test program in UEFI. Since the operating system will not start, the UEFI firmware will not release at least part of the memory space it occupies. Therefore, this part of the memory space that has not been released does not need to be verified and is not the target memory space. It should be noted that compared with entering STR under the operating system, the target memory space to be tested is reduced by verifying the memory data during the last STR state through the test program in UEFI, so the verification speed is faster. At the same time, although the target memory space that needs to be tested for memory fault detection under UEFI firmware is smaller, the fault will basically occur randomly in each memory space, and the probability of a fault occurring only in an unverified memory space is basically zero. Therefore, by using the test program in UEFI to verify the memory data during the last STR state, the target memory space that needs to be tested is smaller, but it still has basically the same reliability as the STR test under the operating system.

[0050] Figure 3 A schematic diagram of the allocation of a CPU address space disclosed in the present invention is shown. Figure 3As shown in the figure, the CPU address space from 0x0 to 0x280000000 is divided into 6 parts, numbered 1 to 6. Among them, the address space corresponding to number 1 is from 0x0 to 0x00100000, the address space corresponding to number 2 is from 0x00100000 to 0xf000000, the address space corresponding to number 3 is from 0xf000000 to 0x10000000, the address space corresponding to number 4 is from 0x10000000 to 0x90000000, the address space corresponding to number 5 is from 0x90000000 to 0x100000000, and the address space corresponding to number 6 is from 0x100000000 to 0x2800000000. The address space numbered 4 is non-memory space and is mainly used as register space. Regardless of whether STR is entered under the operating system or the test program in UEFI enters the STR test wake-up state, the UEFI firmware startup will use memory spaces numbered 1 and 3. As mentioned earlier, when STR is entered under the operating system and the operating system is started, the UEFI firmware will release the memory space numbered 5. Therefore, in this example, when performing the STR test under the operating system, the memory space to be tested needs to include memory spaces numbered 2, 5, and 6. In this example, when the test program in UEFI enters the STR test wake-up state, the UEFI firmware will not release the memory space numbered 5. The target memory spaces to be tested are the memory spaces numbered 2 and 6. Compared with entering STR under the operating system, when the test program in UEFI enters the STR test wake-up state, the target memory space to be tested does not include the memory space numbered 5.

[0051] Step 202: Switch the software and hardware systems between the STR state and the STR test wake-up state through UEFI, wherein in the STR test wake-up state, UEFI is started and the operating system remains dormant.

[0052] Step 202 can refer to the relevant records of the aforementioned step 101 and can achieve the same or similar beneficial effects. In order to avoid repetition, it will not be described here.

[0053] Step 203: In the STR test wake-up state, the memory data in the target memory space during the last STR state is verified by the test program in the UEFI.

[0054] Step 204: If the memory data in the target memory space fails verification, it is determined that a circuit fault exists in the memory.

[0055] In the STR test wake-up state, the memory data in the target memory space during the last STR state is verified through the test program in UEFI. Since the STR test wake-up state does not enter the kernel and operating system and does not involve peripherals, etc., new data will not be saved to the target memory space to be tested during the STR test. Therefore, if the memory data in the target memory space to be tested does not change before and after the STR verification, the memory data in the target memory space to be tested has passed the verification. If the memory data in the target memory space to be tested is different before and after the STR verification, the memory data in the target memory space to be tested has failed the verification.

[0056] Optionally, after step 201 and before step 203, the method may further include: writing an initial value in the target memory space. Step 204 may include: when the memory data in the target memory space is different from the aforementioned initial value, determining that there is a circuit fault in the memory. Specifically, in the STR test wake-up state, the memory data in the target memory space during the last STR state is verified by the test program in UEFI, and no new data is saved in the target memory space to be verified. Therefore, before and after the verification, the memory data in the target memory space of the memory to be verified has not changed, that is, the memory data verification in the target memory space has passed. Before and after the verification, the memory data in the target memory space to be verified is different, that is, the memory data verification in the target memory space has failed. However, since the specific original memory data in the target memory space may not be clear before the verification, the above-mentioned target memory space can be directly assigned an initial value, and then there is no need to obtain the original memory data in the target memory space, so that memory fault detection can be quickly achieved. Compared with obtaining the original memory data in the target memory space, the time required to directly assign the initial value is significantly shorter. For the same computer, for multiple memory fault detections, it is only necessary to assign the initial value once, and there is no need to re-assign the initial value for subsequent multiple memory fault detections, which saves more time.

[0057] It should be noted that the initial value here can be some data that is easy to compare, such as all 0s or all 1s. For example, writing an initial value of all 0s in the target memory space can further improve the STR test efficiency.

[0058] Optionally, the aforementioned step 202 may include: starting the UEFI firmware, setting the memory to enter self-refresh through UEFI, and setting the ACPI (Advanced Configuration and Power Interface) register on the bridge chip so that the software and hardware system switches between the STR state and the STR test wake-up state. The above method can successfully switch the software and hardware system between the STR state and the STR test wake-up state.

[0059] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present disclosure are not limited by the order of the actions described, because according to the embodiments of the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present disclosure.

[0060] Reference Figure 4 , Figure 4 The following is a structural block diagram of an embodiment of a memory fault detection device disclosed herein, which may include the following modules:

[0061] A switching module 301 is configured to switch the software and hardware systems between an STR state and an STR test wake-up state through UEFI, wherein in the STR test wake-up state, UEFI is started and the operating system remains dormant;

[0062] The verification module 302 is used to verify the memory data during the last STR state through the test program in the UEFI in the STR test wake-up state;

[0063] The fault determination module 303 is configured to determine that a circuit fault exists in the memory when the memory data verification fails.

[0064] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0065] The present application is further explained below with reference to specific embodiments. Figure 5 A flow chart of a memory failure detection method disclosed in the present invention is shown.

[0066] First, determine the target memory space to be verified in the memory. For example, refer to Figure 3 As shown, it is determined that in the STR test awakening state, the target memory spaces to be verified in the memory are the memory spaces numbered 2 and 6.

[0067] First, the UEFI firmware is normally started.

[0068] Second, initial values are written into the target memory spaces. For example, initial values 0x5a5a5a5a are written into the target memory spaces numbered 2 and 6.

[0069] Third, the memory is set to self-refresh by the UEFI.

[0070] Fourth, the bridge ACPI register is set by the UEFI to enable the system to switch between the STR state and the STR test wake state.

[0071] Fifth, the system is left to wait for several minutes and then booted.

[0072] Sixth, the UEFI firmware is normally started and the operating system remains in hibernation.

[0073] Seventh, the memory data in the target memory spaces during the last STR state is checked by a test program in the UEFI to determine whether the memory data in the target memory spaces is the same as the initial values. If the memory data in the target memory spaces is the same as the initial values, it is determined that the memory does not have a circuit fault. If the memory data in the target memory spaces is different from the initial values, it is determined that the memory has a circuit fault.

[0074] More specifically, after the UEFI firmware is started, the memory data in the target memory spaces numbered 2 and 6 is checked to determine whether the memory data in the target memory spaces numbered 2 and 6 is the same as the previously written 0x5a5a5a5a. If the memory data is the same, it is determined that the memory does not have a circuit fault. If the memory data is different, it is determined that the memory has a circuit fault.

[0075] If the memory has a circuit fault, an error message can be reported, i.e., the memory has a circuit fault. The memory fault detection is paused or ended, and the memory is checked for a circuit fault. After the fault is checked, the detection is performed again. Since the occurrence of a circuit fault in the memory is random, the circuit faults in the memory are detected completely after multiple fault detections. Therefore, if the memory does not have a circuit fault, the fourth step described above can be entered again to detect whether the memory has a circuit fault again. Through multiple detections of the memory fault, the stability of the STR of the memory can be further improved.

[0076] Figure 6 is a structural diagram of an electronic device provided by an embodiment of the present disclosure. Referring to Figure 6 The present disclosure also provides an electronic device, which is described with reference to Figure 6, including: a processor 501, a memory 502, and a computer program 5021 stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of each embodiment of the above-mentioned memory failure detection method are implemented.

[0077] In one embodiment, the memory is the aforementioned UEFI firmware, the STR test program and the wake-up program are set in the UEFI, and the processor executes the processes in each method embodiment according to the programs in the UEFI.

[0078] The present disclosure also provides a readable storage medium. When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the steps of each embodiment of the above-mentioned memory failure detection method.

[0079] The present disclosure also provides a computer program product, including instructions, which, when executed by a processor in an electronic device, enable the electronic device to perform the steps of each embodiment of the above-mentioned memory failure detection method.

[0080] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0081] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, devices, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0082] The embodiments of the present disclosure are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0083] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0084] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0085] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0086] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0087] The above is a detailed introduction to a memory fault detection method and device, an electronic device, and a storage medium provided by the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and core ideas of the present disclosure. At the same time, for those skilled in the art, according to the ideas of the present disclosure, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A method for detecting memory failure, characterized in that: The method comprises: Switching the hardware and software systems between the STR state and the STR test wake-up state through UEFI, wherein in the STR test wake-up state, UEFI is started and the operating system remains dormant; In the STR test wake-up state, the memory data during the last STR state is verified through the test program in UEFI; If the memory data verification fails, determining that a circuit fault exists in the memory; Before verifying the memory data during the last STR state by the test program in the UEFI, the method further includes: determining a target memory space to be verified in the memory, the target memory space excluding a memory space not released due to the operating system not starting the UEFI; The following steps are used to determine whether the memory has a circuit fault: The first step is to start the UEFI firmware normally; The second step is to write the initial value into the target memory space; The third step is to set the memory to enter self-refresh through UEFI; Step 4: Set the bridge ACPI register through UEFI to switch the software and hardware system between the STR state and the STR test wake-up state; Step 5: Wait for the preset time and then turn on the device to wake up; Step 6: The UEFI firmware starts normally and the operating system remains dormant; In the seventh step, the memory data in the target memory space during the last STR state is verified through the test program in UEFI to determine whether the memory data in the target memory space is the same as the initial value. If the memory data in the target memory space is the same as the initial value, it is determined that there is no circuit fault in the memory. If the memory data in the target memory space is different from the initial value, it is determined that there is a circuit fault in the memory.

2. The method according to claim 1, characterized in that The method further comprises: In the STR test wake-up state, the memory data during the last STR state is verified by the test program in the UEFI, including: In the STR test wake-up state, the memory data in the target memory space during the last STR state is verified through the test program in UEFI; If the memory data verification fails, determining that a circuit fault exists in the memory includes: If the memory data in the target memory space fails verification, it is determined that a circuit fault exists in the memory.

3. The method according to claim 2, characterized in that The method further comprises: Writing an initial value into the target memory space; When the memory data in the target memory space fails verification, determining that a circuit fault exists in the memory includes: When the memory data in the target memory space is different from the initial value, it is determined that a circuit fault exists in the memory.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: Before entering the STR state or the STR test wake-up state, set the memory to enter self-refresh through UEFI; Use UEFI to switch the hardware and software systems between the STR state and the STR test wake-up state, including: Through UEFI, set the ACPI register to switch the software and hardware systems between the STR state and the STR test wake-up state.

5. The method according to any one of claims 1 to 3, characterized in that The method further comprises: If the memory data verification passes, it is determined that there is no circuit fault in the memory.

6. The method according to any one of claims 1 to 3, characterized in that The method further comprises: In the case that a circuit fault occurs in the memory, a fault check is performed on the storage circuit and the self-refresh circuit of the memory.

7. A memory failure detection device, characterized in that: The device comprises: A switching module, configured to switch the software and hardware systems between an STR state and an STR test wake-up state through UEFI, wherein in the STR test wake-up state, UEFI is started and the operating system remains dormant; The verification module is used to verify the memory data during the last STR state through the test program in UEFI in the STR test wake-up state; A fault determination module, configured to determine that a circuit fault exists in the memory when the memory data verification fails; The device is further configured to determine a target memory space to be verified in the memory, wherein the target memory space does not include a memory space that is not released because the operating system does not start UEFI; The following steps are used to determine whether the memory has a circuit fault: The first step is to start the UEFI firmware normally; The second step is to write the initial value into the target memory space; The third step is to set the memory to enter self-refresh through UEFI; Step 4: Set the bridge ACPI register through UEFI to switch the software and hardware system between the STR state and the STR test wake-up state; Step 5: Wait for the preset time and then turn on the device to wake up; Step 6: The UEFI firmware starts normally and the operating system remains dormant; In the seventh step, the memory data in the target memory space during the last STR state is verified through the test program in UEFI to determine whether the memory data in the target memory space is the same as the initial value. If the memory data in the target memory space is the same as the initial value, it is determined that there is no circuit fault in the memory. If the memory data in the target memory space is different from the initial value, it is determined that there is a circuit fault in the memory.

8. An electronic device, characterized in that: include: processor; as well as UEFI firmware has a computer program stored thereon, and when the computer program is executed by the processor, the processor implements the memory failure detection method according to any one of claims 1 to 6.

9. A computer program product comprising instructions, which, when executed by a processor in an electronic device, causes the electronic device to execute the memory failure detection method according to any one of claims 1 to 6.

10. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the memory failure detection method according to any one of claims 1 to 6.

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