Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a preparation method thereof, and a display device. The display substrate comprises a driving circuit layer (20) and a light-emitting structure layer (30) arranged on a substrate (10), wherein the driving circuit layer (20) comprises a plurality of circuit units, a plurality of first initial signal lines (70) extending along a first direction, a plurality of second initial signal lines (80) extending along a second direction, and a low-voltage power supply line (90), wherein the circuit unit comprises at least a pixel driving circuit, and the light-emitting structure layer comprises a plurality of light-emitting devices, wherein the first initial signal line (70) is configured to provide an initial voltage signal to the pixel driving circuit, and the low-voltage power supply line (90) is configured to provide a low power supply voltage signal to the light-emitting device, and the second initial signal line (80) is connected to the first initial signal line (70), and the first initial signal line (70) and the second initial signal line (80) form a meshed connection structure.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] On the one hand, the present disclosure provides a display substrate, including a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the driving circuit layer including a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and a low-voltage power supply line extending along a second direction, the first direction and the second direction intersect, the circuit unit includes at least a pixel driving circuit, the pixel driving circuit includes a storage capacitor and a plurality of oxide transistors, the light-emitting structure layer includes a plurality of light-emitting devices, the first initial signal line is configured to provide an initial voltage signal to the pixel driving circuit, the low-voltage power supply line is configured to provide a low power supply voltage signal to the light-emitting device, the second initial signal line is connected to the first initial signal line, and the first initial signal line and the second initial signal line form a mesh connection structure.

[0005] In an exemplary embodiment, the first initial signal line includes a plurality of initial sub-lines spaced apart along the first direction, and in at least one circuit unit, the initial sub-lines adjacent to each other in the first direction are connected to each other via initial connection electrodes.

[0006] In an exemplary embodiment, the driving circuit layer includes a plurality of conductive layers, the initial sub-line and the initial connection electrode are provided in different conductive layers, and in at least one circuit unit, the initial connection electrode is connected to the initial sub-line through a via hole.

[0007] In an exemplary embodiment, in at least one circuit unit, the second initial signal line is connected to the initial connection electrode.

[0008] In an exemplary embodiment, the driving circuit layer includes a plurality of conductive layers, the initial connection electrode and the second initial signal line are provided in different conductive layers, and in at least one circuit unit, the second initial signal line is connected to the initial connection electrode through a via hole.

[0009] In an exemplary embodiment, the pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor. In at least one circuit unit, the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the second plate of the storage capacitor and the second electrode of the sixth transistor, the first electrode of the second transistor is connected to the first plate of the storage capacitor, the second electrode of the second transistor is connected to the first electrode of the third transistor, the first electrode of the fourth transistor is connected to the data signal line, the second electrode of the fourth transistor is connected to the second electrode of the third transistor, the first electrode of the fifth transistor is connected to the first power line, the second electrode of the fifth transistor is connected to the first electrode of the third transistor, the first electrode of the sixth transistor is connected to the second electrode of the third transistor, and the second electrode of the sixth transistor is connected to the light-emitting device.

[0010] In an exemplary embodiment, in at least one circuit unit, the first transistor, the fourth transistor, and the sixth transistor are arranged on one side of the storage capacitor in the second direction, and the second transistor and the fifth transistor are arranged on a side of the storage capacitor in the opposite direction to the second direction.

[0011] In an exemplary embodiment, in at least one circuit unit, the fourth transistor is arranged on a side of the storage capacitor in the second direction, the sixth transistor is arranged on a side of the fourth transistor away from the storage capacitor, the first transistor is arranged on a side of the sixth transistor away from the storage capacitor, the second transistor is arranged on a side of the storage capacitor in the opposite direction of the second direction, and the fifth transistor is arranged on a side of the second transistor away from the storage capacitor.

[0012] In an exemplary embodiment, in at least one circuit unit, the first transistor includes at least a first active layer, the sixth transistor includes at least a sixth active layer, and the second region of the first active layer and the first region of the sixth active layer are connected to each other as an integral structure.

[0013] In an exemplary embodiment, in at least one circuit unit, the second transistor includes at least a second active layer, the third transistor includes at least a third active layer, and the fourth transistor includes at least a fourth active layer. The second active layer and the fourth active layer are shaped like strips extending along the first direction, the third active layer is shaped like a strip extending along the second direction, the first region of the third active layer and the second region of the second active layer are an integrated structure connected to each other, and the second region of the third active layer and the second region of the fourth active layer are an integrated structure connected to each other.

[0014] In an exemplary embodiment, in at least one circuit unit, the third transistor includes at least a bottom gate electrode and a top gate electrode, the bottom gate electrode is respectively connected to the second electrode of the fourth transistor and the first electrode of the sixth transistor, and the top gate electrode and the first electrode plate of the storage capacitor are an integrated structure.

[0015] In an exemplary embodiment, the driving circuit layer also includes a first scan signal line, a second scan signal line, a third scan signal line, a first light-emitting control line and a second light-emitting control line extending along the first direction. In at least one circuit unit, the first scan signal line is connected to the top gate electrode of the first transistor, the second scan signal line is connected to the top gate electrode of the fourth transistor, the third scan signal line is connected to the top gate electrode of the second transistor, the first light-emitting control line is connected to the top gate electrode of the sixth transistor, and the second light-emitting control line is connected to the top gate electrode of the fifth transistor.

[0016] In an exemplary embodiment, in at least one circuit unit, the second scan signal line is located on the side of the storage capacitor in the second direction, the first light-emitting control line is located on the side of the second scan signal line away from the storage capacitor, the first scan signal line is located on the side of the first light-emitting control line away from the storage capacitor, the third scan signal line is located on the side of the storage capacitor in the opposite direction of the second direction, and the second light-emitting control line is located on the side of the third scan signal line away from the storage capacitor.

[0017] In an exemplary embodiment, in at least one circuit unit, the first initial signal line is disposed on a side of the first scan signal line away from the storage capacitor.

[0018] In an exemplary embodiment, the driving circuit layer includes at least a blocking conductive layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate, the blocking conductive layer includes at least the bottom gate electrodes of multiple oxide transistors, the first conductive layer includes at least the first plate of the storage capacitor and the top gate electrodes of multiple oxide transistors, the second conductive layer includes at least the second plate of the storage capacitor and the first initial signal line, the third conductive layer includes at least the first and second electrodes of multiple oxide transistors, and the fourth conductive layer includes at least the second initial signal line and a low-voltage power supply line.

[0019] In an exemplary embodiment, the multiple unit columns include at least a first unit column, a second unit column, and a third unit column, the pixel driving circuits of the multiple circuit units in the first unit column are connected to the red light-emitting device that emits red light, the pixel driving circuits of the multiple circuit units in the second unit column are connected to the green light-emitting device that emits green light, and the pixel driving circuits of the multiple circuit units in the third unit column are connected to the blue light-emitting device that emits blue light, the low-voltage power line is arranged in the first unit column and the second unit column, and the second initial signal line is arranged in the third unit column.

[0020] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0021] In another aspect, the present disclosure further provides a method for preparing a display substrate, comprising:

[0022] forming a driving circuit layer on a substrate, the driving circuit layer comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and a low-voltage power supply line extending along a second direction, wherein the first direction and the second direction intersect, the circuit unit comprising at least a pixel driving circuit, the pixel driving circuit comprising a storage capacitor and a plurality of oxide transistors, the first initial signal line being configured to provide an initial voltage signal to the pixel driving circuit, the second initial signal line being connected to the first initial signal line, and the first initial signal line and the second initial signal line forming a meshed connection structure;

[0023] A light emitting structure layer is formed on the driving circuit layer. The light emitting structure layer includes a plurality of light emitting devices. The low voltage power line is configured to provide a low power voltage signal to the light emitting devices.

[0024] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0026] Figure 1 is a structural schematic diagram of a display device;

[0027] Figure 2 A schematic diagram of the planar structure of a display substrate;

[0028] Figure 3 A schematic diagram of the cross-sectional structure of a display substrate;

[0029] Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0030] Figure 5 This is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0031] Figure 6 This is a schematic diagram of an embodiment of the present disclosure after forming a shielding conductive layer pattern;

[0032] Figure 7A and Figure 7B This is a schematic diagram of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0033] Figure 8A and Figure 8B This is a schematic diagram after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0034] Figure 9A and Figure 9B This is a schematic diagram after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0035] Figure 10 This is a schematic diagram of an embodiment of the present disclosure after forming a fourth insulating layer pattern;

[0036] Figure 11A and Figure 11B This is a schematic diagram of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0037] Figure 12 This is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern;

[0038] Figure 13A and Figure 13B This is a schematic diagram of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0039] Figure 14 This is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0040] Figure 15 This is a schematic planar structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0041] Figure 16 This is a schematic planar structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0042] Figure 17 This is a schematic planar structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0043] Figure 18 This is a schematic planar structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0044] Figure 19 This is a schematic planar structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0045] Figure 20 This is a schematic planar structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0046] Figure 21 This is a schematic planar structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0047] Figure 22 This is a schematic planar structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0048] Figure 23 FIG. 1 is a schematic planar structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.

[0049] Description of the accompanying drawings:

[0050] 10—base; 11—first shielding line; 12—second shielding line;

[0051] 13—third blocking line; 14—fourth blocking line; 15—fifth blocking line;

[0052] 16—shielding electrode; 20—driving circuit layer; 21—first active layer;

[0053] 22—second active layer; 23—third active layer; 24—fourth active layer;

[0054] 25—fifth active layer; 26—sixth active layer; 27—seventh active layer;

[0055] 30—light-emitting structure layer; 31—first scanning signal line; 32—second scanning signal line;

[0056] 33—third scanning signal line; 34—first light-emitting control line; 35—second light-emitting control line;

[0057] 36 - first electrode plate; 40 - packaging structure layer; 41 - initial sub-line;

[0058] 42—second electrode plate; 43—opening; 50—storage capacitor;

[0059] 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode;

[0060] 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode;

[0061] 57—seventh connection electrode; 58—initial connection electrode; 61—anodic connection electrode;

[0062] 62—first power line; 63—data signal line; 70—first initial signal line;

[0063] 80—second initial signal line; 90—low-voltage power line; 91—first insulation layer;

[0064] 92—second insulating layer; 93—third insulating layer; 94—fourth insulating layer;

[0065] 95—fifth insulating layer; 96—first flat layer; 97—second flat layer;

[0066] 101—first blocking block; 102—second blocking block; 103—third blocking block;

[0067] 104—fourth blocking block; 105—fifth blocking block; 111—shielding block;

[0068] 121—first capacitor block; 122—second capacitor block. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0070] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0071] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0072] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0073] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0074] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0075] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0076] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0077] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0078] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0079] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have some minor deformations due to tolerances, such as chamfers, rounded edges, and deformation. The term "approximately" in this disclosure does not strictly define the boundaries, but allows for values ​​within the range of process and measurement errors.

[0080] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, a display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), the scan driver is connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0081] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0082] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0083] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0084] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels. Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 20 disposed on a base 10, a light emitting structure layer 30 disposed on a side of the driving circuit layer 20 away from the base 10, and an encapsulation structure layer 40 disposed on a side of the light emitting structure layer 30 away from the base 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0085] In an exemplary embodiment, in a plane parallel to the display substrate, the driving circuit layer 20 may include multiple circuit units, each of which may include a pixel driving circuit, as well as scan signal lines, light emission control lines, data signal lines, and a first power supply line connected to the pixel driving circuit. The pixel driving circuit may include at least multiple transistors and a storage capacitor. In a plane perpendicular to the display substrate, the driving circuit layer 20 may include a shielding conductive layer 20-1, a first insulating layer 91, a semiconductor layer 20-2, a second insulating layer 92, a first conductive layer 20-3, a third insulating layer 93, a second conductive layer 20-4, a fourth insulating layer 94, a third conductive layer 20-5, a fifth insulating layer 95, a first planarizing layer 96, a fourth conductive layer 20-6, and a second planarizing layer 97, which are sequentially arranged on the base. The blocking conductive layer 20-1 may include at least a plurality of blocking lines, the semiconductor layer 20-2 may include at least an active layer of a plurality of transistors, the first conductive layer 20-3 may include at least a first electrode plate of a storage capacitor, the second conductive layer 20-4 may include at least a second electrode plate of a storage capacitor, the third conductive layer 20-5 may include at least a first electrode and a second electrode of a plurality of transistors, and the fourth conductive layer 20-6 may include at least an anode connection electrode.

[0086] In an exemplary embodiment, the light-emitting structure layer 30 may include multiple light-emitting devices, each of which may include at least an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color when driven by the anode and cathode. The encapsulation structure layer 40 may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic material / organic material / inorganic material stacked structure, which can prevent external moisture from entering the light-emitting structure layer 30.

[0087] In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of adjacent circuit units may have a small amount of overlap or may be isolated from each other.

[0088] As OLED display technology matures and yield rates continue to improve, the cost of OLED displays continues to decline, leading to their application in a wider range of fields, such as medium and large-sized electronic products. As display substrate sizes increase, the yield rate of display substrates using low-temperature polysilicon (LTPS) thin-film transistors decreases, resulting in higher costs. Consequently, display substrates using only oxide thin-film transistors are gaining attention.

[0089] An exemplary embodiment of the present disclosure provides a display substrate, comprising a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, wherein the driving circuit layer comprises a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and a low-voltage power supply line extending along a second direction, wherein the first direction and the second direction intersect, the circuit unit comprises at least a pixel driving circuit, wherein the pixel driving circuit comprises a storage capacitor and a plurality of oxide transistors, the light-emitting structure layer comprises a plurality of light-emitting devices, the first initial signal line is configured to provide an initial voltage signal to the pixel driving circuit, the low-voltage power supply line is configured to provide a low power supply voltage signal to the light-emitting device, the second initial signal line is connected to the first initial signal line, and the first initial signal line and the second initial signal line form a meshed connection structure.

[0090] In an exemplary embodiment, the first initial signal line includes a plurality of initial sub-lines spaced apart along the first direction, and in at least one circuit unit, the initial sub-lines adjacent to each other in the first direction are connected to each other via initial connection electrodes.

[0091] In an exemplary embodiment, in at least one circuit unit, the second initial signal line is connected to the initial connection electrode.

[0092] In an exemplary embodiment, the multiple unit columns include at least a first unit column, a second unit column, and a third unit column, the pixel driving circuits of the multiple circuit units in the first unit column are connected to the red light-emitting device that emits red light, the pixel driving circuits of the multiple circuit units in the second unit column are connected to the green light-emitting device that emits green light, and the pixel driving circuits of the multiple circuit units in the third unit column are connected to the blue light-emitting device that emits blue light, the low-voltage power line is arranged in the first unit column and the second unit column, and the second initial signal line is arranged in the third unit column.

[0093] The display substrate of this embodiment is described below with reference to some examples.

[0094] Figure 4 FIG1 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 4 As shown, the pixel driving circuit of the exemplary embodiment of the present disclosure may include 6 transistors (first transistor T1 to sixth transistor T6) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 8 signal lines (first scan signal line S1, second scan signal line S2, first light-emitting signal line E1, second light-emitting signal line E2, initial signal line INIT, data signal line D, first power line VDD and second power line VSS).

[0095] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate of the storage capacitor C, respectively; the second node N2 is connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5, respectively; the third node N3 is connected to the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6, respectively; the fourth node N4 is connected to the second electrode of the first transistor T1, the second electrode of the sixth transistor T6, and the second plate of the storage capacitor C, respectively; and the fourth node N4 is further connected to the first electrode of the light emitting device EL.

[0096] In an exemplary embodiment, the first plate of the storage capacitor C is connected to the first node N1, and the second plate of the storage capacitor C is connected to the fourth node N4, that is, the first end of the storage capacitor C is connected to the gate electrode of the third transistor T3, and the second end of the storage capacitor C is connected to the first electrode of the light emitting device EL.

[0097] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the initialization signal line INIT, and a second electrode of the first transistor T1 is connected to the second plate of the storage capacitor C and the fourth node N4. When an on-level scan signal is applied to the first scan signal line S1, the first transistor T1 is turned on and transmits an initialization voltage to the second plate of the storage capacitor C and the first electrode of the light-emitting device EL, respectively, to initialize the storage capacitor C and the light-emitting device EL.

[0098] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the second node N2. When an on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the gate electrode of the third transistor T3 to the first electrode of the third transistor T3.

[0099] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first plate of the storage capacitor C, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor. The third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the light-emitting device based on the potential difference between the gate electrode and the first electrode.

[0100] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the third node N3. When an on-level scan signal is applied to the second scan signal line S2, the fourth transistor T4 inputs a data voltage of the data signal line D to the third node N3.

[0101] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the second light emitting signal line E2, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. A gate electrode of the sixth transistor T6 is connected to the first light emitting signal line E1, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. When an on-level light emitting signal is applied to the first light emitting signal line E1 and the second light emitting signal line E2, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the light emitting device, causing the light emitting device to emit light.

[0102] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer and a second electrode (cathode), or can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer and a second electrode (cathode).

[0103] In an exemplary embodiment, the six transistors of the pixel driving circuit may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the yield of the product.

[0104] In an exemplary embodiment, the six transistors of the pixel driving circuit may be oxide thin-film transistors. The active layer of the oxide thin-film transistors may be made of an oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current. Using a display substrate provided with oxide thin-film transistors can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0105] In an exemplary embodiment, the second electrode of the light-emitting device EL is connected to the second power line VSS. The first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit. The second power line VSS can be configured to provide a constant second voltage signal to the pixel driving circuit, and the first voltage signal is greater than the second voltage signal. The initial signal line INIT can be configured to provide an initial voltage signal to the pixel driving circuit. The initial voltage signal can be a constant voltage signal, and its magnitude can be between the first voltage signal provided by the first power line VDD and the second voltage signal provided by the second power line VSS, but this disclosure is not limited thereto.

[0106] In some examples, taking the example that the first transistor T1 to the sixth transistor T6 included in the pixel driving circuit are all N-type transistors, the operation process of the pixel driving circuit may include the following stages.

[0107] The first phase A1 is called the initialization phase. The high-level signal provided by the first scan signal line S1 turns on the first transistor T1 and the second transistor T2, and the high-level signal provided by the second light-emitting signal line E2 turns on the fifth transistor T5. Turning on the first transistor T1 causes the initial voltage signal provided by the initial signal line INIT to be supplied to the fourth node N4 and the second plate of the storage capacitor C, initializing the storage capacitor C and the light-emitting device EL. This clears the existing data voltage in the storage capacitor C and the pre-stored voltage at the first electrode of the light-emitting device EL, completing initialization and rendering the light-emitting device EL non-luminous. Turning on the second transistor T2 connects the first node N1 to the second node N2. Turning on the fifth transistor T5 causes the first voltage signal output from the first power line VDD to be charged into the first plate of the storage capacitor C via the fifth transistor T5, the second node N2, and the first node N1. Since the first plate of the storage capacitor C is at a high level, the third transistor T3 turns on.

[0108] The second phase A2 is called the data writing phase or the threshold compensation phase. The second scan signal line S2 provides a high-level signal, turning on the fourth transistor T4. The fourth transistor T4 is turned on, causing the data voltage output by the data signal line D to be supplied to the first node N1 via the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is then charged into the first plate of the storage capacitor C.

[0109] The third phase A3 is called the light-emitting phase. The first light-emitting control line E1 and the second light-emitting signal line E2 provide high-level signals to turn on the fifth transistor T5 and the sixth transistor T6. The first voltage signal output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0110] During the driving process of the pixel driving circuit, the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the third transistor T3 , so the pixel driving circuit can better compensate for the threshold voltage of the third transistor T3 .

[0111] Figure 5 This is a schematic diagram of the planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuit in three circuit units in a unit row. In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a driving circuit layer arranged on a substrate, a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, and an encapsulation structure layer arranged on a side of the light-emitting structure layer away from the substrate. In a direction parallel to the display substrate, the driving circuit layer may include circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit may include at least a pixel driving circuit, and at least one pixel driving circuit may include a storage capacitor and a plurality of oxide transistors. The light-emitting structure layer includes a plurality of light-emitting devices, and at least one light-emitting device may include an anode, an organic light-emitting layer, and a cathode.

[0112] In an exemplary embodiment, the driving circuit layer further includes a plurality of first initial signal lines 70 extending along a first direction X, a plurality of second initial signal lines 80 extending along a second direction Y, and a plurality of low-voltage power supply lines 90 extending along the second direction Y, wherein the first direction X intersects the second direction Y. The first initial signal lines 70 are configured to provide initial voltage signals to the pixel driving circuits, the low-voltage power supply lines 90 are configured to provide low power supply voltage signals to the cathodes of the light-emitting devices, and the second initial signal lines 80 are connected to the first initial signal lines 70, such that the first initial signal lines 70 extending along the first direction X and the second initial signal lines 80 extending along the second direction Y form a mesh-like interconnected structure.

[0113] In an exemplary embodiment, the first initial signal line 70 may include a plurality of initial sub-lines 41 spaced apart along the first direction X. In at least one circuit unit, adjacent initial sub-lines 41 in the first direction X are connected to each other through the initial connection electrode 58 to form a first initial signal line 70 extending along the first direction X.

[0114] In an exemplary embodiment, in at least one circuit unit, the second preliminary signal line 80 is connected to the preliminary connection electrode 58 . Since the preliminary connection electrode 58 is connected to the preliminary sub-line 41 , the second preliminary signal line 80 is connected to the first preliminary signal line 70 .

[0115] In an exemplary embodiment, the driving circuit layer may include multiple conductive layers, the initial sub-line 41, the initial connection electrode 58 and the second initial signal line 80 may be arranged in different conductive layers, and in at least one circuit unit, the initial connection electrode 58 is connected to the initial sub-line 41 through a via, and the second initial signal line 80 is connected to the initial connection electrode 58 through a via.

[0116] In an exemplary embodiment, the storage capacitor of the pixel driving circuit may include a first electrode and a second electrode, and the plurality of oxide transistors of the pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. In at least one circuit unit, the first electrode of the first transistor T1 is connected to the first initial signal line 70, the second electrode of the first transistor T1 is connected to the second electrode of the storage capacitor 50, and the second electrode of the sixth transistor T6. The first electrode of the second transistor T2 is connected to the first electrode of the storage capacitor 50, the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3, the first electrode of the fourth transistor T4 is connected to the data signal line 63, the second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the first electrode of the fifth transistor T5 is connected to the first power line 62, the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3, the first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1.

[0117] In an exemplary embodiment, in at least one circuit unit, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 may be located on one side of the storage capacitor 50 in the second direction Y, and the second transistor T2 and the fifth transistor T5 may be located on the side of the storage capacitor 50 in the opposite direction of the second direction Y.

[0118] In an exemplary embodiment, in at least one circuit unit, the fourth transistor T4 may be located on one side of the storage capacitor 50 in the second direction Y, the sixth transistor T6 may be located on the side of the fourth transistor T4 away from the storage capacitor 50, the first transistor T1 may be located on the side of the sixth transistor T6 away from the storage capacitor 50, the second transistor T2 may be located on the side of the storage capacitor 50 in the opposite direction of the second direction Y, and the fifth transistor T5 may be located on the side of the second transistor T2 away from the storage capacitor 50.

[0119] In an exemplary embodiment, the driving circuit layer may further include a first scanning signal line 31, a second scanning signal line 32, a third scanning signal line 33, a first light-emitting control line 34, and a second light-emitting control line 35. The shapes of the first scanning signal line 31, the second scanning signal line 32, the third scanning signal line 33, the first light-emitting control line 34, and the second light-emitting control line 35 may be straight lines or broken lines extending along the first direction X.

[0120] In an exemplary embodiment, each of the first to sixth transistors T1 to T6 includes a top gate electrode and a bottom gate electrode.

[0121] In an exemplary embodiment, a first scan signal line 31 may be connected to the top gate electrode of the first transistor T1, and the first scan signal line 31 is configured to control the on / off state of the first transistor T1. A second scan signal line 32 may be connected to the top gate electrode of the fourth transistor T4, and the second scan signal line 32 is configured to control the on / off state of the fourth transistor T4. A third scan signal line 33 may be connected to the top gate electrode of the second transistor T2, and the third scan signal line 33 is configured to control the on / off state of the second transistor T2. A first emission control line 34 may be connected to the top gate electrode of the sixth transistor T6, and the first emission control line 34 is configured to control the on / off state of the sixth transistor T6. A second emission control line 35 may be connected to the top gate electrode of the fifth transistor T5, and the second emission control line 35 is configured to control the on / off state of the fifth transistor T5.

[0122] In an exemplary embodiment, in at least one circuit unit, the second scan signal line 32 may be located on one side of the storage capacitor 50 in the second direction Y, the first light emission control line 34 may be located on a side of the second scan signal line 32 away from the storage capacitor 50, and the first scan signal line 31 may be located on a side of the first light emission control line 34 away from the storage capacitor 50. The third scan signal line 33 may be located on a side of the storage capacitor 50 opposite to the second direction Y, and the second light emission control line 35 may be located on a side of the third scan signal line 33 away from the storage capacitor 50.

[0123] In an exemplary embodiment, the first preliminary signal line 70 may be located on a side of the first scan signal line 31 away from the storage capacitor 50 .

[0124] In an exemplary embodiment, the plurality of unit columns may include at least a first unit column, a second unit column, and a third unit column. The pixel driving circuits of the plurality of circuit units in the first unit column are connected to red light-emitting devices that emit red light. The pixel driving circuits of the plurality of circuit units in the second unit column are connected to green light-emitting devices that emit green light. The pixel driving circuits of the plurality of circuit units in the third unit column are connected to blue light-emitting devices that emit blue light. The low-voltage power line 90 may be provided in the first and second unit columns, and the second initial signal line 80 may be provided in the third unit column. For example, the n-1th and nth columns may be the first and second unit columns, respectively, and the n+1th column may be the third unit column. The low-voltage power line 90 may be provided in the circuit units in the n-1th and nth columns, respectively, and the second initial signal line 80 may be provided in the circuit unit in the n+1th column.

[0125] In an exemplary embodiment, the driving circuit layer may include at least a blocking conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer and a fourth conductive layer, which are arranged in sequence along a direction away from the substrate. The blocking conductive layer may include at least the bottom gate electrodes of multiple oxide transistors, the semiconductor layer may include at least the active layer of multiple oxide transistors, the first conductive layer may include at least the first plate of the storage capacitor 50 and the top gate electrodes of multiple oxide transistors, the second conductive layer may include at least the second plate of the storage capacitor 50 and the first initial signal line 70, the third conductive layer may include at least the first and second electrodes of multiple oxide transistors, and the fourth conductive layer may include at least the second initial signal line 80 and the low-voltage power supply line 90.

[0126] The following is an exemplary description of the preparation process of the substrate shown in this exemplary embodiment. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0127] In an exemplary embodiment, a process of preparing a display substrate may include the following operations.

[0128] (1) Forming a blocking conductive layer pattern. In an exemplary embodiment, forming a blocking conductive layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking conductive layer pattern on the substrate, such as Figure 6 shown.

[0129] In an exemplary embodiment, the blocking conductive layer pattern may include at least a first blocking line 11 , a second blocking line 12 , a third blocking line 13 , a fourth blocking line 14 , a fifth blocking line 15 and a blocking electrode 16 .

[0130] In an exemplary embodiment, the shapes of the first shielding line 11 , the second shielding line 12 , the third shielding line 13 , the fourth shielding line 14 and the fifth shielding line 15 may be straight lines or broken lines extending along the first direction X.

[0131] In the present disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, the main portion extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B." In an exemplary embodiment, the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.

[0132] In an exemplary embodiment, the first shielding line 11 may be located on one side of the shielding electrode 16 in the second direction Y. The first shielding line 11 is configured to shield the first transistor T1 to reduce the influence of light on the electrical characteristics of the first transistor T1 and is configured as a bottom gate electrode of the first transistor T1.

[0133] In an exemplary embodiment, the second shielding line 12 may be located on one side of the shielding electrode 16 in the second direction Y and between the shielding electrode 16 and the first shielding line 11. A fourth bottom-gate electrode 12-1 is provided on one side of the second shielding line 12 close to the shielding electrode 16. The fourth bottom-gate electrode 12-1 is configured to shield the fourth transistor T4, thereby reducing the impact of light on the electrical characteristics of the fourth transistor T4, and is also configured as the bottom gate electrode of the fourth transistor T4.

[0134] In an exemplary embodiment, the third shielding line 13 may be located on a side of the shielding electrode 16 opposite to the second direction Y, such that the shielding electrode 16 is located between the second shielding line 12 and the third shielding line 13. A second bottom-gate electrode 13-1 is provided on a side of the third shielding line 13 near the shielding electrode 16. The second bottom-gate electrode 13-1 is configured to shield the second transistor T2, thereby reducing the impact of light on the electrical characteristics of the second transistor T2, and is also configured to serve as the bottom gate electrode of the second transistor T2.

[0135] In an exemplary embodiment, the fourth shielding line 14 may be located between the first shielding line 11 and the second shielding line 12. The fourth shielding line 14 is configured to shield the sixth transistor T6 to reduce the influence of light on the electrical characteristics of the sixth transistor T6, and is configured as the bottom gate electrode of the sixth transistor T6.

[0136] In an exemplary embodiment, the fifth shielding line 15 may be located on a side of the third shielding line 13 away from the shielding electrode 16. The fifth shielding line 15 is configured to shield the fifth transistor T5 to reduce the influence of light on the electrical characteristics of the fifth transistor T5, and is configured as a bottom gate electrode of the fifth transistor T5.

[0137] In an exemplary embodiment, the shielding electrode 16 may be in the shape of a strip extending along the second direction Y. The shielding electrode 16 is configured to shield the third transistor T3 to reduce the influence of light on the electrical characteristics of the third transistor T3 and serves as a bottom gate electrode of the third transistor T3.

[0138] In an exemplary embodiment, a shielding connection block 16 - 1 is provided at an end of the shielding electrode 16 close to the first shielding line 11 , and the shielding connection block 16 - 1 is configured to be connected to a fifth connection electrode formed subsequently.

[0139] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, such as Figure 7A and Figure 7B As shown, Figure 7B for Figure 7A Schematic plan view of the semiconductor layer.

[0140] In an exemplary embodiment, the semiconductor layer pattern may include the first active layer 21 of the first transistor T1 to the sixth active layer 26 of the sixth transistor T6, and the second active layer 22, the third active layer 23 and the fourth active layer 24 are an integrated structure connected to each other, and the first active layer 21 and the sixth active layer 26 are an integrated structure connected to each other.

[0141] In an exemplary embodiment, in the second direction Y, the first active layer 21, the fourth active layer 24, and the sixth active layer 26 may be located on one side of the third active layer 23 in the second direction Y, and the second active layer 22 and the fifth active layer 25 may be located on a side of the third active layer 23 in the opposite direction of the second direction Y.

[0142] In an exemplary embodiment, the first to sixth active layers 21 to 26 may be shaped like an "I." The second active layer 22 and the fourth active layer 24 may be shaped like strips extending along the first reverse direction X, and the third active layer 23 may be shaped like a strip extending along the second direction Y. A first end of the second active layer 22 is connected to one end of the third active layer 23, and a second end of the second active layer 22 extends along the first direction X. A first end of the fourth active layer 24 is connected to the other end of the third active layer 23, and a second end of the fourth active layer 24 extends along the first direction X, so that the second active layer 22, the third active layer 23, and the fourth active layer 24 of the integrated structure form a "C" shape.

[0143] In an exemplary embodiment, the orthographic projection of the third active layer 23 on the substrate may be located within the range of the orthographic projection of the shielding electrode 16 on the substrate, so that the channel region of the third transistor T3 may be effectively shielded by the shielding electrode 16 .

[0144] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 21-2 of the first active layer 21 and the second region 26-2 of the sixth active layer 26 are interconnected as a single unitary structure, i.e., the second region 21-2 of the first active layer 21 can serve as the second region 26-2 of the sixth active layer 26. The second region 22-2 of the second active layer 22 and the first region 23-1 of the third active layer 23 are interconnected as a single unitary structure, i.e., the second region 22-2 of the second active layer 22 can serve as the first region 23-1 of the third active layer 23. The second region 24-2 of the fourth active layer 24 and the second region 23-2 of the third active layer 23 are interconnected as a single unitary structure, i.e., the second region 24-2 of the fourth active layer 24 can serve as the first region 23-1 of the third active layer 23. The first region 21-1 of the first active layer 21, the first region 22-1 of the second active layer 22, the first region 24-1 of the fourth active layer 24, the first region 25-1 of the fifth active layer 25, the second region 25-2 of the fifth active layer 25, and the first region 26-1 of the sixth active layer 26 may be separately provided.

[0145] In an exemplary embodiment, the semiconductor layer may be made of oxide, and the first transistor T1 to the sixth transistor T6 are all oxide transistors. In an exemplary embodiment, the semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has high electron mobility. The thickness of the semiconductor layer may be approximately 20 nm to 40 nm. For example, the thickness of the semiconductor layer may be approximately 30 nm.

[0146] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, such as Figure 8A and Figure 8B As shown, Figure 8B for Figure 8A In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0147] In an exemplary embodiment, the first conductive layer pattern includes at least a first scan signal line 31 , a second scan signal line 32 , a third scan signal line 33 , a first light emission control line 34 , a second light emission control line 35 and a first plate 36 of a storage capacitor.

[0148] In an exemplary embodiment, the first electrode plate 36 may be rectangular, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode plate 36 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 36 may simultaneously serve as a plate of the storage capacitor and the top gate electrode of the third transistor T3 (driving transistor), i.e., the top gate electrode of the third transistor T3 and the first electrode plate 36 of the storage capacitor are integrally structured.

[0149] In an exemplary embodiment, the first scan signal line 31 , the second scan signal line 32 , the third scan signal line 33 , the first light emission control line 34 , and the second light emission control line 35 may be straight lines or zigzag lines extending along the first direction X.

[0150] In an exemplary embodiment, the first scanning signal line 31 can be located on one side of the first electrode 36 in the second direction Y, and the area where the first scanning signal line 31 overlaps with the first active layer serves as the top gate electrode of the first transistor T1, that is, the first scanning signal line 31 and the top gate electrode of the first transistor T1 are an integrated structure connected to each other.

[0151] In an exemplary embodiment, the orthographic projection of the first scan signal line 31 on the substrate may be located within the range of the orthographic projection of the first shielding line 11 on the substrate, so that the channel region of the first transistor T1 may be effectively shielded by the first shielding line 11 .

[0152] In an exemplary embodiment, the second scan signal line 32 may be located on one side of the first electrode plate 36 in the second direction Y and between the first electrode plate 36 and the first scan signal line 31. A fourth top gate electrode 32-1 is connected to a side of the second scan signal line 32 close to the first electrode plate 36. The orthographic projection of the fourth top gate electrode 32-1 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The fourth top gate electrode 32-1 is configured as the top gate electrode of the fourth transistor T4.

[0153] In an exemplary embodiment, the orthographic projection of the second scanning signal line 32 on the substrate can be located within the range of the orthographic projection of the second shielding line 12 on the substrate, and the orthographic projection of the fourth top gate electrode 32-1 on the substrate can be located within the range of the orthographic projection of the fourth bottom gate electrode 12-1 on the substrate, so that the channel region of the fourth transistor T4 can be effectively shielded by the fourth bottom gate electrode 12-1.

[0154] In an exemplary embodiment, the third scan signal line 33 may be located on a side of the first electrode plate 36 opposite to the second direction Y, such that the first electrode plate 36 is located between the second scan signal line 32 and the third scan signal line 33. A second top gate electrode 33-1 is connected to a side of the third scan signal line 33 closer to the first electrode plate 36. The orthographic projection of the second top gate electrode 33-1 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second top gate electrode 33-1 is configured as the top gate electrode of the second transistor T2.

[0155] In an exemplary embodiment, the orthographic projection of the third scanning signal line 33 on the substrate can be located within the range of the orthographic projection of the third shielding line 13 on the substrate, and the orthographic projection of the second top gate electrode 33-1 on the substrate can be located within the range of the orthographic projection of the second bottom gate electrode 13-1 on the substrate, so that the channel region of the second transistor T2 can be effectively shielded by the second bottom gate electrode 13-1.

[0156] In an exemplary embodiment, the first scan signal line 31 and the third scan signal line 33 may transmit the same scan signal, and the first scan signal line 31 and the third scan signal line 33 are connected to the same scan signal source.

[0157] In an exemplary embodiment, the first light-emitting control line 34 can be located on a side of the second scanning signal line 32 away from the first electrode 36, and can be located between the first scanning signal line 31 and the second scanning signal line 32. The area where the first light-emitting control line 34 overlaps with the sixth active layer serves as the top gate electrode of the sixth transistor T6, that is, the first light-emitting control line 34 and the top gate electrode of the sixth transistor T6 are an integrated structure connected to each other.

[0158] In an exemplary embodiment, the orthographic projection of the first light emitting control line 34 on the substrate may be located within the range of the orthographic projection of the fourth shielding line 14 on the substrate, so that the channel region of the sixth transistor T6 may be effectively shielded by the fourth shielding line 14 .

[0159] In an exemplary embodiment, the second light-emitting control line 35 can be located on a side of the third scanning signal line 33 away from the first electrode 36, and the area where the second light-emitting control line 35 overlaps with the fifth active layer serves as the top gate electrode of the fifth transistor T5, that is, the second light-emitting control line 35 and the top gate electrode of the fifth transistor T5 are an integrated structure connected to each other.

[0160] In an exemplary embodiment, the orthographic projection of the second light emitting control line 35 on the substrate may be located within the range of the orthographic projection of the fifth shielding line 15 on the substrate, so that the channel region of the fifth transistor T5 may be effectively shielded by the fifth shielding line 15 .

[0161] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the sixth transistor T6, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first transistor T1 to the sixth active layer are both conductorized.

[0162] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, such as Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0163] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least an initial sub-line 41 and a second plate 42 of a storage capacitor.

[0164] In an exemplary embodiment, the outline of the second electrode plate 42 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 42 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 36 on the substrate. The second electrode plate 42 can serve as another electrode plate of the storage capacitor, and the first electrode plate 36 and the second electrode plate 42 constitute the storage capacitor of the pixel driving circuit.

[0165] In an exemplary embodiment, an opening 43 is provided on the second electrode plate 42. Opening 43 can be rectangular and located in the middle of the second electrode plate 42, forming an annular structure. Opening 43 exposes the third insulating layer covering the first electrode plate 36, and the orthographic projection of the first electrode plate 36 on the substrate includes the orthographic projection of opening 43 on the substrate. In an exemplary embodiment, opening 43 is configured to accommodate a first via hole to be formed later. The first via hole is located within opening 43 and exposes the first electrode plate 36, thereby connecting the second electrode of the first transistor T1 to be formed later.

[0166] In an exemplary embodiment, the initial sub-line 41 may be in the shape of a line with a main portion extending along the first direction X. In the first direction X, the initial sub-line 41 may be disposed between the first regions of the first active layers of adjacent circuit units in the first direction X. In the second direction Y, the initial sub-line 41 may be located on a side of the first scan signal line 31 away from the second electrode plate 42. The initial sub-line 41 is configured as a first initial signal line extending along the first direction X, transmitting an initial voltage signal, using a subsequently formed initial connection electrode.

[0167] (5) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, and providing a plurality of via holes on the fourth insulating layer, such as Figure 10 shown.

[0168] In an exemplary embodiment, the plurality of vias include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, and a thirteenth via V13.

[0169] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 43 on the substrate, the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away, exposing the surface of the first electrode 36, and the first via hole V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode 36 through the via hole.

[0170] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the second region of the sixth active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away to expose the surface of the second region of the first active layer, and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor T1 (also the second electrode of the sixth transistor T6) to the second region of the first active layer (also the second region of the sixth active layer) through the via.

[0171] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the third via hole V3 are etched away to expose the surface of the first region of the fifth active layer, and the third via hole V3 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the first region of the fifth active layer through the via hole.

[0172] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via hole V4 are etched away to expose the surface of the second region of the fifth active layer, and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed fifth transistor T5 to the second region of the fifth active layer through the via hole.

[0173] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the second region of the second active layer (also the first region of the third active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away to expose the surface of the second region of the second active layer, and the fifth via V5 is configured to connect the second electrode of the subsequently formed second transistor T2 (also the first electrode of the third transistor T3) to the second region of the second region of the second active layer (also the first region of the third active layer) through the via.

[0174] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away to expose the surface of the first region of the fourth active layer, and the sixth via V6 is configured to connect the first electrode of the subsequently formed fourth transistor T4 to the first region of the fourth active layer through the via.

[0175] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the second region of the fourth active layer (also the second region of the third active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away to expose the surface of the second region of the fourth active layer, and the seventh via V7 is configured to connect the second electrode of the subsequently formed fourth transistor T4 (also the second electrode of the third transistor T3) to the second region of the fourth active layer (also the second region of the third active layer) through the via.

[0176] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first region of the sixth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the eighth via V8 are etched away to expose the surface of the first region of the sixth active layer, and the eighth via V8 is configured to connect the first electrode of the subsequently formed sixth transistor T6 to the first region of the sixth active layer through the via.

[0177] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the first region of the second active layer, and the ninth via V9 is configured to connect the first electrode of the subsequently formed second transistor T2 to the first region of the second active layer through the via.

[0178] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the blocking connection block 16-1 of the blocking electrode 16 on the substrate, and the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the tenth via hole V10 are etched away to expose the surface of the blocking connection block 16-1. The tenth via hole V10 is configured to connect the subsequently formed fifth connection electrode to the blocking electrode 16 through the via hole.

[0179] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second electrode plate 42 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the second electrode plate 42, and the eleventh via hole V11 is configured to connect the subsequently formed seventh connecting electrode to the second electrode plate 42 through the via hole.

[0180] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the first region of the first active layer, and the twelfth via V12 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first region of the first active layer through the via.

[0181] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the end of the initial sub-line 41 close to the first region of the first active layer on the substrate, the fourth insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the end of the initial sub-line 41, and the thirteenth via hole V13 is configured to connect the first electrode of the subsequently formed first transistor T1 to the initial sub-line 41 through the via hole.

[0182] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, such as Figure 11A and Figure 11B As shown, Figure 11B for Figure 11AIn an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0183] In an exemplary embodiment, the third conductive layer of each circuit unit includes at least a first connection electrode 51 , a second connection electrode 52 , a third connection electrode 53 , a fourth connection electrode 54 , a fifth connection electrode 55 , a sixth connection electrode 56 , a seventh connection electrode 57 and an initial connection electrode 58 .

[0184] In an exemplary embodiment, the first connection electrode 51 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the first connection electrode 51 is connected to the first electrode plate 36 via a first via V1, and a second end of the first connection electrode 51 is connected to the first region of the second active layer via a ninth via V9, so that the first electrode plate 36 and the first electrode of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 51 may serve as the first electrode of the second transistor T2 (i.e., the first node N1 of the pixel driving circuit).

[0185] In an exemplary embodiment, the second connection electrode 52 may be polygonal in shape and connected to the first region of the fifth active layer through a third via hole V3. In an exemplary embodiment, the second connection electrode 52 may serve as a first electrode of the fifth transistor T5 and is configured to be connected to a first power line formed subsequently.

[0186] In an exemplary embodiment, the third connection electrode 53 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the third connection electrode 53 is connected to the second region of the fifth active layer via a fourth via hole V4, and a second end of the third connection electrode 53 is connected to the second region of the second active layer via a fifth via hole V5. In an exemplary embodiment, the third connection electrode 53 may simultaneously serve as the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5 (i.e., the second node N2 of the pixel driving circuit).

[0187] In an exemplary embodiment, the fourth connection electrode 54 may be polygonal in shape and connected to the first region of the fourth active layer through a sixth via hole V6. In an exemplary embodiment, the fourth connection electrode 54 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0188] In an exemplary embodiment, the fifth connection electrode 55 may be L-shaped. A first end of the fifth connection electrode 55 is connected to the first region of the sixth active layer via an eighth via V8. A second end of the fifth connection electrode 55 is connected to the shielding connection block 16-1 of the shielding electrode 16 via a tenth via V10. A third end of the fifth connection electrode 55 is connected to the second region of the fourth active layer via a seventh via V7. The third end of the fifth connection electrode 55 is located between the first and second ends. In an exemplary embodiment, the fifth connection electrode 55 may simultaneously serve as the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6 (i.e., the third node N3 of the pixel driving circuit). Because the shielding electrode 16 serves as the bottom gate electrode of the third transistor T3, the bottom gate electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6 via the fifth connection electrode 55.

[0189] In an exemplary embodiment, the sixth connection electrode 56 may be polygonal in shape and connected to the second region of the first active layer (also the second region of the sixth active layer) through a second via hole V2. In an exemplary embodiment, the sixth connection electrode 56 may serve as both the second electrode of the first transistor T1 and the second electrode of the sixth transistor T6. The sixth connection electrode 56 is configured to be connected to a subsequently formed anode connection electrode.

[0190] In an exemplary embodiment, the seventh connection electrode 57 may be polygonal in shape and connected to the second electrode plate 42 through the eleventh via hole V11. In an exemplary embodiment, the seventh connection electrode 57 is configured to be connected to an anode connection electrode formed subsequently.

[0191] In an exemplary embodiment, the shape of the initial connection electrode 58 can be a strip shape with the main part extending along the first direction X. The middle part of the initial connection electrode 58 is connected to the first area of ​​the first active layer through the twelfth via V12, and the two ends of the initial connection electrode 58 are respectively connected to the end of the adjacent initial sub-line 41 through the thirteenth via V13. On the one hand, the mutual connection between the multiple initial sub-lines 41 is realized to form a first initial signal line. On the other hand, the connection between the first initial signal line and the first electrode of the first transistor T1 is realized, so that the initial voltage transmitted by the first initial signal line is written into the first electrode of the first transistor T1.

[0192] (7) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planar layer disposed on the fifth insulating layer, wherein the first planar layer is provided with a plurality of via holes, such as Figure 12 shown.

[0193] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , a twenty-third via V23 , and a twenty-fourth via V24 .

[0194] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 52 on the substrate, the first flat layer and the fifth insulating layer in the twenty-first via hole V21 are etched away to expose the surface of the second connecting electrode 52, and the twenty-first via hole V21 is configured to connect the subsequently formed first power line to the second connecting electrode 52 through the via hole.

[0195] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer and the fifth insulating layer in the twenty-second via hole V22 are etched away to expose the surface of the fourth connecting electrode 54, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the fourth connecting electrode 54 through the via hole.

[0196] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer and the fifth insulating layer in the twenty-third via hole V23 are etched away to expose the surface of the sixth connecting electrode 56, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the sixth connecting electrode 56 through the via hole.

[0197] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the seventh connecting electrode 57 on the substrate, the first flat layer and the fifth insulating layer within the twenty-fourth via V24 are etched away to expose the surface of the seventh connecting electrode 57, and the twenty-fourth via V24 is configured to connect the subsequently formed anode connecting electrode to the seventh connecting electrode 57 through the via.

[0198] In an exemplary embodiment, the partial circuit unit further includes a twenty-fifth via hole V25, the orthographic projection of the twenty-fifth via hole V25 on the substrate at least partially overlapping with the orthographic projection of the initial connection electrode 58 on the substrate, the first flat layer and the fifth insulating layer within the twenty-fifth via hole V25 are etched away to expose the surface of the initial connection electrode 58, and the twenty-fifth via hole V25 is configured to connect a subsequently formed second initial signal line to the initial connection electrode 58 through the via hole.

[0199] In an exemplary embodiment, the twenty-fifth via V25 may be provided in the circuit unit in the n+1th column, that is, the second initial signal line is provided in the circuit unit in the n+1th column, while the circuit units in the n-1th column and the nth column are not provided with the twenty-fifth via V25.

[0200] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the first flat layer, such as Figure 13A and Figure 13B As shown, Figure 13B for Figure 13A In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0201] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least an anode connection electrode 61 , a first power supply line 62 , and a data signal line 63 .

[0202] In an exemplary embodiment, the anode connection electrode 61 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the anode connection electrode 61 is connected to the sixth connection electrode 56 via a twenty-third via hole V23, and a second end of the anode connection electrode 61 is connected to the seventh connection electrode 57 via a twenty-fourth via hole V24. Because the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the first active layer) via a via hole, and the seventh connection electrode 57 is connected to the second electrode plate 42 via a via hole, the second electrode of the first transistor T1, and the second electrode of the sixth transistor T6 have the same potential (i.e., the fourth node N4 of the pixel driving circuit). In an exemplary embodiment, the anode connection electrode 61 is configured to be connected to a subsequently formed anode, thereby enabling the pixel driving circuit to output a driving current to the light-emitting device.

[0203] In an exemplary embodiment, the first power line 62 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The first power line 62 is connected to the second connection electrode 52 through the twenty-first via hole V21. Since the second connection electrode 52 is connected to the first region of the fifth active layer through the via hole, the first power line 62 can write a constant first voltage signal to the first electrode of the fifth transistor T5.

[0204] In an exemplary embodiment, the data signal line 63 may be in the shape of a straight line with a main portion extending along the second direction Y. The data signal line 63 is connected to the fourth connection electrode 54 through the twenty-second via hole V22. Since the fourth connection electrode 54 is connected to the first region of the fourth active layer through the via hole, the data signal line 63 can write a data signal to the first electrode of the fourth transistor T4.

[0205] In an exemplary embodiment, the fourth conductive layer of some circuit units may further include a second initial signal line 80. The second initial signal line 80 may be in the form of a straight line or a zigzag line, with the main portion extending along the second direction Y. The second initial signal line 80 is connected to the initial connection electrode 58 via the twenty-fifth via hole V25. Since the initial sub-line 41 forms a first initial signal line extending along the first direction X through the initial connection electrode 58, and the second initial signal line 80 is connected to the initial connection electrode 58, the first initial signal line extending along the first direction X and the second initial signal line 80 extending along the second direction Y form a network of initial signal lines in the display area. This minimizes the resistance of the initial signal lines, reduces the initial voltage drop, and effectively improves the uniformity of the initial voltage in the display substrate, effectively improving display uniformity and enhancing display quality.

[0206] In an exemplary embodiment, the fourth conductive layer of the partial circuit unit may further include a low-voltage power line (second power line) 90. The low-voltage power line 90 may be in the shape of a straight line or a broken line with a main portion extending along the second direction Y. The low-voltage power line 90 may be located between the first power line 62 and the data signal line 63. The low-voltage power line 90 is configured to output a constant second voltage signal to the cathode of the light-emitting device.

[0207] In some exemplary embodiments, the plurality of unit columns of the display panel may include at least a first unit column, a second unit column, and a third unit column. The pixel driving circuits of the plurality of circuit units in the first unit column are connected to red light-emitting devices that emit red light. The pixel driving circuits of the plurality of circuit units in the second unit column are connected to green light-emitting devices that emit green light. The pixel driving circuits of the plurality of circuit units in the third unit column are connected to blue light-emitting devices that emit blue light. For example, the (n-1)th column may be the first unit column, the (n)th column may be the second unit column, and the (n+1)th column may be the third unit column. The low-voltage power line 90 may be provided in the circuit units in the (n-1)th column and the (n)th column, and the second initial signal line 80 may be provided in the circuit unit in the (n+1)th column.

[0208] In some possible exemplary embodiments, the second initial signal line 80 may be disposed in the circuit units in the nth and n+1th columns, and the low voltage power line 90 may be disposed in the circuit unit in the n-1th column, which is not limited in the present disclosure.

[0209] Subsequently, a second flat film is coated on the substrate on which the aforementioned pattern is formed, and the second flat film is patterned using a patterning process to form a second flat layer covering the pattern of the fourth conductive layer. An anode via is provided on the second flat layer, and the orthographic projection of the anode via on the substrate is within the range of the orthographic projection of the anode connecting electrode on the substrate. The anode via is configured to connect the subsequently formed anode to the anode connecting electrode through the via.

[0210] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a first light-emitting control line, a second light-emitting control line, a first initial signal line, a first power line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a shielding conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer, a fourth conductive layer, and a second flat layer arranged in sequence on the substrate. The shielding conductive layer may include at least a shielding electrode and a plurality of shielding lines, the semiconductor layer may include at least the active layer of the first transistor to the sixth transistor, the first conductive layer may include at least the first plate of the storage capacitor, the second conductive layer may include at least the second plate of the storage capacitor, the third conductive layer may include at least the first and second poles of the first to sixth transistors, and the fourth conductive layer may include at least the anode connection electrode.

[0211] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0212] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as a buffer layer, the second insulating layer and the third insulating layer may be referred to as a gate insulating (GI) layer, the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer may be referred to as a passivation (PVX) layer. The shielding conductive layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or may be made of an alloy material composed of a metal such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure such as Ti / Al / Ti. The first planar layer and the second planar layer may be made of an organic material such as a resin or polyimide.

[0213] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer may be prepared on the driving circuit layer, and an encapsulation structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.

[0214] From the structure and preparation process of the display substrate described above, it can be seen that the pixel driving circuit of this exemplary embodiment uses 6 oxide transistors to meet the driving requirements. Compared with the existing pixel driving circuit structure of 7 transistors, it not only reduces the number of transistors, simplifies the structure of the pixel driving circuit structure, reduces the occupied area of ​​the pixel driving circuit, is conducive to achieving high-resolution (PPI) display, but also can ensure the yield of large-size display substrates and reduce production costs. In this exemplary embodiment, the bottom gate electrode is set in the shielding conductive layer, and the top gate electrode is set in the first conductive layer, which can ensure the shielding effect and improve the electrical performance of the transistor. The present disclosure sets a first initial signal line extending along the first direction X and a second initial signal line extending along the second direction Y in the display area to form an initial signal line of a network connection structure in the display area, which can minimize the resistance of the initial signal line, reduce the voltage drop of the initial voltage, and effectively improve the uniformity of the initial voltage in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality. The present disclosure implements a VSS-in-pixel structure by providing a low-voltage power line within the display area. This not only effectively reduces the resistance of the low-voltage power line, effectively reduces the voltage drop of the low-voltage power signal, and achieves low power consumption, but also effectively improves the uniformity of the low-voltage power signal in the display substrate, effectively improving display uniformity, and improving display quality. The disclosed preparation process is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0215] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this. For example, the display substrate may include two first initial signal lines extending along the first direction (such as a first horizontal initial line and a second horizontal initial line) and two second initial signal lines extending along the second direction (such as a first vertical initial line and a second vertical initial line). In at least one circuit unit, the first horizontal initial line and the first vertical initial line can be connected by a via, and the second horizontal initial line and the second vertical initial line can be connected by a via, forming an initial signal line of a dual network connection structure in the display area. For another example, the display substrate may include a first low-voltage power line extending along the first direction and a second low-voltage power line extending along the second direction. In at least one circuit unit, the first low-voltage power line and the second low-voltage power line are connected by a via, forming a low-voltage power line of a network connection structure in the display area.

[0216] Figure 14 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuits in three circuit units in a unit row. Figure 14As shown, in the exemplary embodiment, this exemplary embodiment shows the main structure of the substrate and Figure 5 The main structure of the display substrate shown is basically the same, except that in at least one circuit unit, a first blocking block 101 is provided on the first power line 62 in the fourth conductive layer.

[0217] In an exemplary embodiment, the first blocking block 101 can be arranged on one side of the first power line 62 in the first direction X (close to the data signal line 63), which is equivalent to providing a protrusion on the first power line 62. The orthographic projection of the first blocking block 101 on the substrate at least partially overlaps with the orthographic projection of the fifth active layer of the fifth transistor T5 on the substrate. The first blocking block 101 is configured to block the fifth transistor T5, reduce the influence of light on the electrical characteristics of the fifth transistor T5, and improve the working stability of the fifth transistor T5.

[0218] In an exemplary embodiment, the first blocking block 101 and the first power line 62 may be an integral structure connected to each other, and an orthographic projection of the first blocking block 101 on the substrate at least partially overlaps with an orthographic projection of the channel region of the fifth active layer on the substrate.

[0219] Figure 15 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuits in three circuit units in a unit row. Figure 15 As shown, in the exemplary embodiment, this exemplary embodiment shows the main structure of the substrate and Figure 5 The main structure of the display substrate shown is basically the same, except that in at least one circuit unit, a second blocking block 102 is provided on the second initial signal line 80 and / or the low-voltage power line 90 in the fourth conductive layer.

[0220] In an exemplary embodiment, the second blocking block 102 can be arranged on the side of the second initial signal line 80 and / or the low-voltage power line 90 in the opposite direction of the first direction X (close to the first power line 62), which is equivalent to setting a protrusion on the second initial signal line 80 and / or the low-voltage power line 90. The positive projection of the second blocking block 102 on the substrate at least partially overlaps with the positive projection of the second active layer of the second transistor T2 on the substrate. The second blocking block 102 is configured to block the second transistor T2, reduce the influence of light on the electrical characteristics of the second transistor T2, and improve the working stability of the second transistor T2.

[0221] In an exemplary embodiment, the second blocking block 102 and the second initial signal line 80 of the partial circuit unit can be an integrated structure connected to each other, and the second blocking block 102 and the low-voltage power line 90 of the partial circuit unit can be an integrated structure connected to each other, and the orthographic projection of the second blocking block 102 on the substrate at least partially overlaps with the orthographic projection of the channel region of the second active layer on the substrate.

[0222] Figure 16 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuits in three circuit units in a unit row. Figure 16 As shown, in the exemplary embodiment, this exemplary embodiment shows the main structure of the substrate and Figure 5 The main structure of the display substrate shown is basically the same, except that in at least one circuit unit, a third blocking block 103 is provided on the second initial signal line 80 and / or the low-voltage power line 90 in the fourth conductive layer.

[0223] In an exemplary embodiment, the third blocking block 103 can be arranged on the side of the second initial signal line 80 and / or the low-voltage power line 90 in the opposite direction of the first direction X (close to the first power line 62), which is equivalent to providing a protrusion on the second initial signal line 80 and / or the low-voltage power line 90. The positive projection of the third blocking block 103 on the substrate at least partially overlaps with the positive projection of the fourth active layer of the fourth transistor T4 on the substrate. The third blocking block 103 is configured to block the fourth transistor T4, reduce the influence of light on the electrical characteristics of the fourth transistor T4, and improve the working stability of the fourth transistor T4.

[0224] In an exemplary embodiment, the third blocking block 103 and the second initial signal line 80 of the partial circuit unit can be an integrated structure connected to each other, and the third blocking block 103 and the low-voltage power line 90 of the partial circuit unit can be an integrated structure connected to each other, and the orthographic projection of the third blocking block 103 on the substrate at least partially overlaps with the orthographic projection of the channel region of the fourth active layer on the substrate.

[0225] Figure 17 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuits in three circuit units in a unit row. Figure 17 As shown, in the exemplary embodiment, this exemplary embodiment shows the main structure of the substrate and Figure 5 The main structure of the display substrate shown is basically the same, except that in at least one circuit unit, a fourth blocking block 104 is provided on the second initial signal line 80 and / or the low-voltage power line 90 in the fourth conductive layer.

[0226] In an exemplary embodiment, the fourth blocking block 104 can be arranged on a side opposite to the first direction X of the second initial signal line 80 and / or the low-voltage power line 90 (close to the first power line 62), which is equivalent to providing a protrusion on the second initial signal line 80 and / or the low-voltage power line 90. The positive projection of the fourth blocking block 104 on the substrate at least partially overlaps with the positive projection of the first active layer of the first transistor T1 on the substrate. The fourth blocking block 104 is configured to block the first transistor T1, reduce the influence of light on the electrical characteristics of the first transistor T1, and improve the working stability of the first transistor T1.

[0227] In an exemplary embodiment, the fourth blocking block 104 and the second initial signal line 80 of the partial circuit unit can be an integrated structure connected to each other, and the fourth blocking block 104 and the low-voltage power line 90 of the partial circuit unit can be an integrated structure connected to each other, and the orthographic projection of the fourth blocking block 104 on the substrate at least partially overlaps with the orthographic projection of the channel region of the first active layer on the substrate.

[0228] In some exemplary embodiments, the fourth blocking block 104 may be disposed at a position of the first power line 62 close to the first transistor T1 , which is equivalent to providing a protrusion on the first power line 62 to shield the first transistor T1 .

[0229] In other exemplary embodiments, depending on the layout of the circuit units, the fourth blocking blocks 104 of some circuit units can be set on the first power line 62, the fourth blocking blocks 104 of some circuit units can be set on the second initial signal line 80, and the fourth blocking blocks 104 of some circuit units can be set on the low-voltage power line 90. The present disclosure does not limit this.

[0230] Figure 18 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuits in three circuit units in a unit row. Figure 18 As shown, in the exemplary embodiment, this exemplary embodiment shows the main structure of the substrate and Figure 5 The main structure of the display substrate shown is basically the same, except that in at least one circuit unit, a fifth blocking block 105 is provided on the anode connection electrode 61 in the fourth conductive layer.

[0231] In an exemplary embodiment, the fifth blocking block 105 can be arranged on one side of the anode connecting electrode 61 in the first direction X (close to the data signal line 63), which is equivalent to increasing the size of the anode connecting electrode 61. The orthographic projection of the fifth blocking block 105 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer of the sixth transistor T6 on the substrate. The fifth blocking block 105 is configured to block the sixth transistor T6, reduce the influence of light on the electrical characteristics of the sixth transistor T6, and improve the operating stability of the sixth transistor T6.

[0232] In an exemplary embodiment, the fifth blocking block 105 and the anode connection electrode 61 may be an integral structure connected to each other, and an orthographic projection of the fifth blocking block 105 on the substrate at least partially overlaps with an orthographic projection of the channel region of the sixth active layer on the substrate.

[0233] Figure 19 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuits in three circuit units in a unit row. Figure 19 As shown, in the exemplary embodiment, this exemplary embodiment shows the main structure of the substrate and Figure 5 The main structure of the display substrate shown is basically the same, except that in at least one circuit unit, a shielding block 111 is provided on the first power line 62 in the fourth conductive layer.

[0234] In an exemplary embodiment, the shielding block 111 can be disposed on one side of the first power line 62 in the first direction X (close to the data signal line 63), which is equivalent to providing a protrusion on the first power line 62. The orthographic projection of the shielding block 111 on the substrate at least partially overlaps with the orthographic projection of the second plate of the storage capacitor 50 on the substrate. The shielding block 111 is configured to shield the fourth node N4 of the pixel driving circuit to stabilize the anode potential.

[0235] In an exemplary embodiment, the shielding block 111 and the first power line 62 may be an integral structure connected to each other.

[0236] Figure 20 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuits in three circuit units in a unit row. Figure 20 As shown, in the exemplary embodiment, this exemplary embodiment shows the main structure of the substrate and Figure 5The main structure of the display substrate shown is basically the same, except that, in at least one circuit unit, the second initial signal line 80 in the fourth conductive layer may include a first initial straight portion 80A, a second initial straight portion 80B, and an initial bending portion 80C located between the first initial straight portion 80A and the second initial straight portion 80B, and / or, the low-voltage power line 90 may include a first power straight portion 90A, a second power straight portion 90B, and a power bending portion 90C located between the first power straight portion 90A and the second power straight portion 90B.

[0237] In an exemplary embodiment, the first end of the initial bend portion 80C is connected to the first initial straight portion 80A, the second end of the initial bend portion 80C is connected to the second initial straight portion 80B, and the middle portion of the initial bend portion 80C protrudes toward the direction close to the first power line 62, so that the positive projection of the second initial signal line 80 on the substrate does not overlap with the positive projection of the first connecting electrode 51 (the first node N1 of the pixel driving circuit) on the substrate. The initial bend portion 80C of the second initial signal line 80 is configured to avoid the first node N1 of the pixel driving circuit to reduce the voltage division of the first node N1 and improve the potential stability of the key nodes of the pixel driving circuit.

[0238] In an exemplary embodiment, the first end of the power bend 90C is connected to the first power straight portion 90A, the second end of the power bend 90C is connected to the second power straight portion 90B, and the middle portion of the power bend 90C protrudes toward the direction close to the first power line 62, so that the positive projection of the low-voltage power line 90 on the substrate does not overlap with the positive projection of the first connecting electrode 51 (the first node N1 of the pixel driving circuit) on the substrate. The power bend 90C of the low-voltage power line 90 is configured to avoid the first node N1 of the pixel driving circuit to reduce the voltage division of the first node N1 and improve the potential stability of the key nodes of the pixel driving circuit.

[0239] Figure 21 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuits in three circuit units in a unit row. Figure 21 As shown, in the exemplary embodiment, this exemplary embodiment shows the main structure of the substrate and Figure 5 The main structure of the display substrate shown is basically the same, except that a complete first initial signal line 70 is formed when the second conductive layer is formed.

[0240] In an exemplary embodiment, the first preliminary signal line 70 may be shaped like a zigzag line with a main portion extending along the first direction X, and the first preliminary signal lines 70 of adjacent circuit units are connected to each other.

[0241] In an exemplary embodiment, the first initial signal line 70 may include an initial straight portion 70A and an initial avoidance portion 70B. The initial straight portion 70A may be in the shape of a line extending along the first direction X and may be disposed between adjacent first active layers in the first direction X. The initial avoidance portion 70B may have both ends in the first direction X connected to the initial straight portion 70A, and a central portion of the initial avoidance portion 70B may protrude away from the first active layer, such that an orthographic projection of the initial avoidance portion 70B on the substrate does not overlap with an orthographic projection of the first active layer on the substrate.

[0242] In an exemplary embodiment, the initial straight portion 70A and the initial avoidance portion 70B may be an integrated structure connected to each other to form a complete first initial signal line 70. Since the complete first initial signal line 70 is formed when the second conductive layer is formed, the corresponding vias and initial connection electrodes can be omitted in subsequent processes, reducing process difficulty.

[0243] Figure 22 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuits in three circuit units in a unit row. Figure 22 As shown, in the exemplary embodiment, this exemplary embodiment shows the main structure of the substrate and Figure 5 The main structure of the display substrate shown is basically the same, except that in at least one circuit unit, a first capacitor block 121 is provided on the anode connection electrode 61 in the fourth conductive layer.

[0244] In an exemplary embodiment, the first capacitor block 121 can be arranged on one side of the anode connecting electrode 61 in the first direction X (close to the data signal line 63), or can be arranged on one side of the anode connecting electrode 61 in the opposite direction of the first direction X (close to the first power line 62), or can be arranged on both sides of the anode connecting electrode 61 in the first direction X, and the positive projection of the first capacitor block 121 on the substrate at least partially overlaps with the positive projection of the second scanning signal line 32 on the substrate, and the first capacitor block 121 is configured to increase the parasitic capacitance between the anode connecting electrode 61 (the fourth node N4 of the pixel driving circuit) and the second scanning signal line 32.

[0245] In an exemplary embodiment, by increasing the parasitic capacitance between the fourth node N4 of the pixel driving circuit and the second scanning signal line 32, after the data is written and before the light-emitting element emits light, the falling edge of the signal on the second scanning signal line 32 can lower the potential of the fourth node N4, thereby enhancing the black screen display effect.

[0246] In an exemplary embodiment, the first capacitor block 121 is provided so that the parasitic capacitance between the anode connection electrode 61 and the second scan signal line 32 is greater than the parasitic capacitance between the anode connection electrode 61 and the first light emission control line 34 .

[0247] In an exemplary embodiment, the first capacitor block 121 and the anode connection electrode 61 may be an integral structure connected to each other.

[0248] Figure 23 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuits in three circuit units in a unit row. Figure 23 As shown, in the exemplary embodiment, this exemplary embodiment shows the main structure of the substrate and Figure 5 The main structure of the display substrate shown is basically the same, except that in at least one circuit unit, a second capacitor block 122 is provided on the anode connection electrode 61 in the fourth conductive layer.

[0249] In an exemplary embodiment, the second capacitor block 122 can be arranged on one side of the anode connecting electrode 61 in the first direction X (close to the data signal line 63), or can be arranged on one side of the anode connecting electrode 61 in the opposite direction of the first direction X (close to the first power line 62), or can be arranged on both sides of the anode connecting electrode 61 in the first direction X, and the positive projection of the second capacitor block 122 on the substrate at least partially overlaps with the positive projection of the first scanning signal line 31 on the substrate, and the second capacitor block 122 is configured to increase the parasitic capacitance between the anode connecting electrode 61 (the fourth node N4 of the pixel driving circuit) and the first scanning signal line 31.

[0250] In an exemplary embodiment, by increasing the parasitic capacitance between the fourth node N4 of the pixel driving circuit and the first scanning signal line 31, after data writing is completed and before the light-emitting element emits light, the potential of the fourth node N4 can be lowered to enhance the black screen display effect.

[0251] In an exemplary embodiment, the second capacitor block 122 is provided so that the parasitic capacitance between the anode connection electrode 61 and the first scan signal line 31 is greater than the parasitic capacitance between the anode connection electrode 61 and the first light emission control line 34 .

[0252] In an exemplary embodiment, the second capacitor block 122 and the anode connection electrode 61 may be an integral structure connected to each other.

[0253] In an exemplary embodiment, Figures 14 to 23 The solutions shown and the structures therein can be combined with each other arbitrarily, and the present disclosure does not limit them here.

[0254] In an exemplary embodiment, the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.

[0255] The present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiment. In an exemplary embodiment, the preparation method may include:

[0256] forming a driving circuit layer on a substrate, the driving circuit layer comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and a low-voltage power supply line extending along a second direction, wherein the first direction and the second direction intersect, the circuit unit comprising at least a pixel driving circuit, the pixel driving circuit comprising a storage capacitor and a plurality of oxide transistors, the first initial signal line being configured to provide an initial voltage signal to the pixel driving circuit, the second initial signal line being connected to the first initial signal line, and the first initial signal line and the second initial signal line forming a meshed connection structure;

[0257] A light emitting structure layer is formed on the driving circuit layer. The light emitting structure layer includes a plurality of light emitting devices. The low voltage power line is configured to provide a low power voltage signal to the light emitting devices.

[0258] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0259] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, the driving circuit layer comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and a low-voltage power supply line extending along a second direction, wherein the first direction and the second direction intersect, the circuit unit comprising at least a pixel driving circuit, the pixel driving circuit comprising a storage capacitor and a plurality of oxide transistors, the light-emitting structure layer comprising a plurality of light-emitting devices, the first initial signal line being configured to provide an initial voltage signal to the pixel driving circuit, the low-voltage power supply line being configured to provide a low power supply voltage signal to the light-emitting devices, the second initial signal line being connected to the first initial signal line, the first initial signal line and the second initial signal line forming a meshed connection structure; in, The multiple unit columns include at least a first unit column, a second unit column and a third unit column. The pixel driving circuits of the multiple circuit units in the first unit column are connected to the first light-emitting device that emits the first color light. The pixel driving circuits of the multiple circuit units in the second unit column are connected to the third light-emitting device that emits the third color light. The pixel driving circuits of the multiple circuit units in the third unit column are connected to the second light-emitting device that emits the second color light. The first color, the second color and the third color are different colors. The low-voltage power line is arranged in the first unit column and the second unit column, and the second initial signal line is arranged in the third unit column.

2. The display substrate according to claim 1, wherein The first initial signal line includes a plurality of initial sub-lines spaced apart along the first direction. In at least one circuit unit, the initial sub-lines adjacent to each other in the first direction are connected to each other via initial connection electrodes.

3. The display substrate according to claim 2, wherein: The driving circuit layer includes multiple conductive layers, the initial sub-line and the initial connection electrode are arranged in different conductive layers, and in at least one circuit unit, the initial connection electrode is connected to the initial sub-line through a via hole.

4. The display substrate according to claim 2, wherein: In at least one circuit unit, the second initial signal line is connected to the initial connection electrode.

5. The display substrate according to claim 4, wherein: The driving circuit layer includes multiple conductive layers, the initial connection electrode and the second initial signal line are arranged in different conductive layers, and in at least one circuit unit, the second initial signal line is connected to the initial connection electrode through a via hole. The display substrate according to claim 1 , wherein: The pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor. In at least one circuit unit, the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the second plate of the storage capacitor and the second electrode of the sixth transistor, the first electrode of the second transistor is connected to the first plate of the storage capacitor, the second electrode of the second transistor is connected to the first electrode of the third transistor, the first electrode of the fourth transistor is connected to the data signal line, the second electrode of the fourth transistor is connected to the second electrode of the third transistor, the first electrode of the fifth transistor is connected to the first power line, the second electrode of the fifth transistor is connected to the first electrode of the third transistor, the first electrode of the sixth transistor is connected to the second electrode of the third transistor, and the second electrode of the sixth transistor is connected to the light-emitting device.

7. The display substrate according to claim 6, wherein: In at least one circuit unit, the first transistor, the fourth transistor and the sixth transistor are arranged on one side of the storage capacitor in the second direction, and the second transistor and the fifth transistor are arranged on a side of the storage capacitor in a direction opposite to the second direction.

8. The display substrate according to claim 7, wherein: In at least one circuit unit, the fourth transistor is arranged on the side of the storage capacitor in the second direction, the sixth transistor is arranged on the side of the fourth transistor away from the storage capacitor, the first transistor is arranged on the side of the sixth transistor away from the storage capacitor, the second transistor is arranged on the side of the storage capacitor in the opposite direction of the second direction, and the fifth transistor is arranged on the side of the second transistor away from the storage capacitor.

9. The display substrate according to claim 6, wherein: In at least one circuit unit, the first transistor includes at least a first active layer, the sixth transistor includes at least a sixth active layer, and the second region of the first active layer and the first region of the sixth active layer are interconnected as an integrated structure.

10. The display substrate according to claim 6, wherein: In at least one circuit unit, the second transistor includes at least a second active layer, the third transistor includes at least a third active layer, and the fourth transistor includes at least a fourth active layer. The second active layer and the fourth active layer are shaped like strips extending along the first direction, the third active layer is shaped like a strip extending along the second direction, the first region of the third active layer and the second region of the second active layer are an integrated structure connected to each other, and the second region of the third active layer and the second region of the fourth active layer are an integrated structure connected to each other.

11. The display substrate according to claim 6, wherein: In at least one circuit unit, the third transistor includes at least a bottom gate electrode and a top gate electrode, the bottom gate electrode is respectively connected to the second electrode of the fourth transistor and the first electrode of the sixth transistor, and the top gate electrode and the first electrode plate of the storage capacitor are an integrated structure.

12. The display substrate according to claim 6, wherein: The driving circuit layer also includes a first scanning signal line, a second scanning signal line, a third scanning signal line, a first light-emitting control line and a second light-emitting control line extending along the first direction. In at least one circuit unit, the first scanning signal line is connected to the top gate electrode of the first transistor, the second scanning signal line is connected to the top gate electrode of the fourth transistor, the third scanning signal line is connected to the top gate electrode of the second transistor, the first light-emitting control line is connected to the top gate electrode of the sixth transistor, and the second light-emitting control line is connected to the top gate electrode of the fifth transistor.

13. The display substrate according to claim 12, wherein: In at least one circuit unit, the second scanning signal line is located on the side of the storage capacitor in the second direction, the first light-emitting control line is located on the side of the second scanning signal line away from the storage capacitor, the first scanning signal line is located on the side of the first light-emitting control line away from the storage capacitor, the third scanning signal line is located on the side of the storage capacitor in the opposite direction of the second direction, and the second light-emitting control line is located on the side of the third scanning signal line away from the storage capacitor.

14. The display substrate according to claim 13, wherein: In at least one circuit unit, the first initial signal line is arranged on a side of the first scanning signal line away from the storage capacitor.

15. The display substrate according to any one of claims 1 to 14, wherein: The driving circuit layer includes at least a blocking conductive layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate, the blocking conductive layer includes at least a plurality of bottom gate electrodes of oxide transistors, the first conductive layer includes at least a first plate of the storage capacitor and top gate electrodes of a plurality of oxide transistors, the second conductive layer includes at least a second plate of the storage capacitor and the first initial signal line, the third conductive layer includes at least a first pole and a second pole of a plurality of oxide transistors, and the fourth conductive layer includes at least the second initial signal line and a low-voltage power supply line.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. A method for preparing a display substrate, comprising: A driving circuit layer is formed on a substrate, the driving circuit layer comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and a low-voltage power supply line extending along a second direction, wherein the first direction and the second direction intersect, the circuit unit comprising at least a pixel driving circuit, the pixel driving circuit comprising a storage capacitor and a plurality of oxide transistors, the first initial signal line being configured to provide an initial voltage signal to the pixel driving circuit, the second initial signal line being connected to the first initial signal line, the first initial signal line and the second initial signal line forming a meshed connection structure; the plurality of unit columns comprising at least a first unit column, a second unit column, and a third unit column; A light-emitting structure layer is formed on the driving circuit layer, the light-emitting structure layer includes a plurality of light-emitting devices, the low-voltage power line is configured to provide a low power supply voltage signal to the light-emitting devices, the pixel driving circuits of the plurality of circuit units in the first unit column are connected to the first light-emitting device emitting a first color light, the pixel driving circuits of the plurality of circuit units in the second unit column are connected to the third light-emitting device emitting a third color light, the pixel driving circuits of the plurality of circuit units in the third unit column are connected to the second light-emitting device emitting a second color light, the first color, the second color, and the third color are different colors, the low-voltage power line is arranged in the first unit column and the second unit column, and the second initial signal line is arranged in the third unit column.

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