A method for manufacturing a heterojunction solar cell with a P-type tunneling structure

Abstract

This invention relates to a method for manufacturing a heterojunction solar cell with a P-type tunneling structure, comprising the following steps: Step A, preparing a solar cell with an N-type heterojunction film layer formed on the front side and a P-type tunneling structure film layer formed on the back side; Step B, forming a front transparent conductive film layer on the front side of the solar cell and a back transparent conductive film layer on the back side of the solar cell; Step C, laser processing the area on the back side of the solar cell to be covered with a back electrode to improve the crystallinity of the back transparent conductive film layer in that area; Step D, forming a front electrode on the front side of the solar cell and a back electrode on the back side of the solar cell. The purpose of this invention is to provide a method for manufacturing a heterojunction solar cell with a P-type tunneling structure, which can improve the electrical power loss caused by carrier transport on the back side of the cell, thereby improving cell efficiency and possessing high feasibility and mass production capability.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a heterojunction solar cell with a P-type tunneling structure. Background Technology

[0002] Heterojunction solar cells are increasingly favored by the photovoltaic industry due to their advantages such as high conversion efficiency, low processing temperature, high stability and low degradation rate, and represent the future development direction of high conversion efficiency solar cells.

[0003] Combining the tubular furnace process in PERC cells with the amorphous or microcrystalline passivation process in heterojunctions, finding an effective way to maintain high conversion efficiency and low overall equipment cost is of great significance for the further development of heterojunction cell technology. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a heterojunction solar cell with a P-type tunneling structure, which can improve the electrical power loss caused by carrier transport on the back of the cell, improve cell efficiency, and has high feasibility and mass production capability.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A method for manufacturing a heterojunction solar cell with a P-type tunneling structure includes the following steps: Step A, preparing a solar cell with an N-type heterojunction film layer formed on the front and a P-type tunneling structure film layer formed on the back; Step B, forming a front transparent conductive film layer on the front of the solar cell and a back transparent conductive film layer on the back of the solar cell; Step C, performing laser treatment on the area on the back of the solar cell to be covered with a back electrode to improve the crystallinity of the back transparent conductive film layer in that area; Step D, forming a front electrode on the front of the solar cell and a back electrode on the back of the solar cell.

[0007] Compared with the prior art, the advantages of the present invention are as follows:

[0008] (1) The battery structure with a front N-type heterojunction film layer and a back P-type tunneling structure film layer has the characteristics of good passivation effect and good conductivity, which not only ensures the open circuit voltage of the battery, but also improves the battery fill factor.

[0009] (2) Local laser treatment of the back transparent conductive film layer improves the vertical conduction performance of the back transparent conductive film layer, the P-type tunneling structure film layer, and the back electrode, thereby improving the fill factor and conversion efficiency of the battery.

[0010] (3) The back-side P-type tunneling structure film layer replaces the amorphous P layer or microcrystalline P layer of the traditional heterojunction, reducing the investment in plate PECVD equipment and significantly reducing the total cost of heterojunction equipment. Attached Figure Description

[0011] Figure 1 This is a schematic cross-sectional view of the manufacturing process in Embodiment 1 of the manufacturing method described in this invention.

[0012] Figure 2 This is a schematic cross-sectional view of the manufacturing process in Embodiment 1 of the manufacturing method described in this invention.

[0013] Figure 3 This is a schematic cross-sectional view of the manufacturing process in Embodiment 1 of the manufacturing method described in this invention.

[0014] Figure 4 This is a schematic cross-sectional view of the manufacturing process in Embodiment 1 of the manufacturing method described in this invention.

[0015] Figure 5 This is a schematic cross-sectional view of the manufacturing process in Embodiment 1 of the manufacturing method described in this invention.

[0016] Figure 6 This is a schematic cross-sectional view of the manufacturing process in Embodiment 1 of the manufacturing method described in this invention.

[0017] Figure 7.1 This is a schematic cross-sectional view of the manufacturing process in Embodiment 1 of the manufacturing method described in this invention.

[0018] Figure 7.2 yes Figure 7.1 A magnified schematic diagram of part I.

[0019] Figure 7.3 This is a schematic cross-sectional view of the manufacturing process in Embodiment 1 of the manufacturing method described in this invention.

[0020] Figure 7.4 yes Figure 7.3 A magnified schematic diagram of part II.

[0021] Figure 7.5 This is a schematic cross-sectional view of the manufacturing process in Embodiment 1 of the manufacturing method described in this invention.

[0022] Figure 7.6 yes Figure 7.5 A magnified schematic diagram of part III.

[0023] Figure 8 This is a schematic cross-sectional view of the manufacturing process in Embodiment 1 of the manufacturing method described in this invention. Detailed Implementation

[0024] A method for manufacturing a heterojunction solar cell with a P-type tunneling structure includes the following steps:

[0025] Step A: Prepare a solar cell with an N-type heterojunction film layer formed on the front and a P-type tunneling structure film layer formed on the back.

[0026] Step B: A front transparent conductive film layer is formed on the front side of the solar cell, and a back transparent conductive film layer is formed on the back side of the solar cell.

[0027] Step C: Laser treatment is performed on the area on the back of the solar cell to be covered with the back electrode to improve the crystallization rate of the transparent conductive film layer on the back of the area.

[0028] Step D: A front electrode is formed on the front side of the solar cell, and a back electrode is formed on the back side of the solar cell.

[0029] The specific method for step A is as follows:

[0030] Step a1: A tunneling oxide film layer and a P-type semiconductor film layer are sequentially formed on the back side of the semiconductor substrate;

[0031] Step a2: Texturing and cleaning the front side of the semiconductor substrate;

[0032] Step a3: Sequentially form a front intrinsic film layer and an N-type semiconductor film layer on the front side of the semiconductor substrate.

[0033] Before step a1, the front and back sides of the semiconductor substrate are polished and cleaned.

[0034] After completing step a1 and before proceeding to step a2, a protective layer is formed on the P-type semiconductor film. This protective layer can be removed during cleaning after texturing in step a2.

[0035] The method for preparing the tunneling oxide film layer is to form a tunneling oxide film layer on the back side of a semiconductor substrate by PECVD deposition oxidation, nitric acid oxidation, ozone oxidation or thermal oxidation.

[0036] The P-type semiconductor film is a P-type polycrystalline silicon film, and its preparation process is as follows: after forming an intrinsic polycrystalline silicon layer on a tunneling oxide film, high-temperature boron diffusion is performed; or, after forming an intrinsic polycrystalline silicon layer on a tunneling oxide film, a high-temperature annealing diffusion is performed after ion implantation of a boron source; or, a P-type amorphous silicon film or a P-type microcrystalline silicon film is formed on a tunneling oxide film by in-situ boron doping, and then a high-temperature annealing is performed to form a P-type polycrystalline silicon film; after forming the P-type polycrystalline silicon film, the borosilicate glass layer on the surface is removed.

[0037] The N-type semiconductor film is an N-type oxygen-doped microcrystalline silicon film.

[0038] The thickness of the tunneling oxide film is 1.2-2.0 nm; the thickness of the P-type semiconductor film is 5-35 nm; the thickness of the front intrinsic film is 3-10 nm; and the thickness of the N-type semiconductor film is 10-30 nm.

[0039] The relationship between the processing depth H of the laser treatment in step C and the thickness D of the transparent conductive film layer on the back and the thickness d of the P-type semiconductor film layer is H = XD + Yd, where X is 0.3-1 and Y is 0-0.5.

[0040] The laser used in step C is a picosecond pulsed laser with a wavelength between 400-700nm and a laser power of 15-40W.

[0041] The laser spot formed on the back of the solar cell by the laser treatment in step C is circular, elliptical, or rectangular, with a laser spot overlap rate of 0-30%.

[0042] In step C, the laser processing area on the surface of the back transparent conductive film layer overlaps with or is slightly wider than the back electrode area covering the back electrode; the slightly wider area is such that the back electrode area is located in the middle of the laser processing area, and the laser processing area not covered by the back electrode area forms a ring structure, the width of which is 5%-20% of the width of the back electrode area.

[0043] The present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0044] Example 1

[0045] like Figures 1 to 7.2 and Figure 8 The diagram shown is an embodiment of a method for manufacturing a heterojunction solar cell with a P-type tunneling structure provided by the present invention. The specific steps of this embodiment are as follows:

[0046] (1) Double-sided polishing of the N-type monocrystalline silicon wafer 1 is performed, and the wire-cut damage layer on the surface of the silicon wafer substrate 1 is removed with an alkaline solution. The alkaline solution can be potassium hydroxide, sodium hydroxide, or a mixture of the two. The reaction temperature of the alkaline solution is generally between 70℃ and 90℃, the reaction time is 15-45 min, and the single-sided polishing thickness is controlled at 5-20 μm. Then, standard RCA cleaning is performed to remove the residual alkaline solution on the surface of the silicon wafer 1 to obtain the desired finish. Figure 1 The structure shown.

[0047] (2) The back side of the double-sided polished silicon wafer 1 is oxidized to form an ultrathin oxide layer 2 (i.e., a tunneling oxide film layer), and then a P-type polycrystalline silicon layer 3.1 (i.e., a P-type semiconductor film layer) is grown to obtain the desired result. Figure 2 The structure shown.

[0048] The ultrathin oxide layer 2 can be formed by nitric acid solution oxidation, ozone oxidation or thermal oxidation. Preferably, in a tubular LPCVD equipment, the back side of the silicon wafer 1 is thermally oxidized for 30 minutes at 550-650°C to form an ultrathin silicon oxide layer with a thickness of 1.2-2.0 nm.

[0049] The P-type polycrystalline silicon layer 3.1 can be formed by depositing an intrinsic polycrystalline silicon layer followed by high-temperature boron diffusion, or by ion implantation into a boron source followed by high-temperature annealing diffusion, or by forming an amorphous silicon or microcrystalline P layer through in-situ boron doping, followed by high-temperature annealing to form the P-type polycrystalline layer. Preferably, in-situ boron doping is performed on the ultrathin oxide layer 2 using a PECVD device, followed by high-temperature annealing at 950-1100℃ to form the P-type polycrystalline silicon layer 3.1. The sheet resistance of the diffused P-type polycrystalline silicon layer is 80-400 Ω / □.

[0050] (3) Remove the borosilicate glass (BSG) layer formed on the surface 3.2. The cleaning solution used is acidic solution such as HF, with the mass percentage of HF acid being 1%-8% and the mass percentage of deionized water being 92%-99%. The silicon wafer is treated in the acid solution for 1-10 minutes, and the treatment temperature is 20℃-30℃.

[0051] (4) A silicon nitride protective layer 4 (i.e., a protective film layer) is deposited on the back side of the silicon wafer 1. In this invention, the silicon nitride protective layer 4 has strong resistance to alkaline solution corrosion and can resist alkaline corrosion in the texturing solution. Preferably, the thickness of the silicon nitride protective layer 4 is within a certain range. The silicon nitride protective layer 4 can be formed using thin film formation methods such as sputtering or CVD. In this embodiment, it is formed by deposition using the PECVD method to obtain the desired result. Figure 3 The structure shown.

[0052] (5) The front side of the silicon wafer 1 is textured using an alkaline solution mixed with a texturing additive. Because the back side of the silicon wafer 1 has a silicon nitride protective layer 4, a pyramidal texture will only form on the front side of the silicon wafer 1 in the solution. The texturing solution is a mixture of potassium hydroxide, texturing additive, and water, wherein the mass percentage of potassium hydroxide is 1%-5% and the mass percentage of the texturing additive is 0.5%-1%. The texturing time is 8-30 minutes and the texturing temperature is 75℃-85℃.

[0053] During the cleaning process following texturing on the front side, the silicon nitride protective layer 4 on the back side of silicon wafer 1 is also removed simultaneously. The cleaning solution used is an acidic solution such as HF, with HF acid accounting for 1%-8% by mass and deionized water accounting for 92%-99% by mass. The processing temperature is 20℃-30℃, and the removal time is determined based on the thickness and corrosion resistance of the silicon nitride protective layer 4, in order to obtain the desired results. Figure 4 The structure shown.

[0054] (6) An amorphous silicon intrinsic layer 5 (i.e., the front intrinsic film layer) and an oxygen-containing N-type microcrystalline silicon layer 6 (i.e., the N-type semiconductor film layer) are deposited on the pyramidal textured surface of the front side of the silicon wafer 1 to obtain the following: Figure 5 The structure is shown. The amorphous silicon intrinsic layer 5 is deposited using PECVD (plasma-enhanced chemical vapor deposition) at a deposition temperature of 150-300°C. A mixture of silane and hydrogen gas is introduced into the reaction chamber, with the silane content ranging from 10% to 99.9999%. The thickness of the amorphous silicon intrinsic layer 5 is 3-10 nm. The oxygen-containing N-type microcrystalline silicon layer 6 is deposited using PECVD, with the introduction of silane, hydrogen, carbon dioxide, and phosphine dopant gases. The deposition thickness is 5-15 nm, and the N-type dopant concentration reaches 1×10⁻⁶. 20 atoms / cm 3 above.

[0055] (7) Deposit transparent conductive layers 7 (i.e., front transparent conductive film layer and back transparent conductive film layer) on the front and back sides of the above silicon wafer to obtain the following: Figure 6 The structure is shown. The transparent conductive layer 7 can be an indium oxide film layer containing one or more different metal dopants (such as tin, tungsten, titanium, etc.), such as ITO, IWO, ITiO, etc.; or a zinc oxide film layer containing one or more different metal dopants (such as aluminum, indium, gallium, etc.), such as AZO, GZO, IZO, etc. Preferably, ITO (i.e., tin-doped indium oxide film layer) is used. Generally, the ITO layer is deposited by PVD (physical vapor deposition), the film transmittance is controlled between 90% and 99%, the sheet resistance is 10-100 Ω / □, and the film thickness is 50-150 nm.

[0056] (8) Local laser processing is performed on the transparent conductive layer 7 on the back side of the silicon wafer 1. The laser is generated by a pulsed laser with a wavelength of 400-700 nm and a pulse width of less than 10 nanoseconds, preferably less than 100 picoseconds. The laser spot formed on the back side of the silicon wafer is circular, elliptical, or rectangular, and the overlap rate of adjacent laser spots is 0-30%. Preferably, the overlap rate of adjacent laser spots is 0, and the laser power is 15-40W. The area processed by the laser on the transparent conductive layer 7 is related to the processed area 7a and the back side... The area and texture of the back electrode are roughly equal to or slightly wider. Local laser processing is performed on the transparent conductive layer 7 on the back of the silicon wafer 1. The processing depth H is related to the thickness D of the transparent conductive layer 7 and the thickness d of the P-type polycrystalline silicon layer 3.1 by the formula H = XD + Yd, where X ranges from (0.3-1) and Y ranges from (0-0.5). Preferably, in this embodiment, the laser processing depth is between 80-200 nm, X is 1, and Y is 0.3. Furthermore, the positions of the gate electrode printing and the laser processing positions basically coincide, specifically as follows... Figure 7.1 and Figure 7.2 .

[0057] (9) Metal gate electrodes 8 (i.e., front electrode and back electrode) are formed on the front and back sides of the silicon wafer to obtain, as shown in the figure. Figure 8 The structure shown facilitates subsequent IV testing.

[0058] Example 2

[0059] The difference between this embodiment and embodiment 1 is only that: in step (8), local laser processing is performed on the transparent conductive layer 7 on the back side of the silicon wafer 1. The relationship between the processing depth H and the thickness D of the conductive layer and the thickness d of the P-type polycrystalline silicon is H = XD + Yd, where X ranges from (0.3-1) and Y ranges from (0-0.5). In this embodiment, X is 1 and Y is 0. The depth of laser processing is between 50-150 nm, specifically as follows: Figure 7.3 and Figure 7.4 ;

[0060] Example 3

[0061] The difference between this embodiment and embodiment 1 is only that: in step (8), local laser processing is performed on the transparent conductive layer 7 on the back side of the silicon wafer 1. The relationship between the processing depth H and the thickness D of the conductive layer and the thickness d of the P-type polycrystalline silicon is H = XD + Yd, where X ranges from (0.3-1) and Y ranges from (0-0.5). In this embodiment, X is 0.5 and Y is 0. The depth of laser processing is between 50-80 nm, specifically as follows: Figure 7.5 and Figure 7.6 ;

[0062] Comparative Example 1

[0063] The only difference between this comparative example and Example 1 is that the laser treatment in step (8) is not performed.

[0064]

[0065] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention.

[0066] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations of the invention fall within the scope of the claims of the invention and their equivalents, the invention is also intended to include these modifications and variations.

Claims

1. A method for manufacturing a heterojunction solar cell with a P-type tunneling structure, characterized in that: It includes the following steps, Step A: Prepare a solar cell with an N-type heterojunction film layer formed on the front and a P-type tunneling structure film layer formed on the back; the P-type tunneling structure film layer is formed by sequentially forming a tunneling oxide film layer and a P-type semiconductor film layer on the back of a semiconductor substrate. Step B: A front transparent conductive film layer is formed on the front side of the solar cell, and a back transparent conductive film layer is formed on the back side of the solar cell. Step C: Laser treatment is performed on the area on the back of the solar cell to be covered with the back electrode to improve the crystallization rate of the transparent conductive film layer on the back of the area. Step D: A front electrode is formed on the front side of the solar cell, and a back electrode is formed on the back side of the solar cell. The relationship between the processing depth H of the laser treatment in step C and the thickness D of the back transparent conductive film layer and the thickness d of the P-type semiconductor film layer is H = XD + Yd, where X is 1, Y is 0-0.5, and Y is not 0.

2. The method for manufacturing a heterojunction solar cell with a P-type tunneling structure according to claim 1, characterized in that: The laser used in step C is a picosecond pulsed laser with a wavelength between 400-700nm and a laser power of 15-40W.

3. The method for manufacturing a heterojunction solar cell with a P-type tunneling structure according to claim 1, characterized in that: The laser spot formed on the back of the solar cell by the laser treatment in step C is circular, elliptical, or rectangular, with a laser spot overlap rate of 0-30%.

4. The method for manufacturing a heterojunction solar cell with a P-type tunneling structure according to claim 1, characterized in that: In step C, the laser processing area on the surface of the back transparent conductive film layer overlaps with or is slightly wider than the back electrode area covering the back electrode; the slightly wider area is such that the back electrode area is located in the middle of the laser processing area, and the laser processing area not covered by the back electrode area forms a ring structure, the width of which is 5%-20% of the width of the back electrode area.

5. The method for manufacturing a heterojunction solar cell with a P-type tunneling structure according to any one of claims 1-4, characterized in that: The specific method for step A is as follows: Step a1: A tunneling oxide film layer and a P-type semiconductor film layer are sequentially formed on the back side of the semiconductor substrate; Step a2: Texturing and cleaning the front side of the semiconductor substrate; Step a3: Sequentially form a front intrinsic film layer and an N-type semiconductor film layer on the front side of the semiconductor substrate.

6. The method for manufacturing a heterojunction solar cell with a P-type tunneling structure according to claim 5, characterized in that: After completing step a1 and before proceeding to step a2, a protective film is formed on the P-type semiconductor film layer, which is then removed during the cleaning process following texturing in step a2.

7. The method for manufacturing a heterojunction solar cell with a P-type tunneling structure according to claim 5, characterized in that: The P-type semiconductor film is a P-type polycrystalline silicon film, and its preparation process is as follows: after forming an intrinsic polycrystalline silicon layer on the tunneling oxide film, high-temperature boron diffusion is performed; or, after forming an intrinsic polycrystalline silicon layer on the tunneling oxide film, a boron source is implanted by ion and then high-temperature annealing diffusion is performed; or, a P-type amorphous silicon film or a P-type microcrystalline silicon film is formed on the tunneling oxide film by in-situ boron doping, and then high-temperature annealing is performed to form a P-type polycrystalline silicon film.

8. The method for manufacturing a heterojunction solar cell with a P-type tunneling structure according to claim 7, characterized in that: The N-type semiconductor film is an N-type oxygen-doped microcrystalline silicon film.

9. The method for manufacturing a heterojunction solar cell with a P-type tunneling structure according to claim 5, characterized in that: The thickness of the tunneling oxide film is 1.2-2.0 nm; the thickness of the P-type semiconductor film is 5-35 nm; the thickness of the front intrinsic film is 3-10 nm; and the thickness of the N-type semiconductor film is 10-30 nm.

Images