Encoding Method, Apparatus, Electronic Device and Storage Medium of LDPC Code

Abstract

The present invention discloses an encoding method, device, electronic device and storage medium for LDPC codes, which relates to the technical field of data encoding. The key points of its technical solution are: obtaining an initial parity-check matrix constructed from LDPC codes; constructing an auxiliary matrix for verifying whether there are short cycles in the initial parity-check matrix; when it is determined that short cycles need to be eliminated, performing a first verification mode to verify the elements of the auxiliary matrix to obtain a first result, and reconstructing the parity-check matrix of the LDPC code according to the first result until a parity-check matrix without short cycles is constructed; or, when it is determined that short cycles do not need to be completely eliminated, performing a second verification mode to verify the elements of the auxiliary matrix to obtain a second result, and reconstructing the parity-check matrix of the LDPC code according to the second result until a parity-check matrix with the number of short cycles meeting a preset condition is constructed; performing LDPC encoding based on the reconstructed parity-check matrix. The method reduces the resource overhead of the LDPC encoder and improves the performance of the code set.

Description

Technical Field

[0001] The present invention relates to the technical field of data encoding, and more specifically, to an encoding method, apparatus, electronic device, and storage medium for LDPC codes. Background Art

[0002] Low-Density Parity-Check (LDPC) codes are adopted as long codes in the 5G New Radio (NR) standard. This code has excellent error performance approaching the Shannon limit and flexible coding efficiency, etc. It is one of the most mainstream channel codes currently and is widely used in various communication protocols, which can significantly improve transmission reliability.

[0003] Traditional construction methods of LDPC parity-check matrices include the Gallager construction method, the Mackay construction method, the Davey construction method, etc. However, the problem with the above methods is that there are short cycles in the constructed LDPC parity-check matrices. The existence of short cycles will cause the degradation of code performance. The reason is that the decoding of LDPC codes uses an iterative decoding algorithm, and the premise for deriving this algorithm is that the information transmitted between each node is statistically independent. However, if there is a cycle in the bipartite graph corresponding to the parity-check matrix, the information sent by a certain node will be transmitted back to itself after a cycle length, which will cause the superposition of its own information, and then the assumption of information independence is violated, affecting the decoding accuracy, and thus reducing the code performance. But in actual application scenarios, the encoding process is implemented based on an encoder. Therefore, the prior art does not consider that the encoding performance may also be affected by the channel environment parameters of the encoder or the information transmission quality requirements, but only blindly eliminates the short cycles existing in the parity-check matrix, which increases the resource overhead of the LDPC encoder. Summary of the Invention

[0004] To solve the above deficiencies of the prior art, the present invention provides an encoding method, apparatus, electronic device, and storage medium for LDPC codes. The present invention constructs an auxiliary matrix through an initial parity-check matrix to judge short cycles. On this basis, combined with the channel state of the encoder, it is determined whether to eliminate short cycles when constructing the parity-check matrix, so as to adaptively control the generation process of the parity-check matrix, thereby avoiding some unnecessary execution processes and achieving the effect of reducing the resource overhead of the LDPC encoder.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] In a first aspect, an encoding method for LDPC codes is provided, and the method includes:

[0007] Obtain an initial parity-check matrix constructed by LDPC codes;

[0008] Construct an auxiliary matrix for verifying whether there are short cycles in the initial parity-check matrix based on the initial parity-check matrix and the transpose of the initial parity-check matrix;

[0009] When it is determined according to the channel state of the LDPC encoder that the short cycles in the initial parity-check matrix need to be eliminated, execute the first verification mode to verify the elements of the auxiliary matrix, obtain a first result, and reconstruct the parity-check matrix of the LDPC code according to the first result until a parity-check matrix without short cycles is constructed; or, when it is determined according to the channel state of the LDPC encoder that the short cycles in the initial parity-check matrix do not need to be completely eliminated, execute the second verification mode to verify the elements of the auxiliary matrix, obtain a second result, and reconstruct the parity-check matrix of the LDPC code according to the second result until a parity-check matrix with the number of short cycles meeting the preset condition is constructed, where the first verification mode is determined by the short-cycle elimination algorithm and the second verification mode is determined by the short-cycle limitation algorithm;

[0010] Perform LDPC encoding according to the reconstructed parity-check matrix.

[0011] In one implementation, the first verification mode is specifically: determine whether the elements of the auxiliary matrix other than the diagonal elements are all 1 or all 0, and use the determination result as the first result;

[0012] Reconstruct the parity-check matrix of the LDPC code by the random construction method according to the first result until a parity-check matrix without short cycles is constructed, including: when the first result is that the elements of the auxiliary matrix other than the diagonal elements are all 1 or all 0, the initial parity-check matrix has no short cycles, and perform LDPC encoding with the initial parity-check matrix;

[0013] When the first result is that the elements of the auxiliary matrix other than the diagonal elements are not all 1 or all 0, the initial parity-check matrix has short cycles, reconstruct the parity-check matrix of the LDPC code by the random construction method until a parity-check matrix without short cycles is constructed, and perform LDPC encoding with the reconstructed parity-check matrix.

[0014] In one implementation, the second verification mode is specifically: preset a number threshold for short cycles, count the number of elements greater than 1 in the auxiliary matrix other than the diagonal, compare the size between half of the number and the number threshold, and use the size result as the second result;

[0015] Reconstruct the parity-check matrix of the LDPC code by the random construction method according to the second result until a parity-check matrix with the number of short cycles meeting the preset condition is constructed, including:

[0016] When the number of half times of the second result is greater than or equal to the number threshold, the number of short cycles in the initial parity-check matrix exceeds or reaches the number threshold, and the preset condition is not satisfied. The parity-check matrix of the LDPC code is reconstructed by the random construction method until a parity-check matrix with the number of short cycles satisfying the preset condition is constructed, and LDPC encoding is performed with the reconstructed parity-check matrix.

[0017] When the number of half times of the second result is less than the number threshold, the number of short cycles in the initial parity-check matrix does not exceed the number threshold, and the preset condition is satisfied. LDPC encoding is performed with the initial parity-check matrix.

[0018] In one implementation, the method further includes: constructing an initial parity-check matrix of the LDPC code by improving the progressive edge-growth algorithm based on the method of optimizing the short-cycle distribution.

[0019] In one implementation, constructing an initial parity-check matrix of the LDPC code by the progressive edge-growth algorithm based on the method of optimizing the short-cycle distribution includes:

[0020] S11, taking the first column of the initial parity-check matrix as the current column, and setting the variable node to 0;

[0021] S12, putting non-zero elements corresponding to any degree in the degree sequence of the variable node in the current column. Specifically: S121, in the current initial parity-check matrix, select the row with the smallest row weight and put the first non-zero element, and increment the variable node by one; S122, count the number of short cycles contained in each row position as an alternative, sort them in ascending order according to the cycle length of the short cycles, gradually select the position with the smallest number of short cycles, and put a non-zero element in this position, and increment the variable node by one; S123, if the variable node is equal to the degree of the variable node, increment the current column by one and set the variable node to zero, and set the column after incrementing the current column as the current column, and continue with step S13. If the variable node is not equal to the degree of the variable node, loop through steps S121 - S123;

[0022] S13, if the column after incrementing the current column set as the current column is equal to the number of columns of the initial parity-check matrix plus one, the construction ends, otherwise return to step S121 to continue execution until the column after incrementing the current column set as the current column is equal to the number of columns of the initial parity-check matrix plus one.

[0023] In a second aspect, an encoding device for an LDPC code is further provided. The device includes:

[0024] A matrix acquisition module, configured to acquire an initial parity-check matrix constructed by the LDPC code;

[0025] An auxiliary matrix construction module, configured to construct an auxiliary matrix for verifying whether there are short cycles in the initial parity-check matrix according to the initial parity-check matrix and the transpose of the initial parity-check matrix;

[0026] A processing module, configured to, when short cycles in an initial parity-check matrix obtained according to the channel state of an LDPC encoder need to be eliminated, execute a first verification mode to verify elements of the auxiliary matrix, obtain a first result, and reconstruct the parity-check matrix of the LDPC code according to the first result until a parity-check matrix without short cycles is constructed; or, when short cycles in the initial parity-check matrix obtained according to the channel state of the LDPC encoder do not need to be completely eliminated, execute a second verification mode to verify elements of the auxiliary matrix, obtain a second result, and reconstruct the parity-check matrix of the LDPC code according to the second result until a parity-check matrix with the number of short cycles meeting a preset condition is constructed, where the first verification mode is determined by a short-cycle elimination algorithm and the second verification mode is determined by a short-cycle limitation algorithm;

[0027] An encoding module, configured to perform LDPC encoding according to the reconstructed parity-check matrix.

[0028] In an implementation, the apparatus further includes: a matrix optimization module, configured to improve the PEG algorithm based on a method of optimizing the short-cycle distribution to construct an initial parity-check matrix of the LDPC code.

[0029] In an implementation, the matrix optimization module is specifically further configured to implement the following steps:

[0030] S11, use the first column of the initial parity-check matrix as the current column, and set the variable node to 0;

[0031] S12, place a non-zero element corresponding to any degree in the degree sequence of the variable node in the current column. Specifically: S121, in the current initial parity-check matrix, select the row with the smallest row weight to place the first non-zero element, and increment the variable node by 1; S122, count the number of short cycles included in each row position as an alternative, sort them in ascending order of the cycle length of the short cycles, gradually select the position with the smallest number of short cycles, place a non-zero element at this position, and increment the variable node by 1; S123, if the variable node is equal to the degree of the variable node, increment the current column by 1 and set the variable node to 0, set the column after incrementing the current column by 1 as the current column, and continue with step S13. If the variable node is not equal to the degree of the variable node, loop through steps S121 - S123;

[0032] S13, if the column after incrementing the current column by 1 set as the current column is equal to the number of columns of the initial parity-check matrix plus 1, the construction ends; otherwise, return to step S121 to continue execution until the column after incrementing the current column by 1 set as the current column is equal to the number of columns of the initial parity-check matrix plus 1.

[0033] In a third aspect, an electronic device is also provided. The electronic device includes: one or more processors; a storage device storing one or more programs thereon; when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the LDPC code encoding method as described in the first aspect of the present application.

[0034] In a fourth aspect, a computer-readable medium is also provided, having a computer program stored thereon, wherein when the program is executed by a processor, the LDPC code encoding method as described in the first aspect of the present application is implemented.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The present invention constructs an auxiliary matrix through an initial parity-check matrix to judge short cycles. On this basis, combined with the channel state of the encoder, it is determined whether short cycles need to be eliminated when constructing the parity-check matrix, so as to adaptively regulate the generation process of the parity-check matrix, thereby avoiding some unnecessary execution processes and achieving the effect of reducing the resource overhead of the LDPC encoder.

[0037] 2. The present invention also makes further adjustments on the basis of existing parity-check matrix construction methods (such as the Gallager construction method, the Mackay construction method, etc.), that is, gradually optimizing the distribution of the number of short cycles where non-zero elements are located in the parity-check matrix, so that the Tanner graph corresponding to the LDPC code has fewer short cycles, thereby simplifying the subsequent calculation process of eliminating short cycles for the parity-check matrix and improving the performance of the code set. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, form a part of this application, and do not limit the embodiments of the present invention.

[0039] Figure 1 A flowchart showing the encoding method of an LDPC code provided by an embodiment of the present invention;

[0040] Figure 2 A schematic diagram showing the improvement principle of the method for optimizing the short cycle distribution provided by an embodiment of the present invention;

[0041] Figure 3 A schematic block diagram showing the principle of an LDPC code encoding device provided by an embodiment of the present invention;

[0042] Figure 4 A schematic diagram showing the result of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] To make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to embodiments and the accompanying drawings. The illustrative embodiments of the present invention and the description thereof are only used to explain the present invention and are not intended to limit the present invention.

[0044] It should be noted that the term "comprising" or "may comprise" that can be used in various embodiments of the present application indicates the presence of the claimed functions, operations or elements, and does not limit the addition of one or more functions, operations or elements. In addition, as used in various embodiments of the present application, the terms "comprising", "having" and their cognates are only intended to represent specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as first excluding the existence or addition of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0045] In addition, terms such as "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0046] An embodiment of the present invention provides a method for encoding an LDPC code. An auxiliary matrix is constructed through an initial parity-check matrix to judge short cycles. On this basis, combined with the channel state of the encoder, it is determined whether short cycles need to be eliminated when constructing the parity-check matrix, so as to adaptively control the generation process of the parity-check matrix, thereby avoiding some unnecessary execution processes and achieving the effect of reducing the resource overhead of the LDPC encoder.

[0047] The method provided in this embodiment will be described in detail below with reference to specific embodiments. As Figure 1 shown, a method for encoding an LDPC code is provided, and the method includes:

[0048] S101, obtaining an initial parity-check matrix constructed from an LDPC code.

[0049] In this embodiment, the construction process of the initial parity-check matrix is well-known to those skilled in the art, so it will not be elaborated in this embodiment.

[0050] S102, constructing an auxiliary matrix for verifying whether there are short cycles in the initial parity-check matrix according to the initial parity-check matrix and the transpose of the initial parity-check matrix.

[0051] In this embodiment, the construction process of constructing an auxiliary matrix for verifying whether there is a short cycle in the initial parity-check matrix based on the initial parity-check matrix and the transpose of the initial parity-check matrix is a well-known technique to those skilled in the art, so it will not be elaborated in this embodiment.

[0052] S103, when it is determined according to the channel state of the LDPC encoder that the short cycles in the initial parity-check matrix need to be eliminated, execute the first verification mode to verify the elements of the auxiliary matrix to obtain a first result, and reconstruct the parity-check matrix of the LDPC code according to the first result until a parity-check matrix without short cycles is constructed; or, when it is determined according to the channel state of the LDPC encoder that the short cycles in the initial parity-check matrix do not need to be completely eliminated, execute the second verification mode to verify the elements of the auxiliary matrix to obtain a second result, and reconstruct the parity-check matrix of the LDPC code according to the second result until a parity-check matrix with the number of short cycles meeting the preset condition is constructed, where the first verification mode is determined by the short-cycle elimination algorithm and the second verification mode is determined by the short-cycle limitation algorithm.

[0053] In this embodiment, as known from the prior art, the occurrence of a short cycle of length 4 in the LDPC bipartite graph is reflected in its parity-check matrix as the positions where any two rows (or two columns) are both 1 exceeding two. Therefore, to avoid the occurrence of short cycles of length 4, it is necessary to ensure that the inner product of any two rows (or two columns) is not greater than 1. Because an inner product equal to 0 means that there is no same position of 1 in any two rows (or two columns), an inner product equal to 1 means that there is one position of 1 at the same time, and an inner product greater than 1 means that there are two or more positions of 1 at the same time.

[0054] Therefore, in this embodiment, starting from the channel state of the LDPC encoder, it is determined whether the short cycles in the parity-check matrix should be completely eliminated or partially retained and partially eliminated, so as to save the resource overhead of the encoder.

[0055] Therefore, for the first verification mode, it specifically includes: judging whether the elements of the auxiliary matrix other than the diagonal elements are all 1 or all 0, and using the judgment result as the first result;

[0056] Reconstructing the parity-check matrix of the LDPC code by the random construction method according to the first result until a parity-check matrix without short cycles is constructed, including: when the first result is that the elements of the auxiliary matrix other than the diagonal elements are all 1 or all 0, the initial parity-check matrix has no short cycles, and LDPC encoding is performed with the initial parity-check matrix;

[0057] When the first result is that the elements of the auxiliary matrix other than the diagonal elements are not all 1 or all 0, the initial parity-check matrix has short cycles, and the parity-check matrix of the LDPC code is reconstructed by the random construction method until a parity-check matrix without short cycles is constructed, and LDPC encoding is performed with the reconstructed parity-check matrix.

[0058] For the second verification mode, specifically: preset a threshold value for the number of short cycles, count the number of elements other than the diagonal elements in the auxiliary matrix that are greater than 1, compare the size between half of the number and the threshold value of the number, and use the size result as the second result;

[0059] According to the second result, reconstruct the parity-check matrix of the LDPC code by the random construction method until a parity-check matrix with the number of short cycles meeting the preset conditions is constructed, including:

[0060] When the second result is that half of the number is greater than or equal to the threshold value of the number, the number of short cycles in the initial parity-check matrix exceeds or reaches the threshold value, not meeting the preset conditions. Reconstruct the parity-check matrix of the LDPC code by the random construction method until a parity-check matrix with the number of short cycles meeting the preset conditions is constructed, and perform LDPC encoding with the reconstructed parity-check matrix;

[0061] When the second result is that half of the number is less than the threshold value of the number, the number of short cycles in the initial parity-check matrix does not exceed the threshold value, meeting the preset conditions, and perform LDPC encoding with the initial parity-check matrix.

[0062] S104, perform LDPC encoding according to the reconstructed parity-check matrix.

[0063] Specifically, performing LDPC encoding according to the parity-check matrix is well-known technology to those skilled in the art, so no redundant elaboration is made here.

[0064] In one embodiment, the method further includes: improving the progressive edge-growth algorithm based on a method of optimizing the short-cycle distribution to construct the initial parity-check matrix of the LDPC code.

[0065] Since the existence of short cycles in the LDPC code will cause the decoder not to converge quickly [35, 36, 37], when there are no short cycles in the Tanner graph corresponding to the LDPC code, the sum-product (SP) decoding algorithm can achieve the best decoding. On the contrary, if there are short cycles in the Tanner graph, the probability obtained by the sum-product (SP) algorithm decoding is not the true posterior probability (because the independence assumption in the iterative process does not hold. In this case, the decoding cannot reach the maximum a posteriori probability decoding symbol by symbol, so the existence of short cycles has a very important impact on the performance of the LDPC code. To address this problem, this embodiment proposes a design method for a low-complexity 4-cycle elimination LDPC code. This method is based on the protograph and uses a simple copy-permutation algorithm, which can be applied to LDPC codes with different code rates. The simulation results in the AWGN channel show that the performance of the multi-code rate LDPC code has a certain improvement compared with the random code, and the error performance is better than that of the PEG code within a certain signal-to-noise ratio range.

[0066] Since there should not be too many short cycles in the bipartite graphs corresponding to good LDPC codes and concatenated convolutional codes, an algorithm for constructing a parity-check matrix of LDPC codes with a large girth based on improving the short-cycle distribution is introduced below. As Figure 2 shown, assuming that the positions of the non-zero elements in the first 4 columns of H are already determined, the problem lies in how to determine the position of the second non-zero element in the 5th column so that g v5 is as large as possible. For this purpose, in this embodiment, for each alternative position h i，5 = 0 in the 5th column, the number of 4-cycles, 6-cycles, and 8-cycles formed by [1, 4] and the current parity-check matrix H is counted. According to Figure 2 the shown alternative position cycle number distribution diagram, it can be obtained that the number of 4-cycles in the first row of the 5th column is the least compared with other alternative positions in the 5th column. Therefore, take h 1,5 = 1.

[0067] Correspondingly, based on Figure 2 and the above embodiment, the steps of a specific improved progressive edge growth algorithm are implemented as follows: S11, take the first column of the initial parity-check matrix as the current column, and set the variable node to 0;

[0068] S12, put non-zero elements corresponding to any degree in the degree sequence of the variable node in the current column. Specifically: S121, in the current initial parity-check matrix, select the row with the smallest row weight and put the first non-zero element, and increment the variable node by one; S122, count the number of short cycles contained in each alternative row position, sort them in ascending order of the cycle length of the short cycles, gradually select the position with the least number of short cycles, and put a non-zero element at this position, and increment the variable node by one; S123, if the variable node is equal to the degree of the variable node, increment the current column by one and set the variable node to zero, and set the column after incrementing the current column by one as the current column, and continue with step S13. If the variable node is not equal to the degree of the variable node, loop through steps S121 - S123;

[0069] S13, if the column set as the current column after incrementing the current column by one is equal to the column of the initial parity-check matrix plus one, the construction ends. Otherwise, return to step S121 and continue to execute until the column set as the current column after incrementing the current column by one is equal to the column of the initial parity-check matrix plus one.

[0070] Based on the steps S11 - S13 provided in the above embodiments, in this embodiment, a statistical comparison of the local girth of the constructed LDPC code and the corresponding PEG code is carried out. First, a regular LDPC code with a code length of 504, a column weight of 3, and a code rate of 0.5 is constructed. The code length of the PEG code selected for comparison is 504, and the column weight is 3, among which 8 rows have a row weight of 7 and 244 rows have a row weight of 6. It is statistically obtained that there are 483 variable nodes with a local girth of 8 and 21 variable nodes with a local girth of 10 in the constructed code. In the PEG code, except for one variable node with a local girth of 10, the local girths of the remaining variable nodes are all 8, and their average local girths are 8.083333 and 8.003968 respectively. Therefore, the LDPC code constructed through the loop number distribution optimization in this embodiment has a better local girth distribution. In addition, a regular LDPC code with a code length of 1008, a column weight of 3, and a code rate of 0.5 is constructed. The code length of the PEG code selected for comparison is 1008, and the column weight is 3, among which 17 rows have a row weight of 7 and 487 rows have a row weight of 6. It is statistically found that the proportion of variable nodes with a local girth of 8 in both is 14.8810%, and the average local girth is 9.702371.

[0071] The present invention also provides an encoding device for an LDPC code, which can be used to execute the encoding method of the LDPC code described in any one of the above embodiments of the present invention.

[0072] Please refer to Figure 3 , which shows a schematic block diagram of an encoding device for an LDPC code provided by an embodiment of the present invention. The device includes:

[0073] A matrix acquisition module 310, configured to acquire an initial parity - check matrix constructed from an LDPC code;

[0074] An auxiliary matrix construction module 320, configured to construct an auxiliary matrix for verifying whether there are short loops in the initial parity - check matrix according to the initial parity - check matrix and the transpose of the initial parity - check matrix;

[0075] A processing module 330, configured to, when it is determined according to the channel state of the LDPC encoder that the short loops in the initial parity - check matrix need to be eliminated, execute a first verification mode to verify the elements of the auxiliary matrix to obtain a first result, and reconstruct the parity - check matrix of the LDPC code according to the first result until a parity - check matrix without short loops is constructed; or, when it is determined according to the channel state of the LDPC encoder that the short loops in the initial parity - check matrix do not need to be completely eliminated, execute a second verification mode to verify the elements of the auxiliary matrix to obtain a second result, and reconstruct the parity - check matrix of the LDPC code according to the second result until a parity - check matrix with the number of short loops meeting a preset condition is constructed, where the first verification mode is determined by a short - loop elimination algorithm and the second verification mode is determined by a short - loop restriction algorithm;

[0076] An encoding module 340 for performing LDPC encoding based on the reconstructed parity-check matrix.

[0077] In one embodiment, the apparatus further includes: a matrix optimization module for improving the PEG algorithm based on optimizing the short cycle distribution to construct an initial parity-check matrix of the LDPC code.

[0078] In one embodiment, the matrix optimization module is specifically further configured to implement the following steps:

[0079] S11, taking the first column of the initial parity-check matrix as the current column and setting the variable node to 0;

[0080] S12, placing in the current column a number of non-zero elements corresponding to any degree in the degree sequence of the variable node. Specifically: S121, in the current initial parity-check matrix, selecting the row with the smallest row weight to place the first non-zero element and incrementing the variable node by one; S122, counting the number of short cycles contained in each alternative row position, sorting them in ascending order of the cycle length of the short cycles, gradually selecting the position with the fewest short cycles, placing a non-zero element at this position, and incrementing the variable node by one; S123, if the variable node is equal to the degree of the variable node, incrementing the current column by one and setting the variable node to zero, setting the column after incrementing the current column as the current column, and continuing with step S13. If the variable node is not equal to the degree of the variable node, looping through steps S121 - S123;

[0081] S13, if the column after incrementing the current column set as the current column is equal to the column of the initial parity-check matrix plus one, the construction ends. Otherwise, return to step S121 to continue execution until the column after incrementing the current column set as the current column is equal to the column of the initial parity-check matrix plus one.

[0082] The LDPC code encoding apparatus in the embodiments of the present application and the above Figure 1 shown LDPC code encoding method are inventions under the same concept. Through the above detailed description of the LDPC code encoding method, those skilled in the art can clearly understand the implementation process of the LDPC code encoding apparatus in this embodiment. Therefore, for the sake of brevity of the specification, it will not be elaborated here.

[0083] Correspondingly, the LDPC code encoding apparatus provided in this embodiment determines short cycles by constructing an auxiliary matrix from the initial parity-check matrix. On this basis, combined with the channel state of the encoder, it decides whether to eliminate short cycles when constructing the parity-check matrix, thereby adaptively regulating the generation process of the parity-check matrix to avoid some unnecessary execution processes and achieve the effect of reducing the resource overhead of the LDPC encoder.

[0084] Based on the existing check matrix construction methods (such as Gallager construction method, Mackay construction method, etc.), the present invention has made further adjustments, that is, gradually optimizing the distribution of the number of short cycles where non-zero elements are located in the check matrix, so that the Tanner graph corresponding to the LDPC code has fewer short cycles, and thus making the subsequent calculation process of eliminating short cycles for the check matrix more simplified to improve the performance of the code set.

[0085] Based on the same inventive concept as the LDPC code encoding method in the foregoing embodiment, in another embodiment of the present invention, an electronic device is further provided. Please refer to Figure 4 , Figure 4 FIG. shows a schematic structural diagram of an electronic device provided by an embodiment of the present application. Among them, the electronic device 400 includes a processor 410, a memory 420, a communication interface 430, and at least one communication bus for connecting the processor 410, the memory 420, and the communication interface 430. The memory 420 includes, but is not limited to, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (PROM), or a portable read-only memory (CD-ROM). The memory 420 is used for relevant instructions and data.

[0086] The communication interface 430 is used to receive and send data. The processor 410 can be one or more CPUs. When the processor 410 is a single CPU, the CPU can be a single-core CPU or a multi-core CPU. The processor 410 in the electronic device 400 is used to read one or more programs 421 stored in the memory 420 and perform the following operations: obtaining an initial check matrix constructed by the LDPC code; an auxiliary matrix construction module 320, configured to construct an auxiliary matrix for verifying whether there are short cycles in the initial check matrix according to the initial check matrix and the transpose of the initial check matrix; when it is obtained according to the channel state of the LDPC encoder that the short cycles of the initial check matrix need to be eliminated, performing a first verification mode to verify the elements of the auxiliary matrix, obtaining a first result, and reconstructing the check matrix of the LDPC code according to the first result until a check matrix without short cycles is constructed; or, when it is obtained according to the channel state of the LDPC encoder that the short cycles of the initial check matrix do not need to be completely eliminated, performing a second verification mode to verify the elements of the auxiliary matrix, obtaining a second result, and reconstructing the check matrix of the LDPC code according to the second result until a check matrix with the number of short cycles meeting a preset condition is constructed, where the first verification mode is determined by a short cycle elimination algorithm, and the second verification mode is determined by a short cycle limitation algorithm; performing LDPC encoding according to the reconstructed check matrix.

[0087] It should be noted that the specific implementation of each operation can be as described above Figure 1Corresponding descriptions of the foregoing method embodiments, the electronic device 400 may be used to execute the LDPC code encoding method in the foregoing method embodiments of this application, which will not be elaborated herein specifically.

[0088] Based on the same inventive concept as the LDPC code encoding method in the foregoing embodiments, in another embodiment of the present invention, a computer-readable storage medium is further provided. The computer-readable storage medium is a memory device in a computer device and is used to store programs and data. It can be understood that the computer-readable storage medium here may include both the built-in storage medium in the computer device and, of course, the extended storage medium supported by the computer device. The computer-readable storage medium provides a storage space that stores the operating system of the terminal. And, one or more instructions suitable for being loaded and executed by the processor are stored in this storage space. These instructions may be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here may be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. One or more instructions stored in the computer-readable storage medium can be loaded and executed by the processor to implement the corresponding steps of the LDPC code encoding method in the foregoing embodiments. Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0089] The specific embodiments described above further elaborate the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A coding method for LDPC codes, characterized in that, The method includes: Obtaining an initial parity-check matrix constructed by an LDPC code; Constructing an auxiliary matrix for verifying whether there are short cycles in the initial parity-check matrix according to the initial parity-check matrix and the transpose of the initial parity-check matrix; Determining whether all short cycles in the initial parity-check matrix are eliminated according to the channel state of the LDPC encoder to save the resource overhead of the encoder. Wherein, when it is obtained according to the channel state of the LDPC encoder that the short cycles in the initial parity-check matrix need to be eliminated, execute the first verification mode to verify the elements of the auxiliary matrix to obtain a first result, and reconstruct the parity-check matrix of the LDPC code according to the first result until a parity-check matrix without short cycles is constructed; or, when it is obtained according to the channel state of the LDPC encoder that the short cycles in the initial parity-check matrix do not need to be completely eliminated, execute the second verification mode to verify the elements of the auxiliary matrix to obtain a second result, and reconstruct the parity-check matrix of the LDPC code according to the second result until a parity-check matrix with the number of short cycles meeting the preset condition is constructed, where the first verification mode is determined by a short-cycle elimination algorithm, and the second verification mode is determined by a short-cycle limitation algorithm; Performing LDPC encoding according to the reconstructed parity-check matrix; The specific first verification mode is: judging whether the elements of the auxiliary matrix other than the diagonal elements are all 1 or all 0, and using the judgment result as the first result; When the first result is that the elements of the auxiliary matrix other than the diagonal elements are all 1 or all 0, there are no short cycles in the initial parity-check matrix, and LDPC encoding is performed using the initial parity-check matrix; When the first result is that the elements of the auxiliary matrix other than the diagonal elements are not all 1 or all 0, there are short cycles in the initial parity-check matrix, and the parity-check matrix of the LDPC code is reconstructed by a random construction method until a parity-check matrix without short cycles is constructed, and LDPC encoding is performed using the reconstructed parity-check matrix; The specific second verification mode is: presetting a number threshold for short cycles, counting the number of elements greater than 1 in the auxiliary matrix other than the diagonal, and comparing the size between half of the number and the number threshold as the second result; When the second result is that half of the number is greater than or equal to the number threshold, the number of short cycles in the initial parity-check matrix exceeds or reaches the number threshold and does not meet the preset condition, and the parity-check matrix of the LDPC code is reconstructed by a random construction method until a parity-check matrix with the number of short cycles meeting the preset condition is constructed, and LDPC encoding is performed using the reconstructed parity-check matrix; When the second result is that half of the number is less than the number threshold, the number of short cycles in the initial parity-check matrix does not exceed the number threshold and meets the preset condition, and LDPC encoding is performed using the initial parity-check matrix.

2. The encoding method of the LDPC code according to claim 1, characterized in that, The method further includes: improving the progressive edge growth algorithm based on a method of optimizing the short-cycle distribution to construct an initial parity-check matrix of an LDPC code.

3. The encoding method of the LDPC code according to claim 2, characterized in that, Improving the progressive edge growth algorithm based on a method of optimizing the short-cycle distribution to construct an initial parity-check matrix of an LDPC code, including: S11, taking the first column of the initial parity-check matrix as the current column, and setting the variable node to 0; S12. Place the non-zero elements corresponding to any degree in the degree sequence of the variable nodes in the current column, including: S121. In the current initial parity-check matrix, select the row with the minimum row weight and place the first non-zero element, and increment the variable node by one; S122. Count the number of short cycles contained in each alternative row position, sort them in ascending order according to the cycle length of the short cycles, and gradually select the position with the minimum number of short cycles, place the non-zero element at this position, and increment the variable node by one; S123. If the variable node is equal to the degree of the variable node, increment the current column by one and set the variable node to zero, and set the column after incrementing the current column as the current column, and continue with step S13. If the variable node is not equal to the degree of the variable node, loop through steps S121 - S123; S13. If the column set as the current column after incrementing the current column is equal to the column of the initial parity-check matrix plus one, the construction is completed. Otherwise, go back to step S121 and continue to execute until the column set as the current column after incrementing the current column is equal to the column of the initial parity-check matrix plus one.

4. An encoding apparatus for LDPC codes, characterized in that, The device includes: A matrix acquisition module for acquiring the initial parity-check matrix constructed by the LDPC code; An auxiliary matrix construction module for constructing an auxiliary matrix for verifying whether there are short cycles in the initial parity-check matrix according to the initial parity-check matrix and the transpose of the initial parity-check matrix; A processing module for determining whether all short cycles in the initial parity-check matrix are eliminated according to the channel state of the LDPC encoder to save the resource overhead of the encoder. Among them, when it is obtained according to the channel state of the LDPC encoder that the short cycles of the initial parity-check matrix need to be eliminated, execute the first verification mode to verify the elements of the auxiliary matrix to obtain a first result, and reconstruct the parity-check matrix of the LDPC code according to the first result until a parity-check matrix without short cycles is constructed; or, when it is obtained according to the channel state of the LDPC encoder that the short cycles of the initial parity-check matrix do not need to be completely eliminated, execute the second verification mode to verify the elements of the auxiliary matrix to obtain a second result, and reconstruct the parity-check matrix of the LDPC code according to the second result until a parity-check matrix with the number of short cycles meeting the preset conditions is constructed, where the first verification mode is determined by the short cycle elimination algorithm, and the second verification mode is determined by the short cycle limitation algorithm; An encoding module for performing LDPC encoding according to the reconstructed parity-check matrix; The first verification mode is specifically: determining whether the remaining elements in the auxiliary matrix except the diagonal elements are all 1 or all 0, and using the determination result as the first result; When the first result is that the remaining elements in the auxiliary matrix except the diagonal elements are all 1 or all 0, there are no short cycles in the initial parity-check matrix, and LDPC encoding is performed with the initial parity-check matrix; When the first result is that the remaining elements in the auxiliary matrix except the diagonal elements are not all 1 or all 0, there are short cycles in the initial parity-check matrix, and the parity-check matrix of the LDPC code is reconstructed by the random construction method until a parity-check matrix without short cycles is constructed, and LDPC encoding is performed with the reconstructed parity-check matrix; The specific second verification mode is as follows: preset a threshold for the number of short cycles, count the number of elements other than the diagonal elements in the auxiliary matrix that are greater than 1, and compare the size between half of this number and the threshold for the number as the second result; When the second result is that half of the number is greater than or equal to the threshold for the number, the number of short cycles in the initial check matrix exceeds or reaches the threshold for the number, and it does not meet the preset conditions. The check matrix of the LDPC code is reconstructed by the random construction method until a check matrix with the number of short cycles meeting the preset conditions is constructed, and LDPC coding is performed with the reconstructed check matrix; When the second result is that half of the number is less than the threshold for the number, the number of short cycles in the initial check matrix does not exceed the threshold for the number, and it meets the preset conditions. LDPC coding is performed with the initial check matrix.

5. The encoding apparatus for LDPC codes according to claim 4, characterized in that, The device further includes: a matrix optimization module, configured to construct an initial check matrix of an LDPC code by improving the progressive edge growth algorithm based on a method of optimizing the short cycle distribution.

6. The encoding apparatus for LDPC codes according to claim 5, characterized in that, The matrix optimization module is specifically further configured to implement the following steps: S11, use the first column of the initial check matrix as the current column, and set the variable node to 0; S12, place the number of non-zero elements corresponding to any degree in the degree sequence of the variable node in the current column, including: S121, in the current initial check matrix, select the row with the smallest row weight and place the first non-zero element, and increment the variable node by one; S122, count the number of short cycles included in each row position as an alternative, sort them in ascending order according to the cycle length of the short cycles, gradually select the position with the smallest number of short cycles, and place a non-zero element at this position, and increment the variable node by one; S123, if the variable node is equal to the degree of the variable node, increment the current column by one and set the variable node to zero, and set the column after incrementing the current column as the current column, and continue with step S13. If the variable node is not equal to the degree of the variable node, loop through steps S121 - S123; S13, if the column set as the current column after incrementing the current column is equal to the number of columns of the initial check matrix plus one, the construction ends, otherwise return to step S121 and continue to execute until the column set as the current column after incrementing the current column is equal to the number of columns of the initial check matrix plus one.

7. An electronic device, characterized in that, The electronic device includes one or more processors; a storage device on which one or more programs are stored; when the one or more programs are executed by the one or more processors, the one or more processors implement the LDPC code encoding method according to any one of claims 1 to 3.

8. A computer-readable medium, characterized in that, A computer program is stored thereon, wherein when the program is executed by a processor, the LDPC code encoding method according to any one of claims 1 to 3 is implemented.

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