Technology for indicating line activation

Abstract

This application relates to techniques for indicating row activation. A memory device can receive an indication associated with an activation command, which enables the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include the location of the next row as part of the access of the activation command. The indication may be included in a previous activation command or a precharge command. The memory device can begin the activation operation of the next row before the precharge operation of the current row is completed. The memory device can receive the activation command for the next row after receiving the indication, and can complete the activation operation after receiving the activation command.

Description

[0001] Cross-reference

[0002] This patent application is the national phase application of International Patent Application No. PCT / US2022 / 076275, filed September 12, 2022, entitled "Technologies for Indicating Row Activation," filed by Milichigni et al., claiming priority to U.S. Patent Application No. 17 / 511,314, filed October 26, 2021, entitled "Technologies for Indicating Row Activation," each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to techniques for indicating row activation. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to support one of two states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of them. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program states into the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, chalcogenide memory technology, and so on. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for extended periods, even in the absence of external power. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from external power. Summary of the Invention

[0006] A method for memory operation is described. The method may include: receiving a first activation command to open a first row of memory cells in a first subarray of a memory bank of a memory device; receiving an instruction based at least in part on receiving the first activation command and prior to receiving a second activation command for a second subarray of the memory bank; activating a portion of the second subarray of the memory bank based at least in part on receiving the instruction; and receiving the second activation command to open a second row of memory cells in the second subarray of the memory bank after activating the portion of the second subarray.

[0007] A method for memory operation is described. The method may include: transmitting a first activation command to open a first row of memory cells in a first subarray of a memory bank of a memory device; transmitting an instruction based at least in part on transmitting the first activation command and prior to transmitting a second activation command for a second subarray of the memory bank; and transmitting the second activation command to open a second row of memory cells in a second subarray of the memory bank.

[0008] A memory device is described. The memory device may include: a storage bank of memory cells, comprising one or more subarrays; and a controller coupled to the storage bank and configured to cause the memory device to: receive a first activation command to open a first row of memory cells in a first subarray of the storage bank; receive an instruction for the second activation command at least in part based on receiving the first activation command and prior to receiving a second activation command for a second subarray of the storage bank; activate a portion of a second subarray of the storage bank at least in part based on receiving the instruction; and receive the second activation command to open a second row of memory cells in the second subarray of the storage bank after activating the portion of the second subarray. Attached Figure Description

[0009] Figure 1 This document describes instances of systems that support techniques for indicating row activation, based on the examples disclosed herein.

[0010] Figure 2 This document describes instances of memory dies that support techniques for indicating row activation, based on examples disclosed herein.

[0011] Figure 3 This document describes an example of a memory system that supports techniques for indicating row activation, based on the examples disclosed herein.

[0012] Figure 4A and 4B This document describes instances of command timelines that support techniques for indicating line activation, based on examples disclosed herein.

[0013] Figure 5 A block diagram illustrating a memory device supporting techniques for indicating row activation, based on examples disclosed herein.

[0014] Figure 6 A block diagram of a host device supporting techniques for indicating row activation, based on examples disclosed herein.

[0015] Figure 7 and 8 The flowchart illustrates one or more methods for indicating line activation based on the examples disclosed herein. Detailed Implementation

[0016] To access memory cells within a row of a subarray within the memory bank of a memory device (e.g., a random access memory (RAM) device), individual operations can be performed, triggered by a separate corresponding command to the memory device (e.g., sent by a host device or its controller). For example, the memory device may receive an activation command for a row of memory cells, which triggers an activation operation. The activation operation opens a row of memory cells within a given subarray of a given memory bank. Following the activation command, the memory device may receive a data access command (e.g., read, write, program, rewrite, etc.) directed to the opened row. Based on the data access command, the memory device may read data from or write data to one or more memory cells in the opened row. The memory device may then receive a precharge command directed to the opened row. Based on the precharge command, the memory device may close the opened row, which can cause the row access operation to complete.

[0017] Each step of a row access operation (e.g., activation, access, precharge) may have an associated delay. In some cases, the memory device may support timing signals (e.g., phases) associated with the execution of activation, data access, and precharge commands, which can trigger internal operations for accessing memory cells within a row. In some cases, if an existing row access operation is still in progress, the activation operation to open a row of the memory cell may not be initiated. For example, if an existing access row has not been closed (e.g., at the end of a precharge operation), the memory device may not be able to access different rows or different portions of the memory at the opened row. The delay between the completion of a precharge operation (e.g., closing one or more rows of the memory cell) and the activation command for a subsequent row of the memory cell can increase the amount of time required to access cells within the memory device.

[0018] According to the aspects described herein, a memory device may receive an indication (e.g., a prompt) associated with an activation command that may arrive at a future time. The indication (e.g., a prompt) enables the memory device to begin aspects of the activation operation for the next row before receiving the associated activation command. For example, the prompt may contain the location of the next row to be accessed (e.g., a segment index or row address). In some cases, the location of the next row access operation may be in the same memory segment as the currently accessed row (e.g., the current row access operation) or a different memory segment. In some cases, the indication (e.g., a prompt) may be included in a previous activation command or precharge command. For example, after receiving an indication (e.g., a prompt) in a precharge command, the memory device may begin the activation operation for the next row access operation before the precharge operation of the current row access operation is completed. The memory device may receive the activation command for the next row access operation after receiving the indication (e.g., a prompt) and may complete the activation operation in response to receiving the activation command. That is, the memory device may perform a portion of the activation operation for the next row access operation during the precharge operation of the current row access operation. By performing part of the activation operation in advance (e.g., before receiving the activation command), the memory device can reduce the overall latency of the next row access operation and thus improve the performance at the memory device.

[0019] Firstly, in reference Figure 1 and 2 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figure 3 Features of this disclosure are described in the context of the memory system and command timeline described in section 4. These and other features of this disclosure are further illustrated and described with reference to device diagrams and flowcharts relating to the techniques used to indicate row activation, such as references to Figures 5 to 8 describe.

[0020] Figure 1 This document describes an example of a system 100 that supports techniques for indicating line activation, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0021] System 100 may include portions of an electronic device, such as a computing device, mobile computing device, wireless device, graphics processing device, vehicle, or other system. For example, system 100 may describe aspects of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data for use by one or more other components of system 100.

[0022] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to perform processes (e.g., a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other instances). In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0023] In some instances, host device 105 may transmit multiple activation commands to memory device 110 (e.g., via external memory controller 120). For example, the host device may determine one or more rows of memory cells within memory device 110 (e.g., within the same or different subarrays of memory device 110, or within the same or different memory banks of memory device 110) and may transmit a first activation command to access the first row of memory cells and a second activation command to access the second row of memory cells. In some cases, the host device may be configured to include an indication (e.g., a prompt) in a command that may contain location information associated with a second activation command that will appear later. The first and second rows may be in the same memory bank, or in some cases may be the same row. The host device may determine the timing of transmitting the second activation command based on several factors, including whether the prompt is included in a previous command and whether the first and second rows are in the same subarray. According to some aspects, the host device may select between a default tRP or tRP_S when determining the timing of transmitting the second activation command. The host device may transmit a second activation command after transmitting the precharge command to the first line, where the delay corresponds to the selected default tRP or tRP_S. In some cases, a transmission cue may enable the memory device to shorten the tRCD associated with performing the activation operation.

[0024] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals; various pin configurations for transmitting signals; various physical package dimensions of host device 105 and memory device 110; clock signaling and synchronization between host device 105 and memory device 110; timing conventions; or other factors.

[0025] Memory device 110 is operable to store data for components of host device 105. In some instances, memory device 110 may act as an auxiliary or subordinate device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0026] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (such as one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using bus 135.

[0027] Processor 125 is operable to provide control or other functionality to at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other instances thereof. In some instances, external memory controller 120 may be implemented by or be part of processor 125.

[0028] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0029] In some instances, system 100 or host device 105 may include various peripheral components. Peripheral components may be any input or output device, or an interface for such devices, which may be integrated into or with system 100 or host device 105. Examples may include one or more of the following: disk controller, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, serial or parallel port, or peripheral card slot (e.g., peripheral component interconnect (PCI) or dedicated graphics port). Peripheral components may be other components understood by those skilled in the art as peripheral devices.

[0030] In some instances, system 100 or host device 105 may include an I / O controller. The I / O controller manages data communication between processor 125 and peripheral components, input devices, or output devices. The I / O controller can also manage peripheral devices not integrated into or not integrated with system 100 or host device 105. In some instances, the I / O controller may represent a physical connection or port to an external peripheral component.

[0031] In some instances, system 100 or host device 105 may include input components, output components, or both. Input components may represent devices or signals external to system 100 that provide information, signals, or data to system 100 or its components. In some instances, input components may include a user interface or an interface with or between other devices. In some instances, input components may be peripheral devices that interface with system 100 via one or more peripheral components or can be managed by an I / O controller. Output components may represent devices or signals external to system 100 that are operable to receive output from any of system 100 or its components. Examples of output components may include a display, an audio speaker, a printing device, another processor on a printed circuit board, and others. In some instances, outputs may be peripheral devices that interface with system 100 via one or more peripheral components or can be managed by an I / O controller.

[0032] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) for supporting a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more dies, one or more segments), wherein each memory cell is operable to store at least one data bit. Memory device 110 comprising two or more memory dies 160 may be referred to as a multi-die memory or multi-die package or multi-chip memory or multi-chip package.

[0033] In some instances, memory array 170 may comprise multiple memory banks, and each memory bank may comprise multiple subarrays. In some cases, each subarray may comprise multiple rows of memory cells that can be accessed by external devices (e.g., host device 105, external memory controller 120). A given subarray may include or utilize corresponding latching circuitry that allows memory device 110 to maintain the phase of rows of memory cells in a given subarray (e.g., timing signals associated with row access operations) independently of the phase of rows of memory cells in other subarrays (even other subarrays within the same memory bank).

[0034] Memory die 160 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. A 2D memory die 160 may contain a single memory array 170. A 3D memory die 160 may contain two or more memory arrays 170 that may be stacked or positioned adjacent to each other (e.g., relative to a substrate). In some instances, the memory arrays 170 in a 3D memory die 160 may be referred to as layers, hierarchies, layers, or dies. A 3D memory die 160 may contain any number of stacked memory arrays 170 (e.g., two highs, three highs, four highs, five highs, six highs, seven highs, eight highs). In some 3D memory dies 160, different layers may share at least one common access line such that some layers may share one or more of word lines, digital lines, or plate lines.

[0035] Device memory controller 155 may include circuitry, logic, or components operable to control the operation of memory device 110. Device memory controller 155 may include hardware, firmware, or instructions enabling memory device 110 to perform various operations, and is operable to receive, transmit, or execute commands, data, or control information relating to components of memory device 110. Device memory controller 155 is operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, device memory controller 155 may control the operation of memory device 110 as described herein in conjunction with local memory controller 165 of memory die 160.

[0036] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0037] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, the local memory controller 165 is operable to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155 and a local memory controller 165, or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0038] External memory controller 120 is operable to enable the transfer of one or more of the information, data, or commands between a component of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or their functions as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or its functions as described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0039] External memory controller 120 may be part of or associated with a host device and may send one or more commands to memory device 110 via CA bus 186. Each of the commands may have an associated delay. In some instances, the external memory controller may send an activation command to memory device 110 to open a row of memory cells in a subarray, followed by an access command to access a row of memory cells in the subarray, and a precharge command to close a row of memory cells in the subarray. In some cases, external memory controller 120 may include a prompt in one of the commands for the location of a subsequent activation command (e.g., an activation command for a second row of memory cells). External memory controller 120 may determine the second row of memory cells to be accessed (e.g., in the same or a different subarray) and may determine the timing for sending subsequent commands based on previously sent prompts. In some cases, determining timing based on prompts may enable system 100 to reduce the overall delay of row access operations.

[0040] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 are operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path operable to carry a signal. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins are operable to act as part of a channel.

[0041] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or double data rate (DDR) signaling may be transmitted via channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be entered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be entered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0042] In some instances, CA channel 186 is operable to transmit commands between host device 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, a command carried by CA channel 186 may include a read command with an address containing the desired data. In some instances, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) for decoding one or more of the address or command data.

[0043] In some instances, clock signal channel 188 is operable to transmit one or more clock signals between host device 105 and memory device 110. Each clock signal is operable to oscillate between high and low states and can support coordination (e.g., timing) between the actions of host device 105 and memory device 110. In some instances, the clock signal may be single-ended. In some instances, the clock signal may provide a timing reference for command and addressing operations of memory device 110, or other system-wide operations of memory device 110. Therefore, the clock signal may be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal may be generated by a system clock that may include one or more hardware components (e.g., an oscillator, crystal, logic gate, transistor).

[0044] Channel 115 may contain any number of signal paths (including a single signal path). In some instances, channel 115 may contain multiple individual signal paths. For example, the channel may be x4 (e.g., containing four signal paths), x8 (e.g., containing eight signal paths), x16 (containing sixteen signal paths), etc.

[0045] One or more different modulation schemes can be used to modulate the signal transmitted via channel 115. In some instances, a binary symbol (or binary level) modulation scheme can be used to modulate the signal transmitted between host device 105 and memory device 110. The binary symbol modulation scheme can be an example of an M-ary modulation scheme, where M equals 2. Each symbol of the binary symbol modulation scheme is operable to represent a digital data bit (e.g., a symbol can represent logic 1 or logic 0). Examples of binary symbol modulation schemes include (but are not limited to) non-return-to-zero (NRZ), single-pole coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0046] In some instances, multi-symbol (or multi-level) modulation schemes may be used to modulate signals transmitted between host device 105 and memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of the multi-symbol modulation scheme is operable to represent more than one digital data bit (e.g., the symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include (but are not limited to) PAM3, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme containing at least three levels to encode more than one information bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols.

[0047] Figure 2 This document describes an example of a memory die 200 that supports techniques for indicating row activation, based on the examples disclosed herein. The memory die 200 may be used as a reference. Figure 1 Examples of memory die 160 described herein. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each of which may be programmed to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., multilevel memory cell) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, for example, as shown in the reference array. Figure 1 The memory array 170 is described.

[0048] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material for storing charge representing a programmable state. In other memory architectures, other memory devices and components are possible. For example, a nonlinear dielectric material may be used. Memory cell 205 may include logic storage components (e.g., capacitor 230) and switching components 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. Nodes of capacitor 230 may be coupled to a voltage source 240, which may be a cell plate reference voltage (e.g., Vpl) or grounded (e.g., Vss).

[0049] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digital lines 215) arranged in a pattern (e.g., a grid pattern). The access lines may be conductive lines coupled to the memory cell 205 and used to perform access operations on the memory cell 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, are interchangeable without loss of understanding or operability. The memory cell 205 may be located at the intersection of word lines 210 and digital lines 215.

[0050] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines (e.g., one or more of word line 210 or digital line 215). A single memory cell 205 can be accessed at its intersection by applying a bias voltage to word line 210 and digital line 215 (e.g., applying a voltage to word line 210 or digital line 215). The intersection of word line 210 and digital line 215, arranged in a two-dimensional or three-dimensional configuration, can be referred to as the address of memory cell 205.

[0051] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive a row address from local memory controller 260 and activate word line 210 based on the received row address. Column decoder 225 can receive a column address from local memory controller 260 and activate number line 215 based on the received column address.

[0052] In some instances, a portion of memory cell 205 may be a row of memory cells 205 in a subarray of memory. A row of memory cells 205 can be accessed via one or more commands (e.g., by a host device). For example, a row of memory cells 205 may be opened based on an activation command. Access commands (e.g., read commands or write commands) may access data stored on a row of memory cells 205 or write data to a row of memory cells 205, and a row of memory cells 205 may be closed based on a precharge command. In some instances, an indication of the location of a second activation command may be included in a previous command (e.g., a first activation command or a precharge command). Access to a second row of memory cells 205 may be initiated at an earlier time (e.g., before the second activation command is received) based on the indication.

[0053] The selection or deselection of memory cell 205 can be accomplished by activating or deactivating switching component 235 using word line 210. Capacitor 230 can be coupled to digital line 215 using switching component 235. For example, when switching component 235 is deactivated, capacitor 230 can be isolated from digital line 215, and when switching component 235 is activated, capacitor 230 can be coupled to digital line 215.

[0054] Word line 210 may be a conductive line electrically connected to memory cell 205, used to perform access operations on memory cell 205. In some architectures, word line 210 may be coupled to the gate of switching component 235 of memory cell 205 and operable to control the switching component 235 of memory cell 205. In some architectures, word line 210 may be coupled to a node of capacitor in memory cell 205 and memory cell 205 may not contain a switching component.

[0055] Digital line 215 may be a conductive line connecting memory cell 205 to sensing component 245. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during a portion of an access operation. For example, word line 210 and switching component 235 of memory cell 205 may be operable to couple and / or isolate capacitor 230 of memory cell 205 and digital line 215. In some architectures, memory cell 205 may be coupled to digital line 215.

[0056] Sensing component 245 is operable to detect a state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine a logic state of memory cell 205 based on the stored state. Sensing component 245 may include one or more sensing amplifiers for amplifying or otherwise converting the signal caused by accessing memory cell 205. Sensing component 245 may compare the signal detected from memory cell 205 with reference 250 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 245 (e.g., to input / output 255) and can indicate the detected logic state to another component of the memory device including memory die 200.

[0057] The local memory controller 260 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 may be a reference. Figure 1 Examples of local memory controller 165 described herein. In some instances, one or more of row decoder 220, column decoder 225, and sensing component 245 may be co-located with local memory controller 260. Local memory controller 260 is operable to receive one or more commands or data from one or more different memory controllers (e.g., external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of one or more operations. Local memory controller 260 may generate row signals and column address signals to activate target word line 210 and target digital line 215. Local memory controller 260 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed in the operational memory die 200.

[0058] The local memory controller 260 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 is operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0059] The local memory controller 260 can transmit commands to the sensing component 245 or the line decoder 220 to initiate a line access operation (e.g., by initiating a first activation operation to open a line). In some cases, the local memory controller 260 can be based on a reference... Figure 1 The host device 105 described herein transmits commands. In some cases, the local memory controller 260 may be configured to include in the command (e.g., a prompt) an indication (e.g., a hint) associated with the location of a future activation command (e.g., a second activation command). Based on the prompt, the sensing component 245 or the line decoder 220 may initiate the second activation operation before the precharge operation can be completed.

[0060] In some cases, the local memory controller 260 may include different information in the prompt. For example, in some cases, the second activation operation may occur in the same or different segments, and the prompt may include the same or different segment indices. Furthermore, the prompt may include specific row address bit information. Depending on the information included in the prompt and whether the second activation operation is in the same or different segments, the tRCD associated with the second activation operation and the data access operation may have different time periods.

[0061] The local memory controller 260 is operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 260 can identify the target memory cell 205 on which the write operation is performed. The local memory controller 260 can identify the target word line 210 and target digital line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and target digital line 215 (e.g., apply a voltage to the word line 210 or digital line 215) to access the target memory cell 205. The local memory controller 260 can apply a specific signal (e.g., a write pulse) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205. The pulse used for the write operation may contain one or more voltage levels over a duration.

[0062] The local memory controller 260 is operable to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 260 can identify the target memory cell 205 on which the read operation is performed. The local memory controller 260 can identify the target word line 210 and target digital line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and target digital line 215 (e.g., apply a voltage to the word line 210 or digital line 215) to access the target memory cell 205. The target memory cell 205 can transmit a signal to the sensing component 245 in response to a bias applied to the access line. The sensing component 245 can amplify the signal. The local memory controller 260 can activate the sensing component 245 (e.g., a latching sensing component) and thereby compare the signal received from the memory cell 205 with the reference 250. Based on the comparison, the sensing component 245 can determine the logical state stored in the memory cell 205.

[0063] Figure 3 This document describes an example of a memory system 300 that supports techniques for indicative row activation, based on the examples disclosed herein. The memory system 300 may include a host device 305 and a memory device 310. The host device 305 may include a memory controller 315 (which may be referenced). Figure 1 An example of an external memory controller described herein, which can be connected to a memory device 310 (which may be referenced) via a CA bus 320 or a data bus 325. Figure 1(Example of the described memory device 110) Communication. The memory device 310 may use DRAM, FeRAM or other types of memory to store data at the memory device 310. The process by which the memory controller 315 accesses and retrieves data stored in the memory device 310 is referred to as an access operation or data access operation.

[0064] Access operations (e.g., read or write operations) can be transmitted (e.g., sent by host device 305) to memory device 310 as a series of commands (e.g., as a command sequence). Commands can be transmitted to memory device 310 via memory controller 315 via CA bus 320 (which may be an instance of CA bus 186). Commands can be received at memory device 310 and can trigger corresponding operations at memory device 310 to read, write, or otherwise access data stored at memory device 310 (e.g., at one or more memory cells of memory device 310). Data stored at or written to memory device 310 can be transmitted between host device 305 and memory device 310 via data bus 325 (which may be an instance of DQ bus 190).

[0065] Memory device 310 may include multiple subarrays 335. Subarrays 335 may store data contained in memory device 310. Subarrays 335 may be grouped into memory banks 330. In some instances, memory device 310 may include thirty-two memory banks 330, each of which may contain multiple subarrays 335 of memory cells. For example, one or more memory banks 330 may contain sixteen subarrays 335. First subarray 335-a and second subarray 335-b may be instances of subarrays 335, and as shown in this example, are located in the same memory bank 330 of memory device 310. Subarrays 335 may each contain individual rows of memory cells (e.g., row 340), which may store data associated with memory device 310 or to which data may be written.

[0066] In some cases, commands received by memory device 310 may cause memory device 310 to generate one or more associated phases (e.g., using phase generator 350). For example, for each activation, data access, or precharge command received by memory device 310, phase generator 350 of memory device 310 may generate a set of associated phases. The set of associated phases may refer to or may include timing signals that jointly trigger or otherwise control the sequence of internal operations within subarray 335.

[0067] In some cases, a command received by memory device 310 (e.g., a command transmitted via CA bus 320) may include an indication (e.g., a prompt) of the location of a subsequent row to be accessed by a future access operation. In some cases, memory controller 315 may be configured to include an indication. For example, in some cases, a first activation command associated with an enabled row of subarray 335 may include an indication that a second activation command may be associated with a different row of the same subarray 335. In some cases, a precharge command may include an indication. Upon receiving the indication, phase generator 350 may generate a set of timing signals (e.g., one or more associated phases) such that a portion of the second activation command can be executed before the precharge command can be completed, or before the second activation command can be received, or both.

[0068] Executing a command operation may involve a set of internal operations (e.g., performing an activation operation at subarray 335 may involve a first set of phase control internal operations, performing an access operation such as a read or write operation at subarray 335 may involve a second set of phase control internal operations, and performing a precharge operation at subarray 335 may involve a third set of phase control internal operations). Therefore, the phase can manage the internal timing of access operations to a given row of a given subarray 335 to which the command points. In some instances, the phase may be an internal timing signal that triggers electrical operations (e.g., physical electrical operations) corresponding to the command operation on an individual row basis to access a memory cell of a given row 340.

[0069] Row access operations and data access operations at memory device 310 may each have associated delays. For example, the delay of a row access operation may be associated with the internal timing of a data access operation, which may be associated with the set of timing signals generated at phase generator 350. In some cases, the set of timing signals may include tRCD (e.g., the minimum time between an activation command and a data access command), which may be longer due to the increased delay associated with the activation command or data access operation. To reduce the time associated with tRCD and improve overall delay, phase generator 350 may be enabled to perform a portion of the activation operation while a precharge operation is in progress, based on an indication included in previous signals. For example, based on an indication of the location of the next row access operation, phase generator 350 may perform a precharge operation at a row within subarray 335-a, while phase generator 350 may also begin performing an activation operation at a row within subarray 335-b. In some cases, phase generator 350 can perform a precharge operation at a row within subarray 335-a while simultaneously initiating an activation operation at a portion of the memory in the same row of subarray 335-a. By enabling phase generator 350 to generate overlapping timing signals that allow closing a row (e.g., executing a precharge command) and opening the next row (e.g., executing the next activation command), the memory device can improve system operating latency and overall efficiency.

[0070] Memory device 310 may include any number of phase generators 350 (e.g., one phase generator per subarray 335, one phase generator per bank 330, one phase generator per memory die, or one phase generator per memory device 310). In some instances, subarray-level phasing can enable parallel subarray operation. As an example, phase generators 350 may be included in or incorporated into a device memory controller 155 or a local memory controller 165 included in memory device 310. As another example, phase generators 350 may include logic or other special-purpose circuitry that may be included in, coupled to, or otherwise associated with a bank 330 designated by a corresponding command (e.g., each bank 330 may include, be coupled to, or otherwise associated with a corresponding phase generator 350), i.e., phases may be generated on a per-bank 330 basis. Phases and other signals generated within the memory device 310 but outside the corresponding subarray 335 may include, be coupled to, or otherwise associated with the corresponding phase generator 350, and may be generated locally for each subarray 335.

[0071] Each memory bank 330 can generate a global phase. This can support concurrent (parallel, with accesses to rows in different memory banks 330 overlapping at least partially in time) accesses to different memory banks 330. In some instances, activation or precharge operations may occur on row 340 in memory bank 330 simultaneously on row 340 in different memory banks 330 of memory device 310.

[0072] In some instances, each subarray 335 may include, use, or otherwise associate with a corresponding (e.g., a corresponding) row buffer for accessing data stored in the subarray 335. Alternatively, each subarray 335 within the memory bank 330 may include, use, or otherwise associate with a corresponding latch circuit 345 that can replicate and maintain (e.g., save, store) the phase associated with the subarray 335 independently of the phase associated with the remaining subarrays 335 in the memory bank 330 or memory device 310. For example, the latch circuit 345 may store a copy of the global phase or other signal associated with the corresponding subarray 335 (e.g., for performing operations on the corresponding subarray 335). The latch circuit 345 may enable improvements to the memory system 300 according to the examples described herein. For example, this may support concurrent (e.g., parallel, accesses to rows in different subarrays 335 of the same memory bank at least partially overlap in time) accesses to different subarrays 335 of the same memory bank. In some instances, activation or precharge operations may occur on row 340 of the first subarray 335 of the memory bank 330, while activation or precharge operations may also occur on row 340 of the second subarray of the memory bank 330 in the memory device 310.

[0073] Accessing row 340 may involve one or more operations, each of which may reduce the overall latency of the access row. Such operations may be based on (e.g., in response to) a corresponding command, which may be passed to memory device 310 via memory controller 315. Commands for accessing row 340 within subarray 335 of memory bank 330 may include activation commands (e.g., corresponding to an activation operation), data access commands (e.g., corresponding to read, write, program, reset, or rewrite operations), and precharge commands (e.g., corresponding to an activation operation). An activation operation may open row 340 of a memory cell. An access operation may access data contained in the opened (e.g., activated) row 340 (e.g., in the case of a read operation) or write data into the opened row 340 (e.g., in the case of a write operation). A precharge operation may close the opened row 340.

[0074] All three operations can be performed to access a row 340 of a memory cell within a subarray 335 of the memory bank 330 of the memory device 310. In some instances, an activation operation can be performed before the access operation to enable the row 340. Additionally, a precharge operation can be performed to disable the activated row 340. In some cases, a precharge operation can be performed before subsequent access operations to the row 340 within the same memory bank 330. Corresponding commands can be passed from the memory controller 315 to the memory device 310 as a series of commands (e.g., as a command sequence). Commands may include an activation command, a data access command, and a precharge command, and can be received in the order in which the corresponding operations are performed.

[0075] Figure 4A This document describes an example of a command timeline 400-a that supports techniques for indicating row activation, based on the examples disclosed herein. Command timeline 400-a may include a CA bus 320-a, which may be used as a reference. Figure 3 An example of the CA bus 320 is described. Command timeline 400-a illustrates an example in which the indication correctly identifies the next line being accessed (e.g., a hit prompt) and the first and second (subsequent) lines are located in different segments of the memory device.

[0076] Command timeline 400-a may include several commands associated with one or more row access operations, including a first activation command 415-a, a second activation command 415-b, a first data access command 420-a, a second data access command 420-b, and a precharge command 425-a. Command timeline 400-a may include a set of timing signals, including one or more precharge phases 440-a, one or more activation phases 445-a, and one or more activation phases 445-b. Precharge phase 440-a may include a precharge operation 460, which in some cases may include a hidden portion 430. Precharge operation 460 may be associated with tRP 465 (e.g., row precharge time) and tRAS 455 (e.g., row activity time). Activation phase 445-a may include an activation operation 470-a, which may be associated with a duration 450 (e.g., standard tRCD, row address to column address delay). In some cases, duration 450 may be the amount of time (e.g., a minimum amount) the controller may wait before sending a data access command (e.g., command 420-a, command 420-b). Activation phase 445-b may include activation operation 470-b, which may include hidden portion 435. In some cases, activation operation 470-b may be associated with duration 451 (e.g., shortening tRCD).

[0077] tRAS 455 can be the duration (e.g., the number of clock cycles, which may be a minimum number of clock cycles) between the memory device 310 receiving the first activation command 415-a and the memory device 310 receiving the precharge command 425-a. tRP can be the duration between the memory device receiving the precharge command 425-a and the completion of the precharge operation 460. tRCD can be the duration between the memory device 310 receiving the first activation command 415-a and the memory device 310 receiving the first data access command 420-a.

[0078] Command timeline 400-a may be an example of a "hint hit" case, where the first activation command 415-a or precharge command 425-a may contain an indication (e.g., a "hint") of the location of the second activation command 415-b. In some instances, the hint may contain more than one information bit and a portion of the hint may be included in each of the first activation command 415-a and the precharge command 425-a. In some cases, the hint may enable a memory device (e.g., memory device 310, as referenced) to... Figure 3 (Description) The second activation operation 470-b can be started while the precharge operation 460 is in progress. In some cases, starting the second activation operation 470-b earlier can reduce the duration 451 (e.g., shorten tRCD), which can reduce the overall latency of the row access operation.

[0079] To initiate a row access operation, memory device 310 may receive a first activation command 415-a via CA bus 320-a, which may be sent from the memory controller. The first activation command 415-a may be used to enable a subarray (e.g., as shown in reference...). Figure 3 The first row of the described subarray 335 is associated with this. A first activation command 415-a can trigger activation phase 445-a, which may include timing or other signals for enabling internal operations of the first row. For example, this can be achieved via a phase generator (e.g., as referenced). Figure 3 The described phase generator 350 generates an activation phase 445-a. A first activation operation 470-a can be performed within a duration 450 (e.g., standard tRCD). In some cases, the memory controller may start a timer corresponding to the duration 450 (e.g., standard tRCD) to determine when to send subsequent commands associated with row access operations.

[0080] When the first row is opened, memory device 310 may receive a first data access command 420-a via CA bus 320-a. For example, the first data access command may be a read command, a write command, or another type of data access command. The first data access command 420-a may contain instructions to access a portion of memory at the first row opened by the first activation operation 470-a. The first data access command 420-a may trigger additional phases, which may include timing or other signals for internal operations of reading, writing, or otherwise accessing the memory cell at the opened row. The memory controller may initiate additional timers corresponding to the internal operations. The first data access command 420-a and any additional associated phases may occur after a duration of 450 (e.g., standard tRCD).

[0081] After completing the first data access operation, the memory device 310 may receive a precharge command 425-a. The precharge command 425-a may trigger a precharge phase 440-a, which may include timing or other signals for closing an internal operation (e.g., precharge operation 460) of the first row. In some cases, the precharge command 425-a may additionally include an indication (e.g., a prompt) of the location (e.g., row) of the second activation command 415-b. In some cases, the prompt may include a segment index (e.g., row) that can be associated with the second activation command 415-b. In some cases, the prompt may include specific row address bits associated with the second data access command. The prompt may enable the memory device 310 to trigger a second set of activation phases 445-b before the precharge operation 460 completes.

[0082] When a portion 435 of the second activation operation 470-b of the second row is executed during at least a portion of the time while the precharge operation 460 of the first row is still being executed (e.g., portion 435 occurs simultaneously with a portion of the precharge operation 460), the overall latency of the access row can be reduced. In such an example, portion 435 of the second activation 470-b may occur before the memory system receives the second activation command 415-b based on a received prompt. The overlap (in time) between these two operations reduces the overall latency of the access row.

[0083] Similarly, the overall latency of the access row can be further reduced when a portion 430 of the precharge operation 460 is performed during at least a portion of the time during which the second activation operation 470-b is still being executed (e.g., portion 430 occurs concurrently with the portion of the second activation 470-b). In such instances, portion 430 of the precharge operation 460 may occur after the memory system receives the second activation command 415-b. To reduce latency in such scenarios, the duration of tRP can be adjusted. For example, the precharge operation (e.g., the first row is closed) may be completed within the tRP 465 period. In some cases, the memory controller may start a timer corresponding to tRP 465 to determine when to send subsequent commands associated with the row access operation. In some cases, due to the time overlap between the precharge operation 460 and the second activation operation 470-b (e.g., portion 430), a portion 430 of the precharge operation 460 (e.g., a hidden portion) may exist that occurs after the second activation command 415-b has been received. Hidden portion 430 can reduce the tRP 465 period (e.g., tRP_S). For example, increased overlap between precharge operation 460 and second activation operation 470-b can result in a shorter tRP 465. In some cases, the memory controller can determine to start a shorter timer corresponding to the shorter tRP (e.g., tRP_S). For example, if the memory controller previously included a hint in a command transmitted via CA bus 320-a, then the memory controller can determine to use a timer associated with the shorter tRP 465. In some cases, extending the precharge operation to reduce tRP 465 can be referred to as a method for tRP improvement or reduction.

[0084] In some cases, the memory controller may use a shorter tRP (e.g., tRP_S) without prior indication in the command. For example, if the next activation command 415 (e.g., the second activation command 415-b) is associated with a row in a different segment, the memory controller may include a hidden portion 430 in the precharge operation 460 and thus reduce tRP 465.

[0085] The second row associated with the second activation operation 470-b may be in the same segment as the first row associated with the first activation operation 470-a or in a different segment. The reduction in overall latency may depend on whether the two rows are in the same segment or in different segments. The memory device 310 may receive a second activation command 415-b via the CA bus 320, which may trigger activation phase 445-b. The second activation command 415-b may be associated with the second row of the enabled subarray, which may be the location indicated in the prompt within the precharge command 425-a.

[0086] In some cases, the second position of the second activation operation 470-b may have a segment index (e.g., a different line) different from the position of the first activation operation 470-a, as shown in command timeline 400-a. The second activation operation 470-b may complete within duration 451 (e.g., shortened tRCD) when no prompt or indication is used. A prompt within precharge command 425-a may have already triggered a portion of activation phase 445-b. In such cases, a portion 435 (e.g., a hidden portion) of the second activation operation 470-b may be completed before the second activation command 415-b can be received (e.g., before duration 451 begins). In such cases, duration 451 may be shorter than the standard tRCD (e.g., duration 450) that occurs when no indication or prompt is used. For example, in some cases where the second activation operation 470-b occurs in a different segment than the first activation operation 470-a, the tRCD may be tRCD_DS (e.g., the tRCD for a different segment), which may be shorter than the standard tRCD when no indication or prompt is used.

[0087] In some cases, the second position of the second activation operation 470-b may have the same segment index (e.g., the same line) as the position of the first activation operation 470-a. A prompt within the precharge command 425-a may have triggered a portion of the activation phase 445-b. In such cases, a portion 435 (e.g., a hidden portion) of the second activation operation 470-b may be completed before the second activation command 415-b can be received (e.g., before the start of duration 451). In such cases, the tRCD may be shorter than the standard tRCD that occurs when no indication or prompt is used. For example, in some cases where the second activation operation 470-b occurs at the same segment as the first activation operation 470-a, the tRCD may be tRCD_SS (e.g., the tRCD of the same segment), which may be shorter than the standard tRCD that occurs when no indication or prompt is used. In some cases, the tRCD_DS of a prompt between different segments may be shorter than the standard tRCD and shorter than the tRCD_SS of a prompt between the same segments.

[0088] The duration of a tRCD (e.g., standard tRCD, tRCD_SS, tRCD_DS) can vary based on various conditions, such as whether two adjacent activation operations are access rows in different segments or the same segment of the memory array. Different durations of tRCDs can also mean that the duration of portion 435 can vary between different combinations of activation operations. In some cases, the duration of portion 435 and the tRCD can vary based on whether the row is in different segments, in the same segment, other factors, or a combination thereof. For example, the duration of the tRCD can vary based on the relative positions of different segments within the memory array.

[0089] The indication or prompt may contain various information about the location of the next line accessed by the second activation operation 470-b. Examples of different types of information contained in the indication or prompt may include an indication of whether the line is in a different segment or the same segment, an indication of the segment index of the next line, one or more bits of the specific line address of the next line, or a combination thereof. If the prompt indicates whether the next line is in the same segment as the current line or a different segment, then the prompt may contain two or more bits to indicate three or more states. The three or more states indicated by the prompt may include a first state indicating that no prompt has been delivered, a second state indicating that the next line is in the same segment as the current line, or a third state indicating that the next line is in a different segment than the current line. If the prompt indicates the segment index of the next line, then the indication may use three or more bits to indicate whether a prompt has been delivered or the segment index of the next line.

[0090] In some cases, the indication or prompt may include specific or additional row address bits for the next row associated with the second activation operation 470-b. This information in the prompt can allow for further reduction in the overall latency of row access. For example, if activation operation 470-b occurs in the same segment, the duration of tRCD and portion 435 may vary based on the relative position between specific rows within the same segment. In some instances, tRCD may be tRCD_SS*, which may be shorter than both the standard tRCD and tRCD_SS for other row addresses. In some cases, if the prompt includes specific row address bits and the activation operation occurs in different segments, tRCD may be tRCD_DS*, which may be shorter than the standard tRCD, tRCD_SS, tRCD_SS*, and tRCD_DS. In some cases, the memory controller may select a value for the time and start a timer corresponding to tRCD to determine when to send subsequent commands associated with the row access operation based on the specific row address included in the prompt. In some cases, the memory controller may determine the type of timer to be set based on the type of prompt contained in the existing command (e.g., a timer corresponding to the standard tRCD, tRCD_SS, tRCD_SS*, tRCD_DS, or tRCD_DS*).

[0091] Different combinations of information in the indications or prompts can be used to achieve different delays for row activation. In some instances, the same / different indication can be used to allow the memory controller to adjust the duration of section 435 and tRCD. In some instances, the same / different indication can be used in combination with tRP adjustment to allow the memory controller to adjust the duration of section 435, tRCD, section 430, and tRP. In some cases, tRP adjustment may be independent of the same / different indication. In some instances, the same / different indication and one or more bits indicating a specific row address of the next row can be used to allow the memory controller to adjust the duration of section 435 and tRCD. In some instances, the same / different indication and one or more bits indicating a specific row address of the next row can be used in combination with tRP adjustment to allow the memory controller to adjust the duration of section 435, tRCD, section 430, and tRP. In some instances, the segment index indication of the next row can be used to allow the memory controller to adjust the duration of section 435 and tRCD. In some instances, the next-line segment index indicator can be used in combination with tRP adjustment to allow the memory controller to adjust the duration of section 435, tRCD, section 430, and tRP. In some instances, the next-line segment index indicator and one or more bits indicating a specific row address of the next line can be used to allow the memory controller to adjust the duration of section 435 and tRCD. In some instances, the next-line segment index indicator and one or more bits indicating a specific row address of the next line can be used in combination with tRP adjustment to allow the memory controller to adjust the duration of section 435, tRCD, section 430, and tRP.

[0092] When the second row is opened, memory device 310 may receive a second data access command 420-b via CA bus 320-a. The second data access command 420-b may contain instructions to access a portion of memory at the second row opened by the second activation operation 470-b. The second data access command 420-b may trigger an additional phase, which may include timing or other signals for internal operations of reading, writing, or otherwise accessing the memory cell at the opened row. The second data access command 420-b and any additional associated phase may occur after duration 451. In some cases, duration 451 may be shorter than duration 450 because portion 435 of the second activation operation 470-b occurs before precharge operation 460 is completed. Therefore, a prompt included in precharge command 425-a can reduce the overall time of the row access operation. In some cases, the prompt may be included in the first activation command 415-a (e.g., not in precharge command 425-a).

[0093] Figure 4BThis document describes an example of a command timeline 400-b that supports techniques for indicating line activation, based on the examples disclosed herein. Command timeline 400-b may include a CA bus 320-b, which may be used as a reference. Figure 3 The description includes an instance of the CA bus 320. Command timeline 400-b indicates an instance where the next line being accessed is incorrectly identified (e.g., a miss message).

[0094] Command timeline 400-b may include several commands associated with one or more row access operations, including a first activation command 415-c and a second activation command 415-d, a first data access command 420-c and a second data access command 420-d, and a precharge command 425-b. Command timeline 400-a may include a set of timing signals, including one or more precharge phases 440-b, one or more activation phases 445-c, and one or more activation phases 445-d. Precharge phase 440-b may include a precharge operation 460. Precharge operation 460 may be associated with tRP 465 and tRAS 455. Activation phase 445-c may include an activation operation 470-c that may be associated with a duration 450 (e.g., a standard tRCD), and an activation operation 470-d that may be associated with a duration 450 (e.g., a standard tRCD). Activation phase 445-d may include a portion of activation operation 470-e.

[0095] Command timeline 400-b may be an example of a "prompt miss" case, where the first activation command 415-c or precharge command 425-b may contain an indication (e.g., a "prompt") of the location of the second activation command 415-d, but the prompt may not match the second activation command 415-d. In such cases, the memory device may begin a portion of the second activation operation 470-e based on the prompt, but must then stop this operation to execute the second activation operation 470-d after receiving the second activation command 415-d. In some cases, the prompt may enable the memory device 310 to begin a portion of the activation operation 470-e while the precharge operation 460 is in progress. In some cases, executing a portion of the activation operation 470-e may not affect the duration 450 (e.g., standard tRCD) because the prompt may not match the activation command 470-d.

[0096] To initiate a row access operation, memory device 310 may receive a first activation command 415-c via CA bus 320-b, which may be sent from the memory controller. The first activation command 415-c may be associated with activating the first row of a subarray. The first activation command 415-c may trigger an activation phase 445-c, which may include timing or other signals for internal operations to activate the first row. A first activation operation 470-c may be performed over a duration 450. In some cases, the memory controller may start a timer corresponding to the duration 450 to determine when to send subsequent commands associated with the row access operation.

[0097] When the first row is opened, memory device 310 may receive a first data access command 420-c via CA bus 320-b. The first data access command 420-c may contain instructions to access a portion of memory at the first row opened by the first activation operation 470-c. The first data access command 420-c may trigger an additional phase, which may contain timing or other signals for internal operations of reading, writing, or otherwise accessing the memory cell at the opened row. The memory controller may initiate an additional timer corresponding to the internal operations. The first data access command 420-c and any additional associated phases may occur after a duration of 450.

[0098] After completing the first data access operation, the memory device 310 may receive a precharge command 425-b. The precharge command 425-b may trigger a precharge phase 440-b, which may include timing or other signals for an internal operation (e.g., precharge operation 460) to close the first row. In some cases, the precharge command 425-b may include an indication (e.g., a prompt) of the location of the second activation command 415-d. In some cases, the prompt may include an indication of whether a segment of the second row is different from or the same as a segment of the current row, a segment index (e.g., row) that may be associated with the second activation command 415-d, a specific row address bit, or a combination thereof, that may be associated with the second data access command 420-d. The prompt may enable the memory device 310 to trigger a second set of activation phases 445-d before the precharge operation 460 is completed. For example, in some cases, the memory device 310 may execute a portion of the activation command 470-e based on the prompt (e.g., may begin opening the second row).

[0099] In some cases, such as reference Figure 4A The memory controller can determine that a shorter tRP (e.g., tRP_S) is used without prior indication in the command. For example, if the next activation command (e.g., second activation command 415-d) is associated with a row in a different segment, the memory controller can include a hidden portion (e.g., as indicated by a hidden portion) in the precharge operation 460. Figure 4AThe hidden portion 430 shown in the image is thus reduced to tRP 465.

[0100] The memory device 310 may receive a second activation command 415-d via CA bus 320-b. The second activation command 415-d may be associated with the second row of the enabled subarray, which may not be the location indicated in the prompt within the precharge command 425-b. In response to receiving a second activation command 415-d containing a location different from the prompt, the memory device may stop the operation associated with the second activation operation 470-e (as indicated by the prompt) and may begin the operation associated with the second activation operation 470-d (as indicated in the second activation command 415-d).

[0101] There may be several instances of situations that could lead to a "miss message" error, such as... Figure 4B The following are examples. In some instances, the hint may indicate that the next line is in the same segment as the current line, and the second activation command 415-d may indicate that the next line is in a different segment than the current line. In some instances, the hint may indicate that the second index of the next line is different from the segment index indicated in the second activation command 415-d. In some instances, the hint may indicate that one or more line address bits of the next line that do not match the line address indicated in the second activation command 415-d may indicate that the next line is in the same segment as the current line. Other instances of cache misses are also possible, including any combination of the instances described herein.

[0102] In some cases, the second activation command 415-d may have a segment index different from that of the first activation operation 415-c (e.g., a different row). In some cases, the second activation command 415-d may have the same segment index as the first activation operation 415-c (e.g., the same row), as shown in command timeline 400-b. The second activation command 415-d may trigger activation phase 445-c, which may include timing or other signals for an internal operation (e.g., the second activation operation 470-d) to enable the second row. Because a portion of the activation command 470-d may be executed at a row that may not match the second activation command 415-d, the memory device 310 may have to perform a full activation operation 470-d at the correct row (e.g., the row indicated by the second activation command 415-d). Therefore, the duration 450 associated with the second activation operation 470-d may be a standard tRCD. In some cases, the memory controller may start a timer corresponding to the duration 450 to determine when to send subsequent commands associated with the row access operation.

[0103] In some cases, the memory device may reduce tRP based on overlapping a portion of the precharge operation 460 with a portion of the second activation command. In some cases of a cue miss and tRP reduction, the memory device may restore the tRP timer to its standard tRP duration and complete the precharge operation 460 before executing the second activation operation 470-d indicated by the second activation command 415-d. In some cases of a cue miss, the memory device may maintain a shorter tRP (e.g., tRP_S).

[0104] When the second row is opened, memory device 310 may receive a second data access command 420-d via CA bus 320-b. The second data access command 420-d may contain instructions to access a portion of memory at the second row opened by the second activation operation 470-d. The second data access command 420-d may trigger an additional phase, which may include timing or other signals for internal operations of reading, writing, or otherwise accessing the memory cell at the opened row. The second data access command 420-d and any additional associated phases may occur after a duration 450. In some cases, due to a mismatch between the prompt and the second activation command 415-d, duration 450 may be longer than duration 451, as referenced. Figure 4A describe.

[0105] Figure 5 A block diagram 500 illustrates a memory device 520 supporting techniques for indicating row activation, based on examples disclosed herein. The memory device 520 may be referenced. Figure 1 Examples of aspects of the memory device described in section 4. The memory device 520 or its various components may be examples of means for performing the various aspects of the techniques described herein for indicative row activation. For example, the memory device 520 may include an activation component 525, an indication component 530, a timing signal generation component 535, a precharge component 540, a data access operation component 545, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0106] Activation component 525 may be configured or otherwise supported to support means for receiving a first activation command to open a first row of memory cells in a first subarray of the memory bank of the memory device. Indication component 530 may be configured or otherwise supported to support means for receiving an indication at least partially based on receiving the first activation command and, prior to receiving a second activation command, for a second subarray of the memory bank. In some instances, activation component 525 may be configured or otherwise supported to support means for activating a portion of the second subarray of the memory bank at least partially based on receiving the indication. In some instances, activation component 525 may be configured or otherwise supported to support means for receiving a second activation command to open a second row of memory cells in the second subarray after activating a portion of the second subarray of the memory bank.

[0107] In some instances, the second subarray includes the first subarray, and the timing signal generation component 535 may be configured or otherwise supported for generating a first set of timing signals to activate the first subarray of the memory bank, at least in part based on receiving a first activation command. In some instances, the second subarray includes the first subarray, and the timing signal generation component 535 may be configured or otherwise supported for generating a second set of timing signals to activate the first subarray of the memory bank, at least in part based on receiving an indication and before receiving a second activation command.

[0108] In some instances, the data access operation component 545 may be configured or otherwise supported to receive a read command within a time period following the receipt of a second activation command, the time period including the shortened row address to column address delay (tRCD_SS) of the same segment index, which is less than the default row address to column address delay (tRCD).

[0109] In some instances, the second subarray differs from the first subarray, and the timing signal generation component 535 may be configured or otherwise supported to generate a first set of timing signals to activate the first subarray of the memory bank, at least in part based on receiving a first activation command. In some instances, the second subarray differs from the first subarray, and the timing signal generation component 535 may be configured or otherwise supported to generate a second set of timing signals to activate the second subarray of the memory bank, at least in part based on receiving an indication and before receiving a second activation command.

[0110] In some instances, the data access operation component 545 may be configured or otherwise supported to receive a read command within a time period following the receipt of the second activation command, the time period including the row address to column address delay (tRCD_DS) of the different segment indexes, which is less than the default row address to column address delay (tRCD).

[0111] In some instances, the precharge component 540 may be configured or otherwise supported for receiving a precharge command to shut down the first row of the memory cell before receiving a second activation command.

[0112] In some instances, an instruction is received in the precharge command.

[0113] In some instances, a second activation command is received before the first row of memory cells in the first subarray of the memory bank is closed.

[0114] In some instances, a second activation command is received within a time period following the receipt of the precharge command, the time period including a shortened row precharge time (tRP_S) that is less than the default row precharge time (tRP).

[0115] In some instances, timing signal generation component 535 may be configured or otherwise supported to generate a set of timing signals to close a first row of memory cells, at least in part based on receiving a precharge command. In some instances, timing signal generation component 535 may be configured or otherwise supported to maintain said set of timing signals after receiving a second activation command. In some instances, precharge component 540 may be configured or otherwise supported to close the first row of memory cells, at least in part based on maintaining said set of timing signals, after receiving a second activation command.

[0116] In some instances, activation component 525 may be configured or otherwise supported to support a second instruction for receiving at least part of a third activation command for a third subarray of the memory bank, based on a second activation command and prior to receiving a third activation command. In some instances, activation component 525 may be configured or otherwise supported to support a portion of the third subarray of the memory bank for activating at least part of the portion of the third subarray based on receiving the second instruction. In some instances, activation component 525 may be configured or otherwise supported to support a third row of memory cells in a fourth subarray of the memory bank after receiving a third activation command to activate a portion of the third subarray, wherein the third subarray is distinct from the fourth subarray.

[0117] In some instances, the data access operation component 545 may be configured or otherwise supported to receive a read command within a time period following the receipt of a third activation command, the time period including the default row address to column address delay (tRCD).

[0118] In some instances, the instruction is received in the first activation command.

[0119] In some instances, the indication includes one or more bits indicating the segment index, one or more bits indicating the row address, or both.

[0120] Figure 6 A block diagram 600 illustrates a host device 620 supporting techniques for indicating row activation, based on examples disclosed herein. The host device 620 may be a reference. Figure 1 Examples of aspects of the host device described in section 4. The host device 620 or its various components may be examples of components for performing the various aspects of the techniques described herein for instructing line activation. For example, the host device 620 may include an activation command component 625, an instruction transmission component 630, a data access command component 635, a precharge command component 640, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0121] The activation command component 625 may be configured or otherwise support means for transmitting a first activation command to open a first row of memory cells in a first subarray of the memory bank of the memory device. The instruction transmission component 630 may be configured or otherwise support means for transmitting an instruction at least in part based on the transmission of the first activation command and prior to the transmission of a second activation command for a second subarray of the memory bank. In some instances, the activation command component 625 may be configured or otherwise support means for transmitting a second activation command to open a second row of memory cells in a second subarray of the memory bank.

[0122] In some instances, the second subarray includes the first subarray, and the data access command component 635 may be configured or otherwise supported for transmitting a read command within a time period following the transmission of the second activation command, the time period including the shortened row address to column address delay (tRCD_SS) of the same segment index, which is less than the default row address to column address delay (tRCD).

[0123] In some instances, the second subarray differs from the first subarray, and the data access command component 635 may be configured or otherwise supported to support the transmission of read commands within a time period following the transmission of the second activation command, the time period including the row address to column address delay (tRCD_DS) of the different segment index shortening, which is less than the default row address to column address delay (tRCD).

[0124] In some instances, the precharge command component 640 may be configured or otherwise supported for transmitting a precharge command to shut down the first row of the memory cell before transmitting the second activation command.

[0125] In some instances, the indication is transmitted in the precharge command.

[0126] In some instances, a second activation command is transmitted before the first row of memory cells in the first subarray of the memory bank is closed.

[0127] In some instances, a second activation command that can be associated with a segment different from the first activation command is transmitted within a time period following the transmission of the precharge command. This time period includes a shortened row precharge time (tRP_S), which is less than the default row precharge time (tRP).

[0128] In some instances, the activation command component 625 may be configured or otherwise supported to support a second indication for transmitting a third activation command based at least in part on a third subarray of the memory bank, prior to the transmission of a second activation command and before the transmission of a third activation command. In some instances, the activation command component 625 may be configured or otherwise supported to support a component for transmitting a third activation command to activate a third row of memory cells in a fourth subarray of the memory bank, wherein the third subarray is distinct from the fourth subarray.

[0129] In some instances, the data access command component 635 may be configured or otherwise supported for transmitting a read command within a time period following the transmission of a third activation command, the time period including a default row address to column address delay (tRCD).

[0130] In some instances, the indication is transmitted in the first activation command. In some instances, the indication includes one or more bits indicating the segment index, one or more bits indicating the row address, or both.

[0131] Figure 7 The flowchart illustrates a method 700 for indicating line activation, based on examples disclosed herein. Operation of method 700 can be implemented using a memory device or its components described herein. For example, it can be implemented using references... Figures 1 to 5 The described memory device performs the operation of method 700. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0132] At 705, the method may include receiving a first activation command to enable a first row of memory cells in a first subarray of the memory bank of the memory device. The operation of 705 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 5 The described aspect of the activation component 525 performing the operation 705.

[0133] In 710, the method may include at least a partial indication based on receiving a first activation command and receiving a second activation command for a second subarray of the memory bank prior to receiving a second activation command. The operation of 710 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 5 The description indicates that the instruction component 530 performs the operation of 710.

[0134] In 715, the method may include a portion that activates a second subarray of the memory bank, at least in part, based on a received instruction. The operation of 715 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference. Figure 5 The described activation component 525 performs the operation of 715.

[0135] At 720, the method may include receiving a second activation command to open a second row of memory cells in the second subarray after activating a portion of the second subarray of the memory bank. The operation of 720 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference. Figure 5 The described activation component 525 performs the operation of 720.

[0136] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0137] Aspect 1: An apparatus comprising features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a first activation command to open a first row of memory cells in a first subarray of a memory bank of a memory device; receiving an instruction based at least in part on receiving the first activation command and prior to receiving a second activation command for a second subarray of the memory bank; activating a portion of the second subarray of the memory bank based at least in part on receiving the instruction; and receiving the second activation command to open a second row of memory cells in the second subarray of the memory bank after activating the portion of the second subarray.

[0138] Aspect 2: The apparatus according to aspect 1, wherein the second subarray comprises the first subarray and the method, apparatus, and non-transitory computer-readable medium further comprises operations, features, circuitry, logic, components, or instructions or any combination thereof for: generating a first set of timing signals to activate the first subarray of the memory at least in part based on receiving the first activation command and generating a second set of timing signals to activate the first subarray of the memory at least in part based on receiving the instruction and prior to receiving the second activation command.

[0139] Aspect 3: The device according to aspect 2 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for receiving a read command within a time period following the receipt of the second activation command, the time period including the shortened row address to column address delay (tRCD_SS) of the same segment index, which is less than the default row address to column address delay (tRCD).

[0140] Aspect 4: The apparatus according to any one of aspects 1 to 3, wherein the second subarray is different from the first subarray and the method, apparatus, and non-transitory computer-readable medium further comprises operations, features, circuitry, logic, components, or instructions or any combination thereof for: generating a first set of timing signals to activate the first subarray of the memory at least in part based on receiving the first activation command and generating a second set of timing signals to activate the second subarray of the memory at least in part based on receiving the instruction and before receiving the second activation command.

[0141] Aspect 5: The device according to aspect 4 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for receiving a read command within a time period following the receipt of the second activation command, the time period including a shortened row address to column address delay (tRCD_DS) of a different segment index, which is less than the default row address to column address delay (tRCD).

[0142] Aspect 6: The device according to any one of aspects 1 to 5 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for: receiving a precharge command to turn off the first row of the memory cell before receiving the second activation command.

[0143] Aspect 7: The device according to aspect 6 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for receiving the instruction in the precharge command.

[0144] Aspect 8: The device according to any one of aspects 6 to 7 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for receiving the second activation command before closing the first row of memory cells in the first subarray of the memory bank.

[0145] Aspect 9: The device according to aspect 8 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for receiving the second activation command within a time amount following receiving the precharge command, the time amount including shortening the row precharge time (tRP_S), which is less than the default row precharge time (tRP).

[0146] Aspect 10: The device according to any one of aspects 8 to 9 further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof for: generating a set of timing signals to turn off the first row of the memory cell at least in part based on receiving the precharge command; maintaining the set of timing signals after receiving the second activation command; and turning off the first row of the memory cell after receiving the second activation command at least in part based on maintaining the set of timing signals.

[0147] Aspect 11: The device according to any one of aspects 1 to 10 further comprises an operation, feature, circuit system, logic, component, or instruction or any combination thereof for: receiving a second instruction at least in part based on receiving the second activation command and before receiving a third activation command for a third subarray of the memory bank; activating a portion of the third subarray of the memory bank at least in part based on receiving the second instruction; and receiving the third activation command to open a third row of memory cells in a fourth subarray of the memory bank after activating the portion of the third subarray, wherein the third subarray is different from the fourth subarray.

[0148] Aspect 12: The device according to aspect 11 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for receiving a read command within a time amount following the receipt of the third activation command, the time amount including the default row address to column address delay (tRCD).

[0149] Aspect 13: The device according to any one of aspects 1 to 12 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for receiving the instruction in the first activation command.

[0150] Aspect 14: The device according to any one of aspects 1 to 13 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for the following: the indication includes one or more bits indicating a segment index, one or more bits indicating a row address or both.

[0151] Figure 8The flowchart illustrates a method 800 for indicating line activation, based on examples disclosed herein. The operation of method 800 can be implemented via a host device or its components described herein. For example, it can be implemented via reference... Figure 1 The host device described in sections 4 and 6 performs the operation of method 800. In some instances, the host device may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the host device may use dedicated hardware to perform aspects of the described functions.

[0152] In 805, the method may include transmitting a first activation command to activate a first row of memory cells in a first subarray of the memory bank of the memory device. The operation of 805 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 6 The described aspect of the activation command component 625 performing the operation of 805.

[0153] In 810, the method may include an instruction at least in part based on transmitting a first activation command and transmitting the second activation command prior to transmitting a second activation command for a second subarray of the memory bank. Operation 810 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 6 The description indicates the aspects of the operation of the transmission component 630 performing 810.

[0154] In 815, the method may include transmitting a second activation command to activate a second row of memory cells in a second subarray of the memory bank. The operation of 815 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference... Figure 6 The described aspect of the activation command component 625 performing the operation of 815.

[0155] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0156] Aspect 15: An apparatus comprising features, circuitry, logic, components, or instructions, or any combination thereof, for: transmitting a first activation command to open a first row of memory cells in a first subarray of a memory bank of a memory device; transmitting an instruction at least in part based on transmitting the first activation command and prior to transmitting a second activation command for a second subarray of the memory bank; activating a portion of the second subarray of the memory bank at least in part based on receiving the instruction; and transmitting the second activation command to open a second row of memory cells in the second subarray of the memory bank.

[0157] Aspect 16: The apparatus according to aspect 15, wherein the second subarray comprises the first subarray and the method, apparatus and non-transitory computer-readable medium further comprise operations, features, circuitry, logic, components or instructions or any combination thereof for transmitting a read command within a time duration following the transmission of the second activation command, the time duration comprising a shortened row address to column address delay (tRCD_SS) of the same segment index, which is less than the default row address to column address delay (tRCD).

[0158] Aspect 17: The apparatus according to any one of aspects 15 to 16, wherein the second subarray is different from the first subarray and the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuitry, logic, components, or instructions or any combination thereof for transmitting a read command within a time period following the transmission of the second activation command, the time period including a shortened row address to column address delay (tRCD_DS) of a different segment index, which is less than the default row address to column address delay (tRCD).

[0159] Aspect 18: The device according to any one of aspects 15 to 17 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for transmitting a precharge command to turn off the first row of the memory cell before transmitting the second activation command.

[0160] Aspect 19: The device according to aspect 18 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for transmitting the indication in the precharge command.

[0161] Aspect 20: The device according to any one of aspects 18 to 19 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for transmitting the second activation command before closing the first row of memory cells in the first subarray of the memory bank.

[0162] Aspect 21: The device according to aspect 20 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for transmitting the second activation command within a time amount following the transmission of the precharge command, the time amount including shortening the row precharge time (tRP_S), which is less than the default row precharge time (tRP).

[0163] Aspect 22: The device according to any one of aspects 15 to 21 further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof for: at least in part based on transmitting the second activation command and transmitting a second indication of the third activation command prior to transmitting a third activation command of the third subarray of the memory bank and transmitting the third activation command to open a third row of memory cells in a fourth subarray of the memory bank, wherein the third subarray is different from the fourth subarray.

[0164] Aspect 23: The device according to aspect 22 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for transmitting a read command within a time amount following the transmission of the third activation command, the time amount including the default row address to column address delay (tRCD).

[0165] Aspect 24: The device according to any one of aspects 15 to 23 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for transmitting the instruction in the first activation command.

[0166] Aspect 25: The device according to any one of aspects 15 to 24 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for the following: the indication includes one or more bits indicating a segment index, one or more bits indicating a row address or both.

[0167] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods may be combined.

[0168] This describes a device. An overview of aspects of the device described herein is provided below:

[0169] Aspect 26: An apparatus comprising: a storage bank of memory cells including one or more subarrays; and a controller coupled to the storage bank and configured such that the apparatus: receives a first activation command to open a first row of memory cells in a first subarray of the storage bank; receives an instruction to the second activation command at least in part based on receiving the first activation command and prior to receiving a second activation command for a second subarray of the storage bank; activates a portion of the second subarray of the storage bank at least in part based on receiving the instruction; and receives the second activation command to open a second row of memory cells in the second subarray of the storage bank after activating the portion of the second subarray.

[0170] Aspect 27: The device according to aspect 26, wherein the second subarray comprises the first subarray, and the controller is further configured to cause the device to: generate a first set of timing signals to activate the first subarray of the memory at least in part based on receiving the first activation command; and generate a second set of timing signals to activate the first subarray of the memory at least in part based on receiving the instruction and before receiving the second activation command.

[0171] Aspect 28: The device according to aspect 27, wherein the controller is further configured to cause the device to: receive a read command within a time period following the receipt of the second activation command, the time period including the row address to column address delay (tRCD_SS) of the same segment index, which is less than the default row address to column address delay (tRCD).

[0172] Aspect 29: The device according to any one of aspects 26 to 28, wherein the second subarray is different from the first subarray, the controller is further configured to cause the device to: generate a first set of timing signals to activate the first subarray of the memory at least in part based on receiving the first activation command; and generate a second set of timing signals to activate the second subarray of the memory at least in part based on receiving the instruction and before receiving the second activation command.

[0173] Aspect 30: The device according to aspect 29, wherein the controller is further configured to cause the device to: receive a read command within a time period following the receipt of the second activation command, the time period including the row address to column address delay (tRCD_DS) of the different segment index shortening, which is less than the default row address to column address delay (tRCD).

[0174] Aspect 31: The device according to any one of aspects 26 to 30, wherein the controller is further configured to cause the device to: receive a precharge command to shut down the first row of the memory cell before receiving the second activation command.

[0175] Aspect 32: The device according to aspect 31, wherein the instruction is received in the pre-charge command.

[0176] Aspect 33: The device according to any one of aspects 31 to 32, wherein the second activation command is received before the first row of memory cells in the first subarray of the storage body is turned off.

[0177] Aspect 34: The device according to aspect 33, wherein the second activation command is received within a time period following the receipt of the precharge command, the time period including a shortened row precharge time (tRP_S) which is less than the default row precharge time (tRP).

[0178] Aspect 35: The device according to any one of aspects 33 to 34, wherein the controller is further configured to cause the device to: generate a set of timing signals to close the first row of the memory cell at least in part based on receiving the precharge command; maintain the set of timing signals after receiving the second activation command; and close the first row of the memory cell after receiving the second activation command at least in part based on maintaining the set of timing signals.

[0179] Aspect 36: The device according to any one of aspects 26 to 35, wherein the controller is further configured to cause the device to: receive a second instruction based at least in part on receiving the second activation command and before receiving a third activation command for a third subarray of the memory bank; activate a portion of the third subarray of the memory bank based at least in part on receiving the third instruction; and receive the third activation command to open a third row of memory cells in a fourth subarray of the memory bank after activating the portion of the third subarray, wherein the third subarray is different from the fourth subarray.

[0180] Aspect 37: The device according to aspect 36, wherein the controller is further configured to cause the device to receive a read command within a time period following the receipt of the third activation command, the time period including the default row address to column address delay (tRCD).

[0181] Aspect 38: The device according to any one of aspects 26 to 37, wherein the instruction is received in the first activation command.

[0182] Aspect 39: The device according to any one of aspects 26 to 38, wherein the indication comprises a segment index, one or more row address bits, or both.

[0183] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal can represent a signal bus, where the bus can have various bit widths.

[0184] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that supports signal flow between them. Components are considered to be in electronic communication (or conductive contact, connection, or coupling) if any conductive path exists between them that supports signal flow between them at any given time. At any given time, the conductive path between components that are in electronic communication (or conductive contact, connection, or coupling) may be open or closed based on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between the components, or it may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0185] The term "coupling" refers to the condition that changes from an open-circuit relationship between components (where signals cannot currently travel between components via conductive paths) to a closed-circuit relationship between components (where signals can travel between components via conductive paths). When a component, such as a controller, couples other components together, the component triggers a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0186] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, when a switch positioned between two components is turned on, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0187] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0188] As used herein, the term "electrode" may refer to an electrical conductor and, in some instances, may serve as an electrical contact for a memory cell or other component of a memory array. Electrodes may include traces, wires, conductive lines, conductive layers, or the like that providing a conductive path between elements or components of the memory array.

[0189] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0190] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0191] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," and not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0192] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a hyphen after the reference numeral and a second numeral to differentiate them. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0193] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located at various locations, including distribution such that portions of the functions are implemented at different physical locations.

[0194] For example, the various specification boxes and modules described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in alternative examples, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0195] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0196] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave) is included in the media definition. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0197] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure will be made, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: Receive a first activation command to activate the first row of memory cells in the first subarray of the memory bank of the memory device; At least in part, based on receiving the first activation command and receiving the second activation command prior to receiving the second activation command for the second subarray of the memory bank; At least in part based on receiving the instruction, a portion of the second subarray of the memory is activated; and The second activation command is received to open the second row of memory cells in the second subarray of the storage body after the portion of the second subarray is activated.

2. The method of claim 1, wherein the second subarray and the first subarray are identical, the method further comprising: At least in part, a first set of timing signals is generated based on receiving the first activation command to activate the first subarray of the memory; and The first subarray of the memory bank is activated at least in part based on receiving the instruction and generating a second set of timing signals before receiving the second activation command.

3. The method according to claim 2, further comprising: The read command is received within a time period following the receipt of the second activation command, the time period including the shortened row address to column address delay (tRCD_SS) of the same segment index, which is less than the default row address to column address delay (tRCD).

4. The method of claim 1, wherein the second subarray is different from the first subarray, the method further comprising: At least in part, a first set of timing signals is generated based on receiving the first activation command to activate the first subarray of the memory; and The second subarray of the memory bank is activated at least in part based on receiving the instruction and generating a second set of timing signals before receiving the second activation command.

5. The method of claim 4, further comprising: The read command is received within a time period following the receipt of the second activation command, the time period including the row address to column address delay (tRCD_DS) of the different segment indexes, which is less than the default row address to column address delay (tRCD).

6. The method of claim 1, further comprising: A precharge command is received to close the first row of the memory cell before the second activation command is received.

7. The method of claim 6, wherein the instruction is received in the precharge command.

8. The method of claim 6, wherein the second activation command is received before the first row of memory cells in the first subarray of the memory bank is closed.

9. The method of claim 8, wherein the second activation command is received within a time period following the receipt of the precharge command, the time period including shortening the row precharge time (tRP_S), which is less than the default row precharge time (tRP).

10. The method of claim 8, further comprising: A set of timing signals is generated, at least in part, based on receiving the precharge command, to turn off the first row of the memory cell; The set of timing signals is maintained after receiving the second activation command; and At least in part, this is based on maintaining the set of timing signals to close the first row of memory cells after receiving the second activation command.

11. The method of claim 1, further comprising: At least in part, based on a second indication that the third activation command is received before the third activation command for the third subarray of the memory bank is received; At least in part based on receiving the second instruction, a portion of the third subarray of the memory is activated; and The third activation command is received to open the third row of memory cells in the fourth subarray of the memory bank after activating the portion of the third subarray, wherein the third subarray is different from the fourth subarray.

12. The method of claim 11, further comprising: The read command is received within a time period following the receipt of the third activation command, the time period including the default row address to column address delay (tRCD).

13. The method of claim 1, wherein the instruction is received in the first activation command.

14. The method of claim 1, wherein the indication includes one or more bits indicating a segment index, one or more bits indicating a row address, or both.

15. A method comprising: Transmit a first activation command to activate the first row of memory cells in the first subarray of the memory bank of the memory device; At least in part, based on the instruction to transmit the second activation command before transmitting the second activation command for the second subarray of the memory bank; and The second activation command is transmitted to enable the second row of memory cells in the second subarray of the memory bank.

16. The method of claim 15, wherein the second subarray and the first subarray are identical, the method further comprising: The read command is transmitted within a time period following the transmission of the second activation command, the time period including the shortened row address to column address delay (tRCD_SS) of the same segment index, which is less than the default row address to column address delay (tRCD).

17. The method of claim 15, wherein the second subarray is different from the first subarray, the method further comprising: The read command is transmitted within a time period following the transmission of the second activation command. This time period includes the shortened row address to column address delay (tRCD_DS) of different segment indexes, which is less than the default row address to column address delay (tRCD).

18. The method of claim 15, further comprising: A precharge command is transmitted to close the first row of the memory cell before the second activation command is transmitted.

19. The method of claim 18, wherein the indication is transmitted in the precharge command.

20. The method of claim 18, wherein the second activation command is transmitted before the first row of memory cells in the first subarray of the memory bank is closed.

21. The method of claim 20, wherein the second activation command is transmitted within a time period following the transmission of the precharge command, the time period including shortening the row precharge time (tRP_S), which is less than the default row precharge time (tRP).

22. The method of claim 15, further comprising: At least in part, based on a second indication that transmits the second activation command and transmits the third activation command before transmitting the third activation command for the third subarray of the memory bank; and The third activation command is transmitted to open the third row of memory cells in the fourth subarray of the memory bank, wherein the third subarray is different from the fourth subarray.

23. The method of claim 22, further comprising: The read command is transmitted within a time period following the transmission of the third activation command, the time period including the default row address to column address delay (tRCD).

24. The method of claim 15, wherein the indication is transmitted in the first activation command.

25. An apparatus comprising: A memory cell is a storage unit that includes one or more subarrays; and A controller, coupled to the storage and configured to cause the device to: Receive a first activation command to open the first row of memory cells in the first subarray of the memory bank; At least in part, based on receiving the first activation command and receiving the second activation command prior to receiving the second activation command for the second subarray of the memory bank; At least in part, a portion of the second subarray of the memory is activated based on receiving the instruction; and The second activation command is received to open the second row of memory cells in the second subarray of the memory bank after the portion of the second subarray is activated.

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