Data processing method, storage device, storage medium and computer program product

Abstract

The embodiment of the present application discloses a data processing method, a storage device, a storage medium and a computer program product, wherein the storage device also includes a storage module, wherein the data processing method includes: responding to an operation signal triggered externally, when the operation signal indicates that two read operations and one write operation are required, controlling a first path connected between the storage module and the control module to perform a read operation and a write operation, and controlling a second path connected between the storage module and the control module to perform a read operation. In this way, the two-read and one-write functions can be realized through the storage device, so as to reduce the area occupied by the storage device and reduce the device cost while ensuring high performance and the two-read and one-write functions.

Description

Technical Field

[0001] The present application relates to but is not limited to the field of communication technology, and in particular to a data processing method, device, storage medium and program product. Background Art

[0002] Memory is an electronic device used to store programs and data, and is composed of multiple storage modules. The circuit structure of the storage module determines the read and write performance of the memory.

[0003] Memories such as static random access memory (SRAM) have read and write functions of a single port, but the port can only perform read operations or only perform write operations. Read operations and write operations cannot be performed at the same time, resulting in low read and write performance. Summary of the invention

[0004] In view of this, the embodiments of the present application at least provide a data processing method, a storage device, a storage medium and a computer program product. In this way, the two-read-one-write function can be realized through the storage device, so as to reduce the area occupied by the storage device and reduce the device cost while ensuring high performance and the two-read-one-write function.

[0005] The technical solution of the embodiment of the present application is implemented as follows:

[0006] On the one hand, an embodiment of the present application provides a data processing method, which is applied to a control module in a storage device, wherein the storage device also includes a storage module. The data processing method includes: responding to an externally triggered operation signal, when the operation signal indicates that two read operations and one write operation are required, controlling a first path connected between the storage module and the control module to perform a read operation and a write operation, and at the same time controlling a second path connected between the storage module and the control module to perform a read operation.

[0007] In some embodiments, the storage device includes a pre-charging circuit, the first path includes a read-write word line, a first bit line and a second bit line, and the read-write word line is used to control the first bit line and the second bit line to discharge; the control of the first path connected between the storage module and the control module to perform read operations and write operations includes: controlling the read-write word line to connect to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the first data to be read by the operation signal, and complete the current read operation; controlling the pre-charging circuit to charge the first bit line and the second bit line to a target voltage, and writing the second data to be written by the operation signal into the storage module through the first path, and completing the current write operation.

[0008] In some embodiments, the storage device includes a positioning device; the control of the read / write word line to connect to the first path and control at least one of the first bit line and the second bit line to discharge to read the first data to be read by the operation signal includes: controlling the read / write word line to connect to the first bit line and the second bit line in the first path; determining the first storage unit from multiple eight-tube storage units of the storage device based on the first address data in the operation signal through the positioning device; controlling at least one of the first bit line and the second bit line to discharge to read the first data in the first storage unit.

[0009] In some embodiments, the storage device includes a positioning device; writing the second data to be written by the operation signal into the storage module through the first path includes: determining the second storage unit from multiple eight-tube storage units of the storage device based on the second address data in the operation signal through the positioning device; and writing the second data into the second storage unit through the first path.

[0010] In some embodiments, the storage device includes a pre-charging circuit, the second path includes a read word line and a third bit line, the read word line is used to control the third bit line to discharge; the control is connected to the second path between the storage module and the control module to perform a reading operation, including: controlling the pre-charging circuit to stop charging the third bit line; controlling the read word line to connect to the second path, and controlling the third bit line to discharge, so as to read the third data to be read by the operation signal, and complete the reading operation.

[0011] In some embodiments, when the operation signal indicates that a read operation is required, the data processing method further includes: when the operation signal indicates that a single read operation is required, controlling the first path to perform a read operation, or controlling the second path to perform a read operation; when the operation signal indicates that two read operations are required, controlling the first path and the second path to perform read operations respectively.

[0012] In some embodiments, the storage device includes a pre-charging circuit, the first path includes a read-write word line, a first bit line and a second bit line, the read-write word line is used to control the first bit line and the second bit line to discharge; the control of the first path to perform a read operation includes: controlling the pre-charging circuit to stop charging the first bit line and the second bit line; controlling the read-write word line to connect to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the fourth data to be read by the operation signal, and complete the current read operation.

[0013] In some embodiments, the storage device includes a pre-charging circuit, the first path includes a read-write word line, a first bit line and a second bit line, and the read-write word line is used to control the first bit line and the second bit line to discharge; when the operation signal indicates that a write operation is required, the data processing method also includes: controlling the pre-charging circuit to stop charging the first bit line and the second bit line; controlling the read-write word line to connect to the first path, and writing the fifth data to be written by the operation signal into the storage module through the first bit line and the second bit line to complete this write operation.

[0014] In some embodiments, when the operation signal indicates that a read operation and a write operation are required, the data processing method further includes: controlling the first path to perform a read operation and a write operation; or, controlling the first path to perform a write operation and controlling the second path to perform a read operation.

[0015] On the other hand, an embodiment of the present application provides a storage device, comprising: a storage module and a control module, the storage module being composed of a plurality of eight-tube storage units; a first path and a second path being connected between the control module and the storage module; the control module being used to perform read operations and write operations through the first path, and to perform read operations through the second path, thereby realizing two reads and one write of data for the storage module.

[0016] In some embodiments, the first path includes a first transistor, a second transistor, a first port and a second port, and the second path includes a third transistor, a fourth transistor and a third port; the first end of the first transistor, the first end of the second transistor and the first end of the third transistor are respectively connected to the latch, the second end of the first transistor is connected to the first port, the second end of the second transistor is connected to the second port, the second end of the third transistor is connected to the first end of the fourth transistor, and the second end of the fourth transistor is connected to the third port.

[0017] In some embodiments, the first path includes: a read / write word line and a first bit line and a second bit line, the first bit line and the second bit line are a pair of complementary bit lines; the first end of the read / write word line is connected to the control module, and the second end of the read / write word line is respectively connected to the control end of the first transistor and the control end of the second transistor; the first port is connected to the first end of the first bit line and the first end of the second bit line, the second port is connected to the first end of the first bit line and the first end of the second bit line, the second end of the first bit line is connected to the second end of the first transistor, and the second end of the second bit line is connected to the second end of the second transistor; the control module is used to control the read / write word line to connect the first transistor and the second transistor to connect the first path, and control at least one of the first bit line and the second bit line to discharge, so as to read out the data of at least one eight-transistor storage unit in the storage module through the first port to realize the read operation; control the first bit line and the second bit line to write the data into at least one eight-transistor storage unit in the storage module through the second port to realize the write operation.

[0018] In some embodiments, the second path includes a read word line and a third bit line; the first end of the read word line is connected to the control module, and the second end of the read word line is connected to the control end of the fourth transistor; the third port is connected to the first end of the third bit line, and the second end of the third bit line is connected to the second end of the fourth transistor; the control module is used to control the read word line to connect the third transistor and the fourth transistor to connect the second path, and control the third bit line to discharge, so as to read out the data of at least one eight-transistor storage unit in the storage module through the third port to realize the read operation.

[0019] In some embodiments, the storage device includes an addressing module; the addressing module is connected between the control module and the storage module; the addressing module is used to determine the storage unit corresponding to any address data from multiple eight-tube storage units of the storage module.

[0020] In some embodiments, the addressing module includes a first addressing device and a second addressing device; the first end of the first addressing device is connected to the control module, and the second end of the first addressing device is connected to the read-write word line and the read word line in the first path; the first end of the second addressing device is connected to the control module, and the second end of the second addressing device is connected to the first bit line and the second bit line in the first path; the first addressing device is used to determine the row corresponding to any address data from the multiple eight-tube storage units of the storage module; the second addressing device is used to determine the column corresponding to any address data from the multiple eight-tube storage units of the storage module.

[0021] In some embodiments, the storage device includes a precharge circuit; the precharge circuit is connected between the control module and the storage module; the precharge circuit is used to charge the bit line in the storage device to a target voltage after the read and write operations are completed.

[0022] In some embodiments, the control module includes a pre-decoding circuit and a control circuit; the pre-decoding circuit is used to pre-decode any address data and transmit the decoded address data to the first addressing device; the control circuit is used to control the interaction of various components in the storage device.

[0023] In some embodiments, the storage device includes a first read circuit; a first end of the first read circuit is connected to the first port, and a second end of the first read circuit is connected to a first end of the first bit line and a first end of the second bit line; the first read circuit is used to amplify and latch a signal carrying data read from the storage module through the first path, and output a first processed signal from the first port.

[0024] In some embodiments, the storage device includes a write circuit; a first end of the write circuit is connected to the second port, and a second end of the write circuit is connected to a first end of the first bit line and a first end of the second bit line; the write circuit is used to write data to the first bit line and the second bit line based on instructions from the control module, and then write data to the storage module.

[0025] In some embodiments, the storage device includes a second read circuit; a first end of the second read circuit is connected to the control module, and a second end of the second read circuit is connected to the third bit line; the second read circuit is used to amplify and latch a signal carrying data read from the storage module through the second path, and output a second processed signal from the second port.

[0026] On the other hand, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements part or all of the steps in the above method when executed by a processor.

[0027] On the other hand, an embodiment of the present application provides a computer program, including a computer-readable code. When the computer-readable code is executed in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.

[0028] On the other hand, an embodiment of the present application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, it implements some or all of the steps in the above method.

[0029] In the embodiment of the present application, a first path having both a read function and a write function and a second path having a read function are constructed between the control module and the storage module; thus, the control module can control the first path to implement a read operation and a write operation, and control the second path to implement a read operation, so that the storage device has two read and one write functions, so as to reduce the area occupied by the storage device while ensuring high performance and two read and one write functions, thereby reducing the overall area of ​​the SRAM made based on the storage device, thereby reducing the chip cost.

[0030] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application.

[0032] Figure 1 A schematic diagram of the composition structure of a storage device provided in an embodiment of the present application Figure 1 ;

[0033] Figure 2 A schematic diagram of the composition structure of an eight-tube storage unit in a storage device provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of the composition structure of a storage device provided in an embodiment of the present application Figure 2 ;

[0035] Figure 4 A schematic diagram of an implementation process of a data processing method provided in an embodiment of the present application Figure 1 ;

[0036] Figure 5 A schematic diagram of an implementation process of a data processing method provided in an embodiment of the present application Figure 2 ;

[0037] Figure 6 A schematic diagram of a working timing of a write port and a read port working simultaneously provided in an embodiment of the present application;

[0038] Figure 7 A schematic diagram of the working timing of a read port provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0040] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0041] The terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing this application and are not intended to limit this application.

[0043] In order to better understand the data processing method provided in the embodiment of the present application, the solution in the related technology is first described below.

[0044] With the development of Moore's Law, integrated circuit technology continues to advance, and chips have put forward higher requirements on the functions of various memories. In order to meet these requirements, the circuit design of memories is also constantly evolving.

[0045] The earliest static memory circuit used a six-tube storage module, which was divided into high-performance single-port SRAM and high-density single-port SRAM according to requirements such as read and write performance and the physical area occupied.

[0046] High-performance single-port SRAM uses a storage module in which the size relationship between the transmission tube, the pull-down N-type metal-oxide-semiconductor field-effect transistor (NMOS tube), and the pull-up NMOS tube is 2:2:1. It has a high read and write speed and can meet the high-speed requirements of data processing.

[0047] The functions of high-density single-port SRAM and high-performance single-port SRAM are the same. The difference is that high-density single-port SRAM uses a high-density 6-tube bit cell (bitcell), and usually uses a storage module with a size relationship of 1:1:1 between the transmission tube, the pull-down NMOS tube, and the pull-up NMOS tube. This design reduces the area of ​​the storage module, but the disadvantage is that the read current becomes smaller and the performance becomes worse. This type of SRAM has a single-port read and write function. The port can only perform read operations or only perform write operations, and cannot perform read operations and write operations at the same time. .

[0048] To this end, the present application hopes to realize the two-read and one-write functions based on a storage module with fewer transistors through a special design of peripheral circuits.

[0049] The present application embodiment provides a storage device 10. Figure 1 As shown, the storage device 10 includes: a storage module 12 and a control module 11; a first path 13 and a second path 14 are connected between the control module 11 and the storage module 12; the control module 11 is used to perform read operations and write operations through the first path 13, and perform read operations through the second path 14, so as to realize two reads and one write for the data of the storage module 12.

[0050] The storage device 10 is used to store various types of data. The data that can be stored in the storage device 10 may include but is not limited to: programs, codes, files, etc. In a feasible implementation, the storage device 10 can be made into a device with storage function such as a hard disk, a solid state drive, a mobile hard disk, a USB flash drive, a memory card, an optical disk, and a cloud storage.

[0051] The storage module 12 is composed of a plurality of eight-transistor storage units. An eight-transistor storage unit may refer to a basic storage unit composed of eight transistors. Each storage unit may store one bit (the smallest unit of information). In a feasible implementation, the storage module 12 may be an array composed of a large number of eight-transistor storage units or storage elements, so the storage module 12 may also be referred to as an eight-transistor storage unit array, or an eight-transistor memory.

[0052] The first path 13 refers to a path that has both read and write functions, so the first path 13 can also be called a read-write path, or a shared path; the second path 14 refers to a path that only has a read function, so the second path 14 can also be called a read path. In this way, the storage device 10 having the first path 13 and the second path 14 can achieve two read and one write functions.

[0053] In a feasible implementation, a first path 13 having both read and write functions and a second path 14 having a read function can be constructed between the control module 11 and the storage module 12; and, the control logic of the two read and one write functions is determined, and the control logic of the two read and one write functions is compiled into the control module 11; in this way, the control module 11 controls the first path 13 to implement one read operation and one write operation, and implements one read operation through the second path 14, thereby realizing two reads and one write.

[0054] It should be noted that the existing eight-tube memory can only realize one read operation and one write operation, that is, the existing eight-tube memory only has one read and one write function; however, the present application optimizes the circuit and processing logic of the existing eight-tube memory, and adds a read function without changing the occupied area, so that the optimized eight-tube memory can realize two read operations and one write operation, that is, the optimized eight-tube memory has two read and one write functions. In this way, while ensuring high performance and two read and one write functions, the area occupied by the storage device can be reduced, thereby reducing the overall area of ​​the SRAM made based on the storage device, thereby reducing the chip cost.

[0055] In the embodiment of the present application, a first path having both a read function and a write function and a second path having a read function are constructed between the control module and the storage module; thus, the control module can control the first path to implement a read operation and a write operation, and control the second path to implement a read operation, so that the storage device has two read and one write functions, so as to reduce the area occupied by the storage device while ensuring high performance and two read and one write functions, thereby reducing the overall area of ​​the SRAM made based on the storage device, thereby reducing the chip cost.

[0056] In some embodiments, Figure 2 As shown, the eight-transistor storage unit 120 includes a latch 121, a first path 13 and a second path 14. The first transistor MNP0 and the second transistor MNP1 of the first path 13; the third transistor MNDR and the fourth transistor MNPR of the second path 14. The first end of the first transistor MNP0, the first end of the second transistor MNP1 and the first end of the third transistor MNDR are respectively connected to the latch, the second end of the first transistor MNP0 is connected to the first port, the second end of the second transistor MNP1 is connected to the second port, the second end of the third transistor MNDR is connected to the first end of the fourth transistor MNPR, and the second end of the fourth transistor MNPR is connected to the third port.

[0057] The first transistor MNP0, the second transistor MNP1, the third transistor MNDR, the fourth transistor MNPR and the fifth transistor can all be NMOS transistors. The first transistor MNP0 and the second transistor MNP1 are used as transmission transistors to form a first path 13 (read-write path). The third transistor MNDR and the fourth transistor MNPR are used as transmission transistors to form a second path 14 (read path). In a feasible implementation, the first transistor MNP0, the second transistor MNP1, the third transistor MNDR and the fourth transistor MNPR can all be NMOS transistors with transmission function.

[0058] The latch 121 is used to store data. In a feasible implementation, the latch 121 may include four fifth transistors. The four fifth transistors may include Figure 2 The first pull-up transistor MPU0, the second pull-up transistor MPU1, the first pull-down transistor MND0 and the second pull-down transistor MND1 are shown. In the structure of the latch 121, the transistor is used as a switch, and the current flow in the latch 121 is controlled by turning on and off the transistor, thereby realizing the storage and transmission of the signal.

[0059] like Figure 2 As shown, the first pull-up transistor MPU0, the second pull-up transistor MPU1, the first pull-down transistor MND0 and the second pull-down transistor MND1 can be interconnected to form a latch 121. The first end of the first transistor MNP0, the first end of the second transistor MNP1, and the first end of the third transistor MNDR are respectively connected to the latch 121, the second end of the first transistor MNP0 is connected to the first port, the second end of the second transistor MNP1 is connected to the second port, the second end of the third transistor MNDR is connected to the first end of the fourth transistor MNPR, and the second end of the fourth transistor MNPR is connected to the third port.

[0060] In the above embodiment, the first path 13 can be formed by the first transistor MNP0 and the second transistor MNP1 to read the data stored in the latch 121 and write the data into the latch 121; the second path 14 can be formed by the third transistor MNDR and the fourth transistor MNPR to read the data stored in the latch 121; the latch 121 can be formed by four transistors to store data.

[0061] In some embodiments, Figure 2As shown, the first path 13 includes: a read / write word line RWWL and a first bit line RWBLB, a second bit line RWBL, a first port and a second port, wherein the first bit line RWBLB and the second bit line RWBL are a pair of complementary bit lines; a first end of the read / write word line RWWL is connected to the control module 11, and a second end of the read / write word line RWWL is respectively connected to a control end of the first transistor MNP0 and a control end of the second transistor MNP1; the first port is connected to a first end of the first bit line RWBLB and a first end of the second bit line RWBL, the second port is connected to a first end of the first bit line RWBLB and a first end of the second bit line RWBL, and a second end of the first bit line RWBLB is connected to the first The second end of the transistor MNP0 and the second end of the second bit line RWBL are connected to the second end of the second transistor MNP1; the control module 11 is used to control the read-write word line RWWL to connect the first transistor MNP0 and the second transistor MNP1 to connect the first path 13, and control at least one of the first bit line RWBLB and the second bit line RWBL to discharge, and read the data of at least one eight-transistor storage unit in the storage module 12 through the first port to realize the read operation; control the first bit line RWBLB and the second bit line RWBL to write the data into at least one eight-transistor storage unit in the storage module 12 through the second port to realize the write operation.

[0062] The word line is used to control the conduction of the bit line. The bit line is used to read and write the storage unit in the storage module 12. The read-write word line RWWL is used to control the connection and disconnection of the first path 13; specifically, the read-write word line RWWL is used to control the connection of the first transistor MNP0 and the second transistor MNP1 to connect the storage module 12 with the first bit line RWBLB and the second bit line RWBL, thereby controlling the connection of the first path 13. The first bit line RWBLB and the second bit line RWBL are a pair of complementary bit lines for reading and writing data.

[0063] The first port is a port for performing a read operation through the first path 13. The second port is a port for performing a write operation through the first path 13. Data read from one or more eight-pipe storage units in the storage module 12 can be transmitted to an external device through the first path 13 through the first port, and external data can be written into one or more eight-pipe storage units in the storage module 12 through the first path 13 through the second port.

[0064] When a write operation is performed through the first path 13, the first path 13 is used as a write path, the read / write word line RWWL is controlled to connect to the first path 13 (the first transistor MNP0 and the second transistor MNP1), and the data transmitted from the second port is written into the storage module 12 through the first bit line RWBLB and the second bit line RWBL; when a read operation is performed through the first path 13, the first path 13 is used as a read path, the read / write word line RWWL is controlled to connect to the first path 13 (the first transistor MNP0 and the second transistor MNP1), and any one of the first bit line RWBLB and the second bit line RWBL is controlled to discharge, and the data read from the storage module 12 is transmitted to the first port through the first bit line RWBLB and the second bit line RWBL, and then transmitted to the external device. Controlling any one of the first bit line RWBLB and the second bit line RWBL to discharge may include: controlling the first bit line RWBLB to discharge, controlling the second bit line RWBL to discharge, and controlling the first bit line RWBLB and the second bit line RWBL to discharge.

[0065] Since data can be read when the charge is moved out of the storage unit, when reading data through the first path 13, it is necessary to control the first bit line RWBLB and / or the second bit line RWBL to discharge so that the charge is moved out of the storage unit to realize the reading of the data of the first path 13; when reading data through the second path 14, it is necessary to control the third bit line RBLB to discharge so that the charge is moved out of the storage unit to realize the reading of the data of the second path 14.

[0066] In one possible implementation, Figure 2 As shown, the first end of the read / write word line RWWL is connected to the control module 11, and the second end of the read / write word line RWWL is respectively connected to the control end of the first transistor MNP0 and the control end of the second transistor MNP1; the first port is connected to the first end of the first bit line RWBLB and the first end of the second bit line RWBL, the second port is connected to the first end of the first bit line RWBLB and the first end of the second bit line RWBL, the second end of the first bit line RWBLB is connected to the second end of the first transistor MNP0, and the second end of the second bit line RWBL is connected to the second end of the second transistor MNP1.

[0067] In the above embodiment, the connection and disconnection of the first path 13 can be controlled by the read-write word line RWWL; data can be read and written through a pair of complementary bit lines, namely, the first bit line RWBLB and the second bit line RWBL.

[0068] In some embodiments, the second path 14 includes a read word line RWL, a third bit line RBLB and a third port; the first end of the read word line RWL is connected to the control module 11, and the second end of the read word line RWL is connected to the control end of the fourth transistor MNPR; the third port is connected to the first end of the third bit line RBLB, and the second end of the third bit line RBLB is connected to the second end of the fourth transistor MNPR; the control module 11 is used to control the read word line RWL to connect the third transistor MNDR and the fourth transistor MNPR to connect the second path 14, and control the third bit line RBLB to discharge, so as to read out the data of at least one eight-transistor storage unit in the storage module 12 through the third port to realize the read operation.

[0069] The read word line RWL is used to control the connection and disconnection of the second path 14; specifically, the read word line RWL is used to control the connection and disconnection of the third transistor MNDR and the fourth transistor MNPR to control the connection and disconnection of the second path 14. The third bit line RBLB is used to implement a read operation by discharging.

[0070] The third port is a port for performing a read operation through the second path 14. The third port can transmit data read from one or more eight-transistor storage units in the storage module 12 to an external device through the second path 14.

[0071] When a read operation is performed through the second path 14, the second path 14 is used as a read path, the read word line RWL is controlled to connect to the second path 14 (the third transistor MNDR and the fourth transistor MNPR), and the third bit line RBLB is controlled to discharge, and the data read from the storage module 12 is transmitted to the third port through the third bit line RBLB, and then transmitted to the external device.

[0072] In the above embodiment, the connection and disconnection of the second path 14 can be controlled by the read word line RWL; and data can be read by the third bit line RBLB.

[0073] In some embodiments, Figure 1 As shown, the storage device 10 includes an addressing module 15; the addressing module 15 is connected between the control module 11 and the storage module 12; the addressing module 15 is used to determine the storage unit corresponding to any address data from multiple eight-tube storage units of the storage module 12.

[0074] The storage module 12 is used to quickly determine a storage unit corresponding to any address data from a plurality of eight-transistor storage units of the storage module 12 based on the instruction output by the control module 11 .

[0075] In the above embodiment, the addressing module 15 can quickly locate the storage unit corresponding to any address data, thereby realizing fast addressing and improving the data processing rate.

[0076] In some embodiments, Figure 3 As shown, the addressing module 15 includes a first addressing device 151 and a second addressing device 152; the first end of the first addressing device 151 is connected to the control module 11, and the second end of the first addressing device 151 is connected to the read-write word line RWWL and the read word line RWL in the first path 13; the first end of the second addressing device 152 is connected to the control module 11, and the second end of the second addressing device 152 is connected to the first bit line RWBLB and the second bit line RWBL in the first path 13; the first addressing device 151 is used to determine the row corresponding to any address data from the multiple eight-tube storage units of the storage module 12; the second addressing device 152 is used to determine the column corresponding to any address data from the multiple eight-tube storage units of the storage module 12.

[0077] The first addressing device 151 is used to determine a specific row corresponding to any address data from a plurality of eight-pipe storage units of the storage module 12. In a feasible implementation, the first addressing device 151 may be a row decoder. The second addressing device 152 is used to determine a specific column corresponding to any address data from a plurality of eight-pipe storage units of the storage module 12. In a feasible implementation, the second addressing device 152 may be a column selector.

[0078] In the above embodiment, the first addressing device 151 can determine the specific column corresponding to any address data from the multiple eight-tube storage units of the storage module 12, and the second addressing device 152 can determine the specific column corresponding to any address data from the multiple eight-tube storage units of the storage module 12, and then determine the eight-tube storage unit corresponding to any address data based on the specific row and the specific column.

[0079] In some embodiments, Figure 3 As shown, the storage device 10 includes a pre-charging circuit 16; the pre-charging circuit 16 is connected between the control module 11 and the storage module 12; the pre-charging circuit 16 is used to charge the bit line in the storage device 10 to a target voltage after the read and write operations are completed.

[0080] The precharge circuit 16 is used to charge the bit lines in the storage device 10 to a target voltage to provide a stable reference point for read and write operations, thereby improving the accuracy of data reading. The target voltage can be a power supply voltage or half of the operating voltage of the storage device 10.

[0081] Since a data writing operation is performed when charges are moved into a memory cell, and a data reading operation is performed when charges are moved out of a memory cell, the bit line needs to be charged to an appropriate voltage after the read and write operations are completed.

[0082] In some embodiments, the control module 11 includes a pre-decoding circuit and a control circuit; the pre-decoding circuit is used to pre-decode any address data and transmit the decoded address data to the first addressing device 151; the control circuit is used to control the interaction of each component in the storage device 10.

[0083] Any address data may refer to the address where the data to be read is located, or the address where the data is to be written. The pre-decoding circuit is mainly used to pre-decode the address data and transmit the pre-decoded address data to the row decoder.

[0084] In some embodiments, Figure 3 As shown, the storage device 10 includes a first read circuit 17; a first end of the first read circuit 17 is connected to the first port, and a second end of the first read circuit 17 is connected to a first end of the first bit line RWBLB and a first end of the second bit line RWBL; the first read circuit 17 is used to amplify and latch a signal carrying data read from the storage module 12 through the first path 13, and output a first processed signal from the first port.

[0085] The first read circuit 17 is used to transmit the data read through the first path 13, specifically, to transmit the data read from the first bit line RWBLB and the second bit line RWBL to the first port. In a feasible implementation, the first read circuit 17 may include but is not limited to: a sense amplifier and a read circuit. The sense amplifier is used to amplify the weak signal read from the storage unit so that it can be read by an external circuit. Since the read current of the storage unit is very small, a sense amplifier is required to amplify this weak signal to ensure the correct reading of the data. The read circuit is responsible for latching the signal amplified by the sense amplifier and driving it to the first port.

[0086] In some embodiments, the storage device 10 includes a write circuit 18; a first end of the write circuit 18 is connected to the second port, and a second end of the write circuit 18 is connected to a first end of the first bit line RWBLB and a first end of the second bit line RWBL; the write circuit 18 is used to write data into the first bit line RWBLB and the second bit line RWBL based on instructions from the control module 11, and then write into the storage module 12.

[0087] The write circuit 18 is used to transmit data to the column selector, and then write the data into the storage module 12 through the first path 13. In a feasible implementation, the write circuit 18 may include but is not limited to a first data input channel and a control gate to write data (usually a binary number 0 or 1) into a specific storage element according to the instruction of the control module 11.

[0088] In some embodiments, the storage device 10 includes a second read circuit 19; a first end of the second read circuit 19 is connected to the control module 11, and a second end of the second read circuit 19 is connected to the third bit line RBLB; the second read circuit 19 is used to amplify and latch a signal carrying data read from the storage module 12 through the second path 14, and output a second processed signal from the second port.

[0089] The second read circuit 19 is used to transmit the data read through the second path 14, specifically, to transmit the data read from the third bit line RBLB to the third port. In a feasible implementation, the second read circuit 19 and the first read circuit 17 can have the same structure, or the second read circuit 19 and the first read circuit 17 can be customized according to different read requirements.

[0090] In the above embodiment, the signal carrying the data read from the storage module 12 can be amplified and latched through the first reading circuit 17 and the second reading circuit 19 to ensure the reliability of signal transmission and improve the stability of data transmission; the data can be written into a specific storage element through the writing circuit.

[0091] In some embodiments, Figure 3 As shown, the control module 11 may include a first pin ME_R1 , a second pin ME_R2 , a third pin ME_W, a fourth pin CLK_R1 , a fifth pin CLK_R2 , a sixth pin CLK_W, and a seventh pin ADR_W / R1 / R2 .

[0092] The first pin ME_R1 is used to trigger a read request for a read operation through the first path 13. The second pin ME_R2 is used to trigger a read request for a read operation through the second path 14. The third pin ME_W is used to trigger a write request for a write operation through the first path 13. The fourth pin CLK_R1 is used to trigger a clock signal for synchronizing the reading of data of the first path 13. The fifth pin CLK_R2 is used to trigger a clock signal for synchronizing the reading of data of the second path 14. The sixth pin CLK_W is used to trigger a clock signal for synchronizing the writing of data of the first path 13. The seventh pin ADR_W / R1 / R2 is a pseudo instruction in the ARM assembly instruction. ADR_W / R1 / R2 generally represents a register configuration of an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC); specifically, ADR_W represents a write address register. R1 and R2 represent two different read address registers, which can be used to store different configuration parameters, such as gain setting, reference voltage, input range, output format, etc.

[0093] It should be noted that Figure 3 The storage device 10 shown may be a 2R1W SRAM, that is, an SRAM capable of implementing two read and one write functions, wherein "2R" refers to two read operations and "1W" refers to one write operation.

[0094] The present application provides a data processing method for Figure 3 The control module 11 in the storage device 10 shown in FIG. Figure 4 As shown, the method includes the following step 401:

[0095] Step 401, in response to an externally triggered operation signal, when the operation signal indicates that two read operations and one write operation are required, control a first path connected between the storage module and the control module to perform a read operation and a write operation, and simultaneously control a second path connected between the storage module and the control module to perform a read operation.

[0096] The operation signal characterization requires two read operations and one write operation, that is, the operation signal characterization requires two read and one write functions.

[0097] In a feasible implementation, the operation signal may be triggered by a preset option on the menu bar, or may be triggered by a physical button.

[0098] In a feasible implementation, when the operation signal causes the first pin ME_R1 , the second pin ME_R2 and the third pin ME_W to change from low level to high level, it is determined that the operation signal requiring two reads and one write is triggered.

[0099] In a feasible implementation, the specific implementation of two reads and one write can be: through the control module, first control the first path to perform a read operation and then a write operation (complete one read and one write), and at the same time control the second path to perform a read operation (one read), thus achieving two reads and one write.

[0100] It should be noted that the operations of the two paths can be performed simultaneously or sequentially, and this application does not limit this.

[0101] In some embodiments, the step 401 of “controlling the first path connected between the storage module and the control module to perform a read operation and a write operation” can be implemented by the following steps 4011 to 4012:

[0102] Step 4011, control the read / write word line to connect to the first path, and control at least one of the first bit line and the second bit line to discharge, so as to read the first data to be read by the operation signal, and complete the current read operation.

[0103] In some embodiments, the specific implementation method of step 4011 can be: controlling the read-write word line to connect the first bit line and the second bit line in the first path; determining the first storage unit from the multiple eight-tube storage units of the storage device based on the first address data in the operation signal through the positioning device; controlling at least one of the first bit line and the second bit line to discharge, and reading the first data in the first storage unit.

[0104] Controlling the read / write word line to connect the first bit line and the second bit line in the first path refers to controlling the read / write word line to turn on the first transistor MNP0 and the second transistor MNP1 to connect the first bit line and the second bit line, thereby achieving connectivity of the first path.

[0105] The first data refers to the data to be read through the first path. The first address data refers to the address where the first data is located. The first storage unit is one or more eight-pipe storage cells storing the first data.

[0106] Determining the first storage unit from a plurality of eight-tube storage units of a storage device based on the first address data in an operation signal by a positioning device means that a row corresponding to the first address data is selected from a plurality of eight-tube storage units of a storage device by a row decoder, and a column corresponding to the first address data is selected from a plurality of eight-tube storage units of a storage device by a column selector, and then the first storage unit is obtained according to the selected row and column.

[0107] Since data can be read when charges are moved out of the storage unit, when reading data in the first path, it is necessary to control the first bit line and / or the second bit line to discharge so that charges are moved out of the storage unit to read data in the first path.

[0108] Controlling at least one of the first bit line and the second bit line to discharge and read the first data in the first storage unit includes the following three situations: In the first situation, the first bit line is controlled to discharge, and the first data in the first storage unit is transmitted to the first reading circuit through the column selector, and then transmitted to the first port through the first reading circuit to realize the reading of the data in the first path. In the second situation, the second bit line is controlled to discharge, and the first data in the first storage unit is transmitted to the first reading circuit through the column selector, and then transmitted to the first port through the first reading circuit to realize the reading of the data in the first path. In the third situation, the first bit line and the second bit line are controlled to discharge, and the first data in the first storage unit is transmitted to the first reading circuit through the column selector, and then transmitted to the first port through the first reading circuit to realize the reading of the data in the first path.

[0109] Step 4012: Control the precharge circuit to charge the first bit line and the second bit line to a target voltage, write the second data to be written by the operation signal into the storage module through the first path, and complete the write operation.

[0110] Since step 4011 realizes reading of data in the first path by discharging any one of the first bit line and the second bit line, when performing a write operation here, it is necessary to control the precharge circuit to charge the first bit line and the second bit line to the target voltage to perform a write operation, and write the second data to be written into the storage module through the first path.

[0111] In some embodiments, the specific implementation method of "writing the second data to be written by the operation signal into the storage module through the first path" in the above step 4012 can be: through the positioning device, determine the second storage unit from the multiple eight-tube storage units of the storage device based on the second address data in the operation signal; write the second data into the second storage unit through the first path.

[0112] The second data refers to the data to be written. The second address data refers to the address where the second data is to be written. The second storage unit refers to one or more eight-pipe storage units where the second data is to be written.

[0113] Determining the second storage unit from the multiple eight-tube storage units of the storage device based on the second address data in the operation signal by the positioning device means that the row corresponding to the second address data is selected from the multiple eight-tube storage units of the storage device by the row decoder, and the column corresponding to the second address data is selected from the multiple eight-tube storage units of the storage device by the column selector, and then the second storage unit is obtained according to the selected row and column.

[0114] Writing the second data into the second storage unit through the first path means that the second data is transmitted to the column selector through the second port and the write circuit, and then transmitted to the second storage unit in the storage module by the column selector.

[0115] In some embodiments, the storage device includes a pre-charging circuit, and the second path includes a read word line and a third bit line, and the read word line is used to control the third bit line to discharge; the specific implementation method of "controlling the second path connected between the storage module and the control module to perform a reading operation" in the above step 401 can be: controlling the pre-charging circuit to stop charging the third bit line; controlling the read word line to connect to the second path, and controlling the third bit line to discharge, so as to read the third data to be read by the operation signal, and complete this reading operation.

[0116] In a feasible implementation, the specific implementation of controlling the pre-charging circuit to stop charging the third bit line may be: controlling the charging signal Pchg_R of the pre-charging circuit to turn off charging through a control module.

[0117] The third data refers to data to be read through the second path.

[0118] In a feasible implementation, the specific implementation of "controlling the read word line to connect to the second path, and controlling the third bit line to discharge, so as to read the third data to be read by the operation signal" is: controlling the read word line to connect to the third bit line in the second path; determining the third storage unit from the multiple eight-tube storage units in the storage device based on the third address data in the operation signal through the positioning device; controlling the third bit line to discharge, and reading the third data in the third storage unit.

[0119] Controlling the read word line to connect to the third bit line in the second path refers to controlling the read word line to turn on the third transistor MNDR and the fourth transistor MNPR to connect to the third bit line, thereby achieving connection of the second path.

[0120] The third address data refers to the address where the third data is located. The third storage unit is an eight-pipe storage element storing the third data.

[0121] Determining the third storage unit from the multiple eight-tube storage units of the storage device based on the third address data in the operation signal by the positioning device means that the row corresponding to the third address data is selected from the multiple eight-tube storage units of the storage device by the row decoder, and the column corresponding to the third address data is selected from the multiple eight-tube storage units of the storage device by the column selector, and then the third storage unit is obtained according to the selected row and column.

[0122] Controlling the third bit line to discharge and read the third data in the third storage unit means controlling the third bit line to discharge and transmitting the third data in the third storage unit to the second reading circuit via the column selector, and then transmitting to the third port via the second reading circuit.

[0123] Based on the above embodiment, when the operation signal indicates that a read operation is required, the data processing method provided by the present application further includes the following steps 402 to 403:

[0124] Step 402: When the operation signal indicates that a single read operation is required, control the first path to perform a read operation, and control the second path to perform a read operation.

[0125] In a feasible implementation, it can be determined whether the operation signal is to perform a single read operation or two read operations based on the pin change caused by the operation signal. Specifically, if the operation signal causes a change in any one of the first pin and the second pin, it is determined that the operation signal is to perform a single read operation; if the operation signal causes changes in both the first pin and the second pin, it is determined that the operation signal is to perform two read operations.

[0126] In a feasible implementation, when the operation signal causes the first pin ME_R1 to change from a low level to a high level, it is determined that the operation signal needs to perform a single read operation through the first path, and the first path is controlled to perform a read operation. When the operation signal causes the second pin ME_R2 to change from a low level to a high level, it is determined that the operation signal needs to perform a single read operation through the second path, and the second path is controlled to perform a read operation.

[0127] In some embodiments, the storage device includes a pre-charging circuit, the first path includes a read-write word line, a first bit line, and a second bit line, and the read-write word line is used to control the first bit line and the second bit line to discharge; the specific implementation method of "controlling the first path to perform a reading operation" in step 402 can be: controlling the pre-charging circuit to stop charging the first bit line and the second bit line; controlling the read-write word line to connect to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the fourth data to be read by the operation signal, and complete this reading operation.

[0128] In a feasible implementation, the specific implementation of controlling the pre-charging circuit to stop charging the first bit line and the second bit line may be: controlling the charging signal Pchg_RW of the pre-charging circuit to turn off charging through the control module.

[0129] It should be noted that the operation of "controlling the read / write word line to be connected to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the fourth data to be read by the operation signal" here is similar to the operation of "controlling the read / write word line to be connected to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the first data to be read by the operation signal" in the above-mentioned step 4011. For details, please refer to the description in step 4011, and the embodiments of the present application will not repeat them here.

[0130] Specifically, the specific implementation method of "controlling the read / write word line to connect to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the fourth data to be read by the operation signal" can be: controlling the read / write word line to connect to the first bit line and the second bit line in the first path; determining the corresponding storage unit from the multiple eight-tube storage units of the storage device based on the address data in the operation signal through the positioning device; controlling at least one of the first bit line and the second bit line to discharge, and reading the fourth data in the corresponding storage unit.

[0131] It should be noted that the implementation method of "controlling the second path to perform a read operation" in step 402 is similar to the implementation method of "controlling the second path connected between the storage module and the control module to perform a read operation" in step 401. For details, please refer to the description in step 401, and the embodiment of the present application will not repeat it again.

[0132] Specifically, the specific implementation method of "controlling the second path to perform a reading operation" in step 402 can be: controlling the pre-charging circuit to stop charging the third bit line; controlling the read word line to connect to the second path, and controlling the third bit line to discharge, so as to read the data to be read by the operation signal, and complete the current reading operation.

[0133] Step 403: When the operation signal indicates that two read operations are required, control the first path and the second path to perform read operations respectively.

[0134] In a feasible implementation, when the operation signal causes both the first pin ME_R1 and the second pin ME_R2 to change from low level to high level, it is determined that the operation signal indicates that two read operations are required, and the first path and the second path are controlled to perform read operations simultaneously.

[0135] It should be noted that the implementation method of "controlling the first path to perform a read operation" here is similar to the implementation method of "controlling the first path to perform a read operation" in the above step 402. For details, please refer to the description in step 402, and the embodiment of the present application will not repeat it again.

[0136] Specifically, the specific implementation method of "controlling the first path to perform a read operation" here can be: controlling the read-write word line to connect the first bit line and the second bit line in the first path; through the positioning device, determining the corresponding storage unit from the multiple eight-tube storage units of the storage device based on the address data in the operation signal; controlling at least one of the first bit line and the second bit line to discharge, and reading the data in the corresponding storage unit.

[0137] It should be noted that the implementation method of "controlling the second path to perform a reading operation" here is similar to the implementation method of "controlling the second path connected between the storage module and the control module to perform a reading operation" in the above step 401. For details, please refer to the description in step 401, and the embodiment of the present application will not repeat it again.

[0138] Specifically, the specific implementation method of "controlling the second path to perform a reading operation" here can be: controlling the pre-charging circuit to stop charging the third bit line; controlling the read word line to connect to the second path, and controlling the third bit line to discharge, so as to read the data to be read by the operation signal, and complete this reading operation.

[0139] It is worth mentioning that controlling the first path to perform a reading operation and controlling the second path to perform a reading operation may be performed simultaneously or sequentially, and this is not limited in the embodiment of the present application.

[0140] Based on the above embodiment, when the operation signal indicates that a write operation is required, the data processing method provided by the present application further includes the following steps 404 to 405:

[0141] Step 404: Control the precharge circuit to stop charging the first bit line and the second bit line.

[0142] In a feasible implementation, when the operation signal causes the third pin ME_W to change from a low level to a high level, it is determined that the operation signal indicates that a write operation is required, and the write operation is performed through the first path, which is specifically implemented through steps 404 to 405.

[0143] In a feasible implementation, the specific implementation of controlling the pre-charging circuit to stop charging the first bit line and the second bit line may be: controlling the charging signal Pchg_RW of the pre-charging circuit to turn off charging through the control module.

[0144] Step 405 , controlling the read / write word line to connect to the first path, and writing the fifth data to be written by the operation signal into the storage module through the first bit line and the second bit line, thereby completing this write operation.

[0145] It should be noted that the implementation method of step 405 is similar to the implementation method of "writing the second data to be written by the operation signal into the storage module through the first path" in the above-mentioned step 4012. For details, please refer to the description in step 4012, and the embodiment of the present application will not be repeated here.

[0146] Specifically, the specific implementation method of "writing the fifth data to be written by the operation signal into the storage module through the first bit line and the second bit line" can be: through the positioning device, the corresponding storage unit is determined from the multiple eight-tube storage units of the storage device based on the address data in the operation signal; the data is written into the corresponding storage unit through the first bit line and the second bit line in the first path.

[0147] Based on the above embodiment, when the operation signal indicates that a write operation and a read operation need to be performed, the data processing method provided by the present application further includes the following step 406:

[0148] Step 406: Control the first path to perform a read operation and a write operation; or, control the first path to perform a write operation and control the second path to perform a read operation.

[0149] In a feasible implementation, when the operation signal causes both the first pin ME_R1 and the third pin ME_W to change from a low level to a high level, it is determined that the operation signal indicates that a write operation and a read operation need to be performed through the first path, and the first path is controlled to perform a read operation and a write operation. When the operation signal causes both the second pin ME_R2 and the third pin ME_W to change from a low level to a high level, it is determined that the operation signal indicates that a write operation needs to be performed through the first path and a read operation needs to be performed through the second path, and the first path is controlled to perform a write operation, and the second path is controlled to perform a read operation.

[0150] It should be noted that the implementation method of "controlling the first path to perform read operations and write operations" in step 406 is similar to the implementation method of "controlling the first path connected between the storage module and the control module to perform read operations and write operations" in the above step 401. For details, please refer to the description in the above step 401, and the embodiment of the present application will not repeat it again.

[0151] It should be noted that the implementation method of "controlling the first path to perform a write operation" in step 406 is similar to the implementation method described in the above steps 404 to 405. For details, please refer to the description in the above steps 404 to 405, and the embodiment of the present application will not repeat it again.

[0152] It should be noted that the implementation method of "controlling the second path to perform a read operation" in step 406 is similar to the implementation method of "controlling the second path to perform a read operation" in the above step 403. For details, please refer to the description in the above step 403, and the embodiment of the present application will not repeat it again.

[0153] The present application provides a data processing method for Figure 3 The control module in the storage device shown in FIG. Figure 5 As shown, the method includes the following steps 501 to 503:

[0154] Step 501: respond to an externally triggered operation signal and determine a current working mode based on the type of the operation signal.

[0155] The types of operation signals may be read type, write type and read-write type. Further, the read type may include a first read type for performing a read operation once through the first path, a second read type for performing a read operation once through the second path, and a third read type for performing two read operations through the first path and the second path. The read-write type may include a first read-write type for performing a write operation once through the first path and a read operation once through the second path, a second read-write type for performing a write operation once and a read operation once through the first path, a second read-write type for performing a write operation once and a read operation once through the first path, and a third read-write type for performing a read operation once through the second path.

[0156] In a feasible implementation, if the operation signal characterizes that a read operation needs to be performed through the first path, then the type of the operation signal is determined to be the first read type (one read); if the operation signal characterizes that a read operation needs to be performed through the second path, then the type of the operation signal is determined to be the second read type (one read); if the operation signal characterizes that two read operations need to be performed through the first path and the second path, then the type of the operation signal is determined to be the third read type (two reads).

[0157] Similarly, if the operation signal indicates that a write operation needs to be performed through the first path and a read operation needs to be performed through the second path, then the type of the operation signal is determined to be the first read-write type (one read and one write); if the operation signal indicates that a write operation and a read operation need to be performed through the first path, then the type of the operation signal is determined to be the second read-write type (one read and one write); if the operation signal indicates that a write operation and a read operation need to be performed through the first path, then the type of the operation signal is determined to be the third read-write type (two reads and one write).

[0158] In a feasible implementation, if the type of the operation signal is the first read type, then the current working mode is determined to be the first mode; if the type of the operation signal is the second read type, then the current working mode is determined to be the second mode; if the type of the operation signal is the third read type, then the current working mode is determined to be the third mode; if the type of the operation signal is the write type, then the current working mode is determined to be the fourth mode; if the type of the operation signal is the first read-write type, then the current working mode is determined to be the fifth mode; if the type of the operation signal is the second read-write type, then the current working mode is determined to be the sixth mode; if the type of the operation signal is the third read-write type, then the current working mode is determined to be the seventh mode.

[0159] Step 502: Based on the current working mode, select a target path from the first path and the second path.

[0160] When the current working mode is the first mode, the first path is selected as the target path; when the current working mode is the second mode, the second path is selected as the target path; when the current working mode is the third mode, the first path and the second path are selected as the target path; when the current working mode is the fourth mode, the first path is selected as the target path; when the current working mode is the fifth mode, the first path and the second path are selected as the target path; when the current working mode is the sixth mode, the first path is selected as the target path; when the current working mode is the seventh mode, the first path and the second path are selected as the target path.

[0161] Step 503: Process the operation signal based on the target path.

[0162] When the current working mode is the first mode, a read operation is performed based on the first path to process the operation signal; when the current working mode is the second mode, a read operation is performed based on the second path to process the operation signal; when the current working mode is the third mode, two read operations are performed based on the first path and the second path to process the operation signal; when the current working mode is the fourth mode, a write operation is performed based on the first path to process the operation signal; when the current working mode is the fifth mode, a write operation is performed based on the first path and a read operation is performed based on the second path to process the operation signal; when the current working mode is the sixth mode, a write operation and a read operation are performed based on the first path to process the operation signal; when the current working mode is the seventh mode, a write operation and a read operation are performed based on the first path and a read operation is performed based on the second path to process the operation signal.

[0163] The following describes the application of the data processing method provided in the embodiment of the present application in an actual scenario, taking a storage device as 2R1WSRAM as an example.

[0164] like Figure 2 As shown, the structure of the 2R1W SRAM provided by the present application may include: a first transistor MNP0 and a second transistor MNP1 for constituting a first path 13, a third transistor MNDR and a fourth transistor MNPR for constituting a second path 14, and four fifth transistors for constituting a latch. The four fifth transistors constituting the latch are respectively a first pull-up transistor MPU0, a second pull-up transistor MPU1, a first pull-down transistor MND0, and a second pull-down transistor MND1.

[0165] In the related art, the two NMOS transistors used as transmission tubes can only be used as a write path, but in the present application, they can be used as a shared path of the write path and one of the read paths, and the read-write word line RWWL is used to control the opening and closing of the path. When used as a write path, the read-write word line RWWL is turned on, and data is written to the storage module through the complementary first bit line RWBLB and the second bit line RWBL. When used as a read path, the read-write word line RWWL is turned on, and the storage module discharges one of the complementary first bit line RWBLB and the second bit line RWBL through the two transmission tubes, thereby completing the information reading operation; the two NMOS transistors MNPR and MNDR serve as another read path, and the discharge of the third bit line RBLB is controlled by the read word line RWL to perform the reading operation.

[0166] like Figure 3As shown, the overall architecture of the 2R1W SRAM may include an eight-tube memory cell array (memory module 12), a controller (control module 11), a precharge circuit 16, a row decoder (a first addressing device 151), a column selector (a second addressing device 152), a write circuit 18, a first read circuit 17 and a second read circuit 19.

[0167] Among them, the eight-tube storage unit array is a matrix (array) composed of multiple eight-tube storage units, each storage unit can store one bit (the smallest unit of data), thereby forming a memory array that can store a large amount of data and is used for read and write operations.

[0168] The controller (control module 11) includes a pre-decoding circuit and a control circuit. The pre-decoding circuit is mainly used to pre-decode the address data and then send the pre-decoded address data to the row decoder. The control circuit is used to manage, coordinate and control the functional implementation and timing of the circuits of various parts of the system, and is responsible for managing the interaction between the memory array and various other components (such as bit selection circuits, sense amplifiers and write circuits) to ensure that the data arrives at the location at a specific working timing and is correctly read and written.

[0169] The precharge circuit 16 is used to charge each bit line of the memory array to the power supply voltage after the read / write phase is completed. This process prepares for the subsequent read / write operation because the bit line needs to be charged to the appropriate voltage level first when the charge is transferred into or out of the memory array to write or read data.

[0170] The row decoder circuit (first addressing device 151) is used to post-decode the read and write addresses, thereby selecting a specific row for subsequent read and write operations.

[0171] The column selection circuit (second addressing device 152), also known as a column selector, is responsible for selecting a specific bit (i.e., a specific storage array in the vertical direction) for read / write operations in the memory system. This circuit usually works based on a signal received from a controller to determine which specific bit to read / write.

[0172] The write circuit 18 writes data (usually 1 or 0) into a specific storage array according to the instruction of the controller. The write circuit usually includes a data input channel and a control gate for writing data into the storage array.

[0173] The first read circuit 17 includes a sense amplifier and a read circuit. The sense amplifier plays a key role in the static random access memory (SRAM) and is used to amplify the weak signal read from the memory array so that the weak signal can be read by the external circuit. Since the read current of the memory array is very small, a sense amplifier is needed to amplify this weak signal to ensure the correct reading of the data. The read circuit is responsible for latching the signal amplified by the sense amplifier and driving it to the output port QB1 (first port).

[0174] The second read circuit 19 is used to latch the single-ended read signal of RBLB and drive it to the output port QB2 (second port).

[0175] 2R1W SRAM can include the following working modes:

[0176] The first is the write-only mode. In this mode, ME_R1=0, ME_R2=0, ME_W=1, and WEA=1 in the memory enable signal. The controller controls the charging signal Pchg_RW of the precharge circuit to turn off the charging, and controls the write circuit to write the signal DA to RWBL_W and RWBLB_W, and writes to RWBL and RWLBLB through the column selector. At the same time, the address data of ADR_W is used to open a specific RWWL, select a specific row in the eight-tube memory module array, and write to the memory module of the row through the RWBL and RWLBLB that have been written with data.

[0177] The second is a working mode of reading only one port, which is further divided into read-only READ PORT1 (first port) and read-only READ PORT2 (third port).

[0178] In the read-only READ PORT1 working mode, ME_R1=1, ME_R2=0, ME_W=0, and WEA=0 in the memory enable signal. The controller controls the charging signal Pchg_RW of the pre-charge circuit to turn off the charging, and opens a specific RWWL through the address data of ADR_R1 to select a specific row in the eight-tube storage module array. The data in the storage module is read to the column selector through RWBL and RWLBLB, and the signals of RWBL and RWLBLB are transmitted to RWBL_R1 and RWLBLB_R1 through the column selector. Finally, the first read circuit 1 is controlled to amplify the signals RWBL_R1 and RWLBLB_R1 through the sense amplifier and finally driven to the output port QB1.

[0179] In the read-only READ PORT2 working mode, ME_R1=0, ME_R2=1, ME_W=0, and WEA=0 in the memory enable signal. The controller controls the charging signal Pchg_R of the pre-charge circuit to turn off the charging, and opens a specific RWL through the address data of ADR_R2 to select a specific row in the eight-tube storage module array. The data in the storage module is read to the column selector through RBLB, and the signal of RBLB is passed to RWLBLB_R2 through the column selector. Finally, the second read circuit 2 is controlled to drive the signal RBLB_R2 to the output port QB2.

[0180] The third is a working mode for reading from two read ports simultaneously. In this working mode, ME_R1=1, ME_R2=1, ME_W=0, and WEA=0 in the memory enable signal.

[0181] For READ PORT1, the controller controls the charging signal Pchg_RW of the pre-charging circuit to turn off charging, and opens a specific RWWL through the address data of ADR_R1, selects a specific row in the eight-tube storage module array, reads the data in the storage module to the column selector through RWBL and RWLBLB, and transmits the signals of RWBL and RWLBLB to RWBL_R1 and RWLBLB_R1 through the column selector, and finally controls the first reading circuit 1 so that the signals RWBL_R1 and RWLBLB_R1 are amplified through the sensitive amplifier and finally driven to the output port QB1.

[0182] For READ PORT2, the controller controls the charging signal Pchg_R of the pre-charging circuit to be turned off, and opens a specific RWL through the address data of ADR_R2, selects a specific row in the eight-tube storage module array, reads the data in the storage module to the column selector through RBLB, and transmits the signal of RBLB to RWLBLB_R2 through the column selector, and finally controls the second reading circuit 2 to drive the signal RBLB_R2 to the output port QB2.

[0183] The fourth mode is a mode in which a read port and a write port (second port) work simultaneously. This working mode is further divided into a mode in which the write port and the READ PORT1 read port work simultaneously, and a mode in which the write port and the READ PORT2 read port work simultaneously.

[0184] In the mode where the write port and READ PORT1 read port work simultaneously, ME_R1=1, ME_R2=0, ME_W=1, and WEA=1 in the memory enable signal, the controller controls the charging signal Pchg_RW of the pre-charge circuit to turn off the charging, and opens a specific RWWL through the address data of ADR_R1, selects a specific row in the eight-tube storage module array, reads the data in the storage module to the column selector through RWBL and RWLBLB, and transmits the signals of RWBL and RWLBLB to RWBL_R1 and RWLBLB_R1 through the column selector, and finally controls the read circuit 1 so that the signals RWBL_R1 and RWLBLB_R1 are amplified through the sensitive amplifier and finally driven to the output port QB1. At the same time, the write circuit is controlled to write the signal DA into RWBL_W and RWBLB_W, and after the sense amplifier is amplified, RWWL is closed and RWBL and RWBLB are charged to a high level, and then the column selector is opened to write the data of RWBL_W and RWBLB_W into RWBL and RWLBLB. At the same time, a specific RWWL is opened through the address data of ADR_W, a specific row in the eight-tube storage module array is selected, and the data is written into the storage module of the row through RWBL and RWLBLB.

[0185] In the working mode where both the write port and the READ PORT2 port are working, ME_R1=0, ME_R2=1, ME_W=1, and WEA=1 in the memory enable signal, the read operation and the write operation are different from the previous order, but are operated separately. The read operation controls the charging signal Pchg_R of the pre-charge circuit to be turned off through the controller, and opens a specific RWL through the address data of ADR_R2, selects a specific row in the eight-tube storage module array, reads the data in the storage module to the column selector through RBLB, and transmits the signal of RBLB to RWLBLB_R2 through the column selector, and finally controls the read circuit 1 to drive the signal RBLB_R2 to the output port QB2; in this mode, the write operation is the same as the first working mode.

[0186] The fifth mode is the mode where two read ports and one write port work at the same time, that is, the two read and one write mode. In this mode, ME_R1=1, ME_R2=1, ME_W=1, and WEA=1 in the memory enable signal, and the working mode of the write port and the READ PORT1 read port is the same as the mode where the write port and the READ PORT1 read port work at the same time in the fourth mode, and the working order is read first and then write; the working mode of the READ PORT2 read port is the same as the second read-only READ PORT2 read port working mode.

[0187] like Figure 6 As shown, the writing port and the READ PORT1 reading port work at the same time. The working sequence is: read 1 and write 0 in the first cycle, and read 0 and write 1 in the second cycle. When CLK_W / CLK_R1 rises, the address data of ADR_R1 opens a specific RWWL through the decoder, selects a specific row in the eight-tube storage module array, transfers the information in the storage module to RWBL and RWBLB, and transmits it to RWBL_R1 and RWBLB_R1 through the opened column selection circuit. It can be seen that at this time, since the first cycle reads 1, RWBL remains unchanged, and RWBLB drops to a certain voltage. When RWL / RWLB and RWBL_R1 / RWBLB_R1 reach a certain voltage difference, the controller controls the column selection circuit to close. At this time, RWL / RWLB is charged back to VDD by the charging circuit, and RWBL_R1 / RWBLB_R1 is amplified to high and low levels by the sensitive amplifier in the reading circuit 1, and is finally driven to the output end to see QB1, and read 1 successfully. In addition, the controller controls the column selector to close the read port and open the write port at the same time. Before that, RWBL_W / RWBLB_W has been driven by the write circuit to change to high and low levels according to the input DA signal. After the column selector opens the write path, RWL / RWLB, which has been charged to a high level, changes to the same high and low levels as RWBL_W / RWBLB_W through the column selector. At this time, the previously closed RWWL is again selected and pulled high according to the decoding according to the address of ADR_W in the write phase, and is written into the storage module of the row through RWL / RWLB, and the write is completed at this time.

[0188] like Figure 7 As shown, the working sequence of READ PORT2 is: read 0 in the first cycle and read 1 in the second cycle. When CLK_R2 rises, the address data of ADR_R2 opens a specific RWL through the decoder, selects a specific row in the eight-tube storage module array, transfers the information in the storage module to RBLB, and transmits it to RBLB_R2 through the opened column selection circuit, and finally drives it to the output port QB2 through the second read circuit 2, and the reading is successful.

[0189] It should be noted that the purpose of the present application is to design a circuit structure of a 2R1W SRAM based on an eight-tube storage unit, which is different from the current two-read and one-write based on three channels of the ten-tube storage unit. Instead, it is optimized on two channels (one write channel and one read channel) of the traditional eight-tube storage unit. In order to achieve the effect of two reads and one write under the ten-tube storage unit, the effect of reading and writing through one channel is achieved by multiplexing the write channel in one cycle and performing write first and then read or read first and then write. In addition, the original other read port is added, so that the effect of two read ports and one write port is finally achieved externally. The read and write functions of two reads and one write are finally realized by sharing the read and write channels in one cycle. While ensuring high performance and functions, the storage unit area is reduced and the overall area of ​​the SRAM is reduced, thereby reducing the chip cost, thereby solving the problems of excessive area caused by the ten-tube storage unit and poor read and write functions caused by the eight-tube storage unit.

[0190] It should be noted that in the embodiment of the present application, if the above-mentioned data processing method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a disk or an optical disk. In this way, the embodiment of the present application is not limited to any specific hardware, software or firmware, or any combination of hardware, software, and firmware.

[0191] The embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, some or all of the steps in the above method are implemented. The computer-readable storage medium can be transient or non-transient.

[0192] An embodiment of the present application provides a computer program, including a computer-readable code. When the computer-readable code is run in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.

[0193] The embodiment of the present application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, some or all of the steps in the above method are implemented. The computer program product can be implemented specifically by hardware, software or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium, and in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0194] It should be noted here that the description of the various embodiments above tends to emphasize the differences between the various embodiments, and the same or similar aspects can be referenced to each other. The description of the above device, storage medium, computer program and computer program product embodiments is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the embodiments of the device, storage medium, computer program and computer program product of this application, please refer to the description of the method embodiment of this application for understanding.

[0195] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The serial numbers of the embodiments of the present application mentioned above are for description only and do not represent the advantages and disadvantages of the embodiments.

[0196] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0197] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0198] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0199] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0200] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0201] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0202] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A data processing method, characterized in that: A control module applied to a storage device, wherein the storage device further comprises a storage module, wherein the storage module is an eight-tube memory, and the data processing method comprises: In response to an operation signal triggered externally, when the operation signal indicates that two read operations and one write operation are required, controlling a first path connected between the storage module and the control module to perform a read operation and a write operation, and controlling a second path connected between the storage module and the control module to perform a read operation; Wherein, the storage device includes a precharge circuit, the first path includes a read / write word line, a first bit line and a second bit line, the read / write word line is used to control the first bit line and the second bit line to discharge, and the first bit line and the second bit line are a pair of complementary bit lines; The control of performing a read operation and a write operation on a first path connected between the storage module and the control module includes: Control the read / write word line to connect to the first path, and control at least one of the first bit line and the second bit line to discharge, so as to read the first data to be read by the operation signal, and complete the current reading operation; Control the precharge circuit to charge the first bit line and the second bit line to a target voltage, write the second data to be written by the operation signal into the storage module through the first path, and complete the current write operation; The second path includes a read word line and a third bit line, and the read word line is used to control the third bit line to discharge; The controlling a second path connected between the storage module and the control module to perform a read operation includes: Controlling the pre-charging circuit to stop charging the third bit line; The read word line is controlled to be connected to the second path, and the third bit line is controlled to be discharged, so as to read the third data to be read by the operation signal, and complete the current read operation.

2. The data processing method according to claim 1, characterized in that: The storage device includes a positioning device; The step of controlling the read / write word line to connect to the first path and controlling at least one of the first bit line and the second bit line to discharge, so as to read the first data to be read by the operation signal, comprises: Controlling the read / write word line to connect the first bit line and the second bit line in the first path; Determine, by the positioning device, a first storage unit from a plurality of eight-tube storage units of the storage device based on the first address data in the operation signal; At least one of the first bit line and the second bit line is controlled to discharge, and first data in the first storage unit is read.

3. The data processing method according to claim 1, characterized in that: The storage device includes a positioning device; Writing the second data to be written by the operation signal into the storage module through the first path includes: Determine, by the positioning device, a second storage unit from a plurality of eight-tube storage units of the storage device based on the second address data in the operation signal; The second data is written into the second storage unit through the first path.

4. The data processing method according to any one of claims 1 to 3, characterized in that: In the case where the operation signal indicates that a read operation needs to be performed, the data processing method further includes: When the operation signal indicates that a single read operation is required, controlling the first path to perform a read operation, or controlling the second path to perform a read operation; When the operation signal indicates that two read operations need to be performed, the first path and the second path are controlled to perform read operations respectively.

5. The data processing method according to claim 4, characterized in that: The storage device comprises a precharge circuit, the first path comprises a read / write word line, a first bit line and a second bit line, the read / write word line is used to control the first bit line and the second bit line to discharge; The controlling the first path to perform a read operation includes: Controlling the precharge circuit to stop charging the first bit line and the second bit line; The read / write word line is controlled to connect to the first path, and at least one of the first bit line and the second bit line is controlled to discharge, so as to read the fourth data to be read by the operation signal, and complete the current reading operation.

6. The data processing method according to any one of claims 1 to 3, characterized in that: The storage device comprises a precharge circuit, the first path comprises a read / write word line, a first bit line and a second bit line, the read / write word line is used to control the first bit line and the second bit line to discharge; In the case where the operation signal indicates that a write operation is required, the data processing method further includes: Controlling the precharge circuit to stop charging the first bit line and the second bit line; The read / write word line is controlled to be connected to the first path, and the fifth data to be written by the operation signal is written into the storage module through the first bit line and the second bit line, so as to complete the current write operation.

7. The data processing method according to any one of claims 1 to 3, characterized in that: In the case where the operation signal indicates that a read operation and a write operation need to be performed, the data processing method further includes: Controlling the first path to perform a read operation and a write operation; or, The first path is controlled to perform a write operation, and the second path is controlled to perform a read operation.

8. A storage device, characterized in that: The storage device comprises: a storage module and a control module, wherein the storage module is an eight-tube memory; A first passage and a second passage are connected between the control module and the storage module; The control module is used to perform a read operation and a write operation through the first path, and perform a read operation through the second path, so as to realize two reads and one write for the data of the storage module; Wherein, the storage device includes a precharge circuit, the first path includes a read-write word line and a first bit line and a second bit line, the first bit line and the second bit line are a pair of complementary bit lines; the second path includes a read word line and a third bit line, the read word line is used to control the third bit line to discharge; The control module is used to control the read / write word line to connect to the first path, and control at least one of the first bit line and the second bit line to discharge, so as to read the first data to be read by the operation signal, and complete the current read operation; control the precharge circuit to charge the first bit line and the second bit line to a target voltage, and write the second data to be written by the operation signal into the storage module through the first path, so as to complete the current write operation; The control module is used to control the pre-charging circuit to stop charging the third bit line; control the read word line to connect to the second path, and control the third bit line to discharge, so as to read the third data to be read by the operation signal and complete the current reading operation.

9. The storage device according to claim 8, characterized in that: The first path includes a first transistor, a second transistor, a first port and a second port, and the second path includes a third transistor, a fourth transistor and a third port; The first end of the first transistor, the first end of the second transistor and the first end of the third transistor are respectively connected to the latch, the second end of the first transistor is connected to the first port, the second end of the second transistor is connected to the second port, the second end of the third transistor is connected to the first end of the fourth transistor, and the second end of the fourth transistor is connected to the third port.

10. The storage device according to claim 9, characterized in that: The first end of the read / write word line is connected to the control module, and the second end of the read / write word line is connected to the control end of the first transistor and the control end of the second transistor respectively; The first port is connected to a first end of the first bit line and a first end of the second bit line, the second port is connected to a first end of the first bit line and a first end of the second bit line, the second end of the first bit line is connected to a second end of the first transistor, and the second end of the second bit line is connected to a second end of the second transistor; The control module is used to control the read / write word line to connect the first transistor and the second transistor to connect the first path, and control at least one of the first bit line and the second bit line to discharge, so as to read out the data of at least one eight-transistor storage unit in the storage module through the first port to realize the read operation; and control the first bit line and the second bit line to write the data into at least one eight-transistor storage unit in the storage module through the second port to realize the write operation.

11. The storage device according to claim 9 or 10, characterized in that: The first end of the read word line is connected to the control module, and the second end of the read word line is connected to the control end of the fourth transistor; The third port is connected to a first end of the third bit line, and a second end of the third bit line is connected to a second end of the fourth transistor; The control module is used to control the read word line to connect the third transistor and the fourth transistor to connect the second path, and control the third bit line to discharge, and read out the data of at least one eight-transistor storage unit in the storage module through the third port to realize the read operation.

12. The storage device according to any one of claims 9 to 10, characterized in that: The storage device comprises an addressing module; The addressing module is connected between the control module and the storage module; The addressing module is used to determine the storage unit corresponding to any address data from the multiple eight-tube storage units of the storage module.

13. The storage device according to claim 12, characterized in that: The addressing module comprises a first addressing device and a second addressing device; A first end of the first addressing device is connected to the control module, and a second end of the first addressing device is connected to a read / write word line and a read word line in the first path; A first end of the second addressing device is connected to the control module, and a second end of the second addressing device is connected to a first bit line and a second bit line in the first path; The first addressing device is used to determine the row corresponding to any address data from the multiple eight-pipe storage units of the storage module; The second addressing device is used to determine the column corresponding to any address data from the multiple eight-transistor storage units of the storage module.

14. The storage device according to claim 8, characterized in that: The pre-charging circuit is connected between the control module and the storage module; The precharge circuit is used to charge the bit line in the storage device to a target voltage after the read and write operations are completed.

15. The storage device according to any one of claims 8 to 10 or 13, characterized in that: The control module includes a pre-decoding circuit and a control circuit; The pre-decoding circuit is used to pre-decode any address data and transmit the decoded address data to the first addressing device; The control circuit is used to control the interaction of various components in the storage device.

16. The storage device according to claim 10, characterized in that: The storage device includes a first read circuit; A first end of the first reading circuit is connected to the first port, and a second end of the first reading circuit is connected to a first end of the first bit line and a first end of the second bit line; The first reading circuit is used to amplify and latch a signal carrying data read from the storage module through the first path, and output a first processed signal from the first port.

17. The storage device according to claim 10, characterized in that: The storage device includes a write circuit; A first end of the write circuit is connected to the second port, and a second end of the write circuit is connected to a first end of the first bit line and a first end of the second bit line; The write circuit is used to write data into the first bit line and the second bit line based on the instruction of the control module, and then write data into the storage module.

18. The storage device according to claim 11, characterized in that: The storage device includes a second read circuit; A first end of the second reading circuit is connected to the control module, and a second end of the second reading circuit is connected to the third bit line; The second reading circuit is used to amplify and latch a signal carrying data read from the storage module through the second path, and output a second processed signal from the third port.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

20. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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