An active high-density electrode array and a method of fabricating the same

Abstract

The application discloses an active high-density electrode array and a preparation method thereof, and relates to the field of active high-density electrode arrays. The active high-density electrode array comprises a plurality of active electrode units; each active electrode unit comprises an active amplification circuit and an electrode; all the active electrode units are arranged in a matrix type and are arranged in a longitudinal and transverse manner to form the active high-density electrode array; the number of rows and the number of columns of the active high-density electrode array are the same; the amplification device, the load device and the bias device are all thin film transistors; the active amplification circuit is formed by connecting an AC-DC integration circuit and a negative feedback amplification circuit; the negative feedback amplification circuit is formed by connecting the amplification device, the load device, the bias device and a negative feedback capacitor; and the AC-DC integration circuit is formed by connecting an AC-DC integration resistor and an AC-DC integration capacitor in parallel. The application can reduce the difficulty of the wearability of the electrode and improve the quality of the electromyographic signal.

Description

Technical Field

[0001] This invention relates to the field of active high-density electrode arrays, and in particular to an active high-density electrode array and its fabrication method. Background Technology

[0002] In recent years, surface electromyography (sEMG) acquisition technology has received widespread attention and research. However, both the fabrication of sEMG electrodes and the analysis of EMG signals face significant challenges. Many factors influence sEMG signal acquisition, such as the intensity and duration of muscle contraction, the condition of surrounding tissues (skin thickness, conductivity, etc.), and the quality of electrode-skin contact. Furthermore, noise interference from other tissues and the environment, along with the high impedance of the electrodes themselves, affects the acquisition quality of surface EMG signals, further complicating the process. Therefore, fabricating an active amplification electrode array for acquiring surface EMG signals is of great significance.

[0003] In terms of electrode fabrication, compared to needle electrodes, traditional single passive sEMG electrodes reduce the physical and psychological stress on the test subject. However, due to the single sampling point, there are limitations in the discrimination of action potentials. With the continuous advancement of electromyography (EMG) signal acquisition technology, subsequent array-based studies have found that due to the weakness of EMG signals, the increased number of channels in passive arrays leads to increased crosstalk between signals, exacerbating interference from external electromagnetic waves and significantly reducing the signal-to-noise ratio (SNR), severely degrading the transmission quality of EMG signals. Based on research into traditional silicon-based processes, it has been found that integrating active circuits with passive electrodes—that is, integrating board-level hardware system functional modules with passive electrodes—can improve the quality of surface EMG signals to some extent. However, this process introduces motion artifacts and increases the difficulty of wearing the electrodes during signal acquisition, easily introducing new noise and further reducing the SNR. Summary of the Invention

[0004] The purpose of this invention is to provide an active high-density electrode array and its fabrication method, which can reduce the difficulty of electrode wearability and improve the quality of electromyographic signals.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] An active high-density electrode array includes: a plurality of active electrode units; each active electrode unit includes an active amplifier circuit and an electrode; all active electrode units are arranged in a matrix configuration to form the active high-density electrode array; the active high-density electrode array has the same number of rows and columns.

[0007] The active amplifier circuit includes amplification devices, load devices, bias devices, negative feedback capacitors, AC / DC integrated capacitors, and AC / DC integrated resistors.

[0008] The amplifying device, the load device, and the biasing device are all thin-film transistors;

[0009] The active amplifier circuit is composed of an AC / DC integrated circuit and a negative feedback amplifier circuit connected together; the negative feedback amplifier circuit is composed of the amplifying device, the load device, the bias device and the negative feedback capacitor connected together; the AC / DC integrated circuit is composed of the AC / DC integrated resistor and the AC / DC integrated capacitor connected in parallel.

[0010] A method for fabricating an active high-density electrode array, applied to the aforementioned active high-density electrode array, the fabrication method comprising:

[0011] The raw materials for preparing the gate, feedback capacitor, and AC / DC integrated capacitor of the amplifying device, load device, and bias device are magnetron sputtered to form the initial gate layer.

[0012] Photoresist is coated on the initial gate layer. After the coated photoresist is dried, the initial gate layer is exposed in conjunction with the first mask to form the exposed initial gate layer.

[0013] After development, the exposed initial gate layer is wet-etched to form the gates of the amplifying device, load device, and bias device, as well as the lower electrode of the feedback capacitor and the AC / DC integrated capacitor. The lower electrode of the negative feedback capacitor is made of the same material as the initial gate layer and is connected to the gate of the load device. The lower electrode of the AC / DC integrated capacitor is made of the same material as the initial gate layer and is connected to the gate of the amplifying device.

[0014] The raw materials for depositing insulating layers on the lower plates of the gates, feedback capacitors, and AC / DC integrated capacitors of the amplifying devices, load devices, and bias devices are used to form insulating layers.

[0015] The raw materials for preparing the active layers of amplifying devices, load devices, and bias devices are magnetron sputtered onto the insulating layer to form an initial active layer;

[0016] Photoresist is coated onto the initial active layer. After the coated photoresist is dried, the initial active layer is exposed in conjunction with a second mask to form the exposed initial active layer.

[0017] After the initial active layer after exposure is developed, it is etched to form the precursor of the active layer of the amplifier device, load device and bias device.

[0018] The precursor is annealed to form the active layer of the amplifying device, the load device, and the bias device;

[0019] The raw materials for preparing the etching layer are chemically deposited on the active layer to form the initial etching layer;

[0020] Photoresist is coated onto the initial etched layer. After the coated photoresist is dried, the initial etched layer is exposed in conjunction with a third mask to form the exposed initial etched layer.

[0021] After developing the initial etched layer after exposure, dry etching is performed to create etched layers between the active layers of the amplifier device, load device, and bias device and the corresponding SD drain and source, between the gate and drain of the bias device, between the source of the bias device and one end of the gate of the load device, between the source of the load device and the drain of the amplifier device, between the gate of the amplifier and one end of the AC / DC integrated capacitor, and between the gate of the amplifier and the resistor.

[0022] The raw materials for fabricating the source and drain of the amplifier device, load device, and bias device, as well as the upper plates of the coupling capacitor and coupling resistor, are magnetron sputtered onto the etching layer to achieve interconnection between the active layer of the amplifier device, load device, and bias device and the corresponding SD drain and source, between the gate and drain of the bias device, between the source of the bias device and one end of the gate of the load device, between the source of the load device and the drain of the amplifier device, between the gate of the amplifier and one end of the AC / DC integrated capacitor, and between the gate of the amplifier and the resistor, thus forming an SD electrode film.

[0023] Photoresist is coated onto the SD electrode film. After the coated photoresist is dried, the SD electrode film is exposed using a fourth mask to form the exposed SD electrode film.

[0024] The exposed SD electrode film is developed and then etched to form the source and drain of the amplifier device, load device and bias device, as well as the upper plate of the AC / DC integrated capacitor and resistor.

[0025] The raw materials for preparing the barrier layer are chemically deposited on the source and drain electrodes of the amplifier device, load device, and bias device, as well as on the upper plates of the coupling capacitor and coupling resistor, to form the initial barrier layer.

[0026] Photoresist is coated onto the initial barrier layer. After the coated photoresist is dried, the initial barrier layer is exposed using a fifth mask to form the exposed initial barrier layer.

[0027] The initial barrier layer after exposure is developed and then dry-etched to form a barrier layer.

[0028] Copper is vapor-deposited onto the barrier layer to form the initial copper plating layer;

[0029] Photoresist is coated onto the initial copper plating layer. After the coated photoresist is dried, the initial copper plating layer is exposed in conjunction with the sixth mask to form the exposed initial copper plating layer.

[0030] The initial copper plating layer after exposure is developed and then etched to form a copper plating layer and the upper electrode of the negative feedback capacitor; a portion of the copper plating layer connects the drain of the bias device and the drain of the load device.

[0031] A portion of the copper plating layer is connected to the junction between the source of the load device and the drain of the amplifying device as an output terminal.

[0032] A portion of the copper plating layer is connected to the source of the amplifying device and then grounded;

[0033] A portion of the copper plating layer is connected to the other end of the resistor;

[0034] The upper electrode of the negative feedback capacitor is fabricated on the copper plating layer, and the upper electrode of the negative feedback capacitor is used as the other port of the negative feedback capacitor and connected to the output V. OUT Terminal connection;

[0035] The raw materials for preparing the encapsulation layer are chemically vapor deposited onto the copper plating layer and the upper electrode of the negative feedback capacitor to form the initial encapsulation layer;

[0036] Photoresist is coated onto the initial encapsulation layer. After the coated photoresist is dried, the initial encapsulation layer is exposed in conjunction with the seventh mask to form the exposed initial encapsulation layer.

[0037] After the initial encapsulation layer is exposed, it is developed and then dry-etched to form an encapsulation layer, thus obtaining the active amplifier circuit.

[0038] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0039] This invention integrates the acquisition electrode and signal amplification circuit into a single unit with high integration. It designs a high-gain active amplification circuit and fabricates a multi-channel active electrode array by drawing a mask. Each electrode is matched with a corresponding amplification circuit, which performs preliminary amplification of the electromyographic signal before transmission and acquisition, thereby improving the acquisition quality of the electromyographic signal. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 The layout of the 10×10 active electrode array of Example 1 is drawn and will be used as a mask for this experiment;

[0042] Figure 2 This is a cross-sectional schematic diagram of the active amplifier circuit of the present invention;

[0043] Figure 3 This is a schematic diagram of the active amplifier circuit of the present invention;

[0044] Figure 4 This is a cross-sectional view of the flexible substrate;

[0045] Figure 5 This is a structural diagram of the active amplifier circuit of the present invention;

[0046] Figure 6 This is a transfer characteristic curve of a single thin-film transistor in Example 1;

[0047] Figure 7 This is a schematic diagram of the common-source amplifier circuit for Comparative Example 1;

[0048] Figure 8 The diagram shows the inverter characteristics of the common-source amplifier circuit in Comparative Example 1 under DC test conditions.

[0049] Figure 9 The gain analysis diagram of the common-source amplifier circuit of Comparative Example 1 under DC test conditions is shown.

[0050] Figure 10 This is a test diagram of the inverter characteristics of the active amplifier circuit of a single amplification unit in Example 1 under DC test conditions;

[0051] Figure 11 This is a gain analysis diagram of the active amplifier circuit of a single amplification unit in Example 1 under DC test conditions. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] The purpose of this invention is to provide an active high-density electrode array and its fabrication method, which can reduce the difficulty of electrode wearability and improve the quality of electromyographic signals.

[0054] Furthermore, this invention relates to the fields of thin-film transistor fabrication and photolithography.

[0055] This invention integrates passive electrodes and amplification circuits onto a flexible substrate, reducing noise during electromyography (EMG) signal acquisition, improving the integration of the acquisition system, and reducing electromagnetic interference during signal transmission. Each passive electrode is equipped with an amplification circuit to improve signal acquisition quality. To enable simultaneous acquisition of EMG signals from different locations, multi-channel flexible electrodes are used.

[0056] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] Example 1

[0058] like Figure 1 , Figure 2 and Figure 3 As shown, an active high-density electrode array in this embodiment includes: multiple active electrode units; each active electrode unit includes an active amplifier circuit and an electrode; all active electrode units are arranged in a matrix configuration to form the active high-density electrode array; the number of rows and columns of the active high-density electrode array are the same. Each active electrode unit is an independent unit, and the VD, VG, and GND of each independent unit are externally connected to the corresponding interfaces of other units, respectively, through a unified external power supply, saving the number of port pins.

[0059] The active amplifier circuit includes an amplifying device, a load device, a bias device, a negative feedback capacitor, an AC / DC integrated capacitor, and an AC / DC integrated resistor. In this invention, the amplifying device, the load device, and the bias device are the amplifying transistor, the load transistor, and the bias transistor, respectively.

[0060] The amplifying device, the load device, and the bias device are all thin-film transistors (TFTs). TFTs possess excellent field-effect mobility, stability, low-temperature manufacturing, flexibility, and low noise. For TFTs, Mo and ITO are selected as the bottom gate materials, IGZO as the active layer material, silicon oxide and silicon nitride as the insulating layers, and Mo and ITO as the source and drain electrode layer materials. IGZO is... Figure 2 The AL part in it.

[0061] The active amplifier circuit is composed of an AC / DC integrated circuit and a negative feedback amplifier circuit connected together; the negative feedback amplifier circuit is composed of the amplifying device, the load device, the bias device and the negative feedback capacitor connected together; the AC / DC integrated circuit is composed of the AC / DC integrated resistor and the AC / DC integrated capacitor connected in parallel.

[0062] Specifically, the connection method of the active amplifier circuit includes:

[0063] The source of the bias device is connected to the gate of the load device and one end of the negative feedback capacitor, respectively; the other end of the negative feedback capacitor is connected to the source of the load device and the drain of the amplifying device, respectively; the connection point of the negative feedback capacitor, the source of the load device, and the drain of the amplifying device serves as the output terminal of the bootstrap inverter circuit; the gate of the amplifying device is connected to one end of the AC / DC integrated capacitor; the source of the amplifying device is grounded; the drain of the load device, as well as the gate and drain of the bias device, are both connected to an external power supply; one end of the AC / DC integrated capacitor is connected to one end of the AC / DC integrated resistor; the other end of the AC / DC integrated resistor is connected to the external power supply.

[0064] Furthermore, the other end of the AC / DC integrated capacitor is connected to the electrode.

[0065] Active amplifier circuit structure as follows Figure 3 As shown, its main structure consists of a bootstrap inverter circuit as the amplification section, connected to an RC coupling circuit to form an active structure. The bootstrap inverter is essentially a common-source circuit (load transistor and amplifier transistor connected in series) with an added bias transistor and a negative feedback capacitor. The purpose is to keep the load transistor in a high-saturation state, thereby improving the circuit's amplification gain. In the active amplifier circuit, the source of the bias transistor is connected to the gate of the load transistor and the negative feedback capacitor, respectively. The other end of the negative feedback capacitor is connected to the junction of the source of the load transistor and the drain of the amplifier transistor, serving as the output terminal of the bootstrap inverter circuit. The gate of the amplifier is connected to one end of the AC / DC integrated capacitor in the coupling circuit. The source of the amplifier transistor is grounded, and the drain of the load transistor and the gate and drain of the bias transistor are both connected to an external power supply. The coupling circuit connects the other end of the AC / DC integrated capacitor to a resistor, and one end of the resistor is connected to an external power supply.

[0066] In one specific implementation, the active electrode unit is an integral structure; the active electrode unit is formed by integrating the electrode and the active amplifier circuit on a flexible substrate using photolithography technology of metal oxide thin-film transistors. The test electrode (i.e., the electrode in this invention) is preferably located above the active amplifier circuit; the test electrode and the active amplifier circuit are preferably integrated on a single flexible substrate. Integrating the test electrode and the active amplifier circuit onto a flexible substrate improves the integration of the acquisition system, reduces electromagnetic interference received during signal transmission, and provides an amplifier circuit for each passive electrode to improve signal acquisition quality.

[0067] Preferably, the active high-density electrode array is a 10×10 electrode array. The number of active amplifier circuits used is 100. The matrix-style horizontal and vertical arrangement allows for simultaneous acquisition of electromyographic signals from different sites. The test electrodes are preferably semi-circular in shape, with a diameter of 2 mm, a spacing of 3 mm to 5 mm between adjacent test electrodes, and an impedance of 190 MΩ. Using circular electrodes perpendicular to the muscle fibers, increasing the electrode size within a certain range reduces the impedance between the skin and the electrode, thereby improving acquisition quality. The spacing between the test electrodes is controlled between 3 mm and 5 mm to ensure adequate MUAP spatial resolution between the two electrodes, improving the quality of the acquired electromyographic signals.

[0068] The active electrode module of this invention is constructed using a thin-film transistor based on IGZO metal oxide, and is formed by integrating the test electrode and the active amplifier circuit on a flexible substrate. The electrode has a semi-circular protruding structure on its surface.

[0069] In this invention, during the fabrication process of the active high-density electrode array, test electrodes are dry-etched onto the packaging layer of the active amplifier circuit.

[0070] In practical applications, the flexible substrate material is selected as a polyimide (PI) film. This is because PI film is an organic polymer film that is not only resistant to hydrolysis, high temperatures, and corrosion, but also possesses good biocompatibility and beneficial insulation properties. Therefore, polyimide is chosen as the base material for the substrate. Due to the high field-effect mobility, good stability, low-temperature manufacturing, flexibility, and low noise characteristics of thin-film transistors (TFTs), IGZO oxide thin-film transistors are selected as the basic device for the amplification circuit.

[0071] Specifically, the flexible polyimide film substrate includes a polyimide film layer and a buffer layer stacked sequentially from bottom to top; the buffer layer includes a silicon nitride film and a silicon dioxide film stacked sequentially from bottom to top.

[0072] Furthermore, the thickness of the silicon nitride film is 300 nm. The thickness of the silicon dioxide film is 200 nm.

[0073] In one specific implementation, the amplifying device, the load device, and the bias device are all composed of a bottom gate layer, an active layer, an ES etch layer, an SD drain-source electrode layer, an etch protection layer, a copper plating layer, and a protective layer stacked sequentially from bottom to top. In the first layer, the bottom gate structures of the amplifier transistor, bias transistor, and load transistor, as well as the AC / DC coupling capacitor, AC / DC coupling resistor, and the lower electrode of the negative feedback capacitor are fabricated. Before fabricating the active layer, an insulating layer is first fabricated using silicon oxide and silicon nitride, and then the active layer IGZO is grown. The purpose of the third etching layer is to ensure the interconnection between the active layer and the SD drain-source layer through dry etching. Then, the drain-source electrodes of the amplifier transistor, bias transistor, and load transistor, as well as the upper electrode of the coupling capacitor and coupling resistor are fabricated in the SD drain-source electrode layer. The insulating layer and the etching layer are used as the dielectric layer of the capacitor. The SD and gate layers are connected to form a resistor using dry etching. A water-oxygen isolation layer is then fabricated on the SD layer to protect the circuit structure. A copper layer is then fabricated to form the copper electrode and the upper electrode of the negative feedback capacitor. Each active circuit is connected to the peripheral interface with copper wires. Finally, a protective layer is laid on the copper layer to protect and encapsulate the copper wires. The electrodes and each test interface are exposed using dry etching to facilitate electromyography signal testing.

[0074] In this invention, the amplifier, load transistor, and bias transistor are preferably integrated into a thin-film transistor.

[0075] In this invention, the thin-film transistor preferably includes an insulating layer, an etched layer, a barrier layer, and an encapsulation layer stacked sequentially from bottom to top.

[0076] In this invention, the thin-film transistor preferably includes an insulating layer; the insulating layer preferably includes a silicon nitride film and a silicon oxide film stacked sequentially from bottom to top; the insulating layer can prevent the electrical performance of the active amplifier circuit from being affected.

[0077] Preferably, the insulating layer contains the lower electrode of the gate of the amplifier, load transistor, and bias transistor, the feedback capacitor, and the AC / DC integrated capacitor; the lower electrode of the gate of the amplifier, load transistor, and bias transistor, the feedback capacitor, and the AC / DC integrated capacitor preferably includes a Mo film and an ITO film stacked sequentially from bottom to top.

[0078] In this invention, the thin-film transistor preferably includes an etched layer attached to the surface of the insulating layer; the etched layer preferably includes a silicon oxide film; the etched layer preferably contains an active layer for the amplifier, load transistor, and bias transistor; the active layer preferably includes an IGZO film.

[0079] The thin-film transistor preferably includes a barrier layer attached to the surface of the etched layer; the barrier layer preferably includes a silicon oxide film; the source and drain of the amplifier, load transistor and bias transistor are preferably disposed in the barrier layer; the source, drain and upper plate preferably include a Mo film and an ITO film stacked sequentially from bottom to top.

[0080] In this invention, the thin-film transistor preferably includes an encapsulation layer attached to the surface of the barrier layer, and the encapsulation layer preferably includes a silicon oxide film. In this invention, the encapsulation layer preferably contains a copper electrode and the upper plate of a negative feedback capacitor. Copper has advantages such as stable chemical properties and high conductivity. In flexible electronics, it possesses the characteristic of simultaneously achieving both conductivity and flexibility, and exhibits low resistivity change during bending. The function of the copper layer is similar to that of the SD electrode layer; however, because the designed active electrode acts on the skin surface, molybdenum (Mo) is harmful to human skin and is unsuitable as the electrode material for this layer. Compared to molybdenum electrodes, copper electrodes are harmless to the human body.

[0081] This invention designs a bootstrap amplifier circuit structure based on a-IGZO, introduces a negative feedback structure to enable the circuit to achieve higher gain, and the TFT has low noise characteristics, which can reduce the introduction of noise while amplifying the acquired electromyographic signals, thereby giving the entire circuit a higher signal-to-noise ratio.

[0082] Example 2

[0083] This invention also provides a method for fabricating an active high-density electrode array, applied to the active high-density electrode array described in Example 1, the fabrication method comprising:

[0084] The raw materials for fabricating the gates of the amplifier transistor, load transistor, and bias transistor, as well as the lower plate of the feedback capacitor and the AC / DC integrated capacitor, are magnetron sputtered to form the initial gate layer.

[0085] Photoresist is coated onto the initial gate layer. After the coated photoresist is dried, the initial gate layer is exposed in conjunction with the first mask to form the exposed initial gate layer.

[0086] After development, the exposed initial gate layer is wet-etched to form the gates of the amplifier transistor, load transistor, and bias transistor, as well as the lower electrode of the feedback capacitor and the AC / DC integrated capacitor. The lower electrode of the negative feedback capacitor is made of the same material as the initial gate layer and is connected to the gate of the load transistor; the lower electrode of the AC / DC integrated capacitor is made of the same material as the initial gate layer and is connected to the gate of the amplifier transistor.

[0087] The raw materials for preparing the insulating layer are deposited on the gate of the amplifier tube, load tube and bias tube, the lower plate of the feedback capacitor and the AC / DC integrated capacitor to form the insulating layer.

[0088] The raw materials for preparing the active layers of the amplifying tube, load tube, and bias tube are magnetron sputtered onto the insulating layer to form the initial active layer.

[0089] Photoresist is coated onto the initial active layer. After the coated photoresist is dried, the initial active layer is exposed using a second mask to form the exposed initial active layer.

[0090] After the initial active layer is exposed, it is developed and then etched to form the precursors of the active layers of the amplification tube, load tube, and bias tube.

[0091] The precursor is annealed to form the active layer of the amplifier tube, load tube, and bias tube.

[0092] The raw materials for preparing the etching layer are chemically deposited on the active layer to form the initial etching layer.

[0093] Photoresist is coated onto the initial etched layer. After the coated photoresist is dried, it is exposed to the initial etched layer in conjunction with a third mask to form the exposed initial etched layer.

[0094] After developing the initial etched layer after exposure, dry etching is performed to create etched layers between the active layers of the amplifier tube, load tube, and bias tube and their corresponding SD drain and source, between the gate and drain of the bias tube, between the source of the bias tube and one end of the gate of the load tube, between the source of the load tube and the drain of the amplifier tube, between the gate of the amplifier and one end of the AC / DC integrated capacitor, and between the gate of the amplifier and the resistor.

[0095] The raw materials for preparing the source and drain of the amplifier tube, load tube, and bias tube, as well as the upper plates of the coupling capacitor and coupling resistor, are magnetron sputtered onto the etching layer. This achieves interconnection between the active layer of the amplifier tube, load tube, and bias tube and the corresponding SD source and drain, between the gate and drain of the bias tube, between the source of the bias tube and one end of the gate of the load tube, between the source of the load tube and the drain of the amplifier tube, between the gate of the amplifier and one end of the AC / DC integrated capacitor, and between the gate of the amplifier and the resistor, thus forming the SD electrode film.

[0096] Photoresist is coated onto the SD electrode film. After the coated photoresist is dried, the SD electrode film is exposed using a fourth mask to form the exposed SD electrode film.

[0097] After the exposed SD electrode film is developed, it is etched to form the source and drain of the amplifier tube, load tube and bias tube, as well as the upper plate of the AC / DC integrated capacitor and resistor.

[0098] The raw materials for preparing the barrier layer are chemically deposited on the source and drain electrodes of the amplifier tube, load tube, and bias tube, as well as on the upper plates of the coupling capacitor and coupling resistor, to form the initial barrier layer.

[0099] Photoresist is coated onto the initial barrier layer. After the coated photoresist is dried, the initial barrier layer is exposed using a fifth mask to form the exposed initial barrier layer.

[0100] The initial barrier layer after exposure is developed and then dry-etched to form a barrier layer.

[0101] Copper is vapor-deposited onto the barrier layer to form the initial copper plating layer.

[0102] Photoresist is coated onto the initial copper plating layer. After the coated photoresist is dried, the initial copper plating layer is exposed using a sixth mask to form the exposed initial copper plating layer.

[0103] The initial copper plating layer after exposure is developed and then etched to form a copper plating layer and the upper electrode of the negative feedback capacitor; a portion of the copper plating layer connects the drain of the bias transistor and the drain of the load transistor.

[0104] A portion of the copper plating layer is connected to the junction between the source of the load transistor and the drain of the amplifier transistor, serving as the output terminal.

[0105] A portion of the copper plating layer is connected to the source of the amplifier tube and then grounded.

[0106] A portion of the copper plating layer is connected to the other end of the resistor.

[0107] The upper electrode of the negative feedback capacitor is fabricated on the copper plating layer, and the upper electrode of the negative feedback capacitor is used as the other port of the negative feedback capacitor and connected to the output V. OUT Terminal connection.

[0108] The raw materials for preparing the encapsulation layer are chemically vapor deposited onto the copper plating layer and the upper electrode of the negative feedback capacitor to form the initial encapsulation layer.

[0109] Photoresist is coated onto the initial encapsulation layer. After the coated photoresist is dried, the initial encapsulation layer is exposed using a seventh mask to form the exposed initial encapsulation layer.

[0110] After the initial encapsulation layer is exposed, it is developed and then dry-etched to form an encapsulation layer, thus obtaining the active amplifier circuit.

[0111] In practical applications, the present invention uses magnetron sputtering to form the initial gate layer from the raw materials for the gates of the amplifier tube, load tube, and bias tube, the feedback capacitor, and the lower plate of the AC / DC integrated capacitor.

[0112] In this invention, the raw materials for preparing the gates of the amplifier tube, load tube, and bias tube, the feedback capacitor, and the lower plate of the AC / DC integrated capacitor are preferably magnetron sputtered onto a flexible substrate.

[0113] In this invention, the flexible substrate sputtered by magnetron sputtering preferably comprises a PI film, a silicon oxide film, and a silicon nitride film stacked sequentially from bottom to top. The silicon oxide film and silicon nitride film can make the PI film more flat, thereby facilitating the fabrication of subsequent amplification circuits. A cross-sectional view of the flexible substrate is shown below. Figure 4 As shown.

[0114] PI film is an organic polymer film that is not only resistant to hydrolysis, high temperature and corrosion, but also has good biocompatibility and beneficial insulation properties.

[0115] The method for preparing the flexible substrate preferably includes the following steps:

[0116] After coating the glass with PI slurry, it is cured and then the resulting film is annealed to form a PI film.

[0117] Silicon oxide and silicon nitride films were prepared on the PI film using chemical vapor deposition.

[0118] Preferably, the glass is cleaned and dried before coating. The present invention does not impose any special limitations on the cleaning process; any method well-known to those skilled in the art can be used to clean the glass until no dust remains.

[0119] In this invention, the annealing process conditions preferably include 120°C for half an hour, 150°C for half an hour, 180°C for one hour, 250°C for half an hour, and 400°C for ten minutes.

[0120] After forming the gate layer, the present invention coats photoresist on the initial gate layer, dries the coated photoresist, and exposes the initial gate layer in conjunction with the first mask to form the exposed initial gate layer.

[0121] The design pattern is transferred onto photoresist by passing light through and blocking it using a photomask, thus creating the circuit.

[0122] After forming the initial gate layer after exposure, the present invention performs development treatment on the initial gate layer after exposure and then performs wet etching to form the gate of the amplifier tube, the load tube and the bias tube, the feedback capacitor and the lower plate of the AC / DC integrated capacitor.

[0123] In this invention, the development time is preferably 45 seconds.

[0124] In this invention, the product obtained from the development process is preferably cleaned and dried before wet etching.

[0125] In this invention, when the lower plate of the gate, feedback capacitor, and AC / DC integrated capacitor comprises Mo film and ITO film stacked sequentially from bottom to top, the wet etching preferably includes etching the ITO film and Mo film in oxalic acid at 45°C and a molybdenum-aluminum etching solution at room temperature.

[0126] After forming the gate of the amplifier transistor, load transistor, and bias transistor, the lower electrode of the feedback capacitor and the AC / DC integrated capacitor, the present invention deposits the raw materials for preparing the insulating layer on the gate of the amplifier transistor, load transistor, and bias transistor, the lower electrode of the feedback capacitor and the AC / DC integrated capacitor to form the insulating layer.

[0127] After forming the insulating layer, the present invention magnetron sputters the raw materials for preparing the active layers of the amplifying tube, the load tube, and the bias tube onto the insulating layer to form the initial active layer.

[0128] After forming the initial active layer, the present invention coats the initial active layer with photoresist, dries the coated photoresist, and then exposes the initial active layer with a second mask to form the exposed initial active layer.

[0129] After forming the initial active layer after exposure, the present invention performs development treatment on the initial active layer after exposure and then etches it to form the precursor of the active layer of the amplifier tube, the load tube and the bias tube.

[0130] In this invention, the development time is preferably 45 seconds.

[0131] In this invention, the product obtained from the development process is preferably cleaned and dried before wet etching.

[0132] In this invention, when the active layer is an IGZO film, the etching solution used for etching preferably includes oxalic acid.

[0133] After forming the precursor, the present invention anneals the precursor to form the active layer of the amplifier tube, load tube and bias tube.

[0134] In this invention, the annealing conditions preferably include: heating at room temperature to 220°C for 30 minutes, and annealing at a constant 220°C for 1 hour.

[0135] After the annealing is completed, the annealed product is preferably cooled and cleaned.

[0136] After the active layer is formed, the present invention chemically deposits the raw materials for preparing the etching layer onto the active layer to form the initial etching layer.

[0137] After forming the etched layer, the present invention coats photoresist onto the initial etched layer, dries the coated photoresist, and then exposes the initial etched layer with a third mask to form the exposed initial etched layer.

[0138] After forming the etched layer after exposure, the present invention performs dry etching after developing the initial etched layer after exposure to reserve gaps for interconnection between the active layers of the amplifier tube, load tube and bias tube and the corresponding SD drain and source, between the gate and drain of the bias tube, between the gate of the load tube and the source of the bias tube, and between the amplifier tube and the resistor, thus forming the etched layer.

[0139] After the dry etching, the present invention preferably cleans the resulting product. The cleaning preferably includes scrubbing with a positive adhesive stripping solution; the temperature of the positive adhesive stripping solution is preferably 55°C, and the scrubbing time is preferably 5 minutes.

[0140] After forming the etched layer, the present invention magnetron sputters the raw materials for preparing the source and drain of the amplifier tube, load tube and bias tube, as well as the upper plates of the coupling capacitor and coupling resistor, onto the etched layer, thereby achieving interconnection between the active layer of the amplifier tube, load tube and bias tube and the corresponding SD drain and source, between the gate and drain of the bias tube, between the gate of the load tube and the source of the bias tube, and between the amplifier tube and the resistor, thus forming the SD electrode film.

[0141] After forming the SD electrode film, the present invention coats the SD electrode film with photoresist, dries the coated photoresist, and then exposes the SD electrode film with a fourth mask to form the exposed SD electrode film.

[0142] After the exposed SD electrode film is formed, the present invention performs development treatment on the exposed SD electrode film and then etching to form the source and drain of the amplification tube, load tube and bias tube, as well as the upper electrode plate of the coupling capacitor and coupling resistor.

[0143] After forming the source and drain of the amplifier tube, load tube, and bias tube, as well as the upper plates of the coupling capacitor and coupling resistor, the present invention chemically deposits the raw materials for preparing the barrier layer on the source and drain of the amplifier tube, load tube, and bias tube, as well as the upper plates of the coupling capacitor and coupling resistor, to form an initial barrier layer.

[0144] Photoresist is coated onto the initial barrier layer. After the coated photoresist is dried, the initial barrier layer is exposed using a fifth mask to form the exposed initial barrier layer.

[0145] After forming the initial blocking layer after exposure, the present invention performs development treatment on the initial blocking layer after exposure and then performs dry etching to form the blocking layer.

[0146] In this invention, the dry etching preferably includes a drilling process. The dry etching process involves drilling holes at the input, output, gate, and drain terminals of each active amplifier circuit.

[0147] After forming the barrier layer, the present invention deposits copper onto the barrier layer to form an initial copper plating layer.

[0148] After forming the initial copper plating layer, the present invention coats photoresist onto the initial copper plating layer, dries the coated photoresist, and then exposes the initial copper plating layer with a sixth mask to form the exposed initial copper plating layer.

[0149] After forming the initial copper plating layer after exposure, the present invention performs development treatment on the initial copper plating layer after exposure and then etching to form the copper plating layer and the upper electrode of the negative feedback capacitor.

[0150] In this invention, the etching solution used for etching preferably includes a molybdenum-aluminum etchant. The designed circuit shape is formed through etching.

[0151] After the copper plating layer is formed, the raw materials for preparing the encapsulation layer are subjected to chemical vapor deposition on the copper plating layer to form the initial encapsulation layer.

[0152] Photoresist is coated onto the initial encapsulation layer. After the coated photoresist is dried, the initial encapsulation layer is exposed using a seventh mask to form the exposed initial encapsulation layer.

[0153] After the initial encapsulation layer is exposed, it is developed and then dry-etched to etch out test points, thus forming the encapsulation layer.

[0154] like Figure 4 and Figure 5 As shown, taking the active electrode array structure used in this invention as an example, the specific fabrication process is as follows:

[0155] Step 1: Fabrication of the flexible substrate

[0156] (1) Select a glass with a specification of 200mm×200mm and place it in a surface cleaning machine for cleaning. After ensuring that the surface is clean and free of dust, heat and dry it to prevent surface moisture from affecting the subsequent film formation process.

[0157] (2) Spin-coating PI slurry onto the cleaned glass plate, adjusting the spin coater settings to 400 rpm for 30 seconds to achieve a film thickness of 10 μm. After completion, the plate is transferred to an annealing furnace for curing. The annealing process is performed at stepped temperatures and times: 120℃ for half an hour, 150℃ for half an hour, 180℃ for one hour, 250℃ for half an hour, and 400℃ for ten minutes. After cooling to room temperature, to ensure a smoother PI film layer for subsequent amplification circuit fabrication, a 300 nm thick silicon oxide (100 nm) and silicon nitride (200 μm) film is grown on top of the PI film using CVD plasma chemical vapor deposition as a buffer protective layer, denoted as the PI substrate. The growth temperature is 350℃.

[0158] The purpose of annealing PI films is: (1) PI films have good thermal stability at high temperatures, and annealing can further improve their thermal stability. (2) The annealing process can affect the molecular arrangement and crystallinity of polyimide films, thereby adjusting their mechanical properties. This includes improving the strength, hardness, and wear resistance of the film.

[0159] The purpose of annealing the thin-film transistor mentioned later is as follows: (1) Annealing helps improve the crystal structure and quality of oxide thin films. Exposing the thin film at high temperature for a period of time may rearrange the crystal structure and reduce defects. This helps improve the conductivity and overall performance of the transistor. (2) The annealing process can adjust the carrier concentration in the oxide thin film, thereby obtaining better electron transport performance. (3) Annealing can increase the mobility of the transistor and reduce the threshold voltage.

[0160] The second step involves the fabrication of the bottom gate of the active amplifier circuit.

[0161] (1) Place the completed PI substrate in a surface cleaning machine for cleaning. After ensuring that the surface is clean and free of dust, perform a heating and drying process.

[0162] (2) The cleaned PI substrate is placed in a magnetron sputtering PVD process instrument, and the gate layer of the thin film transistor, the feedback capacitor, and the lower plate of the AC / DC integrated capacitor are grown by sputtering process. The corresponding film thicknesses from bottom to top are 70 nm Mo and 30 nm ITO.

[0163] (3) After completing the magnetron sputtering step, the photoresist is spin-coated at 1000 rpm for 30 seconds on the spin coater. After pre-baking, the photolithography machine is used in conjunction with a mask to complete the exposure.

[0164] (4) The exposed glass plate is subjected to a developing process, with the developing time controlled at 45s. The plate is then cleaned in a water bath, dried, and then placed under a microscope to observe the exposure.

[0165] (5) The developed glass plate is subjected to wet etching. ITO and Mo are etched in sequence using heated oxalic acid and room-temperature molybdenum-aluminum etchant to form the final pattern drawn on the bottom gate layer (corresponding to...). Figure 2 Gate-1 has dimensions of 20um × 40um; Gate-2 has dimensions of 22um × 170um; Gate-3 has dimensions of 24um × 220um. The distance between Gate-1 and Gate-2, and the distance between Gate-2 and Gate-3 are 100um and 110um, respectively. After cleaning, the samples were placed under a microscope for observation.

[0166] Step 3: Fabrication of the active layer for the active amplifier circuit:

[0167] (1) Based on the completed gate layer, silicon nitride (200nm) and silicon oxide (100um) films with a thickness of 300nm were grown sequentially as insulating layers using chemical vapor deposition.

[0168] (2) On the insulating layer, an IGZO layer with a thickness of 50 nm is sputtered on the insulating layer using a magnetron sputtering device (PVD, CME-200E, Japan) at room temperature.

[0169] (3) After completing the magnetron sputtering step, the photoresist is spin-coated at 1000 rpm for 30 seconds on the spin coater. After pre-baking, the photolithography machine is used in conjunction with a mask to complete the exposure.

[0170] (4) The exposed glass plate is subjected to a developing process, with the developing time controlled at 45s. The plate is then cleaned in a water bath, dried, and then placed under a microscope to observe the exposure.

[0171] (5) The developed glass plate is wet etched. Under normal temperature conditions, IGZO is etched with oxalic acid to form the final pattern of the active layer (the width / length of the bias tube active layer is 18um / 38um; the width / length of the load tube active layer is 20um / 168um; the width / length of the amplifier tube active layer is 218um / 20um; the spacing between the bias tube active layer and the load tube active layer, and the spacing between the load tube active layer and the amplifier tube active layer are 100um and 110um, respectively).

[0172] (6) Place the glass plate in the annealing furnace and set the annealing conditions to room temperature - 220°C for 30 minutes, maintain at 220°C for one hour. After annealing, wait for it to cool to room temperature and clean the glass plate.

[0173] Step 4: Etching and preparation of the blocking layer for the active amplifier circuit:

[0174] (1) On the active layer, a 200 nm thick silicon oxide layer is grown as a barrier layer by chemical vapor deposition.

[0175] (2) After completing the magnetron sputtering step, the photoresist is spin-coated at 1000 rpm for 30 seconds on the spin coater. After pre-baking, the photolithography machine is used in conjunction with a mask to complete the exposure.

[0176] (3) The exposed glass plate is subjected to a developing process, with the developing time controlled at 45s. The plate is then cleaned in a water bath, dried, and then placed under a microscope to observe the exposure.

[0177] (4) The developed glass plate is subjected to a dry etching process (the input, output, gate and drain terminals of each active amplifier circuit are drilled).

[0178] (5) After the glass plate is dry-etched, place it in a water bath at 60°C and a positive adhesive stripper at 55°C and scrub for 5 minutes to complete the cleaning.

[0179] Step 5: Fabrication of the SD electrode layer for the active amplifier circuit:

[0180] (1) A 70nm thick Mo film and a 30nm thick ITO film corresponding to the SD drain and source electrodes of the thin film transistor were grown sequentially on the glass plate after etching by sputtering process. The interconnection between the active layer of the amplifier transistor, the load transistor and the bias transistor and the corresponding SD drain and source electrodes, between the gate and drain of the bias transistor, between the gate of the load transistor and the source of the bias transistor, and between the amplifier transistor and the resistor was realized.

[0181] Specifically, using a magnetron sputtering apparatus at room temperature, Mo with a film thickness of 70 nm and ITO with a film thickness of 30 nm were sputtered as SD electrode layers on top of an etch barrier layer.

[0182] (2) After completing the magnetron sputtering step, the photoresist is spin-coated at 1000 rpm for 30 seconds on the spin coater. After pre-baking, the photolithography machine is used in conjunction with a mask to complete the exposure.

[0183] (3) The exposed glass plate is subjected to a developing process, with the developing time controlled at 45s. The plate is then cleaned in a water bath, dried, and then placed under a microscope to observe the exposure.

[0184] (4) The developed glass plate is wet etched. ITO and Mo are etched in heated oxalic acid and room temperature molybdenum-aluminum etchant in sequence to form the final pattern of the bottom grid layer (W / L of bias tube is 17um / 20um), (W / L of load tube is 22um / 20um), (W / L of magnification tube is 220um / 8.5um). After cleaning, the plate is moved to a microscope for observation.

[0185] Step 6: Fabrication of the blocking layer for the active amplifier circuit:

[0186] (1) A 200 nm thick silicon oxide layer is grown on the glass plate after the SD electrode layer has been fabricated by chemical vapor deposition process as a barrier layer.

[0187] (2) Photoresist was spin-coated on the barrier layer at 1000 rpm for 30 seconds on a spin coater. After pre-baking, exposure was completed using a photolithography machine with a mask.

[0188] (3) The exposed glass plate is subjected to a developing process, with the developing time controlled at 45s. The plate is then cleaned in a water bath, dried, and then placed under a microscope to observe the exposure.

[0189] (4) The developed glass plate is subjected to dry engraving process.

[0190] (5) After the glass plate is dry-etched, place it in a water bath at 60°C and a positive adhesive stripper at 55°C and scrub for 5 minutes to complete the cleaning.

[0191] Step 7: Active amplifier circuit fabrication and electrode copper plating layer fabrication.

[0192] (1) Place the glass plate after the barrier layer has been made in the evaporation machine, adjust the process parameters to power 75W and time to one hour to evaporate the copper layer with a film thickness of 200nm.

[0193] (2) Photoresist was spin-coated on the barrier layer at 1000 rpm for 30 seconds on a spin coater. After pre-baking, exposure was completed using a photolithography machine with a mask.

[0194] (3) The exposed glass plate is subjected to a developing process, with the developing time controlled at 45s. The plate is then cleaned in a water bath, dried, and then placed under a microscope to observe the exposure.

[0195] (4) The developed glass plate is wet etched to etch the designed circuit shape using a molybdenum-aluminum etching solution.

[0196] Step 8: Fabrication of the active amplifier circuit package layer:

[0197] (1) A 200 nm thick silicon oxide film is grown on the glass plate after the copper electrode layer has been fabricated by chemical vapor deposition process as an encapsulation protective layer.

[0198] (2) Photoresist was spin-coated on the barrier layer at 1000 rpm for 30 seconds on a spin coater. After pre-baking, exposure was completed using a photolithography machine with a mask.

[0199] (3) The exposed glass plate is subjected to a developing process, with the developing time controlled at 45s. The plate is then cleaned in a water bath, dried, and then placed under a microscope to observe the exposure.

[0200] (4) The developed glass plate is subjected to a dry etching process to etch out the amplifier circuit test points and test electrodes of each active electrode.

[0201] (5) After the glass plate is dry-etched, place it in a water bath at 60°C and a positive adhesive stripper at 55°C and scrub for 5 minutes to complete the cleaning.

[0202] The ninth step involves peeling the prepared active electrode array off the glass plate and encapsulating it by fixing it onto a flexible material. This facilitates subsequent electromyography signal acquisition and extends its lifespan, thus forming the final flexible electrode required.

[0203] Based on the preliminary circuit layout design, and combined with the mask template and the aforementioned nine-step process flow, the fabrication was completed. The electrical performance of a randomly selected portion of the oxide transistors from the experimental results was then tested. Their transfer characteristic curves and the inverter performance curve of a single active amplifier circuit are shown below. Figure 6 As shown in Table 1, the electrical characteristic parameters of the designed bootstrap amplifier circuit can be obtained through parameter extraction. The inverter performance of the designed bootstrap amplifier circuit is then tested. Figures 10-11 As shown, the circuit amplification is 11.2 times and the gain is as high as 21.9dB, as obtained by parameter extraction.

[0204] Table 1. Statistical table of electrical parameter characterization of a single thin-film transistor based on transfer characteristics.

[0205]

[0206]

[0207] Comparative Example 1: A common-source amplifier circuit structure was fabricated using the process described in Example 1, and the inverter characteristic curve of the circuit structure was tested as follows. Figures 7-9 As shown, the circuit amplification is 3.45 times, with a gain of 10.8dB, obtained through parameter extraction. Compared with the common-source circuit structure, the active amplifier circuit of this invention significantly improves the gain.

[0208] In summary, the active high-density electrode array designed by this invention can initially amplify weak signals by 20-25dB. By integrating the amplification circuit with the electrodes, signal loss during transmission can be better reduced, thus improving the acquisition quality of electromyographic signals.

[0209] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0210] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An active high-density electrode array, characterized by, The active high-density electrode array comprises a plurality of active electrode units, each of which comprises an active amplification circuit and an electrode, and all of the active electrode units are arranged in a matrix form to form the active high-density electrode array, and the number of rows and the number of columns of the active high-density electrode array are the same. The active amplification circuit comprises an amplification device, a load device, a bias device, a negative feedback capacitor, an AC-DC integration capacitor and an AC-DC integration resistor. The amplification device, the load device and the bias device are all thin film transistors. The active amplification circuit is formed by connecting an AC-DC integration circuit and a negative feedback amplification circuit, the negative feedback amplification circuit is formed by connecting the amplification device, the load device, the bias device and the negative feedback capacitor, and the AC-DC integration circuit is formed by connecting the AC-DC integration resistor and the AC-DC integration capacitor in parallel. The connection mode of the active amplification circuit comprises: The source of the bias device is connected with the gate of the load device and one end of the negative feedback capacitor, respectively; the other end of the negative feedback capacitor is connected with the source of the load device and the drain of the amplification device, respectively; the connection of the negative feedback capacitor, the source of the load device and the drain of the amplification device serves as an output end of a bootstrap inverter circuit; the gate of the amplification device is connected with one end of the AC-DC integration capacitor; the source of the amplification device is grounded; the drain of the load device and the gate and the drain of the bias device are connected with an external power supply; one end of the AC-DC integration capacitor is connected with one end of the AC-DC integration resistor; and the other end of the AC-DC integration resistor is connected with the external power supply.

2. The active high-density electrode array of claim 1, wherein, The other end of the AC-DC integration capacitor is connected with the electrode.

3. The active high-density electrode array of claim 1, wherein, The active electrode unit is an integrated structure, and the electrode and the active amplification circuit are integrated on a flexible substrate by using a photolithography technology of a metal oxide thin film transistor.

4. The active high-density electrode array of claim 3, wherein, The flexible substrate is a flexible polyimide film substrate.

5. The active high-density electrode array of claim 4, wherein, The flexible polyimide film substrate comprises a polyimide film layer and a buffer layer which are stacked in sequence from bottom to top; the buffer layer comprises a silicon nitride film and a silicon dioxide film which are stacked in sequence from bottom to top.

6. The active high-density electrode array of claim 5, wherein, The thickness of the silicon nitride film is 300 nm.

7. The active high-density electrode array of claim 5, wherein, The thickness of the silicon dioxide film is 200 nm.

8. The active high-density electrode array of claim 1, wherein, The amplification device, the load device and the bias device are all composed of a bottom gate layer, an active layer, an ES etching layer, an SD drain-source electrode layer, an etching protection layer, a copper plating layer and a protection layer which are stacked in sequence from bottom to top.

9. A method for fabricating an active high-density electrode array, applied to the active high-density electrode array of any one of claims 1-8, characterized in that, The preparation method comprises: Preparation raw materials of the gate of the amplification device, the load device and the bias device, the feedback capacitor and the AC-DC integration capacitor are subjected to magnetron sputtering to form an initial gate layer; After the coated photoresist is dried, the initial gate layer is exposed by using a first mask plate to form an exposed initial gate layer; The exposed initial gate layer is developed and then wet etched to form the lower plate of the gate, feedback capacitor and AC / DC integrated capacitor of the amplifier device, load device and bias device; the lower plate of the negative feedback capacitor is selected to be consistent with the material of the initial gate layer and is connected with the gate of the load device; the material of the lower plate of the AC / DC integrated capacitor is selected to be consistent with the material of the initial gate layer and is connected with the gate of the amplifier device; Insulating layer preparation materials are deposited on the lower plate of the gate, feedback capacitor and AC / DC integrated capacitor of the amplifier device, load device and bias device to form an insulating layer; Active layer preparation materials of the amplifier device, load device and bias device are magnetron sputtered on the insulating layer to form an initial active layer; Photoresist is coated on the initial active layer, and the coated photoresist is dried before the initial active layer is exposed in cooperation with a second mask plate to form an exposed initial active layer; The exposed initial active layer is developed and then etched to form the active layer precursor of the amplifier device, load device and bias device; The active layer precursor is annealed to form the active layer of the amplifier device, load device and bias device; Etching layer preparation materials are chemically deposited on the active layer to form an initial etching layer; Photoresist is coated on the initial etching layer, and the coated photoresist is dried before the initial etching layer is exposed in cooperation with a third mask plate to form an exposed initial etching layer; The exposed initial etching layer is developed and then dry etched to form reserved pores for the intercommunication between the active layer of the amplifier device, load device and bias device and the corresponding SD drain and source, the gate and drain of the bias device, one end of the source and gate of the bias device, the source of the load device and the drain of the amplifier device, one end of the gate of the amplifier and the AC / DC integrated capacitor, and the gate of the amplifier and the resistance, forming an etching layer; Amplifier device, load device and bias device source and drain and coupling capacitor and coupling resistor upper plate preparation materials are magnetron sputtered on the etching layer to realize the intercommunication between the active layer of the amplifier device, load device and bias device and the corresponding SD drain and source, the gate and drain of the bias device, one end of the source and gate of the bias device, the source of the load device and the drain of the amplifier device, one end of the gate of the amplifier and the AC / DC integrated capacitor, and the gate of the amplifier and the resistance, forming an SD electrode film; Photoresist is coated on the SD electrode film, and the coated photoresist is dried before the SD electrode film is exposed in cooperation with a fourth mask plate to form an exposed SD electrode film; The exposed SD electrode film is developed and then etched to form the source and drain of the amplifier device, load device and bias device and the upper plate of the AC / DC integrated capacitor and resistance; Barrier layer preparation materials are chemically deposited on the source and drain of the amplifier device, load device and bias device and the upper plate of the coupling capacitor and coupling resistor to form an initial barrier layer; Coating photoresist on the initial barrier layer, after drying the coated photoresist, exposing the initial barrier layer with the fifth mask plate, forming the exposed initial barrier layer; After developing the exposed initial barrier layer, dry etching is performed, forming the barrier layer; Evaporating copper on the barrier layer, forming the initial copper plating layer; Coating photoresist on the initial copper plating layer, after drying the coated photoresist, exposing the initial copper plating layer with the sixth mask plate, forming the exposed initial copper plating layer; After developing the exposed initial copper plating layer, etching is performed, forming the copper plating layer and the upper plate of the negative feedback capacitor; part of the copper plating layer connects the drain of the bias device and the drain of the load device; Part of the copper plating layer is connected to the connection between the source of the load device and the drain of the amplifier device as the output end; Part of the copper plating layer is connected to the source of the amplifier device and then grounded; Part of the copper plating layer is connected to the other end of the resistor; An upper plate of a negative feedback capacitor is prepared in the copper plating layer, and the upper plate of the negative feedback capacitor is connected with an output V OUT terminal as another port of the negative feedback capacitor. Chemical vapor deposition of the preparation raw material of the packaging layer on the copper plating layer and the upper plate of the negative feedback capacitor, forming the initial packaging layer; Coating photoresist on the initial packaging layer, after drying the coated photoresist, exposing the initial packaging layer with the seventh mask plate, forming the exposed initial packaging layer; After developing the exposed initial packaging layer, dry etching is performed, forming the packaging layer, obtaining the active amplifier circuit.

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