A multi-terminal system current synchronization method, device, equipment and medium

Abstract

The disclosed embodiment discloses a multi-terminal system current synchronization method, device, equipment and medium, including: constructing a circuit model corresponding to a cable terminal box AC loop multi-terminal system, the circuit model including a reference terminal and at least one correction terminal; for each correction terminal, correcting the current of the correction terminal according to the frequency difference between the correction terminal and the reference terminal, so that the current of the correction terminal is synchronized with the current of the reference terminal. The method constructs the cable terminal box AC loop multi-terminal system as a circuit model, corrects the correction terminal according to the difference between the correction terminal and the reference terminal of the circuit model, realizes the current data synchronization of the multi-terminal system, reduces the current data synchronization error, and improves the monitoring level of the substation AC power supply loop and related cables.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of intelligent monitoring technology, and in particular to a method, device, equipment and medium for synchronizing current in a multi-terminal system. Background Art

[0002] In history, there have been many accidents of cables heating and catching fire due to leakage in power supply loop cables. The current monitoring of leakage in multi-terminal systems of power supply loops has the following difficulties: It is difficult to synchronize the sampling data of multi-terminal system currents. At the same time, the residual current sensor may be deployed in areas with harsh electromagnetic environments, and the synchronization of current sampling is challenging. In addition, since optical fiber is not used, the synchronization error of the current data received by the acquisition device may be large. If there is a difference of one cycle, some synchronization methods will fail.

[0003] There are several existing methods for current data sampling synchronization. Sampling time adjustment method, sampling data correction method, clock correction method, reference vector-based synchronization method, and global positioning system (GPS)-based synchronization method. Among them, except for the reference phasor method and GPS synchronization method, other methods assume that the transmission delay in both directions is equal. For some flexible multiplexed communication systems, such as the synchronous digital hierarchy (SDH), errors may occur. Changes in these communication lines can cause changes in the communication channel transmission delay as large as 10ms. Summary of the invention

[0004] The embodiments of the present disclosure provide a multi-terminal system current synchronization method, device, equipment and medium, which realize current data synchronization of the multi-terminal system.

[0005] In a first aspect, a multi-terminal system current synchronization method is provided, comprising:

[0006] Constructing a circuit model corresponding to the AC loop multi-terminal system of the cable terminal box, wherein the circuit model includes a reference terminal and at least one correction terminal;

[0007] For each of the correction terminals, the current of the correction terminal is corrected according to the frequency difference between the correction terminal and the reference terminal, so that the current of the correction terminal is synchronized with the current of the reference terminal.

[0008] In a second aspect, a multi-terminal system current synchronization device is provided, comprising:

[0009] A model building module, used to build a circuit model corresponding to the cable terminal box AC loop multi-terminal system, wherein the circuit model includes a reference terminal and at least one correction terminal;

[0010] The correction module is used to correct the current of each correction end according to the frequency difference between the correction end and the reference end, so as to synchronize the current of the correction end with that of the reference end.

[0011] According to a third aspect, an electronic device is provided, the electronic device comprising:

[0012] at least one processor; and;

[0013] a memory communicatively connected to the at least one processor; wherein,

[0014] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the multi-terminal system current synchronization method provided by the first aspect above.

[0015] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a controller to implement the multi-terminal system current synchronization method provided in the first aspect of the embodiment of the present disclosure when executed.

[0016] The disclosed embodiments provide a method, device, equipment and medium for current synchronization of a multi-terminal system, including: constructing a circuit model corresponding to a multi-terminal system of an AC loop of a cable terminal box, the circuit model including a reference terminal and at least one correction terminal; for each correction terminal, correcting the current of the correction terminal according to the frequency difference between the correction terminal and the reference terminal, so that the current of the correction terminal is synchronized with the current of the reference terminal. The method constructs the multi-terminal system of the AC loop of a cable terminal box as a circuit model, and corrects the correction terminal according to the difference between the correction terminal and the reference terminal of the circuit model. Compared with the prior art, the technical solution realizes current data synchronization of a multi-terminal system, reduces current data synchronization errors, and improves the monitoring level of the AC power supply loop and related cables of the substation.

[0017] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the embodiments of the present disclosure. Other features of the embodiments of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a flow chart of a multi-terminal system current synchronization method provided in Embodiment 1 of the present disclosure;

[0020] Figure 2 is a schematic diagram of a circuit model provided in Embodiment 1 of the present disclosure;

[0021] Figure 3 is a schematic diagram of a circuit model with three load terminals provided in Embodiment 1 of the present disclosure;

[0022] Figure 4 It is a structural schematic diagram of a multi-terminal system current synchronization device provided in the second embodiment of the present disclosure;

[0023] Figure 5 A schematic diagram of the structure of an electronic device used to implement an embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the solutions of the embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only embodiments of part of the present disclosure, not all embodiments. Based on the embodiments in the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the embodiments of the present disclosure.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0026] Embodiment 1

[0027] Figure 1 This is a flowchart of a multi-terminal system current synchronization method provided in the first embodiment of the present disclosure. This embodiment is applicable to the case of synchronizing the current of a multi-terminal system. The method can be executed by a multi-terminal system current synchronization device. The multi-terminal system current synchronization device can be implemented in the form of hardware and / or software. The multi-terminal system current synchronization device can be configured in an electronic device. Figure 1As shown, the method includes:

[0028] S110: construct a circuit model corresponding to the AC loop multi-terminal system of the cable terminal box, wherein the circuit model includes a reference terminal and at least one correction terminal.

[0029] In this embodiment, the cable terminal box AC loop multi-terminal system can be modeled according to the π-type equivalent circuit to obtain a circuit model corresponding to the cable terminal box AC loop multi-terminal system. The π-type equivalent circuit can make the ideal transformer and the impedance connected in series with it equivalent as a whole, which not only realizes the function of voltage conversion, but also hides the ideal transformer, and is suitable for forming a node admittance matrix in a large-scale network.

[0030] It should be noted that the circuit model may include a reference terminal and at least one correction terminal, wherein the reference terminal may be used as a reference for current synchronization to achieve current correction of other terminals, and the correction terminal may be a terminal that requires current synchronization correction. The circuit model also includes a load terminal; the load terminal may be a terminal in the circuit model that has an external load.

[0031] S120: For each correction end, correct the current of the correction end according to the frequency difference between the correction end and the reference end, so that the current of the correction end is synchronized with the current of the reference end.

[0032] Specifically, the reference end and the correction end can be determined based on the constructed circuit model. Exemplarily, the reference end is the incoming line end of the circuit model; the correction end of the circuit model can include the outgoing line end and the load end of the circuit model.

[0033] Following the above description, after the reference end and the correction end are determined, the current at the correction end can be corrected according to the frequency difference between the correction end and the reference end. By correcting the current at the correction end, the current at the correction end and the current at the reference end are synchronized, wherein the frequency can be the number of cycles of the current per unit time, and the frequency difference can be the difference between the frequency of the current at the correction end and the frequency of the current at the reference end.

[0034] This embodiment provides a method for current synchronization of a multi-terminal system, including: constructing a circuit model corresponding to a multi-terminal system of an AC loop of a cable terminal box, the circuit model including a reference terminal and at least one correction terminal; for each correction terminal, correcting the current of the correction terminal according to the frequency difference between the correction terminal and the reference terminal, so that the current of the correction terminal is synchronized with the current of the reference terminal. This method constructs the multi-terminal system of the AC loop of a cable terminal box as a circuit model, and corrects the correction terminal according to the difference between the correction terminal and the reference terminal of the circuit model. This technical solution realizes the current data synchronization of the multi-terminal system, reduces the current data synchronization error, and improves the monitoring level of the AC power supply loop and related cables of the substation.

[0035] In one embodiment, the current at the correction end is corrected according to the frequency difference between the correction end and the reference end, including:

[0036] If the frequency difference between the correction end and the reference end is within a first range, a linear equation group is constructed according to circuit information of the circuit model, and the current of the correction end is corrected according to the solution of the linear equation group.

[0037] Specifically, after determining the correction end and the reference end of the circuit model, the frequency difference between the correction end and the reference end can be determined. If the frequency difference between the correction end and the reference end is within a first range, a linear equation group is constructed according to the circuit information of the circuit model, wherein the first range can be a first category range to which the frequency difference belongs, and illustratively, the first range can be less than one cycle.

[0038] Specifically, after the linear equation group is constructed, the linear equation group is solved, and the current at the correction end is corrected according to the solution of the linear equation group.

[0039] In one embodiment, the current at the correction end is corrected according to the frequency difference between the correction end and the reference end, including:

[0040] If the frequency difference between the correction end and the reference end is within the second range, the composite signal of the reference end is received through the correction end, and the current of the composite signal of the correction end is corrected according to the composite signal of the reference end; the composite signal of the correction end includes signals of different frequencies.

[0041] Specifically, after the frequency difference between the correction end and the reference end of the circuit model is determined, it is determined whether the frequency difference between the correction end and the reference end is within a second range, wherein the second range may be a second category range to which the frequency difference belongs. Exemplarily, the second category range may be greater than or equal to one frequency.

[0042] Specifically, if the frequency difference between the correction end and the reference end is within the second range, a composite signal can be sent out at the reference end, and the correction end can receive the composite signal of the reference end. After the correction end receives the composite signal, the composite signal of the correction end can be corrected according to the composite signal of the reference end, wherein the composite signal can be a combination of signals with different frequencies.

[0043] For example, considering that the incoming end of the circuit model is close to the power source, the incoming end can be used as the reference end to adjust the current data of the outgoing end and the load end. The composite signal of the outgoing end can be a composite square wave signal of 20Hz and 70Hz, and the composite signal is continuously sent for 100ms. The composite signal in the outgoing end current and the load end current can be extracted, and the current is judged whether it is delayed by analyzing the position of the zero crossing point of the composite signal in the outgoing end current and the load end current, and the composite signal is corrected according to the zero crossing point.

[0044] As an implementation manner, the correcting the current of the composite signal at the correction end according to the composite signal at the reference end includes:

[0045] The current of the composite signal at the correction end is adjusted so that a current zero-crossing point of a first specified frequency component of the composite signal at the correction end coincides with a current zero-crossing point of a second specified frequency component of the composite signal at the reference end.

[0046] Specifically, the zero crossing point of the first specified frequency component of the composite signal at the correction end can be made to coincide with the zero crossing point of the second specified frequency component of the reference end, thereby adjusting the current of the composite signal at the correction end, wherein the first specified frequency can be the frequency component of the correction end that needs to be compared with the zero crossing point, and the second specified frequency can be the frequency component of the reference end that needs to be compared with the zero crossing point.

[0047] Exemplarily, the frequency of the composite signal of the current at the outlet is 20 Hz and 70 Hz, and the zero crossing point of the 20 Hz and 70 Hz signals at the outlet lags behind the incoming line by one cycle (20 ms). Then, the 20 Hz and 70 Hz signals at the outlet 20 ms ago can be adjusted to the composite signal at the current outlet.

[0048] In one embodiment, constructing a linear equation system according to the circuit information of the circuit model includes:

[0049] a1) constructing a first equation for a common node based on Kirchhoff's first law according to the circuit information of the circuit model, constructing a second equation for a first correction branch based on Kirchhoff's second law, and constructing a third equation for a second correction branch based on Kirchhoff's second law;

[0050] In this embodiment, after the circuit model is constructed, a first equation can be constructed for the common node based on Kirchhoff's first law according to the circuit information of the circuit model, where the circuit information may include voltage information, current information and / or impedance information of the circuit model; wherein the common node is the intersection of the branch where the incoming line end is located, the branch where the reference end is located, and the branch where the load end is located.

[0051] It should be noted that after obtaining the circuit information of the circuit model, the first equation can be constructed for the common node based on Kirchhoff's first law; Kirchhoff's first law can also be called the node current law, and Kirchhoff's first law can be that at any node in the circuit, at any time, the sum of the currents flowing into the node is equal to the sum of the currents flowing out of the node;

[0052] Continuing with the above description, according to the obtained circuit information, a second equation can be constructed for the first correction branch based on Kirchhoff's second law, wherein Kirchhoff's second law can be that in any closed loop, the algebraic sum of the voltage drops on each component is equal to the algebraic sum of the electromotive force, that is, when starting from a point and going around the loop and returning to the point, the algebraic sum of the voltages of each segment is always equal to zero; the first correction branch can be the branch from the incoming line end to the common node of the circuit model.

[0053] Continuing with the above description, according to the acquired circuit information, a third equation may be constructed for the second correction branch based on Kirchhoff's second law, wherein the second correction branch is a branch from the load end of the circuit model to the common node.

[0054] b1) constructing a linear equation group according to the first equation, the second equation, the third equation and the voltage-current relationship of the second correction branch.

[0055] It can be known that after obtaining the first equation, the second equation and the third equation, a linear equation group can be constructed according to the first equation, the second equation, the third equation and the voltage-current relationship of the second correction branch, wherein the voltage-current relationship of the second correction branch can be obtained through the equivalent impedance from the common node to the load end.

[0056] As an implementation method of this embodiment, before constructing a linear equation group according to the first equation, the second equation, the third equation and the voltage-current relationship of the second correction branch, it also includes:

[0057] The voltage-current relationship of the second correction branch is determined according to the load end impedance.

[0058] Specifically, the load end impedance can be defined as Z P , then the voltage-current relationship of the second correction branch can be expressed as:

[0059]

[0060] Among them, Z P It can be the equivalent impedance of the cable from the common node to the load end.

[0061] Optionally, the circuit information of the circuit model includes an incoming line end equivalent voltage, a first current, a current of the common node, a second current, and a load end equivalent current;

[0062] The step of constructing a first equation for a common node based on the circuit information of the circuit model and Kirchhoff's first law includes:

[0063] Based on Kirchhoff's first law, the difference between the equivalent current at the incoming line end and the first current is equal to the sum of the current at the common node, the second current and the equivalent current at the load end, so as to construct the first equation for the common node.

[0064] Specifically, circuit information can be obtained according to the circuit model. The circuit information of the circuit model may include the equivalent voltage at the incoming line end, the first current, the current of the common node, the second current and the equivalent current at the load end, wherein the first current is the current of the capacitor branch in the incoming line end, and the second current is the current of the capacitor branch in the load end.

[0065] It can be known that after the circuit information is obtained, based on Kirchhoff's first law, the difference between the equivalent current at the incoming line end and the first current can be equal to the sum of the current at the common node, the second current and the equivalent current at the load end, and the first equation can be constructed for the common node.

[0066] For example, Figure 2 A schematic diagram of a circuit model provided in this embodiment, such as Figure 2 As shown, point X can be defined as a common node, with the M end (incoming end) as the reference end, the N end (outgoing end) and the P end (load end) as the correction end, and the first equation can be:

[0067]

[0068] in, It can be the equivalent voltage and equivalent current at the incoming line end, It can be the equivalent voltage and equivalent current at the load end, C M It can be the ground capacitance of the incoming line, C P It can be the capacitance to ground at the load end, It can be the current at the common node.

[0069] It should be explained that the current of the common node can be determined according to the voltage of the common node and the capacitance of the common node. Specifically, the total capacitance of half the capacitance of each π-type equivalent circuit at the common node X can be C X , Can be defined as:

[0070]

[0071] in, can be the voltage at the common node X, It can be obtained through the P end (load end):

[0072]

[0073] in, It can be the voltage at the N terminal (output terminal), It can be the current at the N terminal (outgoing line terminal), C N It can be the capacitance to ground of the N terminal (outgoing line terminal), Z N It can be the equivalent impedance of the cable between the common node and the N terminal (outgoing line end).

[0074] Optionally, the circuit information of the circuit model includes an incoming line terminal equivalent voltage, a voltage of the common node, an incoming line terminal impedance, a load terminal equivalent current and a first current;

[0075] The constructing a second equation for the first correction branch based on the circuit information of the circuit model and Kirchhoff's second law includes:

[0076] Based on Kirchhoff's second law, the difference between the incoming line equivalent voltage and the voltage of the common node is set equal to the product of the incoming line impedance and the third current, so as to construct a second equation for the first correction branch.

[0077] Specifically, the circuit information obtained according to the circuit model may include the incoming line end equivalent voltage, the voltage of the common node, the incoming line end impedance, the load end equivalent current and the first current, wherein the first current is the current of the capacitor branch in the incoming line end.

[0078] It can be known that after the circuit information is obtained, based on Kirchhoff's second law, the difference between the equivalent voltage at the incoming line end and the voltage of the common node can be made equal to the product of the incoming line end impedance and the third current to construct a second equation for the first correction branch, wherein the third current is the difference between the equivalent current at the load end and the first current.

[0079] Exemplarily, the second equation may be:

[0080]

[0081] Among them, Z M is the line impedance, Z M It can be the equivalent impedance of the cable between the common node and the M terminal (incoming line terminal), and the third current can be:

[0082]

[0083] The first current can be:

[0084]

[0085] Optionally, the circuit information of the circuit model includes the voltage of the common node, the load end equivalent voltage, the load end impedance, the load end equivalent current and the second current;

[0086] According to the circuit information of the circuit model, a third equation is constructed for the second correction branch based on Kirchhoff's second law, including:

[0087] Based on Kirchhoff's second law, the difference between the voltage of the common node and the equivalent voltage at the load end is equal to the product of the load end impedance and the fourth current to construct a third equation for the second correction branch; wherein the fourth current is the sum of the load end equivalent current and the second current.

[0088] Specifically, the circuit information of the circuit model includes the voltage of the common node, the equivalent voltage at the load end, the impedance at the load end, the equivalent current at the load end, and the second current. Based on Kirchhoff's second law, the difference between the voltage of the common node and the equivalent voltage at the load end is equal to the product of the impedance at the load end and the fourth current, and then a third equation is constructed for the second correction branch, wherein the second current can be the current of the capacitor branch in the load end, and the fourth current can be the sum of the equivalent current at the load end and the second current.

[0089] Exemplarily, the third-party program may be:

[0090]

[0091] Among them, Z P is the load end impedance, Z P It can be the equivalent impedance of the cable from the common node to the P terminal (load terminal), and the fourth current can be:

[0092]

[0093] The second current can be:

[0094]

[0095] As an implementation mode, the circuit model further includes a load end; the reference end is an incoming line end of the circuit model; the correction end of the circuit model includes an outgoing line end and a load end of the circuit model;

[0096] The correcting the current at the correction end according to the solution of the linear equation group includes:

[0097] a2) solving the linear equations to obtain the line-end equivalent voltage and the load-end equivalent voltage;

[0098] Specifically, by substituting the voltage-current relationship of the second correction branch into the first equation, the second equation and the third equation, a set of linear equations can be obtained.

[0099] Exemplarily, the linear equations may be:

[0100]

[0101] Among them, Z LP It can be the equivalent load impedance of the P terminal (load terminal) itself.

[0102] It should be explained that there may be multiple loads at the load end. When there are multiple loads at the load end, a linear equation group can be obtained based on the equivalent load impedance of the load end itself. Figure 3 This is a schematic diagram of a circuit model with three load terminals provided in this embodiment, as shown in FIG. Figure 3 As shown, when there are three loads at the load end, the M end (inlet end) is taken as the reference end, the N end (outlet end), the P end (load end), the O end (load end), and the Q end (load end) are taken as the correction ends, and the obtained linear equations can be:

[0103]

[0104] Among them, Z P It can be the equivalent impedance of the cable from the common node to the P end (load end), Z O It can be the equivalent impedance of the cable from the common node to the O end (load end), Z Q It can be the load impedance of the equivalent impedance end of the cable from the common node to the Q end (load end), It can be the equivalent voltage at the O terminal, It can be the equivalent voltage at the Q terminal, C O It can be the capacitance to ground at the O terminal, C Q It can be the capacitance to ground at the Q end, Z LO It can be the equivalent load impedance of the O end (load end) itself, Z LQ It can be the equivalent load impedance of the Q end (load end) itself.

[0105] It can be known that by solving the linear equations, the equivalent voltage at the incoming line end can be obtained. and the equivalent voltage at the load end

[0106] b2) respectively comparing the incoming line end equivalent voltage and the load end equivalent voltage with the actual voltage measured at the corresponding positions to obtain the corresponding phase angle difference;

[0107] In this embodiment, after solving the linear equation group to obtain the incoming line equivalent voltage and the load end equivalent voltage, the actual voltage at the corresponding position is measured, and the calculated incoming line equivalent voltage and load end equivalent voltage are compared with the actual voltage, so as to obtain the corresponding phase angle difference.

[0108] Exemplarily, the phase angle difference may be:

[0109]

[0110] in, It can be the voltage actually measured at the M terminal (incoming terminal), It can be the voltage actually measured at the P terminal (load terminal).

[0111] c2) respectively correcting the current at the corresponding correction end according to each of the phase angle differences.

[0112] Specifically, after the phase angle difference is obtained, the current at the corresponding correction end can be corrected according to the phase angle difference.

[0113] Embodiment 2

[0114] Figure 4 This is a schematic diagram of the structure of a multi-terminal system current synchronization device provided in the second embodiment of the present disclosure. Figure 4 As shown, the device includes: a model building module 210 and a correction module 220.

[0115] The model building module 210 is used to build a circuit model corresponding to the AC loop multi-terminal system of the cable terminal box, wherein the circuit model includes a reference terminal and at least one correction terminal;

[0116] The correction module 220 is used to correct the current of each correction end according to the frequency difference between the correction end and the reference end, so as to synchronize the current of the correction end with that of the reference end.

[0117] Embodiment 2 of the present disclosure provides a multi-terminal system current synchronization device, which realizes current data synchronization of the multi-terminal system, reduces current data synchronization errors, and improves the monitoring level of the substation AC power supply loop and related cables.

[0118] Optionally, the correction module 220 includes:

[0119] The first correction unit is used to construct a linear equation group according to the circuit information of the circuit model if the frequency difference between the correction end and the reference end is within a first range, and correct the current of the correction end according to the solution of the linear equation group.

[0120] Optionally, the correction module 220 further includes:

[0121] A second correction unit, for receiving the composite signal of the reference end through the correction end and correcting the current of the composite signal of the correction end according to the composite signal of the reference end if the frequency difference between the correction end and the reference end is within a second range; the composite signal of the correction end includes signals of different frequencies;

[0122] The first range is less than one cycle, and the second range is greater than or equal to one cycle.

[0123] Optionally, the circuit model also includes a load end; the reference end is the incoming line end of the circuit model; and the correction end of the circuit model includes the outgoing line end and the load end of the circuit model.

[0124] Optionally, the first correction unit may further include:

[0125] An equation construction subunit, configured to construct a first equation for a common node based on Kirchhoff's first law, construct a second equation for a first correction branch based on Kirchhoff's second law, and construct a third equation for a second correction branch based on Kirchhoff's second law according to the circuit information of the circuit model;

[0126] An equation group construction subunit, used for constructing a linear equation group according to the first equation, the second equation, the third equation and the voltage-current relationship of the second correction branch;

[0127] Among them, the common node is the intersection of the branch where the incoming line end is located, the branch where the reference end is located, and the branch where the load end is located, the first correction branch is the branch from the incoming line end to the common node, and the second correction branch is the branch from the load end of the circuit model to the common node.

[0128] Optionally, the first correction unit may further include:

[0129] A relationship determination subunit, used to determine the voltage-current relationship of the second correction branch according to the load end impedance

[0130] Optionally, the circuit information of the circuit model includes an incoming line equivalent voltage, a first current, a current of the common node, a second current, and a load end equivalent current; and the equation construction subunit may be used for:

[0131] Based on Kirchhoff's first law, the difference between the equivalent current at the incoming line end and the first current is equal to the sum of the current at the common node, the second current and the equivalent current at the load end, so as to construct the first equation for the common node;

[0132] The current of the common node is determined according to the voltage of the common node and the capacitance of the common node; the first current is the current of the capacitor branch in the incoming line end, and the second current is the current of the capacitor branch in the load end.

[0133] Optionally, the circuit information of the circuit model includes an incoming line terminal equivalent voltage, a voltage of the common node, an incoming line terminal impedance, a load terminal equivalent current, and a first current; and the equation construction subunit may be used for:

[0134] Based on Kirchhoff's second law, the difference between the incoming line equivalent voltage and the voltage of the common node is set to be equal to the product of the incoming line impedance and the third current, so as to construct a second equation for the first correction branch;

[0135] Wherein, the third current is the difference between the load end equivalent current and the first current;

[0136] The first current is the current of the capacitor branch in the incoming line terminal.

[0137] Optionally, the circuit information of the circuit model includes the voltage of the common node, the load end equivalent voltage, the load end impedance, the load end equivalent current and the second current; the equation construction subunit may also be used for:

[0138] Based on Kirchhoff's second law, the difference between the voltage at the common node and the equivalent voltage at the load end is set equal to the product of the load end impedance and the fourth current, so as to construct a third equation for the second correction branch;

[0139] Wherein, the fourth current is the sum of the load end equivalent current and the second current;

[0140] The second current is a current of a capacitor branch in the load terminal.

[0141] Optionally, the circuit model further includes a load end; the reference end is the incoming line end of the circuit model; the correction end of the circuit model includes the outgoing line end and the load end of the circuit model;

[0142] The first correction unit can also be used to:

[0143] Solving the linear equations to obtain the line-end equivalent voltage and the load-end equivalent voltage;

[0144] Respectively comparing the incoming line end equivalent voltage and the load end equivalent voltage with the actual voltage measured at the corresponding position to obtain the corresponding phase angle difference;

[0145] The current at the corresponding correction end is corrected according to each phase angle difference.

[0146] Optionally, the second correction unit may also be used to:

[0147] The current of the composite signal at the correction end is adjusted so that a current zero-crossing point of a first specified frequency component of the composite signal at the correction end coincides with a current zero-crossing point of a second specified frequency component of the composite signal at the reference end.

[0148] The multi-terminal system current synchronization device provided in the embodiments of the present disclosure can execute the multi-terminal system current synchronization method provided in any embodiment of the present disclosure, and has the corresponding functional modules and beneficial effects of the execution method.

[0149] Embodiment 3

[0150] Figure 5 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of the present disclosure described and / or claimed herein.

[0151] like Figure 5 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0152] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0153] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microprocessor, etc. The processor 11 executes the various methods and processes described above, such as a multi-terminal system current synchronization method.

[0154] In some embodiments, the multi-terminal system current synchronization method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the multi-terminal system current synchronization method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the multi-terminal system current synchronization method in any other appropriate manner (e.g., by means of firmware).

[0155] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0156] The computer programs for implementing the methods of the embodiments of the present disclosure may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.

[0157] In the context of the disclosed embodiments, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0158] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0159] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0160] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0161] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in the embodiments of the present disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions of the embodiments of the present disclosure can be achieved, and this document does not limit this.

[0162] The above specific implementations do not constitute a limitation on the protection scope of the embodiments of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the embodiments of the present disclosure shall be included in the protection scope of the embodiments of the present disclosure.

Claims

1. A multi-terminal system current synchronization method, characterized in that: include: Constructing a circuit model corresponding to a multi-terminal system of an AC loop of a cable terminal box, wherein the circuit model includes a reference terminal and at least one correction terminal; For each of the correction terminals, the current of the correction terminal is corrected according to the frequency difference between the correction terminal and the reference terminal, so that the current of the correction terminal is synchronized with the current of the reference terminal; The step of correcting the current at the correction end according to the frequency difference between the correction end and the reference end comprises: If the frequency difference between the correction end and the reference end is within a first range, constructing a linear equation group according to the circuit information of the circuit model, and correcting the current of the correction end according to the solution of the linear equation group; If the frequency difference between the correction end and the reference end is within a second range, the composite signal of the reference end is received through the correction end, and the current of the composite signal of the correction end is corrected according to the composite signal of the reference end; the composite signal of the correction end includes signals of different frequencies; Wherein, the first range is less than one cycle, and the second range is greater than or equal to one cycle; The circuit model also includes a load end, the reference end is an incoming line end of the circuit model, and the correction end of the circuit model includes an outgoing line end and a load end of the circuit model; The step of correcting the current of the composite signal at the correction end according to the composite signal at the reference end includes: The current of the composite signal at the correction end is adjusted so that a current zero-crossing point of a first specified frequency component of the composite signal at the correction end coincides with a current zero-crossing point of a second specified frequency component of the composite signal at the reference end.

2. The method according to claim 1, characterized in that: A linear equation group is constructed according to the circuit information of the circuit model, including: According to the circuit information of the circuit model, construct a first equation for the common node based on Kirchhoff's first law, construct a second equation for the first correction branch based on Kirchhoff's second law, and construct a third equation for the second correction branch based on Kirchhoff's second law; Constructing a linear equation group according to the first equation, the second equation, the third equation and the voltage-current relationship of the second correction branch; Among them, the common node is the intersection of the branch where the incoming line end is located, the branch where the reference end is located, and the branch where the load end is located, the first correction branch is the branch from the incoming line end to the common node, and the second correction branch is the branch from the load end of the circuit model to the common node.

3. The method according to claim 2, characterized in that Before constructing a linear equation group according to the first equation, the second equation, the third equation and the voltage-current relationship of the second correction branch, the method further includes: The voltage-current relationship of the second correction branch is determined according to the load end impedance.

4. The method according to claim 2, characterized in that: The circuit information of the circuit model includes an incoming line equivalent voltage, a first current, a current of the common node, a second current, and a load end equivalent current; The step of constructing a first equation for a common node based on the circuit information of the circuit model and Kirchhoff's first law includes: Based on Kirchhoff's first law, the difference between the equivalent current at the incoming line end and the first current is equal to the sum of the current at the common node, the second current and the equivalent current at the load end, so as to construct the first equation for the common node; The current of the common node is determined according to the voltage of the common node and the capacitance of the common node; the first current is the current of the capacitor branch in the incoming line end, and the second current is the current of the capacitor branch in the load end.

5. The method according to claim 2, characterized in that: The circuit information of the circuit model includes an incoming line terminal equivalent voltage, a voltage of the common node, an incoming line terminal impedance, a load terminal equivalent current and a first current; The constructing a second equation for the first correction branch based on the circuit information of the circuit model and Kirchhoff's second law includes: Based on Kirchhoff's second law, the difference between the incoming line equivalent voltage and the voltage of the common node is set to be equal to the product of the incoming line impedance and the third current, so as to construct a second equation for the first correction branch; Wherein, the third current is the difference between the load end equivalent current and the first current; The first current is the current of the capacitor branch in the incoming line terminal.

6. The method according to claim 2, characterized in that The circuit information of the circuit model includes the voltage of the common node, the load end equivalent voltage, the load end impedance, the load end equivalent current and the second current; According to the circuit information of the circuit model, a third equation is constructed for the second correction branch based on Kirchhoff's second law, including: Based on Kirchhoff's second law, the difference between the voltage at the common node and the equivalent voltage at the load end is set equal to the product of the load end impedance and the fourth current, so as to construct a third equation for the second correction branch; Wherein, the fourth current is the sum of the load end equivalent current and the second current; The second current is a current of a capacitor branch in the load terminal.

7. The method according to claim 1, characterized in that The circuit model also includes a load end; the reference end is the incoming line end of the circuit model; the correction end of the circuit model includes the outgoing line end and the load end of the circuit model; The correcting the current at the correction end according to the solution of the linear equation group includes: Solving the linear equations to obtain the line-end equivalent voltage and the load-end equivalent voltage; Respectively comparing the incoming line end equivalent voltage and the load end equivalent voltage with the actual voltage measured at the corresponding position to obtain the corresponding phase angle difference; The current at the corresponding correction end is corrected according to each phase angle difference.

8. A multi-terminal system current synchronization device, characterized in that: include: A model building module, used to build a circuit model corresponding to the cable terminal box AC loop multi-terminal system, wherein the circuit model includes a reference terminal and at least one correction terminal; A correction module, for correcting the current of each correction end according to the frequency difference between the correction end and the reference end, so as to synchronize the current of the correction end with that of the reference end; The correction module also includes: A first correction unit, configured to construct a linear equation group according to circuit information of the circuit model and correct the current of the correction end according to a solution of the linear equation group if the frequency difference between the correction end and the reference end is within a first range; A second correction unit, for receiving the composite signal of the reference end through the correction end and correcting the current of the composite signal of the correction end according to the composite signal of the reference end if the frequency difference between the correction end and the reference end is within a second range; the composite signal of the correction end includes signals of different frequencies; Wherein, the first range is less than one cycle, and the second range is greater than or equal to one cycle; The circuit model also includes a load end, the reference end is an incoming line end of the circuit model, and the correction end of the circuit model includes an outgoing line end and a load end of the circuit model; Wherein, the second correction unit is further used for: The current of the composite signal at the correction end is adjusted so that a current zero-crossing point of a first specified frequency component of the composite signal at the correction end coincides with a current zero-crossing point of a second specified frequency component of the composite signal at the reference end.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the multi-terminal system current synchronization method as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the multi-terminal system current synchronization method as described in any one of claims 1-7 is implemented.

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