High dynamic range ADC for unlimited sampling

Abstract

The present invention relates to a high dynamic range ADC for infinite sampling. It comprises a voltage folding module, an ASDM module, a folding number calculation module, a time digital conversion module, and a signal recovery module; wherein the voltage folding module implements a modulus operation on an input signal to obtain a modulus voltage signal; the ASDM module converts the modulus voltage signal into a time signal; the time digital conversion module quantizes the time signal to obtain a multi-bit digital signal; the folding number calculation module calculates the folding number and folding position of the voltage folding module; and the signal recovery module recovers the digital signal using the result of the folding number calculation module to obtain a recovered signal. The present invention can realize a high dynamic range signal input and has a high signal-to-noise ratio.

Description

Technical Field

[0001] The present invention relates to a high dynamic range ADC for infinite sampling. Background Art

[0002] Existing analog-to-digital converters (ADCs), such as CN115967401A, a pipelined folded interpolation analog-to-digital converter, aims to solve the problem that the data conversion results of existing pipelined folded interpolation structure analog-to-digital converters are incorrect due to the correctness of the zero crossing of the folded quantization curve, or the comparator due to accuracy limitation or offset voltage error, resulting in errors in the final data conversion results; and CN101499802B, an improved folded structure ADC, aims to save chip area, and when the accuracy of the fine quantizer allows, it can correct the error at the folding point caused by the accuracy of the coarse quantizer to a certain extent, and has good fault tolerance; obviously, no mention is made of the ADC dynamic range related content; the novel infinite sampling (US) theory enables the analog-to-digital converter (ADC) to effectively manage input signals with a dynamic range far exceeding the threshold voltage. However, the existing US asynchronous sigma-delta modulator ADC (US-ASDM-ADC) design uses nonlinear modulation operations in a dual-channel architecture to generate the remainder and integer part, resulting in significant amplitude loss caused by non-ideal phenomena. Summary of the invention

[0003] The purpose of the present invention is to solve the above-mentioned problems, provide a high dynamic range ADC for infinite sampling, propose a new single-channel architecture and feedback compensation mechanism for US-ASDM-ADC, use a single-channel folding module to generate the remaining analog-to-digital operation, generate the integer part of the analog-to-digital operation at the same time, and start amplitude correction through a feedback system based on a Schmitt trigger, thereby avoiding saturation distortion of the ADC due to excessive signal amplitude; therefore, the present invention can achieve high dynamic range signal input and have a higher signal-to-noise ratio.

[0004] To achieve the above object, the technical solution of the present invention is: a high dynamic range ADC for infinite sampling, comprising a voltage folding module, an ASDM module, a folding number calculation module, a time digital conversion module, and a signal recovery module; wherein,

[0005] The voltage folding module implements the modulo operation on the input signal g(t) to obtain the modulo voltage signal x(t);

[0006] The ASDM module converts the analog voltage signal x(t) into a time signal Z(t);

[0007] The time-to-digital conversion module quantizes the time signal Z(t) to obtain a multi-bit digital signal K(n);

[0008] A folding number calculation module, which calculates the folding number and folding position of the voltage folding module;

[0009] The signal recovery module recovers the digital signal K(n) using the result of the folding number calculation module to obtain a recovered signal Res(t).

[0010] In one embodiment of the present invention, the voltage folding module includes an asynchronous sampling and holding module, Schmitt triggers M1 and M2, an operational amplifier amp2, switches K1 and K2, and a coupling capacitor C C The input end of the asynchronous sampling and holding module is used as the input end of the voltage folding module, and the output end of the asynchronous sampling and holding module is coupled to the output end of the voltage folding module through the coupling capacitor C C They are respectively connected to one end of the switches K1 and K2 and the non-inverting input end of the operational amplifier amp2, the other ends of the switches K1 and K2 are connected to the power supply, the control ends of the switches K1 and K2 are respectively connected to the output ends of the Schmitt triggers M1 and M2, the inverting input end of the operational amplifier amp2 is connected to the output end, and serves as the output end of the voltage folding module.

[0011] In one embodiment of the present invention, the asynchronous sampling and holding module includes a switch K C1 , K C2 , capacitor C1 and operational amplifier amp1, switch K C1 One end of the switch K is used as the input end of the asynchronous sampling and holding module. C1 The other end is connected through switch K C2 Connect one end of capacitor C1 and the non-inverting input end of operational amplifier amp1 respectively, and switch K C1 , K C2 The control end is connected to the output ends of the Schmitt triggers M1 and M2 respectively, the other end of the capacitor C1 is grounded, the inverting input end of the operational amplifier amp1, the output end of the operational amplifier amp1, and the input ends of the Schmitt triggers M1 and M2 are connected and serve as the output end of the asynchronous sampling and holding module. The output ends of the Schmitt triggers M1 and M2 are also connected to the two input ends of the folding number calculation module respectively.

[0012] In one embodiment of the present invention, the voltage folding module regards the compensation signal ε(t) as a DC signal and stores it in the coupling capacitor C C The whole process can be regarded as that when the amplitude of the output signal x(t) reaches the upper threshold λ, the Schmitt trigger M2 is triggered to pull up the output node V of the Schmitt trigger M2. So- The potential of switch K2 is closed, and switch K C1 The asynchronous sampling and holding module is in the holding state; the power supply V connected to the other end of the switch K2 H- The on-resistance R of switch K2 eq2With capacitor C C The filter unit forms the non-inverting input node V of the operational amplifier amp2. x The potential of the node V x When the corresponding threshold voltage is reached, the Schmitt trigger M2 is triggered to turn the node V So- The potential of the switch K2 is disconnected, and the switch K C1 Closed, the asynchronous sampling and holding module is in the sampling state; similarly, when the output signal x(t) reaches the lower threshold -λ, the Schmitt trigger M1 is triggered to pull down the output node V of the Schmitt trigger M1. So+ The potential of switch K1 is closed, and switch K C2 Disconnect, node V x The potential of the node V x When the corresponding threshold voltage is reached, the Schmitt trigger M2 is triggered to turn the node V So- The potential of the switch K1 is pulled high, and the switch K C2 Closed, the asynchronous sample and hold module is in the sampling state; thereby achieving amplitude compensation for the input signal g(t) to prevent the input of the back-end ASDM module from saturation.

[0013] In an embodiment of the present invention, the Schmitt triggers M1 and M2 both adopt a 6-CMOS transistor structure.

[0014] In one embodiment of the present invention, the ASDM module includes an integrator and a Schmitt trigger; the integrator includes resistors R1 and R'1 with the same resistance value, a capacitor C, a two-selection switch and an operational amplifier amp3, one end of the resistor R1 serves as the input end of the ASDM module, the other end of the resistor R1 is respectively connected to one end of the resistor R'1, one end of the capacitor C, and the inverting input end of the operational amplifier amp3, the other end of the resistor R'1 is connected to one end of the two-selection switch, the two input ends of the other end of the two-selection switch are respectively connected to two power supplies, and the control end of the two-selection switch The output end of the capacitor C is connected to the output end of the Schmitt trigger and serves as the output end of the ASDM module. The other end of the capacitor C is connected to the output end of the operational amplifier amp3. The non-inverting input end of the operational amplifier amp3 is connected to the ground. The Schmitt trigger includes a comparator, a resistor R2, and a resistor R3. The inverting input end of the comparator is connected to the output end of the operational amplifier amp3 as the input end of the Schmitt trigger. The non-inverting input end of the comparator is connected to the ground via the resistor R3. The non-inverting input end of the comparator is also connected to the output end of the comparator via the resistor R2 and serves as the output end of the Schmitt trigger.

[0015] In one embodiment of the present invention, the ASDM module performs time domain conversion by performing duty cycle modulation on the input signal x(t), and the output signal generated thereby is a square wave whose duty cycle meets the prescribed standard:

[0016]

[0017] where α M is the high level pulse width, T M is the output signal period, υ M is the amplitude of the input signal, M represents the number of output signal cycles, and b is the positive voltage of the two power supplies connected to the two input terminals of the other end of the two-selective switch;

[0018] The frequency ω0 of the output signal Z(t) satisfies:

[0019] ω0=(1-x(t) 2 / 2)ω c

[0020] where ω c is the angular frequency of the output signal when the input signal x(t) is 0.

[0021] In one embodiment of the present invention, the duty cycle signal output by the ASDM module can be approximately the time period t m →t m+1 The mean of the internal input signal x(t), which satisfies:

[0022]

[0023] where δ satisfies Z(t) max That is, the high level voltage of the duty cycle signal Z(t), k satisfies R1, R2, R3, and C represent the resistance values ​​of resistors R1, R2, and R3, and the capacitance value of capacitor C, respectively. m is the flip time of the duty cycle signal measured by the time-to-digital conversion module, t m+1 is the next flip time of the duty cycle signal measured by the time-to-digital conversion module, and m is the number of flips.

[0024] In one embodiment of the present invention, the operational amplifier amp1 and the operational amplifier amp2 both adopt a rail-to-rail input structure, which adopts a two-stage amplification form, with a folded common source and common gate structure as input and a common source stage amplification as output.

[0025] In one embodiment of the present invention, the operational amplifier amp3 adopts a rail-to-rail input structure, which adopts a two-stage amplification form, with a folded common source and common gate structure as input and a common source stage amplification as output.

[0026] Compared with the prior art, the present invention has the following beneficial effects: the present invention provides a high dynamic range ADC for infinite sampling, proposes a novel single-channel architecture and feedback compensation mechanism for US-ASDM-ADC, utilizes a single-channel folding module to generate the remaining analog-to-digital operation, generates the integer part of the analog-to-digital operation at the same time, and starts amplitude correction through a feedback system based on a Schmitt trigger, thereby avoiding saturation distortion of the ADC due to excessive signal amplitude; therefore, the present invention can realize high dynamic range signal input and has a higher signal-to-noise ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of the US-ASDM-ADC system of the present invention.

[0028] Figure 2 A rail-input operational amplifier with frequency compensation.

[0029] Figure 3 For input signal The waveform of each node when the folding module unit limits the output signal x(t) to the range of ±0.2V; Figure 3 (a) Signal in US-ASDM-ADC; Figure 3 (b) When the switch is in the closed state, the capacitor C C The charge and discharge output; Figure 3 (c) Node V x waveform.

[0030] Figure 4 To use the input signal Get the simulation results.

[0031] Figure 5 It is a classic Schmitt trigger structure. DETAILED DESCRIPTION

[0032] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings.

[0033] The present invention proposes a high dynamic range ADC for infinite sampling, namely US-ASDM-ADC, whose framework is as follows Figure 1 As shown, it includes a voltage folding module, an ASDM module, a folding number calculation module (FNC), a time digital conversion module (TDC) and a signal recovery module. Figure 1 As shown in the figure, the voltage folding module can realize the modulo operation of the input signal g(t), and the ASDM converts the modulo voltage signal x(t) into a time signal Z(t). The time signal Z(t) is quantized by TDC to obtain a multi-bit digital signal K(n). Finally, the recovery module uses the FNC result to recover the digital signal K(n) to obtain the recovered signal Res(t).

[0034] 1. Overall circuit module analysis and design

[0035] 1. Working principle of voltage folding module

[0036] The voltage folding module proposed in the present invention is composed of an asynchronous sampling and holding module, an operational amplifier amp2, a Schmitt trigger M 1,2 , switch K 1,2 and coupling capacitor C C Theoretically, it can achieve voltage folding of unlimited amplitude.

[0037] The voltage folding module treats the compensation signal ε(t) as a DC signal and stores it in the capacitor C C The whole process can be regarded as that when the output signal x(t) reaches the upper threshold λ, the Schmitt trigger M2 is triggered to pull up the node V So- The potential of switch K2 is closed, and switch K C1 Disconnect, the asynchronous sample and hold module is in the hold state. Power supply V H- The on-resistance R of switch K2 eq2 With capacitor C C The filter unit forms the node V x The potential of the node V x When the corresponding threshold voltage is reached, the Schmitt trigger M2 is triggered to turn the node V So- The potential of the switch K2 is disconnected, and the switch K C1 Closed, the asynchronous sample and hold module is in the sampling state. Similarly, when the output signal x(t) reaches the lower threshold -λ, the Schmitt trigger M1 is triggered to pull down the signal V So+ The potential of switch K1 is closed, and switch K C2 Disconnect, node V x The potential of the node V x When the corresponding threshold voltage is reached, the Schmitt trigger M2 is triggered to turn the node V So- The potential of the switch K1 is pulled high, and the switch K C2 Closed, the asynchronous sample and hold module is in the sampling state. This can achieve amplitude compensation of the input signal g(t) to prevent the back-end ASDM input from saturation.

[0038] 2. Working Principle of ASDM

[0039] like Figure 1As shown, the ASDM includes an integrator and a Schmitt trigger, which performs time domain conversion by duty cycle modulating the input signal x(t) of the ASDM module (that is, the output signal x(t) of the voltage folding module). The resulting output signal is a square wave whose duty cycle meets the specified standard:

[0040]

[0041] where α M is the high level pulse width, T M is the output signal period, υ M is the amplitude of the input signal, M represents the number of cycles of the output signal, and b is Figure 1 V th ;

[0042] The frequency ω0 of the output signal Z(t) satisfies:

[0043] ω0=(1-x(t) 2 / 2)ω c

[0044] where ω c is the angular frequency of the output signal when the input signal is 0.

[0045] ASDM is an event-driven sampling ADC. Since the ASDM output is an asynchronous square wave signal, a TDC is required to quantify the pulse width. The TDC sampling result can be approximated as the time period t m →t m+1 The mean value of the internal input signal satisfies:

[0046]

[0047] where δ satisfies k satisfies

[0048] The quantization result of the TDC on the output pulse width time of the ASDM module is a string of binary codes 101010..., such as Figure 3 Quantized values ​​of medium and high level pulse width α0, low level pulse width α1, etc.

[0049] To analyze the output signal-to-noise ratio, the duty cycle signal output by the ASDM can be Fourier expanded to obtain the output spectrum, which is composed of the input baseband signal and odd harmonics. The third harmonic component has the greatest impact. The empirical formula is:

[0050]

[0051] where f x is the input signal frequency.

[0052] From this harmonic noise, we can see that the input voltage range of the ASDM can be effectively reduced through the voltage folding module. While preventing the ASDM input from saturation, its output harmonic noise can be greatly reduced to obtain a higher signal-to-noise ratio.

[0053] 3. Voltage folding module design

[0054] The present invention uses voltage folding to control the input signal amplitude within the threshold. In order to optimize the overall power consumption, the operational amplifiers designed in this paper all use a rail-to-rail input structure, such as Figure 2 As shown, the structure adopts a two-stage amplification form, with a folded common source and common gate structure as input and a common source stage amplification as output. Since the supply voltage is ±0.4V, all tubes work in the subthreshold region, and the current I D With transconductance g m All meet the following requirements:

[0055]

[0056]

[0057] Among them, the saturation current I S Proportional to the width-to-length ratio W / L, I D is the drain-source current, V GS Represents the gate-source voltage, V DS represents the drain-source voltage, q is the electron charge, k is the Boltzmann constant, T is the absolute temperature, V T is the thermal voltage, n is the subthreshold swing coefficient, and ζ represents the non-ideal factor.

[0058] For the selection of parameters, firstly, in order to meet the bandwidth and folding performance requirements of the operational amplifier under low voltage and low current conditions, this design adopts a high aspect ratio design. 1,2 Equivalent impedance and capacitance C C The noise generated during the sampling process of the compensation voltage is limited to select the corresponding specifications. c And resistor R1 for frequency compensation, its DC gain satisfies:

[0059] A V0 ≈(g mn2 +g mp2 ) mp4 (r op4 +(r op6 / / r op2 ))g mp7 (r op7 / / r on7 )

[0060] r ois the intrinsic impedance of the MOS tube, g is the transconductance, r o The subscript of g is the corresponding MOS tube, such as r op4 is the intrinsic impedance of MOS tube Mp4, g mn2 is the transconductance of MOS tube Mn2, and the same is true for the others;

[0061] By measuring, the op amp has a common-mode input voltage V in,CM When in the range of B-0.3V to 0.3V, the phase margin of 66 degrees is satisfied, and the gain bandwidth product is 3.62MHz and the power consumption is 8uW.

[0062] 4. Schmitt trigger design

[0063] like Figure 5 As shown, the Schmitt trigger adopts the classic 6 CMOS tube structure, which can meet the design requirements of low power consumption and low area at high speed.

[0064] 2. Parameter configuration and error compensation

[0065] 1. Parameter configuration

[0066] When the DC gain is A V2 When the operational amplifier op_amp2 is used as a follower, the voltage folding module triggers the signal folding process of the lower threshold, and the switch K1 is closed. To ensure that the folding threshold requirement is met, the theoretical maximum value x(t) that the folding signal x(t) can reach at this time k,max ) must meet:

[0067]

[0068] Where h is the folding voltage value, Δh is the compensation voltage required to meet the actual folding, V x (t k,max ) is V in the folding process x The maximum value of, according to the above formula, needs to satisfy Δh>(h-λ) / (A V2 -1), λ represents the positive value of the threshold set for the modulo operation of the input signal, that is, the threshold voltage of the voltage folding module.

[0069] However, due to the limited gain-bandwidth product GBW and slew rate SR of op_amp2, during the voltage folding process, the folding signal g(t) does not change to the preset potential as ideal, but maintains an approximately linear change trend for a period of time. These non-ideal factors significantly affect the modulation results of ASDM, resulting in the final output time signal Z t This results in a pulse width error. Figure 3 The waveform changes observed at different nodes during the voltage folding process are shown in detail.

[0070] like Figure 3 As shown, in the time period [t k ,t k +Δt), due to the switch K 1,2 and capacitor C C The time constant τ of the low-pass filter is very short, and the node V x The voltage should be at the folding point t k Rapidly transition to the preset potential. However, under the influence of the fixed GBW and SR of op_amp2, the node potential V So- During this period, the analog voltage signal x(t) decays exponentially, so that the duty cycle modulation result of the ASDM has an error during this period.

[0071] Due to the existence of the delay Δt, Figure 3 As shown in the figure, in the folding process, if there is no asynchronous sampling and holding module, the change of the signal g(t) within the delay time Δt will cause an error in the charge stored on the capacitor. During this period, the positive plate V x The potential remains stable, while the potential change of the negative plate g(t) causes an imbalance in charge distribution, which in turn causes a C Storage errors are generated on the capacitor, and this error accumulates over time. Although the errors generated by triggering the upper threshold and the lower threshold at the output end can offset each other in theory, long-term frequent triggering of the same threshold will lead to the continuous accumulation of storage errors on the capacitor, thereby increasing the difficulty of correction. Therefore, the present invention introduces an asynchronous sampling and holding module to lock the input signal g(t) before the delay Δt arrives, effectively preventing the generation of such errors and significantly improving the accuracy and stability of the system.

[0072] For the compensation voltage ε(t k ), it is equivalent to the capacitor C C At time t k The amount of charge stored at. For a capacitor C with an initial charge value of Q0 C For example, at time point t k At, since switch k2 is turned on and discharged, the capacitor charge Q(t k ) will decay to -h, and for time t k At the capacitor, the charge Q(t k ) is defined as:

[0073]

[0074] Where N So+ Defined as the time period [0,t k ) The number of times the Schmitt trigger M1 is triggered, N So- Defined as the time period [0,t k) is the number of times the Schmitt trigger M2 is triggered, and K is the leakage constant.

[0075] 2. Compensation for non-ideal effects

[0076] By introducing the FNC module, the signal V So± The pulse position t k The key to this mechanism is to use the extracted folding information to calculate the corresponding compensation voltage ε(t k ), thereby effectively compensating for the modulation error of the ASDM and the error caused by the capacitor leakage.

[0077] Therefore, if the modulation time t of ASDM m coincides with the delay time Δt, such as Figure 3 As shown, we can use the known folding position t k and a fixed delay time Δt to estimate the interval [t m-1 ,t m ) to compensate for the modulation error of ASDM. When dealing with the problem of cumulative nonlinear time error in the time domain, we use an approximate linearization method. In order to accurately estimate the interval [t m-1 ,t m ), we consider the instantaneous folding position t k The signal amplitude at t m-1 ,t m ) to approximate the average value. This method effectively simplifies the complex nonlinear relationship and improves the accuracy and efficiency of the calculation. Therefore, we can use [t k ,t m+1 The average voltage during the period is approximately:

[0078]

[0079] By using the approximation method of the above formula, the original input signal g(t) can be estimated at [t k ,t m ) time period. By compensating [t m-1 ,t m The nonlinear attenuation part of the integral result within the time period can realize the voltage compensation of the folding node, and the modulation result after compensation can be defined as:

[0080]

[0081] Where k is [t m-1 ,t k ), the approximate slope of the signal g(t).

[0082] However, due to the coupling capacitance C C The voltage across the two ends is the compensation voltage ε(t k ), we can analyze the extracted pulse position t k In this way, when we need to determine the drain voltage at a specific time t, we can use the charge Q(t k ) definition formula for calculation.

[0083] 3. Results Analysis and Conclusion

[0084] The voltage folding module and ASDM are designed using 65nm CMOS technology. The threshold voltage λ of the voltage folding module is 0.2V, the threshold h is 0.3V, and the compensation voltage source V h± is ±0.31V. In addition, the threshold δ of ASDM is 0.2V and the voltage range b is 0.6V. Finally, it should be pointed out that the operating frequency of the TDC clock is 100.007936MHz. The feasibility of the proposed US-ASDM-ADC is verified by co-simulation in Cadence and SIMULINK.

[0085] Figure 4 The simulation waveform of the transistor-level model is shown when a sinusoidal signal with an input frequency of 4.578kHz is applied. Figure 4 (a) shows the ideal waveform of the input signal and its folded signal in the behavioral model, while Figure 4 (b) shows the uncompensated signal. The uncompensated signal includes two types of errors: time position error and leakage error. Error 1 is caused by the folding position error, and error 2 is caused by capacitor leakage. Figure 4 (c) shows the output after compensating for the temporal position error and leakage error.

[0086] To evaluate the performance of US-ASDM-ADC, we define the reconstruction signal-to-noise ratio (RSNR) as

[0087]

[0088] Table 1. Input Signals RSNR of US-ASDM-ADC

[0089]

[0090] The RSNR results are shown in Table 1. The results show that the RSNR of the proposed US-ASDM-ADC with compensation is 62.42dB, which is 1.98dB higher than that without compensation. Overall, our design surpasses the previous techniques in terms of system reliability and hardware utilization efficiency.

[0091] The above are preferred embodiments of the present invention. Any changes made according to the technical solution of the present invention, as long as the resulting functions do not exceed the scope of the technical solution of the present invention, belong to the protection scope of the present invention.

Claims

1. A high dynamic range ADC for infinite sampling, characterized in that: It includes voltage folding module, ASDM module, folding number calculation module, time digital conversion module and signal recovery module; among them, The voltage folding module implements the modulo operation on the input signal g(t) to obtain the modulo voltage signal x(t); The ASDM module converts the analog voltage signal x(t) into a time signal Z(t); The time-to-digital conversion module quantizes the time signal Z(t) to obtain a multi-bit digital signal K(n); A folding number calculation module, which calculates the folding number and folding position of the voltage folding module; The signal recovery module recovers the digital signal K(n) using the result of the folding number calculation module to obtain the recovered signal Res(t); The voltage folding module includes an asynchronous sampling and holding module, Schmitt triggers M1 and M2, an operational amplifier amp2, switches K1 and K2, and a coupling capacitor C C The input end of the asynchronous sampling and holding module is used as the input end of the voltage folding module, and the output end of the asynchronous sampling and holding module is coupled to the output end of the voltage folding module through the coupling capacitor C C They are respectively connected to one end of the switches K1 and K2 and the non-inverting input end of the operational amplifier amp2, the other ends of the switches K1 and K2 are connected to the power supply, the control ends of the switches K1 and K2 are respectively connected to the output ends of the Schmitt triggers M1 and M2, the inverting input end of the operational amplifier amp2 is connected to the output end, and serves as the output end of the voltage folding module.

2. A high dynamic range ADC for infinite sampling according to claim 1, characterized in that: The asynchronous sample-and-hold module includes a switch K C1 , K C2 , capacitor C1 and operational amplifier amp1, switch K C1 One end of the switch K is used as the input end of the asynchronous sampling and holding module. C1 The other end is connected through switch K C2 Connect one end of capacitor C1 and the non-inverting input end of operational amplifier amp1 respectively, and switch K C1 , K C2 The control end is connected to the output ends of the Schmitt triggers M1 and M2 respectively, the other end of the capacitor C1 is grounded, the inverting input end of the operational amplifier amp1, the output end of the operational amplifier amp1, and the input ends of the Schmitt triggers M1 and M2 are connected and serve as the output end of the asynchronous sampling and holding module. The output ends of the Schmitt triggers M1 and M2 are also connected to the two input ends of the folding number calculation module respectively.

3. A high dynamic range ADC for infinite sampling according to claim 2, characterized in that: The voltage folding module treats the compensation signal ε(t) as a DC signal and stores it in the coupling capacitor C. C The whole process can be regarded as that when the amplitude of the output signal x(t) reaches the upper threshold λ, the Schmitt trigger M2 is triggered to pull up the output node V of the Schmitt trigger M2. So- The potential of switch K2 is closed, and switch K C1 The asynchronous sampling and holding module is in the holding state; the power supply V connected to the other end of the switch K2 H- The on-resistance R of switch K2 eq2 With capacitor C C The filter unit forms the non-inverting input node V of the operational amplifier amp2. x The potential of the node V x When the corresponding threshold voltage is reached, the Schmitt trigger M2 is triggered to turn the node V So- The potential of the switch K2 is disconnected, and the switch K C1 Closed, the asynchronous sampling and holding module is in the sampling state; similarly, when the output signal x(t) reaches the lower threshold -λ, the Schmitt trigger M1 is triggered to pull down the output node V of the Schmitt trigger M1. So+ The potential of switch K1 is closed, and switch K C2 Disconnect, node V x The potential of the node V x When the corresponding threshold voltage is reached, the Schmitt trigger M2 is triggered to turn the node V So- The potential of the switch K1 is pulled high, and the switch K C2 Closed, the asynchronous sample and hold module is in the sampling state; thereby achieving amplitude compensation for the input signal g(t) to prevent the input of the back-end ASDM module from saturation.

4. A high dynamic range ADC for infinite sampling according to claim 1, characterized in that: The Schmitt triggers M1 and M2 both adopt a 6-CMOS tube structure.

5. A high dynamic range ADC for infinite sampling according to claim 1, characterized in that: The ASDM module includes an integrator and a Schmitt trigger; the integrator includes resistors R1 and R1' with the same resistance value, a capacitor C, a two-selection switch and an operational amplifier amp3, one end of the resistor R1 serves as the input end of the ASDM module, the other end of the resistor R1 is respectively connected to one end of the resistor R1', one end of the capacitor C, and the inverting input end of the operational amplifier amp3, the other end of the resistor R1' is connected to one end of the two-selection switch, the two input ends of the other end of the two-selection switch are respectively connected to two power supplies, the control end of the two-selection switch is connected to the output end of the Schmitt trigger and serves as the output end of the ASDM module, the other end of the capacitor C is connected to the output end of the operational amplifier amp3, and the non-inverting input end of the operational amplifier amp3 is connected to the ground; the Schmitt trigger includes a comparator, a resistor R2, and a resistor R3, the inverting input end of the comparator is connected to the output end of the operational amplifier amp3 as the input end of the Schmitt trigger, the non-inverting input end of the comparator is connected to the ground via the resistor R3, and the non-inverting input end of the comparator is also connected to the output end of the comparator via the resistor R2 and serves as the output end of the Schmitt trigger.

6. A high dynamic range ADC for infinite sampling according to claim 5, characterized in that: The ASDM module performs time domain conversion by performing duty cycle modulation on the input signal x(t). The output signal generated thereby is a square wave whose duty cycle meets the specified standard: where α M is the high level pulse width, T M is the output signal period, υ M is the amplitude of the input signal, M represents the number of output signal cycles, and b is the positive voltage of the two power supplies connected to the two input terminals of the other end of the two-selective switch; The frequency ω0 of the output signal Z(t) satisfies: ω0=(1-x(t) 2 / 2)ω c where ω c is the angular frequency of the output signal when the input signal x(t) is 0.

7. A high dynamic range ADC for infinite sampling according to claim 6, characterized in that: The duty cycle signal output by the ASDM module can be approximated as the time period t m →t m+1 The mean of the internal input signal x(t), which satisfies: where δ satisfies Z(t) max That is, the high level voltage of the duty cycle signal Z(t), k satisfies R1, R2, R3, and C represent the resistance values ​​of resistors R1, R2, and R3, and the capacitance value of capacitor C, respectively. m is the flip time of the duty cycle signal measured by the time-to-digital conversion module, t m+1 is the next flip time of the duty cycle signal measured by the time-to-digital conversion module, and m is the number of flips.

8. A high dynamic range ADC for infinite sampling according to claim 2, characterized in that: The operational amplifier amp1 and the operational amplifier amp2 both adopt a rail-to-rail input structure, which adopts a two-stage amplification form, with a folded common source and common gate structure as input and a common source stage amplification as output.

9. A high dynamic range ADC for infinite sampling according to claim 5, characterized in that: The operational amplifier amp3 adopts a rail-to-rail input structure. The rail-to-rail input structure adopts a two-stage amplification form, with a folded common source and common gate structure as input and a common source stage amplification as output.

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